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CH No 1 Microprocessor Features
CH No 1 Microprocessor Features
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Microprocessor
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Microprocessor Fifth Generation Pentium
Fourth Generation
During 1980s
Low power version of HMOS technology
(HCMOS)
Third Generation 32 bit processors
During 1978 Physical memory space 224 bytes = 16 Mb
HMOS technology Faster speed, Higher Virtual memory space 240 bytes = 1 Tb
packing density Floating point hardware
16 bit processors 40/ 48/ 64 pins Supports increased number of addressing
Easier to program modes
Dynamically relatable programs
Processor has multiply/ divide arithmetic Intel 80386
hardware
More powerful interrupt handling
capabilities Second Generation
Flexible I/O port addressing During 1973
NMOS technology Faster speed, Higher
Intel 8086 (16 bit processor) density, Compatible with TTL
4 / 8/ 16 bit processors 40 pins
First Generation Ability to address large memory spaces
Between 1971 – 1973 and I/O ports
PMOS technology, non compatible with TTL Greater number of levels of subroutine
4
4 bit processors 16 pins nesting
8 and 16 bit processors 40 pins Better interrupt handling capabilities
Due to limitations of pins, signals are
multiplexed Intel 8085 (8 bit processor)
Microprocessor
Functional blocks
Computational Unit;
performs arithmetic and
Various conditions of the
results are stored as
Internal storage of data
status bits called flags in
logic operations
flag register
5
Generates control signals for
internal and external Decodes instructions; sends
operations of the information to the timing and
microprocessor control unit
8086 Microprocessor
Overview
First 16- bit processor released by Addressable memory space is
INTEL in the year 1978 organized in to two banks of 512 kb
each; Even (or lower) bank and Odd (or
higher) bank. Address line A0 is used to
Originally HMOS, now manufactured select even bank and control signal 𝐁𝐇𝐄
using HMOS III technique is used to access odd bank
Address/Data bus
MN/ MX
MINIMUM / MAXIMUM
READY
CLK
15
8086 Microprocessor
Maximum mode signals
16
8086 Microprocessor
Maximum mode signals
17
8086 Microprocessor
Maximum mode signals
Architecture
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Architecture
Segment
Registers
8086’s 1-megabyte memory The 8086 can directly address four Programs obtain access to code
is divided into segments of segments (256 K bytes within the 1 and data in the segments by
up to 64K bytes each. M byte of memory) at a particular changing the segment register
time. content to point to the desired
segments. 22
8086 Microprocessor
Bus Interface Unit (BIU)
Architecture
Segment Code Segment Register
Registers
16-bit
CS contains the base or start of the current code segment; IP contains the
distance or offset from this address to the next instruction byte to be
fetched.
That is, all instructions of a program are relative to the contents of the CS
register multiplied by 16 and then offset is added provided by the IP.
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8086 Microprocessor
Bus Interface Unit (BIU)
Architecture
Segment Data Segment Register
Registers
16-bit
Points to the current data segment; operands for most instructions are
fetched from this segment.
The 16-bit contents of the Source Index (SI) or Destination Index (DI) or
a 16-bit displacement are used as offset for computing the 20-bit
physical address.
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8086 Microprocessor
Bus Interface Unit (BIU)
Architecture
Segment Stack Segment Register
Registers
16-bit
The 20-bit physical stack address is calculated from the Stack Segment
(SS) and the Stack Pointer (SP) for stack instructions such as PUSH and
POP.
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8086 Microprocessor
Bus Interface Unit (BIU)
Architecture
Segment Extra Segment Register
Registers
16-bit
Points to the extra segment in which data (in excess of 64K pointed to by
the DS) is stored.
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8086 Microprocessor
Bus Interface Unit (BIU)
Architecture
Segment Instruction Pointer
Registers
16-bit
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8086 Microprocessor
Bus Interface Unit (BIU)
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8086 Microprocessor
Execution Unit (EU)
Architecture
EU decodes and
executes instructions.
A decoder in the EU
control system
translates instructions.
and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as :
Index, Destination Index) 29
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL
DX can be used as DH and DL
8086 Microprocessor
Execution Unit (EU)
Architecture
EU Accumulator Register (AX)
Registers
Consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX.
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8086 Microprocessor
Execution Unit (EU)
Architecture
EU Base Register (BX)
Registers
Consists of two 8-bit registers BL and BH, which can be
combined together and used as a 16-bit register BX.
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8086 Microprocessor
Execution Unit (EU)
Architecture
EU Counter Register (CX)
Registers
Consists of two 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX.
Example:
Architecture
EU Data Register (DX)
Registers
Consists of two 8-bit registers DL and DH, which can be
combined together and used as a 16-bit register DX.
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8086 Microprocessor
Execution Unit (EU)
Architecture
EU Stack Pointer (SP) and Base Pointer (BP)
Registers
SP and BP are used to access data in the stack segment.
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8086 Microprocessor
Execution Unit (EU)
Architecture
EU Source Index (SI) and Destination Index (DI)
Registers
Used in indexed addressing.
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8086 Microprocessor
Execution Unit (EU)
Architecture
EU Source Index (SI) and Destination Index (DI)
Registers
Used in indexed addressing.
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8086 Microprocessor
Execution Unit (EU)
Architecture
Flag Register
Auxiliary Carry Flag
lowest nibble, i.e, bit three during This flag is set, when there is
addition, or borrow for the lowest a carry out of MSB in case of
nibble, i.e, bit three, during addition or a borrow in case
subtraction. of subtraction.
This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF DF IF TF SF ZF AF PF CF
Tarp Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction
Direction Flag Interrupt Flag
This is used by string manipulation instructions. If this flag bit 37
is ‘0’, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode. external mask interrupts; clearing IF
Otherwise, the string is processed from the highest address disables these interrupts.
towards the lowest address, i.e., auto incrementing mode.
8086 Microprocessor
Architecture
8086 registers
categorized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
into 4 groups OF DF IF TF SF ZF AF PF CF
AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic operations
AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic operations
BX Base register Used to hold base value in base addressing mode to access memory
data
CX Count Register Used to hold the count value in SHIFT, ROTATE and LOOP instructions
DX Data Register Used to hold data for multiplication and division operations
SP Stack Pointer Used to hold the offset address of top stack memory
BP Base Pointer Used to hold the base value in base addressing using SS register to
access data from stack memory
SI Source Index Used to hold index value of source operand (data) for string
instructions 39
DI Data Index Used to hold the index value of destination operand (data) for string
operations
ADDRESSING MODES
&
Instruction set
8086 Microprocessor
Introduction Program
A set of instructions written to solve a problem.
Instruction
Directions which a microprocessor
follows to execute a task or part of a
task.
Computer language
1. Register Addressing
Group I : Addressing modes for register and
2. Immediate Addressing immediate data
3. Direct Addressing
5. Based Addressing
Group II : Addressing modes for memory data
6. Indexed Addressing
8. String Addressing
1. Addressing Modes
Register Addressing The instruction will specify the name of the
register which holds the data to be operated by
2. Immediate Addressing the instruction.
3. Direct Addressing Example:
4. Register Indirect Addressing
MOV CL, DH
5. Based Addressing
The content of 8-bit register DH is moved to
6. Indexed Addressing another 8-bit register CL
8. String Addressing
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8086 Microprocessor Group I : Addressing modes for register and
immediate data
1. Addressing Modes
Register Addressing
In immediate addressing mode, an 8-bit or 16-bit
2. Immediate Addressing data is specified as part of the instruction
3. Direct Addressing
Example:
4. Register Indirect Addressing
MOV DL, 08H
5. Based Addressing
The 8-bit data (08H) given in the instruction is
6. Indexed Addressing moved to DL
8. String Addressing
MOV AX, 0A9FH
9. Direct I/O port Addressing
The 16-bit data (0A9FH) given in the instruction is
10. Indirect I/O port Addressing
moved to AX register
11. Relative Addressing
(AX) 0A9FH
12. Implied Addressing
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8086 Microprocessor
1. Addressing Modes
Register Addressing
2. Immediate Addressing
Here, the effective address of the memory
3. Direct Addressing
location at which the data operand is stored is
4. Register Indirect Addressing given in the instruction.
12. Implied Addressing This addressing mode is called direct because the
displacement of the operand from the segment
base is specified directly in the instruction.
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8086 Microprocessor Group II : Addressing modes for memory
data
1. Addressing Modes
Register Addressing In Register indirect addressing, name of the
register which holds the effective address (EA)
2. Immediate Addressing will be specified in the instruction.
1. Addressing Modes
Register Addressing In Based Addressing, BX or BP is used to hold the
base value for effective address and a signed 8-bit
2. Immediate Addressing or unsigned 16-bit displacement will be specified
in the instruction.
3. Direct Addressing
In case of 8-bit displacement, it is sign extended
4. Register Indirect Addressing to 16-bit before adding to the base value.
(AL) (MA)
(AH) (MA + 1)
8086 Microprocessor Group II : Addressing modes for memory
data
1. Addressing Modes
Register Addressing SI or DI register is used to hold an index value for
memory data and a signed 8-bit or unsigned 16-
2. Immediate Addressing bit displacement will be specified in the
instruction.
3. Direct Addressing
Displacement is added to the index value in SI or
4. Register Indirect Addressing DI register to obtain the EA.
1. Addressing Modes
Register Addressing In Based Index Addressing, the effective address
is computed from the sum of a base register (BX
2. Immediate Addressing or BP), an index register (SI or DI) and a
displacement.
3. Direct Addressing
Example:
4. Register Indirect Addressing
MOV DX, [BX + SI + 0AH]
5. Based Addressing
Operations:
6. Indexed Addressing
000AH 0AH (Sign extended)
7. Based Index Addressing
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8086 Microprocessor
Group II : Addressing modes for memory
data
1. Addressing Modes
Register Addressing Employed in string operations to operate on string
data.
2. Immediate Addressing
The effective address (EA) of source data is stored
3. Direct Addressing in SI register and the EA of destination is stored in
DI register.
4. Register Indirect Addressing
Segment register for calculating base address of
5. Based Addressing source data is DS and that of the destination data
is ES
6. Indexed Addressing
1. Addressing Modes
Register Addressing These addressing modes are used to access data
from standard I/O mapped devices or ports.
2. Immediate Addressing
In direct port addressing mode, an 8-bit port
3. Direct Addressing address is directly specified in the instruction.
1. Addressing Modes
Register Addressing
2. Immediate Addressing
1. Addressing Modes
Register Addressing
2. Immediate Addressing
3. Direct Addressing
5. Based Addressing
6. Indexed Addressing
Instructions using this mode have no operands.
The instruction itself will specify the data to be
7. Based Index Addressing
operated by the instruction.
8. String Addressing
Example: CLC
9. Direct I/O port Addressing
This clears the carry flag to zero.
10. Indirect I/O port Addressing
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INSTRUCTION SET
8086 Microprocessor
Instruction Set
8086 supports 6 types of instructions.
2. Arithmetic Instructions
3. Logical Instructions
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8086 Microprocessor
Generally involve two operands: Source operand and Destination operand of the
same size.
A 8-bit data can only be moved to 8-bit register/ memory and a 16-bit data can be
moved to 16-bit register/ memory.
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8086 Microprocessor
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8086 Microprocessor
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POP mem MA S = (SS) x 1610 + SP
(mem) (MA S ; MA S + 1)
(SP) (SP) + 2
8086 Microprocessor
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8086 Microprocessor
ADD A, data
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8086 Microprocessor
ADDC A, data
66
8086 Microprocessor
SUB A, data
67
8086 Microprocessor
SBB A, data
68
8086 Microprocessor
69
8086 Microprocessor
70
8086 Microprocessor
74
8086 Microprocessor
CMP A, data
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8086 Microprocessor
76
8086 Microprocessor
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8086 Microprocessor
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8086 Microprocessor
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8086 Microprocessor
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8086 Microprocessor
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8086 Microprocessor
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8086 Microprocessor
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8086 Microprocessor
8086 instruction set includes instruction for string movement, comparison, scan, load and store.
Offset or effective address of the source operand is stored in SI register and that of the destination
operand is stored in DI register.
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8086 Microprocessor
REP
REPNZ/ REPNE
While CX 0 and ZF = 0, repeat execution of string instruction
(Repeat CMPS or SCAS until ZF = 1) and
(CX) (CX) - 1
85
8086 Microprocessor
MOVS
(MAE) (MA)
CMPS
LODS
89
8086 Microprocessor
STOS
90
8086 Microprocessor
CLC Clear CF 0
NOP No operation
ESC opcode mem/ reg Used to pass instruction to a coprocessor which shares the
address and data bus with the 8086 91
Mnemonics Explanation
CALL reg/ mem/ disp16 Call subroutine
92
8086 Microprocessor
Checks flags
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8086 Microprocessor
Mnemonics Explanation
JC disp8 Jump if CF = 1
JP disp8 Jump if PF = 1
JO disp8 Jump if OF = 1
JS disp8 Jump if SF = 1
Assemble Directives
Instructions to the Assembler regarding the program being executed.
Control the generation of machine codes and organization of the program; but no
machine codes are generated for assembler directives.
Used to :
› specify the start and end of a program
› attach value to variables
› allocate storage locations to input/ output data
› define start and end of segments, procedures, macros etc..
97
8086 Microprocessor
Assemble Directives
DB Define Byte
ASSUME Range : 00H – FFH for unsigned value; 00H – 7FH for
positive value and 80H – FFH for negative value
ORG
END General form : variable DB value/ values
EVEN
EQU
PROC
FAR Example:
NEAR LIST DB 7FH, 42H, 35H
ENDP
Three consecutive memory locations are reserved for the variable LIST
SHORT and each data specified in the instruction are stored as initial value in 98
the reserved memory location
MACRO
ENDM
8086 Microprocessor
Assemble Directives
DB Define Word
PROC
FAR Example:
NEAR ALIST DW 6512H, 0F251H, 0CDE2H
ENDP
Six consecutive memory locations are reserved for the variable ALIST and
SHORT each 16-bit data specified in the instruction is stored in two consecutive 99
memory location.
MACRO
ENDM
8086 Microprocessor
Assemble Directives
DB SEGMENT : Used to indicate the beginning of a code/ data/
stack segment
DW
ENDS : Used to indicate the end of a code/ data/ stack
SEGMENT segment
ENDS
General form:
ASSUME
ORG
END Segnam SEGMENT
EVEN
…
EQU … Program code
… or
PROC … Data Defining Statements
…
FAR …
NEAR
ENDP Segnam ENDS
SHORT 100
MACRO User defined name of the
segment
ENDM
8086 Microprocessor
Assemble Directives
DB Informs the assembler the name of the program/ data
segment that should be used for a specific segment.
DW
General form:
SEGMENT
ENDS
ASSUME segreg : segnam, .. , segreg : segnam
ASSUME
ORG
User defined name of the
END Segment Register
segment
EVEN
EQU
PROC Example:
FAR
NEAR ASSUME CS: ACODE, DS:ADATA Tells the compiler that the instructions of the
ENDP program are stored in the segment ACODE and
data are stored in the segment ADATA
SHORT 101
MACRO
ENDM
8086 Microprocessor
Assemble Directives
DB ORG (Origin) is used to assign the starting address (Effective address)
for a program/ data segment
ORG
Examples:
END
EVEN ORG 1000H Informs the assembler that the statements following ORG
EQU 1000H should be stored in memory starting with effective
address 1000H
PROC
FAR
LOOP EQU 10FEH Value of variable LOOP is 10FEH
NEAR
ENDP
_SDATA SEGMENT In this data segment, effective address of memory location
SHORT ORG 1200H 102
assigned to A will be 1200H and that of B will be 1202H and
A DB 4CH 1203H.
EVEN
MACRO B DW 1052H
ENDM _SDATA ENDS
8086 Microprocessor
Assemble Directives
DB PROC Indicates the beginning of a procedure
General form
ASSUME
ORG
procname PROC[NEAR/ FAR]
END
EVEN …
… Program statements of the procedure
EQU
…
Last statement of the procedure
PROC RET
ENDP
FAR procname ENDP
NEAR
Assemble Directives
DB
Examples:
DW
SEGMENT ADD64 PROC NEAR The subroutine/ procedure named ADD64 is declared as
ENDS NEAR and so the assembler will code the CALL and RET
… instructions involved in this procedure as near call and
… return
ASSUME …
RET
ORG
ADD64 ENDP
END
EVEN
EQU CONVERT PROC FAR The subroutine/ procedure named CONVERT is declared as
FAR and so the assembler will code the CALL and RET
… instructions involved in this procedure as far call and return
PROC …
ENDP …
FAR
RET
NEAR CONVERT ENDP
SHORT 104
MACRO
ENDM
8086 Microprocessor
Assemble Directives
DB Reserves one memory location for 8-bit signed displacement
in jump instructions
DW
Example:
SEGMENT
ENDS
ASSUME JMP SHORT AHEAD The directive will reserve one memory location
for 8-bit displacement named AHEAD
ORG
END
EVEN
EQU
PROC
ENDP
FAR
NEAR
SHORT 105
MACRO
ENDM
8086 Microprocessor
Assemble Directives
DB MACRO Indicate the beginning of a macro
PROC
ENDP
FAR
User defined name of the macro
NEAR
SHORT 106
MACRO
ENDM
107
Interfacing memory and i/o ports
8086 Microprocessor
Secondary Memory
Storage media comprising of slow devices such as
magnetic tapes and disks
Hold large data files and programs: Operating 109
system, compilers, databases, permanent programs
etc.
8086 Microprocessor
8086 : 16-bit
110
8086 Microprocessor
4 Read/ Write word at an odd address 0 1 D15 – D0 in first operation byte from
odd bank is transferred
1 0 D7 – D0 in first operation byte from 111
odd bank is transferred
8086 Microprocessor
Allot equal address space in odd and even bank for both
EPROM and RAM
Can be implemented in two IC’s (one for even and other for
odd) or in multiple IC’s
112
8086 Microprocessor
Initialization of stack
Memory mapped
Programmed I/ O
Data transfer is accomplished I/O mapped
through an I/O port controlled by
software
Interrupt driven I/ O
I/O device interrupts the processor and
initiate data transfer 117
Direct memory access
Data transfer is achieved by bypassing
the microprocessor
8086 Microprocessor
The I/O ports or peripherals can be treated like Only IN and OUT instructions can be used for data
memory locations and so all instructions related transfer between I/O device and processor
to memory can be used for data transmission
between I/O device and processor
Data can be moved from any register to ports Data transfer takes place only between
and vice versa accumulator and ports
When memory mapping is used for I/O devices, Full memory space can be used for addressing
full memory address space cannot be used for memory.
addressing memory.
Suitable for systems which require large
Useful only for small systems where memory memory capacity
requirement is less
For accessing the memory mapped devices, the For accessing the I/O mapped devices, the
processor executes memory read or write cycle. processor executes I/O read or write cycle.
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16-bit Data bus lines obtained by demultiplexing 8-bit Data bus lines obtained by demultiplexing
AD0 – AD15 AD0 – AD7
In MIN mode, pin 28 is assigned the signal M / In MIN mode, pin 28 is assigned the signal IO / 𝐌
𝐈𝐎
120
To access higher byte, 𝐁𝐇𝐄 signal is used No such signal required, since the data width is
only 1-byte
8087 Coprocessor
8086 Microprocessor
Each processor have a local bus to access local memory or I/O devices so
that a greater degree of parallel processing can be achieved
122
8086 Microprocessor
Features 1) Can operate on data of the integer, decimal and real types with lengths
ranging from 2 to 10 bytes
3) High performance numeric data processor it can multiply two 64-bit real
numbers in about 27s and calculate square root in about 36 s
123
8086 Microprocessor
124
8086 Microprocessor
125
8086 Microprocessor
𝐑𝐐 / 𝐆𝐓𝟏
126
8086 Microprocessor
INT
127
8086 Microprocessor
𝐒𝟐 𝐒𝟏 𝐒𝟎 Status
1 0 0 Unused
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive
QS0 – QS1
Co-processor – Intel 8087 8086 and 8087 reads 8087 keeps track for ESC
instruction bytes and puts instruction by monitoring 𝑺𝟐 - 𝑺𝟎
8087 instructions them in the respective queues and AD0 – AD15 of 8086.
are inserted in
the 8086 NOP Also keeps track of QS0 – QS1.
program
8087 instructions have 11011 Q status 00; does nothing
as the MSB of their first code
byte Q status 01; 8087 compares the
five MSB bits with 11011
Wake up the
coprocessor
Monitor
ESC
8086/ 8088
Activate the
WAIT
TEST pin
130
Wake up the 8086/
8088
131