Yêu cầu chung cho tất cả các bài tập và các học viên:

1. Yêu cầu chạy và hiểu code chương trình trong Quartus II, xây dựng được biểu
đồ theo thời gian, xác định được code chương trình đó làm việc gì (tính năng
của module này là gì). Có nhiều module giống nhau về tính năng, nhưng khác
nhau về cách viết, các bạn có thể tham khảo nhau để biết và hiểu thêm cách viết
code. Có thể đặt tên lại cho các module đó theo đúng cách hiểu biết của mỗi học
viên. Khuyến khích các bạn làm được nhiều hơn so với yêu cầu, ví dụ có thể
thiết kế lại module này dưới dạng schematic blocks.
2. Làm báo cáo tương ứng với bài tập của mình, trong đó yêu cầu giải thích ý
nghĩa của chương trình, nói qua đặc tính của ít nhất 2 loại device mà khi chạy
thử có thể biết được qua các file báo cáo.
Bài 1.

library IEEE;
use IEEE.Std_Logic_1164.all;

entity Conditional8to3Coder is
port ( POSITION_CODE: in std_logic_vector (7 downto 0);
BINARY_CODE : out std_logic_vector (2 downto 0)
);
end Conditional8to3Coder;

architecture CODERSTRUCT of Conditional8to3Coder is

begin
CODE:
BINARY_CODE <= "000" WHEN (POSITION_CODE = "00000001") ELSE
"001" WHEN (POSITION_CODE = "00000010") ELSE
"010" WHEN (POSITION_CODE = "00000100") ELSE
"011" WHEN (POSITION_CODE = "00001000") ELSE
"100" WHEN (POSITION_CODE = "00010000") ELSE
"101" WHEN (POSITION_CODE = "00100000") ELSE
"110" WHEN (POSITION_CODE = "01000000") ELSE
"111" WHEN (POSITION_CODE = "10000000") ELSE
"XXX" ;
end CODERSTRUCT;
Bài 2.

library IEEE;
use IEEE.Std_Logic_1164.all;
entity Selected8to3Coder is
port ( POSITION_CODE: in std_logic_vector (7 downto 0);
BINARY_CODE : out std_logic_vector (2 downto 0)
);
end Selected8to3Coder;

architecture CODERSTRUCT of Selected8to3Coder is

begin
CODE:
WITH POSITION_CODE SELECT
BINARY_CODE <= "000" WHEN "00000001",
"001" WHEN "00000010",
"010" WHEN "00000100",
"011" WHEN "00001000",
"100" WHEN "00010000",
"101" WHEN "00100000",
"110" WHEN "01000000",
"111" WHEN "10000000",
"XXX" WHEN others;
end CODERSTRUCT;
Bài 3.

library IEEE;
use IEEE.Std_Logic_1164.all;

entity CASE8to3Coder is
port ( POSITION_CODE: in std_logic_vector (7 downto 0);
BINARY_CODE : out std_logic_vector (2 downto 0)
);
end CASE8to3Coder;

architecture CODERSTRUCT of CASE8to3Coder is

begin
CODE: process (POSITION_CODE)
begin
case POSITION_CODE is
when "00000001" => BINARY_CODE <= "000";
when "00000010" => BINARY_CODE <= "001";
when "00000100" => BINARY_CODE <= "010";
when "00001000" => BINARY_CODE <= "011";
when "00010000" => BINARY_CODE <= "100";
when "00100000" => BINARY_CODE <= "101";
when "01000000" => BINARY_CODE <= "110";
when "10000000" => BINARY_CODE <= "111";
when others => BINARY_CODE <= "XXX";
end case;
end process CODE;
end CODERSTRUCT;
Bài 4.

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY Conditional8to3Decoder IS
PORT(
Binary_Code : IN STD_LOGIC_VECTOR ( 2 DOWNTO 0);
Position_Code : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0)
);
END Conditional8to3Decoder;

ARCHITECTURE DecoderStruct OF Conditional8to3Decoder IS

BEGIN
Decode:
Position_Code <= "00000001" WHEN (Binary_Code = "000") ELSE
"00000010" WHEN (Binary_Code = "001") ELSE
"00000100" WHEN (Binary_Code = "010") ELSE
"00001000" WHEN (Binary_Code = "011") ELSE
"00010000" WHEN (Binary_Code = "100") ELSE
"00100000" WHEN (Binary_Code = "101") ELSE
"01000000" WHEN (Binary_Code = "110") ELSE
"10000000" WHEN (Binary_Code = "111") ELSE
"XXXXXXXX";
END DecoderStruct;
Bài 5.

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY Selected8to3Decoder IS
PORT(
Binary_Code : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
Position_Code : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0)
);
END Selected8to3Decoder;

ARCHITECTURE DecoderStruct OF Selected8to3Decoder IS

BEGIN
Decode:
WITH Binary_Code SELECT
Position_Code <= "00000001" WHEN "000",
"00000010" WHEN "001",
"00000100" WHEN "010",
"00001000" WHEN "011",
"00010000" WHEN "100",
"00100000" WHEN "101",
"01000000" WHEN "110",
"10000000" WHEN "111",
"XXXXXXXX" WHEN others;
END DecoderStruct ;
Bài 6.

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY CASE8to3Decoder IS
PORT(
Binary_Code : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
Position_Code : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0)
);
END CASE8to3Decoder;

ARCHITECTURE DecoderStruct OF CASE8to3Decoder IS

BEGIN
Decode: PROCESS (Binary_Code)
BEGIN
CASE Binary_Code IS
WHEN "000" => Position_Code <= "00000001";
WHEN "001" => Position_Code <= "00000010";
WHEN "010" => Position_Code <= "00000100";
WHEN "011" => Position_Code <= "00001000";
WHEN "100" => Position_Code <= "00010000";
WHEN "101" => Position_Code <= "00100000";
WHEN "110" => Position_Code <= "01000000";
WHEN "111" => Position_Code <= "10000000";
WHEN OTHERS => Position_Code <= "XXXXXXXX";
END CASE;
END PROCESS Decode;
END DecoderStruct ;
Bài 7.

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY Conditional8_2to1Mux IS
PORT(
A : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
SEL : IN STD_LOGIC;
EN : IN STD_LOGIC;
DOUT : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END Conditional8_2to1Mux;

ARCHITECTURE MUXArch OF Conditional8_2to1Mux IS

BEGIN
TRANSFER:
DOUT <= A WHEN ( EN = '1') AND (SEL = '0' ) ELSE
B WHEN ( EN = '1') AND (SEL = '1' ) ELSE
"00000000" ;
END MUXArch;
Bài 8.

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY Selected8_2to1MUX IS
PORT(
A : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
SEL : IN STD_LOGIC;
EN : IN STD_LOGIC;
DOUT : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);

END Selected8_2to1MUX;

ARCHITECTURE MUXArch OF Selected8_2to1MUX IS

SIGNAL TMP_SIG : STD_LOGIC_VECTOR (1 DOWNTO 0);

BEGIN
TMP_SIG <= EN & SEL;
TRANSFER:
WITH TMP_SIG SELECT
DOUT <= A WHEN "10",
B WHEN "11",
"00000000" WHEN OTHERS;
END MUXArch;
Bài 9.

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY CASE8_2to1MUX IS
PORT(
A : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
B : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
SEL : IN STD_LOGIC;
EN : IN STD_LOGIC;
DOUT : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END CASE8_2to1MUX;

ARCHITECTURE MUXArch OF CASE8_2to1MUX IS

BEGIN

TRANSFER: PROCESS (A,B,SEL,EN)

VARIABLE TMP_VEC: STD_LOGIC_VECTOR (1 DOWNTO 0);

BEGIN
TMP_VEC := EN & SEL;
CASE TMP_VEC IS
WHEN "10" => DOUT <= A;
WHEN "11" => DOUT <= B;
WHEN OTHERS => DOUT <= "00000000";
END CASE;
END PROCESS TRANSFER;
END MUXArch;
Bài 10.

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY Conditional1to8DeMUX IS
PORT(
DIN : IN STD_LOGIC;
EN : IN STD_LOGIC;
SEL : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END Conditional1to8DeMUX;

ARCHITECTURE DeMUXArch OF Conditional1to8DeMUX IS

BEGIN
TRANSFER:
DOUT <= (0=>DIN, OTHERS =>'0') WHEN (EN = '1') AND (SEL = "000") ELSE
(1=>DIN, OTHERS =>'0') WHEN (EN = '1') AND (SEL = "001") ELSE
(2=>DIN, OTHERS =>'0') WHEN (EN = '1') AND (SEL = "010") ELSE
(3=>DIN, OTHERS =>'0') WHEN (EN = '1') AND (SEL = "011") ELSE
(4=>DIN, OTHERS =>'0') WHEN (EN = '1') AND (SEL = "100") ELSE
(5=>DIN, OTHERS =>'0') WHEN (EN = '1') AND (SEL = "101") ELSE
(6=>DIN, OTHERS =>'0') WHEN (EN = '1') AND (SEL = "110") ELSE
(7=>DIN, OTHERS =>'0') WHEN (EN = '1') AND (SEL = "111") ELSE
(OTHERS => '0');
END DeMUXArch;
Bài 11.

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY Selected1to8DeMUX IS
PORT (
DIN : IN STD_LOGIC;
EN : IN STD_LOGIC;
SEL : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END Selected1to8DeMUX;

ARCHITECTURE DeMUXArch OF Selected1to8DeMUX IS

SIGNAL TMP_SIG : STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
TMP_SIG <= EN & SEL (2 DOWNTO 0);
TRANSFER:
WITH TMP_SIG SELECT
DOUT <= (0 =>DIN, OTHERS =>'0') WHEN "1000",
(1 =>DIN, OTHERS =>'0') WHEN "1001",
(2 =>DIN, OTHERS =>'0') WHEN "1010",
(3 =>DIN, OTHERS =>'0') WHEN "1011",
(4 =>DIN, OTHERS =>'0') WHEN "1100",
(5 =>DIN, OTHERS =>'0') WHEN "1101",
(6 =>DIN, OTHERS =>'0') WHEN "1110",
(7 =>DIN, OTHERS =>'0') WHEN "1111",
(OTHERS => '0') WHEN OTHERS;
END DeMUXArch;
Bài 12.

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY ConditionalBIN2BDC IS
PORT (
BIN_CODE : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
BDC_CODE : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END ConditionalBIN2BDC;

ARCHITECTURE ConvArch OF ConditionalBIN2BDC IS

BEGIN
Convert:
BDC_CODE <= "00000" WHEN (BIN_CODE = "0000") ELSE
"00001" WHEN (BIN_CODE = "0001") ELSE
"00010" WHEN (BIN_CODE = "0010") ELSE
"00011" WHEN (BIN_CODE = "0011") ELSE
"00100" WHEN (BIN_CODE = "0100") ELSE
"00101" WHEN (BIN_CODE = "0101") ELSE
"00110" WHEN (BIN_CODE = "0110") ELSE
"00111" WHEN (BIN_CODE = "0111") ELSE
"01000" WHEN (BIN_CODE = "1000") ELSE
"01001" WHEN (BIN_CODE = "1001") ELSE
"10000" WHEN (BIN_CODE = "1010") ELSE
"10001" WHEN (BIN_CODE = "1011") ELSE
"10010" WHEN (BIN_CODE = "1100") ELSE
"10011" WHEN (BIN_CODE = "1101") ELSE
"10100" WHEN (BIN_CODE = "1110") ELSE
"10101" ;
END ConvArch;
Bài 13.

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;

ENTITY ConditionalComparator IS
GENERIC(WIDTH : NATURAL := 4);
PORT(
A : IN STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0);
B : IN STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0);
G,GE,E,NE,LE,L : OUT STD_LOGIC
);
END ConditionalComparator;

ARCHITECTURE ComparArch OF ConditionalComparator IS

SIGNAL TMP_SIG : STD_LOGIC_VECTOR (5 DOWNTO 0);
BEGIN
(G,GE,E,NE,LE,L) <= TMP_SIG;

Compare:
TMP_SIG <= "110100" WHEN (A > B ) ELSE
"011010" WHEN (A = B ) ELSE
"000111";
END ComparArch;
Bài 14.

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;

ENTITY IFComparator IS
GENERIC(WIDTH : NATURAL := 4);
PORT(
A : IN STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0);
B : IN STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0);
G,GE,E,NE,LE,L : OUT STD_LOGIC
);
END IFComparator;

ARCHITECTURE CompareArch OF IFComparator IS

SIGNAL TMP_SIG : STD_LOGIC_VECTOR (5 DOWNTO 0);

BEGIN
(G,GE,E,NE,LE,L) <= TMP_SIG;
Compare: PROCESS (A,B)
BEGIN
IF (A > B) THEN TMP_SIG <= "110100";
ELSIF (A = B) THEN TMP_SIG <= "011010";
ELSE TMP_SIG <= "000111";
END IF;
END PROCESS Compare;
END CompareArch;
Bài 15.

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;

ENTITY UnsOperAdder IS
GENERIC(WIDTH : NATURAL := 4 );
PORT(
CIN : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR( WIDTH -1 DOWNTO 0);
B : IN STD_LOGIC_VECTOR( WIDTH -1 DOWNTO 0);
SUM : OUT STD_LOGIC_VECTOR( WIDTH -1 DOWNTO 0);
COUT : OUT STD_LOGIC
);
END UnsOperAdder;

ARCHITECTURE AdderArch OF UnsOperAdder IS

SIGNAL TMP : STD_LOGIC_VECTOR (WIDTH DOWNTO 0);
BEGIN
TMP <= ('0'&A) + ('0'&B) + ("0000"&CIN);
COUT <= TMP(WIDTH);
SUM <= TMP (WIDTH-1 DOWNTO 0);
END AdderArch;
Bài 16.

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;

ENTITY UnsProcOperAdder IS
GENERIC(WIDTH : NATURAL := 4 );
PORT(
CIN : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR( WIDTH -1 DOWNTO 0);
B : IN STD_LOGIC_VECTOR( WIDTH -1 DOWNTO 0);
SUM : OUT STD_LOGIC_VECTOR( WIDTH -1 DOWNTO 0);
COUT : OUT STD_LOGIC
);
END UnsProcOperAdder;

ARCHITECTURE AdderArch OF UnsProcOperAdder IS

BEGIN
Add: PROCESS (CIN, A, B)
VARIABLE TMP : STD_LOGIC_VECTOR (WIDTH DOWNTO 0);
BEGIN
TMP := ('0'&A) + ('0'&B) + ("0000"&CIN);
COUT <= TMP(WIDTH);
SUM <= TMP (WIDTH-1 DOWNTO 0);
END PROCESS Add;
END AdderArch;
Bài 17.

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;

ENTITY SigProcOperAdder IS
GENERIC(WIDTH : NATURAL := 4 );
PORT(
CIN : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR( WIDTH -1 DOWNTO 0);
B : IN STD_LOGIC_VECTOR( WIDTH -1 DOWNTO 0);
ADDSUB : IN STD_LOGIC;
SUM : OUT STD_LOGIC_VECTOR( WIDTH DOWNTO 0);
COUT : OUT STD_LOGIC;
OVR : OUT STD_LOGIC
);
END SigProcOperAdder;

ARCHITECTURE AdderArch OF SigProcOperAdder IS

BEGIN
Add: PROCESS (ADDSUB, CIN, A,B )
VARIABLE TMP_VAR : STD_LOGIC_VECTOR (WIDTH + 1 DOWNTO 0);
BEGIN
IF (ADDSUB = '0')
THEN
TMP_VAR := A - B - CIN;
COUT <= TMP_VAR(WIDTH+1);
SUM <= TMP_VAR (WIDTH DOWNTO 0);
OVR <= NOT TMP_VAR(WIDTH+1) AND TMP_VAR(WIDTH) ;
ELSE
TMP_VAR := A + B + CIN;
COUT <= TMP_VAR(WIDTH);
SUM <= '0' & TMP_VAR (WIDTH - 1 DOWNTO 0);
OVR <= TMP_VAR (WIDTH-1) AND TMP_VAR (WIDTH);
END IF;
END PROCESS Add;
END AdderArch;
Bài 18.

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY MealyFSM IS
PORT( clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
Y : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END MealyFSM;

ARCHITECTURE MealyArch OF MealyFSM IS

TYPE STATE_TYPE IS (Q0, Q1, Q2, Q3);
SIGNAL state: STATE_TYPE;
BEGIN
PROCESS (clk, reset)
BEGIN
IF (reset = '1') THEN state <= Q0;

ELSIF (clk'EVENT AND clk = '1') THEN

CASE state IS
WHEN Q0 =>
IF (A = "00") THEN state <= Q2; Y <= "11";
ELSIF (A = "01") THEN state <= Q1; Y <= "00";
ELSIF (A = "10") THEN state <= Q3; Y <= "10";
END IF;

WHEN Q1 =>
IF (A = "00") THEN state <= Q0; Y <= "11";
ELSIF (A = "01") THEN state <= Q1; Y <= "00";
ELSIF (A = "10") THEN state <= Q2; Y <= "00";
END IF;

WHEN Q2 =>
IF (A = "00") THEN state <= Q3; Y <= "00";
ELSIF (A = "10") THEN state <= Q1; Y <= "11";
END IF;

WHEN Q3 =>
IF (A = "00") THEN state <= Q2; Y <= "01";
ELSIF (A = "10") THEN state <= Q0; Y <= "00";
END IF;
END CASE;
END IF;
END PROCESS;
END MealyArch;
Bài 19.

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;

ENTITY ParInputCounter IS
GENERIC(WIDTH : NATURAL := 8);
PORT(
Reset ,CLK, CNT_EN, CLK_EN,LOAD : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(WIDTH -1 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(WIDTH -1 DOWNTO 0)
);
END ParInputCounter;

ARCHITECTURE CntArch OF ParInputCounter IS

signal CUR_VALUE : STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0);
BEGIN
Count:
PROCESS (Reset,CLK)
BEGIN
-- A reaction to async reset
IF (Reset = '1')
THEN CUR_VALUE <= (OTHERS => '0');

-- Clock rise reactions

ELSIF (CLK'EVENT AND CLK = '1')
THEN IF (CLK_EN ='1')
THEN IF (LOAD = '1')
THEN CUR_VALUE <= DIN;
ELSIF (CNT_EN = '1')
THEN CUR_VALUE <= CUR_VALUE + 1;
END IF;
END IF;
END IF;

END PROCESS Count;

DOUT <= CUR_VALUE;
END CntArch;
Bài 20.

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;

ENTITY BDCCounter IS
PORT(
Reset ,CLK, LOAD, CNT_DIR : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END BDCCounter;

ARCHITECTURE CntArch OF BDCCounter IS

BEGIN
Count:
PROCESS (Reset,CLK)
VARIABLE CUR_VALUE : STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
-- A reaction to async reset
IF (Reset = '1')
THEN CUR_VALUE := (OTHERS => '0');
-- Clock rise reactions
ELSIF (CLK'EVENT AND CLK = '1')
THEN IF (LOAD = '1')
THEN IF (DIN <= 9)
THEN CUR_VALUE := DIN;
ELSE CUR_VALUE := (OTHERS => '0');
END IF;
ELSIF (CNT_DIR = '0')
THEN IF (CUR_VALUE = 9)
THEN CUR_VALUE := (OTHERS => '0');
ELSE CUR_VALUE := CUR_VALUE + 1;
END IF;
ELSE IF (CUR_VALUE = 0)
THEN CUR_VALUE := "1001";
ELSE CUR_VALUE := CUR_VALUE - 1;
END IF;
END IF;
END IF;
DOUT <= CUR_VALUE;
END PROCESS Count;
END CntArch;