electronics

Article
Novel Low-Complexity and Low-Power
Flip-Flop Design
Jin-Fa Lin *, Zheng-Jie Hong, Chang-Ming Tsai, Bo-Cheng Wu and Shao-Wei Yu
Department of Information and Communication, Chaoyang University of Technology, Taichung 41349, Taiwan;
s10430051@gm.cyut.edu.tw (Z.-J.H.); s10430014@gm.cyut.edu.tw (C.-M.T.);
s10830615@gm.cyut.edu.tw (B.-C.W.); s10830616@gm.cyut.edu.tw (S.-W.Y.)
* Correspondence: jflin@cyut.edu.tw




Received: 14 April 2020; Accepted: 6 May 2020; Published: 10 May 2020


Abstract: In this paper, a compact and low-power true single-phase flip-flop (FF) design with fully
static operations is presented. The design is developed by using various circuit-reduction schemes
and features a hybrid logic style employing both pass transistor logic (PTL) and static complementary
metal-oxide semiconductor (CMOS) logic to reduce circuit complexity. These circuit optimization
measures pay off in various aspects, including smaller clock-to-Q (CQ) delay, lower average power,
lower leakage power, and smaller layout area; and the transistor-count is only 17. Fabricated in
TSMC 180 nm CMOS technology, it reduces by over 29% the chip area compared to the conventional
transmission gate FF (TGFF). To further show digital circuit/system level advantages, a multi-mode
shift register has been realized. Experimental measurement results at 1.8 V/4 MHz show that,
compared with the TGFF design, the proposed design saves 64.7% of power consumption while
reducing chip area by 26.2%.

Keywords: low power; flip-flop; pass transistor logic; Internet of Things

1. Introduction
With the growth of the Internet of Things (IoT) and wearable devices, the need for ultra-low
power consumption SOC chips is increasing [1]. The speed performance is no longer the focus of
research works; instead, the power consumption and layout area are key points in the design [2].
Flip-flop (FF) is the basic storage block used widely in digital very large-scale integer (VLSI) designs,
which adopt intensive pipelining schemes and employ many FF-rich modules such as shift register,
FIFO (first in first out) and register file. In a commercial SPARCT4 processor, there are more than
2 million FFs consuming over 20% of the total power consumption of the processor [3]. Also, in an
ARM Cortex-M0 processor with minimum instruction and data memories, they are synthesized from
standard cells for IoT applications. In this design, FFs account for 40% of the chip area and 30% of the
total power consumption [4]. Therefore, FF design is critical to the power consumption performance of
the system design and also has a significant impact on chip area. FF design continues to evolve with
the development of new process technologies. Specific application requirements such as low voltage,
low power consumption, or high performance also require new designs [4–17]. In this work, the target
is a low-power and low-circuit complexity FF design solution. A transmission gate-based FF (TGFF) is
the most widely used one today. One of the drawbacks of this FF design is the excessive loading on the
clock signal (a total of 12 transistors driven by the clock signal) as shown in Figure 1a. As a result,
there is considerable dynamic power consumption even when the input data signal switching activity
is zero or low. This problem also occurs in conventional SR-latch-based FF (SRFF) designs, as shown in
Figure 1b.

Electronics 2020, 9, 783; doi:10.3390/electronics9050783 www.mdpi.com/journal/electronics

Electronics 2020, 9, 783 2 of 12
Electronics 2020, 9, 783 2 of 12

Recently, true single-phase clocking (TSPC)-based FF designs are discussed for low power
applications.
Recently,The basic
true idea is mitigating
single-phase clockingthe(TSPC)-based
load capacitanceFF of clock signal
designs by using logic
are discussed and power
for low circuit
simplification
applications. The[9–12].
basicInidea
thisispaper, a novel
mitigating SR latch-based
the load capacitanceFF usingsignal
of clock hybridbylogic
usingcircuit scheme
logic and is
circuit
presented. It follows the principle of TSPC operations to reduce the clock signal loading.
simplification [9–12]. In this paper, a novel SR latch-based FF using hybrid logic circuit scheme is The design
exhibits a lowest
presented. It followstransistor-count
the principle ofand a shorter
TSPC critical
operations path the
to reduce when compared
clock with previous
signal loading. FF
The design
designs.
exhibits a lowest transistor-count and a shorter critical path when compared with previous FF designs.

(a) TGFF (b) SRFF

(c) ACFF (d) TCFF

(e) SSCFF
Figure 1. Representative
Representativeflip-flop
flip-flop(FF)
(FF)designs.
designs.(a)(a)
Transmission gate-based
Transmission FF (TGFF).
gate-based FF (TGFF).(b) SRFF. (c)
(b) SRFF.
adaptive
(c) coupling
adaptive FF FF
coupling (ACFF).
(ACFF). (d)(d)
topologically
topologicallycompressed
compressedFFFF(TCFF).
(TCFF).(e)
(e) static
static contention
contention free
single-phase-clocked FF (SSCFF).

2. Proposed Flip-Flop (FF) Design

2. Proposed Flip-Flop (FF) Design
2.1. Previous Low-Power FF Designs
2.1. Previous Low-Power FF Designs
To mitigate the power consumption problem of TGFF design, three low-power FFs have been
To mitigate the power consumption problem of TGFF design, three low-power FFs have been
proposed. Figure 1c shows the adaptive coupling (AC) flip-flop design [9]. Unlike traditional TGFF
proposed. Figure 1c shows the adaptive coupling (AC) flip-flop design [9]. Unlike traditional TGFF
designs, this design uses a differential latch structure with pass transistor logic (PTL) to achieve true
designs, this design uses a differential latch structure with pass transistor logic (PTL) to achieve true
single-phase clock operation. To overcome the effects of process variation on the master latch, a pair of
single-phase clock operation. To overcome the effects of process variation on the master latch, a pair
level recovery circuits were inserted into the cross-coupled path. In this FF design, the clock drives
of level recovery circuits were inserted into the cross-coupled path. In this FF design, the clock drives
only 4 transistors, and the total number of transistors is 22. When the FF is operating at low and/or
only 4 transistors, and the total number of transistors is 22. When the FF is operating at low and/or
zero data-switching activity, lighter clock loads and reduced circuitry in the FF design can significantly
zero data-switching activity, lighter clock loads and reduced circuitry in the FF design can
reduce dynamic power consumption. However, the pMOS type pass transistor-based latch design
significantly reduce dynamic power consumption. However, the pMOS type pass transistor-based
results in a longer setup time even in the presence of a level recovery circuit. Finally, there are floating
latch design results in a longer setup time even in the presence of a level recovery circuit. Finally,
problems in some nodes inside this FF design, which impose limitations on the applications of ACFF
there are floating problems in some nodes inside this FF design, which impose limitations on the
design [10].
applications of ACFF design [10].
 Figure 1d shows another low-power FF design using a topologically compressed scheme, named
TCFF based on SR-latch circuit structure [11]. Even though the pull-up and pull-down logic networks
are greatly simplified, and the respective logic topologies are no longer dual to each other, the design
is fully static. Despite the improved power performance, the design’s timing parameters deteriorate.
Electronics 2020, 9, 783 3 of 12
Similar to the ACFF design, this design also requires a large setup time because the pull-up network
is weakened. The critical path consists of 3 pMOS transistors in series. Although this circuit problem
can be mitigated
Figure by increasing
1d shows anotherthe metal-oxide
low-power FFsemiconductor
design using (MOS) transistor compressed
a topologically size, both low-power
scheme,
and lowTCFF
named transistor-count
based on SR-latchadvantages
circuitofstructure
the FF design
[11]. will
Evenbethough
compromised [10].and
the pull-up Figure 1e shows
pull-down the
logic
static contention free single-phase-clocked flip-flop, named SSCFF, aimed at
networks are greatly simplified, and the respective logic topologies are no longer dual to each other, alleviating these
problems
the design[12]. It isstatic.
is fully composed
Despiteof the
a conventional
improved power dynamic TSPC-based
performance, theFF designtiming
design’s with 9parameters
transistors
colored in blue
deteriorate. and to
Similar antheadditional 15 transistors
ACFF design, this designto ensure its fully
also requires staticsetup
a large circuittime
operations
because andthe
sufficient output drive capability. This FF design provides better power and energy
pull-up network is weakened. The critical path consists of 3 pMOS transistors in series. Although this performance
compared
circuit to traditional
problem TGFF design.
can be mitigated However,
by increasing thethe height of its
metal-oxide pull-down logic
semiconductor (MOS)added up to three.
transistor size,
This calls for large size transistors and results in a larger layout area [10].
both low-power and low transistor-count advantages of the FF design will be compromised [10].
Figure 1e shows the static contention free single-phase-clocked flip-flop, named SSCFF, aimed at
2.2. Proposed
alleviating FF Design
these problems [12]. It is composed of a conventional dynamic TSPC-based FF design with
9 transistors
In viewcolored in blue
of these and an additional
shortcomings 15 transistors
of previous low-powerto ensure its fully
FF designs, anstatic circuitdesign
enhanced operations
that
and sufficient output drive capability. This FF design provides better power and energy
applies further circuit structure simplification schemes to ACFF designs is proposed. Referring to performance
compared to traditional
Figure 2, the TGFF design.
proposed design adopts However, thestyle
hybrid logic height of itsi.e.,
circuit pull-down
a static logic
CMOS added
style up to three.
SR-latch at
This calls for large size transistors and results in a larger layout area [10].
master stage and a pass transistor logic style SRAM-based latch at slave stage, to reduce circuit
complexity. The proposed circuit design contains 19 transistors as shown in Figure 2. Based on this
2.2. Proposed FF Design
MOS transistor schematic, at the transistor level the following steps are used to further reduce the
numberIn view of thesetransistors.
of n-MOS shortcomings Forofpull-down
previous low-power
logic, one FF designs,
signal an enhanced
“R” controlled thedesign
nMOS that applies
transistor
further circuit structure
can be shared simplification
by two discharging schemes
paths as shownto ACFF designs
in Figure 3a. is proposed.
Note that when Referring
the clockto Figure
signal 2, CK the
is
proposed
high, the design
transistoradopts
N1 ofhybrid logic style
the master latchcircuit
keepsi.e.,
thea input
static CMOS
stage. Instyle
thisSR-latch at masterN2
case, transistor stage and a
(inverter
pass
I2) oftransistor logic style
the slave-latch SRAM-based
is also turned on.latchThus,attheslave
slavestage,
latchto also
reduce circuit acomplexity.
provides discharging The proposed
path for the
circuit
masterdesign
latch ascontains
shown in 19 Figure
transistors
3b. As as ashown
result,init Figure 2. Based
can eliminate theonclock-driven
this MOS transistor
redundancy schematic,
of one
at the transistor level the following steps are used to further reduce the
n-MOS transistor and simplify the circuit. This measure cannot only reduce power consumption and number of n-MOS transistors.
For pull-down
layout area, butlogic,
also one
reducesignal
the“R” controlled
capacitive loadtheof nMOS
the clock.transistor can be
In general, whenshared
usingby fewer
two discharging
transistors
paths as shown
to realize in Figure
a fully static 3a. Note the
design, thatleakage
when thepowerclock signal CK is high,
consumption the transistor
reduces as well.N1 Theof the master
simplified
latch keepsofthe
schematic theinput stage. after
final circuit In this case, transistor
applying logic andN2 (inverter
circuit I2) ofisthe
reduction slave-latch
shown in Figure is 3c.
alsoTheturned
total
on. Thus, the
transistor countslave latch
in our also provides
design a discharging
is 17 (8 pMOS transistors pathand for9 the
nMOSmaster latch as shown
transistors). This FFindesign
Figureuses 3b.
As
onea(true)
result,phase
it canofeliminate
the clockthe clock-driven
signal and only 5redundancy
transistors are of one n-MOS
driven by thetransistor and simplify the
clock signal.
circuit.
TheThis measure
proposed cannot
design only
uses reduceofpower
a hybrid consumption and
fully complementary layout
logic (AOIarea,
gate)butandalso
passreduce the
transistor
capacitive
logic in theload of the clock.
FF circuit design.InItgeneral, whenachieves
successfully using fewer transistors
the purpose of to realize a fullyincreasing
simultaneously static design, the
the leakage power consumption reduces as well. The simplified schematic
timing parameter and reducing the circuit complexity. Figure 4; Figure 5 show the operation of the of the final circuit after
applying
proposedlogic designandat circuit reduction
different inputissignals
shown (clock
in Figure and 3c.data)
The total
casestransistor
operations,count andin the
our design
post layoutis 17
(8 pMOS transistors
simulation waveforms and of9our
nMOS transistors).
design, ThisThe
respectively. FF design
FF design usesoperates
one (true) phase in
correctly of all
thecases,
clock and signal
all
and
nodes only 5 transistors
have a completeare driven
voltage by the clock signal.
swing.

Figure 2. Schematic
Figure 2. Schematic of
of proposed
proposed design.
design.
Electronics 2020, 9, 783 4 of 12
Electronics 2020, 9, 783 4 of 12

Electronics 2020, 9, 783 4 of 12

(a) (b)

(a) (b)

(c)
Figure 3. Proposed
Figure 3. Proposed FF
FF design. (a) Transistor
design. (a) Transistor merging
merging in
in pull-down
pull-down nMOS.
nMOS. (b)
(b) Transistor
Transistor removing
removing in
in
pull-down nMOS. (c) Proposed FF design with 17 transistors.
pull-down nMOS. (c) Proposed FF design with 17 transistors.

The proposed design uses a hybrid of fully complementary logic (AOI gate) and pass transistor
logic in the FF circuit design. It successfully achieves the purpose of simultaneously increasing the
timing parameter and reducing the circuit complexity. Figure 4; Figure 5 show the operation of the
(c)
proposed design at different input signals (clock and data) cases operations, and the post layout
simulation
Figurewaveforms
3. Proposed of
FF our design,
design. respectively.
(a) Transistor TheinFF
merging design operates
pull-down correctly
nMOS. (b) in all
Transistor cases, and
removing in all
nodespull-down
have a complete
nMOS. (c)voltage swing.
Proposed FF design with 17 transistors.

Figure 4. Proposed FF operation diagram at different inputs cases (highlighting the active devices).

Figure 4. Proposed FF operation diagram at different

different inputs
inputs cases
cases (highlighting
(highlighting the
the active
active devices).
devices).
Electronics 2020, 9, 783 5 of 12
Electronics 2020, 9, 783 5 of 12

Figure5.5.Waveforms
Figure Waveforms on
on HSPICE
HSPICE of
of proposed
proposeddesign.
design.

3. Simulation Results
3. Simulation Results
In In
order
order totofully
fullyevaluate
evaluate the performanceofofthe
the performance theproposed
proposed FFFF design,
design, post-layout
post-layout simulations
simulations of
of various
variousFF FFdesigns
designswere were conducted.
conducted. TwoTwo classic
classic master-slave
master-slave basedbased FF designs
FF designs TGFF,and
TGFF, SRFF SRFFthree and
low-power designs, i.e., ACFF [9], TCFF [11] and SSCFF [12] as shown
three low-power designs, i.e., ACFF [9], TCFF [11] and SSCFF [12] as shown in Figure 1, were included in Figure 1, were included in
in comparisons.
comparisons.Besides Besidesthe theTCFF
TCFFdesign,
design,which
whichbasically
basicallytrades
tradesitsitstiming
timingperformance
performance forforpower
power
saving,
saving, anan alternativedesign
alternative design(denoted
(denotedas as*TCFF)
*TCFF) using
using enlarged
enlargedpMOSpMOStransistors
transistorstotoenhance
enhance itsits
pull
pull
up driving capability was also evaluated. However, pulse-triggered
up driving capability was also evaluated. However, pulse-triggered based FF designs are excluded based FF designs are excluded
deliberately
deliberately becausethey
because theyusually
usuallyrequire
require aa complicated
complicated transistor
transistorsize sizetweaking
tweakingprocess
process to to
ensure
ensure
correct trigger timing and pulse width for different settings of V DD and working frequency. The
correct trigger timing and pulse width for different settings of VDD and working frequency. The design
design resilience to the process variations is another concern associated with these designs [14–17].
resilience to the process variations is another concern associated with these designs [14–17]. Note that,
Note that, a TSPC-based FF design using 18-transistors is proposed in [18]. However, there are
a TSPC-based FF design using 18-transistors is proposed in [18]. However, there are floating problems
floating problems in some nodes inside this low-complexity and low-power FF design. Moreover, to
in some nodes inside this low-complexity and low-power FF design. Moreover, to ensure lower
ensure lower VDD operation, a back-bias voltage scheme was employed to reduce the threshold
VDD operation, a back-bias voltage scheme was employed to reduce the threshold voltage, so it is
voltage, so it is not included in the discussion. The decision to use 180 nm technology is for emerging
not included in the discussion. The decision to use 180 nm technology is for emerging low-power
low-power applications where power performance rather than running speed is the ultimate concern.
applications
Therefore, where
it is costpower performance
effective to use more rather
mature than running speed
technology than toisswitch
the ultimate concern.
to advanced Therefore,
technology.
it isIncost effective to use more mature technology than to switch to
addition, compared with more advanced processes, the leakage power and process variation advanced technology. In addition,
of
compared with more advanced
the 180 nm process are relatively low. processes, the leakage power and process variation of the 180 nm
processThe are size
relatively low.
of the transistor depends on the optimization of power-delay-product (PDPCQ) and the
The size of the transistor depends
function at normal VDD (1.8v). Note that, oninthe optimization
*TCFF, the width ofof
power-delay-product
the pMOS transistors(PDP CQ ) andtothe
is increased
function
provideatbetter
normal VDDtime
setup (1.8v). Note that, All
performance. in *TCFF, the width
input signals are of thegenerated
also pMOS transistors is increased
through buffers to
to account
providefor better setup time
the effects performance.
of rise/fall time delays. AllTheinput signalscondition
operating are also generated through buffers
used in simulations is 50
to MHz/1.8
account for V. Five test patterns,
the effects eachtime
of rise/fall showing
delays. a different data-switching
The operating conditionactivity,
used inwere used in is
simulations
50 simulations.
MHz/1.8 V.The Five switching activityeach
test patterns, ranged from 0%
showing a to 100% (input
different data signal toggles
data-switching onwere
activity, every used
clock in
signal cycle).
simulations. TheThe model setup
switching activityforranged
FF simulations
from 0% to in 100%
this work
(input is data
shown in Figure
signal toggles 6. on
Toevery
mimicclock a
realistic scene, it had one clock buffer driving 8 FFs. The current driving
signal cycle). The model setup for FF simulations in this work is shown in Figure 6. To mimic a into FFs was measured and
then divided
realistic scene, itby had8. one
Thus, measured
clock buffer average
driving 8power
FFs. The consumption in this into
current driving workFFsalso considered
was measuredthe and
clock-driving power consumption. The post-layout simulation
then divided by 8. Thus, measured average power consumption in this work also considered results including circuit complexity,the
timing parameter,
clock-driving power average
consumption.power The consumption,
post-layout energy consumption
simulation results(power-delay-product),
including circuit complexity, and
leakage power consumption are summarized in Table 1.
timing parameter, average power consumption, energy consumption (power-delay-product), and
leakage power consumption are summarized in Table 1.
Electronics 2020, 9, 783 6 of 12
Electronics 2020, 9, 783 6 of 12

Figure 6. Test
Test bench
bench for
for FF
FF design
design simulations.
simulations.

In
In terms
terms of of circuit
circuit complexity,
complexity, the the proposed
proposed design design uses
uses the the fewest
fewest numbernumber of of transistors
transistors and and
has
has the smallest layout area in all FF designs. As for the power consumption behavior as shown in
the smallest layout area in all FF designs. As for the power consumption behavior as shown in
Figure
Figure 7a, our design
7a, our design isisthe themost
mostpower
powerefficient
efficientininallall butbutone onecasecase(when(when thethe
inputinput is static,
is static, i.e., i.e.,
0%
0% switching
switching probability,
probability, thethe proposed
proposed design
design is is slightlyinferior
slightly inferiortotoboth bothACFFACFF and and TCFF
TCFF design).
design).
Compared
Compared with traditional TGFF design, the proposed design achieves power consumption saving
with traditional TGFF design, the proposed design achieves power consumption saving
from
from 31.3%
31.3% to to 51.1%.
51.1%. Compared
Compared with with TCFF
TCFF (*TCFF),
(*TCFF), ACFF ACFF and and SSCFF
SSCFF designs,
designs, the the power
power advantage
advantage
of
of the
theproposed
proposeddesign design is maximized
is maximized when whenthe data-switching
the data-switching probability
probability is 100%. The average
is 100%. power
The average
consumption
power consumption saving is up to is
saving 52.6%
up toagainst
52.6%the ACFFthe
against design.
ACFFFor the case
design. For of the12.5%
case data-switching
of 12.5% data-
activities,
switchingtheactivities,
average power consumption
the average power saving against TGFF,
consumption SRFF, ACFF,
saving againstTCFF(*TCFF)
TGFF, SRFF, and SSCFF
ACFF,
were 51.1%, 55.7%, 23.0%, 2.0%(24.2%), and 34.3%, respectively.
TCFF(*TCFF) and SSCFF were 51.1%, 55.7%, 23.0%, 2.0%(24.2%), and 34.3%, respectively. Figure 7b Figure 7b shows the comparison of
average
shows the power consumption
comparison of averageat different
power operating
consumption frequencies.
at different The input signal
operating switching
frequencies. Theactivity
input
was set to 12.5%. The proposed design is the best power efficiency
signal switching activity was set to 12.5%. The proposed design is the best power efficiency in all in all cases. Although the ACFF
design has a competitive
cases. Although the ACFF advantage
design has in athe lower switching
competitive advantageactivity,
in theas the
lower switching
switching activity increases,
activity, as the
its power performance
switching activity increases,will rapidly decrease.
its power The main
performance reason
will rapidly is the frequentThe
decrease. level of switching
main reason isand the
contention issues in its master and slave latches. The SRFF and TGFF
frequent level of switching and contention issues in its master and slave latches. The SRFF and TGFF design have the worst power
consumption
design have the performance
worst power because they have
consumption a higher clock
performance tree loading
because they have than other true-signal-phase
a higher clock tree loading
clocking-based FF designs. The
than other true-signal-phase average power
clocking-based FFconsumption
designs. The@12.5% average switching under different
power consumption VDD
@12.5%
settings (from 1.8V to 1.0 V) is shown in Figure 7c. The working
switching under different VDD settings (from 1.8V to 1.0 V) is shown in Figure 7c. The working frequency was lowered to 10 MHz to
ensure
frequency thatwasall FF designstofunctioned
lowered 10 MHz toproperly ensure in thatlow allVFF settings.functioned
DD designs The SRFF design properly exhibited
in low V the
DD
highest
settings.power in alldesign
The SRFF cases. The TGFF the
exhibited design was power
highest rankedin second,
all cases.followed
The TGFF by thedesign
SSCFFwas andranked
ACFF.
The proposed
second, followeddesignby theandSSCFF
the TCFF anddesign
ACFF.exhibited
The proposed the lower
design powerand consumption.
the TCFF design exhibited the
lower Besides
power the power consumption, the PDP index (the product of the CQ delay and the power
consumption.
consumption)
Besides the waspower
employed as a composite
consumption, the PDPperformance
index (the index in thisofwork.
product the CQ When delaythe and
datatheswitching
power
activity was 12.5%,
consumption) wasthe PDP of theasproposed
employed a composite designperformance
was 17.0%~79.5% indexlower in thisthanwork.
those of Whenthe compared
the data
FF designs.activity
switching A bar was chart summarizing
12.5%, the PDP of thethePDP comparison
proposed designresults under different
was 17.0%~79.5% lower datathan switching
those of
activities is given in Figure 8a. Figure 8b shows the PDP performance
the compared FF designs. A bar chart summarizing the PDP comparison results under different against process variations with
data a
12.5%
switchingdata-switching
activities isactivity.
given For each process
in Figure corner,
8a. Figure 8bthe setupthe
shows timePDP value is scanned for
performance the best
against PDP
process
number.
variations Even
withallaFF designs
12.5% can operate normally
data-switching activity. For witheach
processprocessvariations.
corner,The theproposed
setup time design
valuehas is
the best PDP performance in all cases. This proves the consistent
scanned for the best PDP number. Even all FF designs can operate normally with process variations. performance edge of the proposed
design. Notably,design
The proposed both TGFF has andthe SRFF
best designs have the worst
PDP performance in allPDPcases.
performances.
This proves the consistent
Regarding the timing parameters of the FF designs,
performance edge of the proposed design. Notably, both TGFF and SRFF designs Table 1 also lists the setuphavetime,thetheworst
hold time,
PDP
and the CQ delay of these designs (@50 MHz/1.8 V). As explained before, the setup times of ACFF and
performances.
TCFFRegarding
(even the version
the timing withparameters
enlarged pMOS of the *TCFF) are bothTable
FF designs, much1 larger
also liststhanthethatsetup
of thetime,
TGFF. theThis
hold is
because these two designs adopt weak pull-up logic structures
time, and the CQ delay of these designs (@50 MHz/1.8 V). As explained before, the setup times of for power consumption reduction at
the
ACFF costand
of inferior
TCFF (even timing.the In fact, ifwith
version TCFF uses a typical
enlarged pMOSsize *TCFF)i.e., pMOS
are both = much
1.20 u,larger
its setup
than time
thatwill be
of the
7TGFF.
timesThisthat is
ofbecause
the conventional
these two TGFF designs design.
adopt By weak using hybrid
pull-up logic
logic style scheme
structures for powerand removing
consumption the
redundant
reduction atdischarging path at both
the cost of inferior timing.master
In fact,and if slave
TCFF latch,
uses aour design
typical sizeimproves
i.e., pMOS the= 1.20
setupu,time and
its setup
clock to Qbe
time will delay significantly
7 times that of the when compared TGFF
conventional with the ACFFBy
design. and TCFF
using (*TCFF)
hybrid logic designs. Regarding
style scheme and
the hold-time, all FFs had negative hold times, except for our
removing the redundant discharging path at both master and slave latch, our design improves thedesign. The hold time of the proposed
setup time and clock to Q delay significantly when compared with the ACFF and TCFF (*TCFF)
designs. Regarding the hold-time, all FFs had negative hold times, except for our design. The hold
Electronics 2020, 9, 783 7 of 12
Electronics 2020, 9, 783 7 of 12
time of the proposed design must be positive value to ensure the completion of input data transition
in the slave latch. The proposed design also leads in the clock to Q delay. The delay is 9.5% shorter
design
than themust be positive
nearest rival, i.e.,value to ensure
the SSCFF the Figure
design. completion of input
9 displays data transition
the variations in setup
in both the slave
andlatch.
hold
The proposed design also leads in the clock to Q delay. The delay is 9.5% shorter
time subject to process variations. Due to the circuit simplification of the pull-up network, the than the nearest
setup
rival, i.e., the SSCFF
time fluctuations ofdesign. Figure 9 displays
the low-power TCFF and the ACFF
variations in both
designs aresetup and holdlarger
significantly time subject to
than the
process variations. Due to the circuit simplification of the pull-up network, the
traditional TGFF designs. Although the proposed design also uses logic and circuit structure setup time fluctuations
of the low-power
minimization TCFF and
techniques, ACFF
the setupdesigns are the
time and significantly
hold timelarger than was
variation the traditional TGFF
well confined designs.
due to its
Although the proposed design also uses logic and circuit structure minimization techniques, the setup
circuit simplicity.
time and the hold time variation was well confined due to its circuit simplicity.
Table 1. Comparison summary of various FFs @50 MHz/1.8 V/TT-Corner.
Table 1. Comparison summary of various FFs @50 MHz/1.8 V/TT-Corner.
FF designs TGFF SRFF ACFF TCFF * TCFF SSCFF Proposed
FF Designs
Transistors CK / Total TGFF
12/24 SRFF
10/30 ACFF
4/22 TCFF
3/21 * 3/21
TCFF SSCFF
5/24 Proposed
5/17
Transistors CK/Total
Single-Phase 12/24
No 10/30
No 4/22
Yes 3/21
Yes 3/21
Yes 5/24
Yes 5/17
Yes
Single-Phase
Area (μm 2) No
58.30 No
80.24 Yes
72.62 Yes
76.94 Yes
99.19 Yes
63.96 Yes
41.20
Area (µm2 ) 58.30 80.24 72.62 76.94 99.19 63.96 41.20
Setup Time (pS) 179.15 111.07 371.37 452.34 297.61 170.22 198.04
Setup Time (pS) 179.15 111.07 371.37 452.34 297.61 170.22 198.04
HoldTime
Hold Time(pS)
(pS) -122.55 −11.95
−122.55 -11.95 -166.37
−166.37 -98.88
−98.88 -83.84
−83.84 -34.71
−34.71 54.61
54.61
Clock-to-Q Delay(pS)
Clock-to-Q Delay (pS) 259.62
259.62 379.64
379.64 238.37
238.37 207.69
−207.69 203.53
203.53 194.82
194.82 176.35
176.35
Average Power
Average Power(12.5%)
(12.5%)µW μW 5.135.13 5.67
5.67 3.26
3.26 2.56
2.56 3.31
3.31 3.82
3.82 2.51
2.51
PDP (@12.5% Activity)
PDP (@12.5% Activity) fJfJ 1.33
1.33 2.15
2.15 0.78
0.78 0.53
0.53 0.67
0.67 0.74
0.74 0.44
0.44
Leakage power (nW) 164.5 171.2 407.9 137.2 168.1 142.1 122.5
Leakage power (nW) 164.5 171.2 407.9 137.2 168.1 142.1 122.5
* Enlarged pMOS size. * Enlarged pMOS size.

(a) (b)

(c)

Figure 7. Simulation results for power consumption comparison for

consumption comparison for (a) different switching activity
factors; (b) different
different operation
operation frequencies;
frequencies; (c)
(c) different
differentoperation
operationsupply
supplyvoltages.
voltages.
 Electronics 2020, 9, 783 8 of 12
Electronics 2020, 9, 783 8 of 12
Electronics 2020, 9, 783 8 of 12

(a) (b)
Figure 8. Simulation (a) results for power-delay-product (PDP) performances.
(b) (a) Different switching
activity8.
Figure 8.factors. (b) Different
Simulation
Simulation results process
results for corners.
for power-delay-product
power-delay-product (PDP)performances.
(PDP) performances.(a)(a)Different
Differentswitching
switching
activity factors. (b)
(b) Different
Different process
process corners.
corners.

(a) (b)
Figure
Figure 9. (a) results
Simulation
9. Simulation resultsfor
fortiming
timingvariation
variation under
under different
different process (b)
process corners.
corners. (a) Setup
(a) Setup time.time.
(b)
(b) Hold
Hold time.
time.
Figure 9. Simulation results for timing variation under different process corners. (a) Setup time. (b)
Hold time.
InInterm
termof ofleakage
leakage power
power consumption,
consumption, our our design
design shows
shows the the lowest
lowestleakage
leakagepower powerdue duetotoits
its
circuit
circuit complexity
complexity
In term (17-transistor
of leakage(17-transistor only). The leakage
only). The leakage
power consumption, power
our design powersaving
shows against
saving the conventional
againstleakage
the lowest the conventional TGFF
power due TGFF design
to its
is 25.5%.
design
circuit isAs mentioned
25.5%.
complexity before, before,
As(17-transistor
mentioned due to the
only). Thefloating
due to problem
the floating
leakage of someof
powerproblem
saving internal
some the
against nodes
internal in ACFF
nodes
conventional design,
in TGFF
ACFF
its leakage
design,
design isits power
leakage
25.5%. Asconsumption
power
mentioned will bedue
consumption
before, thetolargest
will bethethe amongproblem
largest
floating all comparison
among all some circuits
of comparison
internal [10].
nodesPost-layout
circuits [10]. Post-
in ACFF
simulation
design, results also
layout simulation
its leakage powershow
results also that
show
consumptionthethat
power consumption
the power
will largestof
be the consumption the ACFF
among ofall design
thecomparison is over
ACFF design is2.4
circuitsovertimes that of
2.4 Post-
[10]. times
the
thatconventional
layout ofsimulation TGFF
the conventional
results design
TGFF indesign
also show thisthat
particular
inthe
this case,
particular
power whichcase,
consumption should
which not
of the be overlooked
should
ACFF not is when
be overlooked
design over 2.4 thetimes
ACFF
when
the
design ACFFis design
employed is employed
in the low in the
power low power
applications. applications.
Figure 10 Figure
presents
that of the conventional TGFF design in this particular case, which should not be overlooked when 10 presents
the Monte the
CarloMonte Carlo
simulation
simulation
results
the ACFF of PDP results
design isofemployed
CQ derived PDPby derived
in theby
CQ executing lowexecuting
1000 1000 runs.
runs. Three
power Three
FF designs,
applications. FigureFF designs,
i.e., TGFF,
10 i.e., TGFF,
ACFF,
presents andMonte
the ACFF,
the and
proposed
Carlo
the proposed
design
simulation design
are simulated.
results are
The
of PDP simulated.
CQplot has aThe
derived plot of
format
by haspower
executing a1000
format of power
consumption
runs. Three FF consumption
asdesigns,
the x-axis as
and
i.e., thethe
TGFF, x-axis
CQ and
ACFF, delaytheas
and
CQ
the delay
y-axis. as the
Therefore,y-axis.
the Therefore,
closer the the
point closer
is to the point
lower is to
left the
part lower
of
the proposed design are simulated. The plot has a format of power consumption as the x-axis and thethe left
plot, part
the of the
better plot,
the the better
performance
the
of
CQ performance
this design.
delay as theFrom of this
y-axis. design. From
the Therefore,
simulation the
results,
the simulation
closerthethe pointresults,
advantage is toofthethelower
our advantage
design of of
is part
left obviousourthe design
in plot, istheobvious
simulation trials.
better
in simulation
the Finally, Figure
performance trials.
of 11
thisshows
design. theFrom
layouttheschematic
simulation of results,
these FFthe designs.
advantage The ofheight of all FF
our design is designs
obvious is
in simulation
fixed at 5.15 µm trials.
and layers up to metal-2 (M2) are used in drawing the layout schematic. The layout-area
size of our design is only 5.15 µm by 8.0 µm. The area saving against the TGFF design is 29.3%.
It should be noted that, although ACFF and TCFF have fewer transistors than the traditional TGFF
design, in order to ensure that the operation requirements of all process variations are met, a larger
transistor size is required to increase the layout area. It is no surprise that the *TCFF design has the
worst layout area to increase the size of pMOS transistors (as shown in Figure 10) in order to improve
the setup-time performance. Finally, the layout area of SSCFF is 10% larger than the TGFF design due
to its need for a larger transistor and complexity layout structure.
Electronics 2020, 9, 783 9 of 12
Electronics 2020, 9, 783 9 of 12

Figure 10. Monte Carlo simulation results.

Finally, Figure 11 shows the layout schematic of these FF designs. The height of all FF designs is
fixed at 5.15 μm and layers up to metal-2 (M2) are used in drawing the layout schematic. The layout-
area size of our design is only 5.15 μm by 8.0 μm. The area saving against the TGFF design is 29.3%.
It should be noted that, although ACFF and TCFF have fewer transistors than the traditional TGFF
design, in order to ensure that the operation requirements of all process variations are met, a larger
transistor size is required to increase the layout area. It is no surprise that the *TCFF design has the
worst layout area to increase the size of pMOS transistors (as shown in Figure 10) in order to improve
the setup-time performance. Finally, the layout area of SSCFF is 10% larger than the TGFF design due
to its need for a larger transistor and complexity layout structure.
Figure 10. Monte Carlo simulation results.

Finally, Figure 11 shows the layout schematic of these FF designs. The height of all FF designs is
fixed at 5.15 μm and layers up to metal-2 (M2) are used in drawing the layout schematic. The layout-
area size of our design is only 5.15 μm by 8.0 μm. The area saving against the TGFF design is 29.3%.
It should be noted that, although ACFF and TCFF have fewer transistors than the traditional TGFF
design, in order to ensure that the operation requirements of all process variations are met, a larger
transistor size is required to increase the layout area. It is no surprise that the *TCFF design has the
worst layout area to increase the size of pMOS transistors (as shown in Figure 10) in order to improve
the setup-time performance. Finally, the layout area of SSCFF is 10% larger than the TGFF design due
to its need for a larger transistor and complexity layout structure.

Figure 11.
Figure Layoutof
11. Layout ofFFs.
FFs.

4. Chip Implementation and Measurement Results

4. Chip Implementation and Measurement Results
The proposed design and TGFF design further extended to a multi-mode 32-bit shift register
The proposed design and TGFF design further extended to a multi-mode 32-bit shift register
(providing 4 × 8bit and 1 × 32bit modes) [18]. This implemented chip is further combined with a
(providing 4 × 8bit and 1 × 32bit modes) [18]. This implemented chip is further combined with a
ATMEL® 8-bit microcontroller ATmega-328P (which is used in the Arduino UNO board) to further verify
ATMEL® 8-bit microcontroller ATmega-328P (which is used in the Arduino UNO board) to further
its function as shown in Figure 12. The chip design in this work is mainly used with a smart-agricultural
verify its function as shown in Figure 12. The chip design in this work is mainly used with a smart-
embedded system design based on the Arduino platform to monitor the environmental information
of a greenhouse. The implemented chip acts as a buffer between the microprocessor (328P) and the
SPI (serial peripheral interface bus) interface to reduce the time required for the microprocessor to
read these sensors to achieve power consumption as shown in Figure 12c. Note that the standard
Figure 11. Layout of FFs.
operating voltage of the ATmega-328P is 3.3 V. In order to combine our chip, we set the relevant
fuse to reduce the operating voltage of the ATmega-328P to the lowest 1.8 V by programming [19].
4. Chip Implementation and Measurement Results
At the same time, the operating frequency uses its built-in oscillator and sets the operation frequency
The proposed
at 8 MHz. design and
The test platform usedTGFF design
is shown in further extended
Figure 13a to a multi-mode
and combines 32-bit (GWINSTEK
an oscilloscope shift register
(providing
GDS-1054B)4 and× 8bit and 1 ×supply
a power 32bit modes)
(GWINSTEK[18]. This implemented
GDP-3303S). chip
Figure 13bisshows
furtherchip
combined with a
measurement
ATMEL® 8-bit microcontroller ATmega-328P (which is used in the Arduino UNO board) to further
verify its function as shown in Figure 12. The chip design in this work is mainly used with a smart-
 programming
set the relevant[19]. fuseAttothe same the
reduce time, the operating
operating voltage frequency uses its built-in
of the ATmega-328P tooscillator
the lowest and1.8setsV the
by
operation frequency at 8 MHz. The test platform used is shown in Figure
programming [19]. At the same time, the operating frequency uses its built-in oscillator and sets the 13a and combines an
oscilloscope (GWINSTEK GDS-1054B) and a power supply (GWINSTEK
operation frequency at 8 MHz. The test platform used is shown in Figure 13a and combines an GDP-3303S). Figure 13b
shows chip measurement
oscilloscope (GWINSTEK GDS-1054B) waveforms of andthea proposed
power supply design. Each signalGDP-3303S).
(GWINSTEK from up to down Figureis13b the
clock signal,
Electronics 2020, 9,the
783 input D0, and the output Q31. The operation
shows chip measurement waveforms of the proposed design. Each signal from up to down is the frequency is 4MHz and10 the
of 12
measurement
clock signal, theresultsinputis shown
D0, andin Table
the 2output
(the measured
Q31. The power consumption
operation results
frequency is recorded
4MHz and in Table
the
2 are the
measurement average of 8 chips). Compared with the traditional TGFF-based design, due to its circuit
waveforms ofresults is showndesign.
the proposed in TableEach2 (thesignal
measured
from power consumption
up to down results
is the clock recorded
signal, in Table
the input D0,
2novelty,
are the our design
average of 8reduces
chips). by more than
Compared 64.7%
with the the power consumption,
traditional TGFF-based
and the output Q31. The operation frequency is 4MHz and the measurement results is shown
while the
design, due layout
to its area is
circuitin
reduced our
novelty, by 26.2%.
design All the above
reduces by results
more than demonstrate
64.7% the that the
power proposed design
consumption, while haslayout
the lower area power is
Table 2 (the measured power consumption results recorded in Table 2 are the average of 8 chips).
consumption
reduced by withand lower
26.2%. layout-area than other FF designs. Hence the proposed design is suitable for
Compared theAll the above
traditional results
TGFF-based demonstrate
design, duethat thecircuit
to its proposed design
novelty, has lower
our design power
reduces by
low-power
consumption applications.
and thelower layout-area than other FF the
designs. Hence the proposed
more than 64.7% power consumption, while layout area is reduced by design
26.2%. is
All suitable
the abovefor
low-power applications.
results demonstrate that the proposed design has lower power consumption and lower layout-area
than other FF designs. Hence the proposed design is suitable for low-power applications.
When En=0 CK

When
D0 En=0 D Q D Q
CK D Q D Q D Q D Q D Q D Q Q7
Q Q Q Q Q Q Q Q
CK

GPIOGPIO
D0 Q7
328P Test Chip OUT
D Q D Q D Q D Q D Q D Q D Q D Q
0

Q1 D0~D7
SPI
D1 1 S
D
Q
Q D
Q
Q D
Q
Q D
Q
Q D
Q
Q D
Q
Q D
Q
Q D
Q
Q
CK
Q Q Q Q Q Q Q Q

Q1 328P Test Chip OUT SPI

D1 1 0S
D Q D Q D Q D Q D Q D Q D Q D Q
D0~D7
D
Q
Q D
Q
Q D
Q
Q D
Q
Q D
Q
Q D
Q
Q D
Q
Q D
Q
Q Q2
D2 1 S
Q Q Q Q Q Q Q Q

0
Mode Selection
D Q D Q D Q D Q D Q D Q D Q D Q Q2
D2 1 0S
D Q D Q D Q D Q D Q D Q D Q D Q Q3
Q Q Q Q Q Q Q Q
D3 1
Mode Selection
S

En Q Q Q Q Q Q Q Q
Q3
0
D Q D Q D Q D Q D Q D Q D Q D Q Q3
D3 1 S

En Q Q
(a) Q Q Q Q Q Q
Q3 (b) (c)
Figure 12. (a)
A multi-mode 32-bit shift register. (a) (b)On-chip configuration for the testing.
(c) (b) Die
photographic.
Figure 12. A
Figure (c) Platform
Amulti-mode
multi-mode implemented
32-bit shiftshift
32-bit in
register. this
register. work.
(a) On-chip configuration
(a) On-chip for the testing.
configuration (b) Die
for the photographic.
testing. (b) Die
(c) Platform implemented
photographic. (c) Platform in this work. in this work.
implemented

(a) (b)
(a)
Figure 13. Photographic (b) (1 ×
of, (a) test setup and, (b)measurement waveforms × 32bit mode).
Figure 13. Photographic
Table 2. of, (a) test setup
Simulation and, (b)measurement
and experimental waveforms
results for (1 × 32bit mode).
the design.

32-Bit Shift Register Designs TGFF Proposed

Layout Area (um2 ) 1832.8 1352.2
1 × 32bit Mode Avg. Power(Simulation/Measurement) 19.11 µW/21.96 µW 7.21 µW/8.28 µW
4 × 8bit Mode Avg. Power(Simulation/Measurement) 15.33 µW/17.64 µW 5.49 µW/6.22 µW

5. Conclusions
In this paper, a novel low-complexity and low-power flip-flop design with fully static operations
is proposed. This design uses an SR latch structure and combines a mixed logic circuit style solution
for low-power applications. A comprehensive evaluation shows that of all the compared FF designs,
the proposed design is the most economical in terms of power and energy consumption. It also
requires the smallest chip area. Our designs can thus be used in cell library designs for power- and
energy-critical applications.

Author Contributions: J.-F.L. and Z.-J.H. proposed the idea and method; C.-M.T. and S.-W.Y. performed the
simulations and experiments; B.-C.W. and Z.-J.H. analyzed the data; J.-F.L. reviewed the manuscript. All authors
have read and agreed to the published version of the manuscript.
Electronics 2020, 9, 783 11 of 12

Funding: This work was supported by the Ministry of Science and Technology, Taiwan under contract No.
107-2221-E- 324-017-MY2 and a grant (Grant No. 109AS-11.3.2-ST-a9) from the Council of Agriculture, ROC.
Acknowledgments: The authors also thank the National Chip Implementation Center (CIC), Taiwan for technical
support in simulations.
Conflicts of Interest: The authors declare no conflict of interest.

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