Network Synthesis: Foster &

Cauer Method
 Network Synthesis
Differences between Network synthesis and Network
Analysis are:
• In network synthesis, there are many different
answers to that particular problems, whereas, in
network analysis there is only one answer.

• By the analysis of a circuit, we mean a study of the

behavior of the circuit: How does it respond to a
given input? How do the interconnected elements
and devices in the circuit interact? Circuit analysis is
the process of determining voltages across (or the
currents through) the elements of the circuit.
• Powerful theorems are used in simplifying difficult
problems in network analysis e.g. Superposition,
Thevenin’s, Nortons, Voltage /Current divider rule
e.t.c.

• In network synthesis, the impedance equations are

given and from these equations, circuit diagrams are
drawn.
Examples of Network Synthesis to consider here are
Foster and Cauer Synthesis.
FOSTER’S SYNTHESIS OF NETWORK.
This is a method of evaluating a function so that it
represents either of the following:
 A series circuit composed of an inductor, capacitor,
and a group of parallel circuit each composed of a
capacitor and inductor, this is foster’s first
approximation. Here an impedance equation is used.
 A parallel circuit composed of the following
branches; 1) Capacitor, 2) Inductor, 3) Capacitor and
Inductor. This is called Foster’s second approximation.
Here an admittance equation is used.
 FOSTER’S 1ST APPROXIMATION.
Foster’s first approximation takes an impedance
equation which is given by;

The approximation circuit is as shown below;

C2 C3

C1
L1
1/2kc 1/2kd
Ka
1/Kb
L2 L3

Foster’s first approximation circuit.

 and

Example One:
Determine Foster’s first approximation for the
function below;
 2𝑠
𝑆3 +2𝑠
2𝑆 4 + 8𝑆 2 + 6
2𝑆 4 + 4𝑆 2
4𝑆 2 +6
The Impedance Equation can now be re-written as

4𝑆 2 + 6
𝑍 𝑠 = 2𝑠 + 3
𝑆 + 2𝑆

4𝑆 2 + 6
Resolve Into partial fraction
𝑆 3 + 2𝑆
4𝑆 2 +6 𝐴 𝐵𝑠
= + 1
𝑆 3 +2𝑆 𝑆 𝑆 2 +2
Resolving equation 1 into partial fraction gives
A = 3 and B = 1

Rewrite equation 1 and substitute those values to give

3 𝑆
𝑍 𝑠 = 2𝑠 + + 2
𝑆 𝑆 2 +2

Recall equation * and compare eq 2 with it

𝐾𝑎 = 2, 𝐾𝑏 = 3, 2𝐾𝑐 = 1, 𝑤𝑐 2 = 2

Therefore from the circuit diagram

 C2 C3

C1
L1
1/2kc 1/2kd
Ka
1/Kb
L2 L3

1
𝐿1 = 𝐾𝑎 = 2𝐻, 𝐶2 = = 1F
2𝐾𝑐

1 1 2𝐾𝑐 1
C1 = = 𝐹 , 𝐿2 = = 𝐻
𝐾𝑏 3 𝑤𝑐 2 2

1F

1/3F
2H
1/2kc
1/2H
Ka
1/Kb
L2
 Foster’s Second Approximation.
The steps involved in this are as follows:
• Take the reciprocal of Z(s), to obtain the admittance

• Finding Y(s), we obtain an expression

The circuit which such an equation represents is

shown below;
 L2 L3

C1 L1

C2 C3

Foster’s Second approximation circuit

 Example Two
Find foster’s second approximation for the equation
below.

𝐹𝑜𝑠𝑡𝑒𝑟 ′ 𝑠 𝑠𝑒𝑐𝑜𝑛𝑑 𝑎𝑝𝑝𝑟𝑜𝑥𝑖𝑚𝑎𝑡𝑒 𝑠ℎ𝑜𝑢𝑙𝑑 𝑏𝑒

𝑎𝑛 𝑎𝑑𝑚𝑖𝑡𝑡𝑎𝑛𝑐𝑒 𝑒𝑞𝑢𝑎𝑡𝑖𝑜𝑛
Finding the inverse of the impedance equation
will give the admittance equation.
𝑆 3 + 2𝑆 𝑆(𝑆 2 +2) 1 (𝑆 2 +2)
𝑌 𝑠 = = = 𝑆
2𝑆 4 + 8𝑆 2 + 6 2(𝑆 4 +4𝑆 2 +3 2 𝑆 4 +4𝑆 2 +3
1 (𝑆 2 +2)
𝑌 𝑠 = 𝑆 *
2 (𝑆 2 +3)(𝑆 2 +1)
 𝑅𝑒𝑠𝑜𝑙𝑣𝑒 equation * into partial fraction to give

1 𝑆(𝑆 2 +2) 1 𝐴𝑠 𝐵𝑠
𝑌 𝑠 = = ( + )
2 (𝑆 2 +3)(𝑆 2 +1) 2 𝑆 2 +3 𝑆 2 +1

A = ½ and B = ½
1 0.5𝑠 0.5𝑠
𝑌 𝑠 = ( + )
2 𝑆 2 +3 𝑆 2 +1
1 1
𝑌 𝑠 = 4𝑠 + 4𝑠 ∗∗
2
𝑆 +3 𝑆 +1 2
Compare eq ** with the foster 2nd approximation eqn.

! 1
2𝐾𝑐 = 𝑤ℎ𝑖𝑐ℎ 𝑖𝑚𝑝𝑙𝑖𝑒𝑠 𝑡ℎ𝑎𝑡𝐾𝑐 ! = 1/8 , 𝑤𝑐 2 = 3
4
1 1
2𝐾𝑑 = which implies that 𝐾𝑑 = , 𝑤𝑑2 = 1
! !
4 8
 1 1
𝐿1 = = = 4H
2𝐾𝑐 ! 1/4
1 1
L2 = = = 4H
2𝐾𝑑 ! 1/4
2𝐾𝑐 ! 1/4 1
C1 = = = 𝐹
𝑤𝑐 2 3 12
2𝐾𝑑! 1/4 1
C2 = 2 = = 𝐹
𝑤𝑑 1 4
The circuit then becomes

L2
4H
4H L1

1/12F C1 1/4F C2
 CAUER’S SYNTHESIS.
Like Foster’s synthesis, this technique also has two
forms: They are named Cauer I and Cauer II.
CAUER I.
In this technique, the impedance equation which is
synthesized can be written in the form;
Note that here the numerator is always more or
higher than the denominator.
The circuit such an equation represents is given
below:
α1 α3

α2 α4

Figure 1
 Example on Cauer 1
Given that

Determine the equivalent circuit using cauer 1

approximation method.
Solution
The steps in determining the equivalent circuit are as
follows:
(1) Divide numerator by denominator
2s
𝑆3 +2𝑆 2𝑆 4 + 8𝑆 2 + 6
2𝑆 4 + 4𝑆 2
4𝑆 2 + 6
(2). Divide original divisor by remainder

S/4
4𝑠2 +6 𝑆 3 + 2𝑆
𝑆 3 + 1.5𝑆
0.5𝑠

(3). Divide divisor of step 2 by the remainder of the last step.

8S

0.5𝑠 4𝑠 2 + 6
4𝑆 2
6
(4). Divide divisor of the last step by the remainder of
last step.

S/12

6 0.5𝑠
0.5𝑠
0
(5). There is no remainder in step 4 and the division is stopped
at this point.

(6). Refer to equation *** and note the following

For step 1, the quotient 2S represents 𝑎1 𝑆
For step 2, the quotient S/4 represents 𝑎2 𝑆
For step 3, the quotient 8S represents 𝑎3 𝑆
For step 4, the quotient S/12 represents 𝑎4 𝑆
Referring to figure 1, we can say that
𝐿1 = 𝑎1 = 2𝐻
1
𝐶1 = 𝑎2 = 𝐹
4
𝐿2 = 𝑎3 = 8𝐻
1
𝐶2 = 𝑎4 = 𝐹
12
The equivalent Circuit is as shown below
α1 α3

2H 8H

¼F α2 1/12 F α4
 CAUER II
In this technique, the impedance equation which is
synthesized can be written in the form;

The Cauer II circuit is as shown below;

b1 b3

b2 b4

Figure 2
 Examples on Cauer II:
Draw a Cauer II representation for the impedance equation
below;

Solution:
First, arrange the numerator and denominator in ascending
power of S.

Then divide the numerator by the denominator.

Divide the numerator by the denominator to
get
3/S

2𝑠+𝑆3 6 + 8𝑆 2 + 2𝑆 4
6 + 3𝑆 2
5𝑆 2 + 2𝑆 4

Divide original divisor by remainder

2
5𝑆

2𝑠 + 𝑆 3
5𝑠2 + 2𝑆4
2𝑆 + 4/5𝑆 3
𝑆3
5
 Divide the divisor of the above by the remainder
25
𝑆
𝑆3
5 5𝑠 2 + 2𝑆 4
5𝑠 2
2𝑆 4
Again , divide the divisor of the previous by the
remainder 1
10𝑆
𝑆3
2𝑆4
5
𝑆3
5
There is no remainder in the last step so we stop the
division.
Note the following as we refer to equation ****
1
For step 1, the quotient 3/s reps 𝑏1 𝑠
2 1
For step 2, the quotient reps
5𝑠 𝑏2𝑠
25 1
For step 3, the quotient reps
𝑠 𝑏3 𝑠
1 1
For step 4, the quotient reps
10𝑠 𝑏4 𝑠
 Referring to figure 2
1
3/s reps 𝑤ℎ𝑖𝑐ℎ 𝑖𝑚𝑝𝑙𝑖𝑒𝑠 𝑡ℎ𝑎𝑡𝑏1 = 1/3
𝑏1𝑠
1
𝐶1 = 𝑏1 = 𝐹
3
2 1
reps 𝑤ℎ𝑖𝑐ℎ 𝑖𝑚𝑝𝑙𝑖𝑒𝑠 𝑡ℎ𝑎𝑡𝑏2 = 5/2
5𝑠 𝑏2𝑠
5
𝐿1 = 𝑏2 = 𝐻
2
25 1
reps 𝑤ℎ𝑖𝑐ℎ 𝑖𝑚𝑝𝑙𝑖𝑒𝑠 𝑡ℎ𝑎𝑡𝑏3 = 1/25
𝑠 𝑏3𝑠
1
𝐶2 = 𝑏3 = 𝐹
25
1 1
reps 𝑤ℎ𝑖𝑐ℎ 𝑖𝑚𝑝𝑙𝑖𝑒𝑠 𝑡ℎ𝑎𝑡𝑏4 = 10
10𝑠 𝑏4𝑠
𝐿2 = 𝑏4 = 10𝐻
The equivalent circuit is as shown below
 b1 b3

1/3F 1/25F

10H
2.5H b4
b2

Figure 2
 Assignment
Find Cauer’s first and second approximation for
the expression below:
Find Cauer’s first and second approximation for the
expression below:

Solution.
For Cauer I
=

Then divide the numerator by the denominator.

Resonance: Series & Parallel
 Resonance
• Resonance occurs when the current is either maximum or minimum
for a particular frequency.
• Resonance is a condition in an RLC circuit in which the capacitive and
inductive reactances are equal in magnitude, thereby resulting in a
purely resistive impedance.
• Resonant circuits (series or parallel) are useful for constructing filters,
as their transfer functions can be highly frequency selective. They are
used in many applications such as selecting the desired stations in
radio and TV receivers.
 Series Resonance
Note that at resonance:
1. The impedance is purely resistive, thus, In other words,
the LC series combination acts like a short circuit, and the entire
voltage is across R.
2. The voltage and the current are in phase, so that the power
factor is unity.
3. The magnitude of the transfer function is minimum.
4. The inductor voltage and capacitor voltage can be much more
than the source voltage.

The frequency response of the circuit’s current magnitude

 Series Resonance
• From the Figure below:

Resonance results when the imaginary part of the transfer function

is zero, or
• The average power dissipated by the RLC circuit is:

The highest power dissipated occurs at resonance, when so,

• At certain frequencies the dissipated power is half the

maximum value; that is,

• Bandwidth
• Hence w1 and w2 are called the half-power frequencies. The half-power
frequencies are obtained by setting Z equal to 2R and writing

• Solving for , we obtain

 Example
• In the circuit of below R  2, L  1mH , C  0.4 F (a) Find the resonant
frequency and the half-power frequencies. (b) Calculate the quality
factor and bandwidth. (c) Determine the amplitude of the current at
wo , w1 and w2
R L

+
20sinwt C

-
Quality Factor
• It is regarded as a measure of the energy storage property of a circuit
in relation to its energy dissipation property.

• In the series RLC circuit, the peak energy stored is , while the
energy dissipated in one period is Hence,
 Quality Factor Cont’d
• Also, it could be defined as the ratio of potential drop across the
inductance or capacitance at resonance to he potential drop across
the resistance (or the applied voltage)
wo LI 1 L
Q 
RI R C
I
woC 1 L
Q 
RI R C
• Notice that the quality factor is dimensionless. The relationship
between the bandwidth B and the quality factor Q is obtained as:
Quality factor is dimensionless and is defined as the ratio
of the circuit’s resonant frequency to its bandwidth. i.e

Note that for high Q circuit (Q ≥ 10), the half-power

frequencies are, for all practical purposes, symmetrical
around the resonant frequency and can be approximated as

High – Q circuits are used often in communications networks.

 Example on series resonant circuit.
In the circuit diagram below, given that R = 2Ω, L = 1mH,
and C = 0.4μF
R L

+
20sinwt C

-
Parallel Resonance
• The parallel RLC circuit below is the dual of the series RLC circuit. The
admittance is

• Resonance occurs when the imaginary part of Y is zero,

 Parallel Resonance.
The parallel RLC circuit shown below is a dual of the series
RLC circuit.

V 1/jwC
I = Im< 0 R JwL
-

The Admittance is = = +
Or

Resonance occurs when the imaginary part of Y is Zero.

Or
LC = 1

=
Note that at resonance, the parallel LC combination acts
like an open circuit, so that the entire current flows
through R.

-
Again, for high- Q circuits (Q ≥ 10).

-
 Example

In the parallel RLC circuit of Fig. above, let R  8k , L  0.2mH , and C  8 F, (a) Calculate o , Q, and B. (b) Find 1 and 2 (c) Determine the power dissipated at o , 1 and 2