Electrónica I

Digital Electronics

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 Electrónica I
Biblio:
• Manuel de Medeiros Silva, "Circuitos com Transístores Bipolares e
MOS", ed. F.C. Gulbenkian, 1999.
• Sedra/Smith, Microelectronic Circuits, 7Ed Oxford University Press,
2015.
• Paul Gray, Paul J. Hurst, Stephen H. Lewis and Robert G. Meyer,
Analysis and Design of Analog Integrated Circuits, 5Ed John Wiley &
Sons, 2009.
• Behzad Razavi, Fundamentals of Microelectronics, 2Ed John Wiley &
Sons, 2014.
• Jacob Baker, CMOS Circuit Design, Layout and Simulation, 4Ed John
Wiley & Sons, 2019.
• Herbert Taub and Donald Shilling “Digital Integrated Electronics”
MacGraw-Hill 1977.

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 Electrónica I
First Transistor (1947) and first integrated circuit (1958)

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 Electrónica I
First integrated circuit

Bipolar logic
1960’s

ECL 3-input Gate

Motorola 1966

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 Electrónica I

Integrated circuit

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 Electrónica I

Die and Package

Die

Package

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 Electrónica I
Metallization:

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 Electrónica I
Metallization

M4

M3
Isolator
M2

M1
Via

CMOS transistor

P-substrate

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 Electrónica I

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 Electrónica I

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 Electrónica I
In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months.
He made a prediction that semiconductor technology will double its effectiveness every 18 months

Moore’s Law
16
COMPONENTS PER INTEGRATED FUNCTION

15
14
13
LOG2 OF THE NUMBER OF

12
11
10
9
8
7
6
5
4
3
2
1
0
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
Electronics, April 19, 1965.
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 Electrónica I
2. Roadmap Silicon radius = 111pm

0.5 µm 0.18 µm 0.12µm

λ
Devices

1995
2000 2002

Interconnects 3 layers 7 layers 8 layers

Frequency

120MHz 500MHz 1500 MHz

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 Electrónica I
2. Roadmap
Technology Year Metal Supply (V) Oxide(A) Vt (V) ST technology
0.7µm 1988 2 5.0 200 0.7 Hcmos4
0.5µm 1992 3 3.3 120 0.6 Hcmos5
0.35µm 1994 5 3.3 75 0.5 Hcmos6
0.25µm 1996 6 2.5 65 0.45 Hcmos7
0.18µm 1999 7 1.9 50 0.40 Hcmos8
0.12µm 2001 8 1.5 40 0.30 Hcmos9
0.10µm 2003 8-9 1.0 35 0.25 Hcmos10

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 Electrónica I
1. Towards nano-scale

300mm wafers In a 300mm fab…

UMC taiwan

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 Electrónica I
Multi-Level Metal Interconnect

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 Electrónica I

5-layer cross-section of chip

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 Electrónica I
Poly Capacitor

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 Electrónica I
Capacitor types

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 Electrónica I
Flux or Fringe Capacitor

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 Electrónica I
Poly resistor

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 Electrónica I
Digital logic families

MOS Bipolar
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 Electrónica I
CMOS inverter

VDD W  W 
Ron = k p < kn ⇒   ≈ 3 
k (VGS − Vt )
2
 L  PMOS  L  NMOS
Balanced inverter
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 Electrónica I
Dynamic behavior

1 1
WC = 2
C .VDD + C .VDD2 Energy by cycle
2 2
P = F .WC = F .C .VDD
2 Power

1.7C 1. 7C
t PLH ≈ t PHL ≈
W  W 
Kp VDD Kn VDD
 L  L

tP =
1
(t PLH + t PHL ) Propagation time
2
DP = P .t P Gate product delay

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 Electrónica I
Noise margin
“ 1” V
OH

V
IH

Indefinite
zone

"1"
V VOH
IL High noise margin
NM H
VIH
“ 0” V
OL Zona indefinida
NM L VIL Lower noise margin
VOL

"0" NM H = VOH − VIH

Gate Output Gate Input NM L = VIL − VOL
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 Electrónica I
CMOS logic gates

Pull-up

Pull-down

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 Electrónica I

NOR NAND

Complex gate
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 Electrónica I
NOR 4 input NAND 4 input

Adder => parallel

Product => series
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 Electrónica I
Enhancement- Depletion-load NMOS
Pseudo NMOS
load NMOS
Resistor
simulation

•Static power dissipation

•Lower transistor count
•Lower noise margin

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 Electrónica I
Pseudo NMOS

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 Electrónica I
Pass transistor gates

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 Electrónica I
CMOS switch

Multiplexer
XOR

Work with analog and digital signals

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 Electrónica I
Dynamic logic

•Pre-charge: CL load to Vdd

•Evaluate: CL stays loaded if Y=1; discharge if Y=0

•During the evaluate phase: Parasitic capacitors are charged from CL, VOH lower

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 Electrónica I
Cascade of domino gates
- In the evaluate phase, CL2 discharges due to the delay
in the falling of Y1
- Y2 gets wrong result (stays L and should be H)

Domino logic

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 Electrónica I
Output restore of Vdd
Mux

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 Electrónica I
Ring oscillator

v0 v1 v2 v3 v4 v5

v0 v1 v5

T = 2 × tp × N
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 Electrónica I
Memory circuits
-Latch

Latch SR
Flip-flop SR with clock

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 Electrónica I
D Flip-flop

D master slave Flip-flop D

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 Electrónica I
MOS Memory Hierarchy
MOS
Volatile Memory Non-volatile

Random Accessed Memory Read Only Memory

(RAM) (ROM)

Static RAM Dynamic RAM Programmable ROM

Mask ROM
(SRAM) (DRAM) (PROM)

EPROM EEPROM

Conventional Flash

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 Electrónica I
– ROM : Read Only Memory
– EPROM : Erasable Programmable ROM
– EEPROM : Electrically Erasable
Programmable ROM
– Flash : Flash Erase EEPROM
EPROM EEPROM Flash

Byte Programming Byte Programming Byte Programming

Program CHE Programming FN Programming CHE/FN Programming

Chip Erasing Byte Erasing Sector Erasing

Erase UV Erasing FN Erasing FN Erasing

EPROM + EEPROM Flash

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 Electrónica I
Volatile vs. Non-volatile

Volatile Non-volatile

DRAM SRAM NVM

BL WL BL
VDD

WL

WL
NVM
GND
CS Cell

BL

BL
Speed Medium (<100ns) Fast (<10ns)
Criterion for retention Need VCC and Refresh Need VCC
Power Consumption High Low
Cost Low High

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 Electrónica I
Memory structure

Word Line (WL)

Memory Cell

Row Decoder
Row
Memory Cell Array
Addresses

Bit Line (BL)

Data I/O
Sense Amplifier
Buffer
Column
Column Decoder
Addresses

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 Electrónica I
Memory structure

RAM memory

CMOS SRAM
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 Electrónica I
ROM memory
Programing is done
during fabrication

programing

Address decoder

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 Electrónica I
ROM memory

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 Electrónica I
Dynamic memory

Needs refresh
since charge
vanish with time

Charge sharing

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 Electrónica I
DRAM Cell
Capacitor
Q Cs
M 1 word
line
Metal word line
SiO2
Poly
n+ n+ Field Oxide Diffused
bit line
Inversion layer
Poly
induced by Polysilicon
Polysilicon
plate bias gate plate

Cross-section Layout

Uses Polysilicon-Diffusion Capacitance

Expensive in Area
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 Electrónica I
SEM of poly-diffusion capacitor 1T-DRAM

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 Electrónica I
EPROM memory

Programing
increases MOS Vt

Transistor during programing

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 Electrónica I
EEPROM
Floating gate Gate I

Source Drain

20–30 nm -10 V V GD

10 V

n1 n1
Substrate
p
10 nm

Fowler-Nordheim
FLOTOX transistor
I-V characteristic

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 Electrónica I
Cross-sections of NVM cells

Flash EPROM
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 Electrónica I
1 Gbit Flash Memory
512Mb Memory Array 512Mb Memory Array
BL0 BL1 ····· BL16895 BL16996 BL16897··· BL33791
SGD
Word Line Driver

Word Line Driver

Word Line Driver

Word Line Driver

WL31
WL0
SGS
Block0 Block0
Block1023 Block1023
BLT0
BLT1 Bit Line Control Circuit
Sense Latches Sense Latches
(10241 32) 3 8 (10241 32) 3 8
Data Caches
(10241 32) 3 8 Data Caches
(10241 32) 3 8
I/O
I/O
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 Electrónica I
125mm2 1Gbit NAND Flash Memory

2kB Page buffer & cache

Charge pump 32 word lines
x 1024 blocks
10.7mm

16896 bit lines

11.7mm
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 Electrónica I

125mm2 1Gbit NAND Flash Memory

• Technology 0.13µm p-sub CMOS triple-well
1poly, 1polycide, 1W, 2Al
• Cell size 0.077µm2
• Chip size 125.2mm2
• Organization 2112 x 8b x 64 page x 1k block
• Power supply 2.7V-3.6V
• Cycle time 50ns
• Read time 25µs
• Program time 200µs / page
• Erase time 2ms / block

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 Electrónica I
ECL Gate

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 Electrónica I
Input output transfer characteristics

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 Electrónica I
Output termination

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 Electrónica I
TTL Gate – Transistor - Transistor-Logic
NAND

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 Electrónica I
TTL Gate

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 Electrónica I
Logic levels

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 Electrónica I
TTL Tp (ns) Pd (mW) Tp . Pd
Standard 74 10 10 100
Schottky 74S 3 20 60
Schottky low power 74LS 10 2 20

Advanced Schottky 74AS 1.5 20 30

Advanced Schottky low 4 1 4
power 74ALS

ECL Tp (ns) Pd (mW)

10k 2 25

100k 0.75 40
10kH 1 25

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 Electrónica I
Texas Instruments 2007

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 Electrónica I
Texas Instruments 2007

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 Electrónica I
LVDS – Low Voltage Differential Signaling Texas Instruments 2007

Speed up to 400 Mbps

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 Electrónica I
Speed and delay of logic families

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 Electrónica I

Texas Instruments 2007

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 Electrónica I

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 Electrónica I
Digital interfaces:

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