2774 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO.

12, DECEMBER 2010

A Fully Integrated 2 1 Dual-Band

Direct-Conversion Mobile WiMAX Transceiver With
Dual-Mode Fractional Divider and Noise-Shaping
Transimpedance Amplifier in 65 nm CMOS
Jun Deguchi, Member, IEEE, Daisuke Miyashita, Member, IEEE, Yosuke Ogasawara, Gaku Takemura,
Masaomi Iwanaga, Kenichi Sami, Rui Ito, Junji Wadatsumi, Yuki Tsuda, Shoko Oda, Shunji Kawaguchi,
Nobuyuki Itoh, Member, IEEE, and Mototsugu Hamada, Member, IEEE

Abstract—This paper presents a fully integrated 2 RX 1

TX dual-band direct-conversion mobile WiMAX transceiver in a
65 nm CMOS technology. The frequency division ratios of 4 for
the low band (2.3–2.7 GHz) and 8/3 for the high band (3.3–3.8
GHz) are employed to provide high immunity to the VCO pulling
and to cover the entire frequency range with a single VCO.
A “distribute-then-fractional” frequency plan is proposed to
provide the frequency division ratios without degrading the LO
signal integrity in the LO distribution path. The proposed plan is
achieved by an inductor-less LO distribution with a novel compact
dual-mode fractional divider. A noise-shaping transimpedance
amplifier (TIA) is also proposed to mitigate the flicker noise of
scaled CMOS devices. The two receivers consume 214.1 mW and
247.7 mW in the low-band and the high-band operations, which
are lower than the power consumption of the mobile WiMAX
transceivers reported previously. In spite of the low power con-
sumption, the receivers achieve the total noise figure of 3.8 dB and
4.5 dB in the low-band and the high-band operations by virtue of
the proposed noise-shaping TIA.
Index Terms—Direct-conversion transceiver, flicker-noise, fre-
quency planning, IEEE 802.16e, mobile WiMAX, multiple-input/
multiple-output (MIMO), pulling, single chip.
I. INTRODUCTION
OBILE worldwide interoperability for microwave
M access (WiMAX), based on IEEE 802.16e standard [1],
[2] is one of the emerging standards for broadband wireless
communication. Mobile WiMAX adopts the multiple-input,
multiple-output (MIMO) technique and the orthogonal fre-
quency division multiple access (OFDMA) modulation scheme,
and supports the option of seamless handover. It offers high
data rates over a wide communication range in mobile environ-
ments. Consequently, mobile WiMAX is achieving worldwide
penetration in a wide variety of products, ranging from mobile
PCs to smartphones. Low-cost implementation of a mobile
WiMAX transceiver is essential under the above-described cir-
cumstances. While its single-chip implementation in a scaled
Manuscript received April 12, 2010; revised June 30, 2010; accepted August
20, 2010. Date of publication October 18, 2010; date of current version De-
cember 03, 2010. This paper was approved by Guest Editor Ranjit Gharpurey.
The authors are with the Toshiba Corporation, Kawasaki, Japan (e-mail: jun.
deguchi@toshiba.co.jp).
Digital Object Identifier 10.1109/JSSC.2010.2075295
0018-9200/$26.00 © 2010 IEEE
Fig. 1. Comparison of floor plans for (a) typical MIMO transceiver and (b)
single-chip MIMO transceiver.
CMOS technology is a straightforward approach, there are
various technical challenges in designing a single-chip MIMO
transceiver as discussed below.
Fig. 1 compares the two types of floor plans for a MIMO
transceiver. As shown in Fig. 1(a), it is favorable to lay out RF
circuits in receivers (RX), transmitters (TX) and synthesizers
(SYN) close to the peripheral pads of the chip to avoid the degra-
dation of the transceiver performance due to the parasitic effects
[3]–[6]. Furthermore, it is important to keep the length of the
local oscillator (LO) distribution path as short as possible by op-
timizing the floor plan of the circuit blocks. In contrast, as shown
in Fig. 1(b), it is often the case that the RF circuits are placed at
only one or two peripheries of the die in the single-chip imple-
mentation [7]–[11]. It leads to difficulty in optimizing the floor
plan of MIMO transceivers. As a result, the LO distribution path
tends to be long, and the signal integrity of the LO distribution
path tends to be degraded. The trend will become pronounced in
the future owing to the increasing number of MIMO transceivers
coexisting with larger-scale integration of digital circuits. It also
results in the increase of the chip-level power consumption as
the number of transceivers increases.
In terms of the floor planning and power consumption, for
mobile WiMAX transceivers, direct-conversion architecture [3],
[7], [8] is usually preferred because of its fewer circuit compo-
nents and lower power consumption compared with super-het-
erodyne architecture. However, direct-conversion architecture
suffers from the issues of flicker noise, voltage controlled oscil-
lator (VCO) pulling, DC-offset, I/Q mismatch and LO leakage.
In the mobile WiMAX system, the first subcarrier in OFDMA
DEGUCHI et al.: A FULLY INTEGRATED 2 1 DUAL-BAND DIRECT-CONVERSION MOBILE WiMAX TRANSCEIVER
Fig. 2. High-level transceiver block diagram.
signals comes at 7.8125 kHz, which is generally far below the
flicker noise corner of scaled CMOS devices. In a direct-conver-
sion mobile WiMAX transceiver in scaled CMOS technology,
the flicker noise becomes a critical issue.
This paper describes a fully integrated 2 RX 1 TX
dual-band direct-conversion mobile WiMAX transceiver in
a 65 nm CMOS technology [12]. Section II presents the
transceiver architecture. The frequency plan based on an in-
ductor-less LO distribution with a dual-mode fractional divider
is discussed in Section III. The frequency plan provides high
immunity to the VCO pulling and copes with the constraints
of floor planning while maintaining the signal integrity of a
long LO distribution path. Section IV focuses on the design
of three key circuits in the transceiver. The first one is a novel
noise-shaping transimpedance amplifier (TIA) for mitigating
the flicker noise of scaled CMOS devices. The second one is
the dual-mode fractional divider employed in the inductor-less
LO distribution path. The third one is a wide-band passive
mixer employed in the transmitter. Then, measurement results
are presented in Section V. Finally, conclusions are presented
in Section VI.
II. TRANSCEIVER ARCHITECTURE
The high-level transceiver block diagram is shown in Fig. 2.
The transceiver is composed of a phase-locked loop (PLL), an
LO generation/distribution block, two receivers (RX-A, RX-B)
and a transmitter. The transceiver covers the frequency ranges of
the dual-band for mobile WiMAX, which are the low-band (LB)
of 2.3–2.7 GHz and the high-band (HB) of 3.3–3.8 GHz. The
transceiver adopts the direct-conversion architecture to mini-
mize the number of circuit components and power consump-
tion. Calibration schemes to tune the oscillation frequency of
the VCO, to tune the cutoff frequency of the low-pass filters
(LPFs), to cancel RX DC offset, to cancel TX LO leakage, and
2775
to cancel TX I/Q mismatch are also implemented in the trans-
ceiver.
The block diagram of the direct-conversion receiver is shown
in Fig. 3. The receiver has two RF paths for the low band and the
high band. The RF input signal is first amplified by a cascoded
common-source low-noise amplifier (LNA) with LC tank, and
then down-converted to the baseband I/Q signals by I/Q mixers.
The LNA is directly connected to the I/Q mixers via AC cou-
pling capacitors. In a direct-conversion mobile WiMAX trans-
ceiver in scaled CMOS technology, the flicker noise is a critical
issue as described in Section I. Therefore, the receiver adopts
the passive mixers to reduce the flicker noise from switching
transistors. Then the flicker noise from the operational amplifier
(op-amp) in the following TIA becomes dominant at low fre-
quencies. Thus, in this paper, a noise-shaping TIA is proposed
to improve the noise figure (NF) of the receiver. The details of
the noise-shaping TIA are described in Section IV. In each I/Q
path, the down-converted signals are filtered and amplified by
the proposed noise-shaping TIA, an LPF and two variable gain
amplifiers. Finally, the signals are converted to the digital sig-
nals by a time-interleaved pipelined analog-to-digital converter
(ADC) in which the amplifiers are shared by I/Q paths for area
and power savings [13].
The block diagram of the direct-conversion transmitter is
shown in Fig. 4. The transmitter has two output paths for
the dual-band operations. The digital I/Q signals are con-
verted to analog baseband I/Q signals by current-steering
digital-to-analog converters (DACs) in I/Q paths. The baseband
signals are filtered by reconstruction LPFs, and then up-con-
verted to the RF signal by I/Q mixers. In order to reduce the
number of circuit components, the I/Q mixers are shared in the
low-band and the high-band paths by employing wide-band
passive mixers. The output power of the up-converted RF
signal is controlled by the programmable gain stages. The
passive mixers in the receivers and the transmitter are driven
2776
Fig. 3. Receiver block diagram.
Fig. 4. Transmitter block diagram.
Fig. 5. Frequency plan.
by quadrature LO signals generated by the PLL and the LO
generation/distribution block as shown in Fig. 2. The details of
the LO generation are discussed in the next section.
III. FREQUENCY PLANNING
Several frequency plans to prevent the VCO pulling in the di-
rect-conversion transceivers have been reported for Bluetooth,
wireless local area network (WLAN) and mobile WiMAX ap-
plications. They are categorized into two approaches. The first
approach is the integer division (typically divide-by-2) of the
VCO operating frequency [3], [8], [14], [15]. However, this ap-
proach might still suffer from the pulling caused by the second
harmonic of the carrier frequency [16]. Integer division ratios
higher than two could reduce the harmonic pulling. The other
approach employing the fractional division of the VCO oper-
ating frequency prevents both direct and harmonic pulling [5],
[7]–[10], [17]–[22]. We employ the division ratio of 4 for the
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 12, DECEMBER 2010
low band and 8/3 for the high band so that a single VCO can
cover the entire frequency range.
The frequency plan employed in this work is shown in Fig. 5.
The single VCO in the PLL covers a frequency tuning range
of 8.8–10.8 GHz. The operating frequency of the VCO is then
divided by 2 just after the VCO. The LO signal of 4.4–5.4 GHz
is globally distributed. For the low-band operation, the global
LO signal is divided by 2 just before the passive mixers in the
receivers and the transmitter. Thus, the low-band LO signal of
2.2–2.7 GHz is obtained. For the high-band operation, the global
LO signal is divided by 4/3, and then the high-band LO signal
of 3.3–4.05 GHz is obtained. In this case, the global LO signal
of 4.4–5.4 GHz is divided by 2 locally. Then, it is mixed with
the global LO signal to generate the LO signal of 6.6–8.1 GHz,
which is finally divided by 2 to generate 3.3–4.05 GHz.
At this point, we will compare the proposed frequency plan
with a conventional one as shown in Fig. 6. LO distribution
based on a fractional division technique with a mixer usually
DEGUCHI et al.: A FULLY INTEGRATED 2 1 DUAL-BAND DIRECT-CONVERSION MOBILE WiMAX TRANSCEIVER
Fig. 6. Comparison of high-band LO signals distributed by (a) the conventional “fractional-then-distribute” plan and (b) the proposed “distribute-then-fractional”
plan.
suffers from the degraded LO signal integrity due to the un-
desired lower side-band spur of the mixer’s image tone [17].
Fig. 6(a) shows the LO signals distributed by the conventional
plan, which we refer to as the “fractional-then-distribute” plan
where a root 4/3 divider is placed just after the VCO. In this plan,
a large root 4/3 divider with an LC band-pass filter (LC-BPF)
shall be required to reduce the lower side-band spur of 2/3 car-
rier frequency at the node a2 in Fig. 6(a), otherwise area-
consuming digital-calibration circuits to suppress the spur are
used [7], [17], [19]. Besides, in order to distribute the LO signal,
additional LC-BPFs are also to be added for suppressing the re-
growing spur at the nodes a3 and a5. As the power consumption
of the buffers inserted in the LO distribution path is reduced for
minimizing the power consumption of the MIMO transceiver,
the cutoff frequency of the buffers becomes low. As a result, the
gain for the lower side-band spur becomes larger than the gain
for the desired LO signal. The low-pass response of the buffers
has a large impact on the spur re-growth in a long LO distribu-
tion path for the MIMO transceiver. Therefore, the conventional
“fractional-then-distribute” plan requires the LC-BPFs.
The LO signals distributed by the proposed frequency plan
are depicted in Fig. 6(b), which we refer to as the “distribute-
2777
then-fractional” plan where local 4/3 dividers are placed just
before the passive mixers in the receivers and the transmitter.
In this plan, there are no lower side-band spurs in the distri-
bution path at the nodes b1, b2, b3 and b5, which contributes
to avoiding the degradation of the LO signal integrity in the
LO distribution path. Therefore, no LC-BPFs are required in
the LO distribution path, i.e. inductor-less LO distribution is
achieved. Though higher side-band spurs such as harmonics of
the LO signal are generated at the output of the divider right
after VCO, the harmonics are sufficiently suppressed by the
low-pass response of the buffers. This plan takes advantage of
scaled CMOS devices for low-power, high-speed and small-area
integration since the LO distribution path is composed of only
simple CMOS inverter buffers [18]. It also provides high flex-
ibility for the floor planning of the LO distribution path, and
the proposed plan can be scalable to larger integrated
MIMO systems. However, the issue here is that this plan re-
quires as many local 4/3 dividers as the number of the receiver
and the transmitter paths. Conventional large 4/3 dividers with
LC-BPFs are not usable in this case. In this work, we resolve
the issue by proposing a novel dual-mode fractional divider. The
circuit details are described in the next section.
2778
Fig. 7. Schematic diagrams of (a) basic TIA, (b) noise-shaping TIA and (c)
noise-shaping TIA with feedback capacitance.
IV. CIRCUIT DESIGN
In this section, the three key circuits in the transceiver are
described. The first one is a noise-shaping TIA for mitigating
the flicker noise of scaled CMOS devices. The second one is the
dual-mode fractional divider employed in the inductor-less LO
distribution path. The third one is the wide-band passive mixer
employed in the transmitter.
A. Noise-Shaping Transimpedance Amplifier
In the receiver design, the passive mixer topology is adopted
to reduce the flicker noise as described in Section II. Thus, the
reducing the flicker noise from the TIA becomes very important.
Enlarging the input transistors of the op-amp in the TIA is a
straightforward approach to mitigate the flicker noise. However,
it may make it much more difficult to design the op-amp, which
is already constrained by stringent specifications such as those
for gain, bandwidth, linearity, and stability. In our case, actually,
even with larger input devices to decrease the flicker noise of the
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 12, DECEMBER 2010
Fig. 8. Block diagrams of (a) basic TIA, (b) noise-shaping TIA and (c) noise-
shaping TIA with feedback capacitance.
op-amp, the required noise performance is not obtained while
maintaining other aspects of performance. In this section, we
propose a novel method to suppress the flicker noise from the
op-amp.
As a starting point, the schematic diagram of the basic TIA
is shown in Fig. 7(a). By solving the Kirchhoff equations in the
TIA, the signal transfer function (STF) from the input to the
output of the TIA and the noise transfer function (NTF) from
the input of the op-amp to the output of the TIA are derived as,
(1)
(2)
where is the conductance seen from the mixer output,
is the feedback conductance of the TIA, is the voltage gain
of the op-amp and is the input-referred noise of the op-amp.
From (1) and (2), the equivalent block diagram of the basic TIA
is derived as shown in Fig. 8(a).
For suppressing the flicker noise from the op-amp in the
closed loop, it is a natural idea to place an additional gain
component before the op-amp, because the input-referred noise
of the op-amp is suppressed by that gain. Consequently, we
focus on the block in Fig. 8(a) that contains .
DEGUCHI et al.: A FULLY INTEGRATED 2 1 DUAL-BAND DIRECT-CONVERSION MOBILE WiMAX TRANSCEIVER 2779

It represents the effective impedance at node in Fig. 7(a),

which converts the current through and into the input
voltage of the op-amp. We utilize this impedance, although its
usefulness is often overlooked behind the large voltage gain
of the subsequent op-amp. In this work, we add a negative
conductance cell at node as shown in Fig. 7(b). It results in
the increase of the impedance at node as shown by the block
in Fig. 8(b). When the block is divided into the original
impedance without the negative conductance cell and
as shown in Fig. 8(b) , we regard as an additional gain
component. We describe as,

(3)
which physically means the mismatch between the original con-
ductance at node and the absolute value of the added nega-
tive conductance. If the values were perfectly matched, the ad-
ditional gain would become infinity. Thus, the magnitude of the
additional gain is determined not by device parameters such as
the gm but only by the relative accuracy of , and . negative conductance cell is derived as follows:
Therefore we can manage or the magnitude of the addi-
tional gain flexibly.
Since the actual implementation of the TIA has 1st order
LPF characteristics, we need to consider the influence of the
feedback capacitance as shown in Fig. 7(c). The effective
impedance at node is modified by the capacitance as
shown in Fig. 8(c). Although the reduces the impedance
at node and the suppression of the noise from the op-amp
at high frequencies, the noise suppression effect is maintained
at low frequencies. It means that the noise is selectively
suppressed only at low frequencies and the NTF is shaped
into a high-pass characteristic. The STF and the NTF of the
noise-shaping TIA with the feedback capacitance are derived
as follows:
(4)
(5)
(6)
With the aid of the additional gain boost by , the STF of the
noise-shaping TIA becomes closer to the ideal low-pass char-
acteristics than the one without the gain boost. Since the nega-
tive conductance cell is placed between the virtual ground nodes
of the TIA, linearity of the negative conductance cell itself is
not critical. Linearity of the proposed TIA is better than a con-
ventional one without the negative conductance cell because the
open loop gain of the TIA is larger owing to the additional gain
boost by . mixer. Thus, the single-gate mixer topology [23] is employed to
Fig. 9. Block diagram of dual-mode fractional divider.
In practice, the noise from the negative conductance cell
shown as in Fig. 8 should also be con-
sidered. The transfer function of the input-referred noise of the
(7)
Even if the circuit is ideally designed ( is zero) and the noise
from the op-amp becomes zero as predicted in (5), the noise
from the negative conductance cell appears at the TIA output. It
is important to design the noise of the negative conductance cell
to be low enough to satisfy the noise specification of the TIA,
which is the case in our design.
B. Dual-Mode Fractional Divider
Fig. 9 shows the block diagram of the proposed dual-mode
fractional divider. It is composed of the divide-by-2 circuit, the
gm-cell and the mixer. In order to eliminate the LC-BPFs used
for suppressing the lower side-band spur generated by the mixer
in the high-band operation, we have adopted single side-band
(SSB) mixer architecture. The divide-by-2 circuit is stacked on
the gm-cell and the mixer. Current-mode connection eliminates
the buffer and LC-BPFs placed often between the divide-by-2
circuit and the mixer. In addition, the power consumption for the
high-band operation is reduced by sharing the biasing current in
the divide-by-2 circuit and the mixer.
The schematic diagram of the dual-mode fractional divider is
depicted in Fig. 10. For the low-band operation, the dual-mode
fractional divider is configured as shown in Fig. 10(a). It com-
prises a conventional divide-by-2 circuit based on a flip-flop
topology, where the transistors M1 through M4 work as the
gm-cells. Meanwhile, for the high-band operation, four sets
of four single-gate mixers (4-SGMs) take the place of four
gm-cells to compose the SSB mixer topology as shown in
Fig. 10(b). If we utilize a conventional Gilbert-cell mixer
here, it is very difficult to stack the divide-by-2 circuit on the
2780
Fig. 10. Schematic diagram of dual-mode fractional divider for (a) low-band
operation and (b) high-band operation.
Fig. 11. Simplified schematic diagram of wide-band passive mixer employed
in transmitter.
achieve low-voltage and low-power operation. In the single-gate
mixer, two LO signals are applied together to the gate of the
transistor, and the mixing function is achieved by the squaring
function of the transistor’s second-order non-linearity. Because
the proposed dual-mode fractional divider has no LC-BPFs and
is shared by both the low-band and the high-band operations, it
is applicable to the proposed “distribute-then-fractional” plan.
C. Wide-Band Passive Mixer in Transmitter
Fig. 11 shows the simplified schematic diagram of the wide-
band passive mixer employed in the transmitter. Actual imple-
mentation is the double-balanced topology for both I/Q paths.
The mixer is composed of resistors , a capacitor for AC
coupling and a switching transistor . The resistor is the
termination resistor as a load of the mixer, which is also used for
biasing the following programmable gain stage. Wideband char-
acteristics are achieved by making small enough to exclude
the effect of parasitic capacitance on impedance at the node X.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 12, DECEMBER 2010
Fig. 12. Measured (a) receiver output noise and (b) receiver gain.
V. MEASUREMENT RESULTS
Fig. 12 shows the measured output noise and gain of the re-
ceiver with or without the noise-shaping function. By enabling
the noise-shaping function, 4 dB improvement of the receiver
output noise at 7 kHz is achieved as shown in Fig. 12(a). In con-
trast, as shown in Fig. 12(b), the difference of STF is negligibly
small with or without the noise-shaping function. Fig. 13 shows
the measured and simulated noise suppression ratio at 1 kHz,
which is the ratio of the noise with the noise-shaping to that
without the noise-shaping, where the total noise from LNA to
the noise-shaping TIA is compared. It proves that, by making
small, we can improve the noise suppression ratio as predicted
in (5). Notice that we cannot make too small. When be-
comes larger than , the polarity of turns negative
and the feedback loop becomes unstable. In this implementa-
tion, are estimated by circuit simulation while con-
necting LNA, mixer and TIA with varying process, voltage, and
temperature (PVT) conditions. The nominal value of is de-
termined so that does not become negative in the worst case.
is set to 0.3, or is . About 4.6 dB improve-
ment of the noise is achieved at the design point. The deviation
between the measurement and the simulation in Fig. 13 is within
the expected range of process variation.
The layout of the compact dual-mode fractional divider is
shown in Fig. 14. The size is 56 um by 118 um. It is laid out
to minimize the lower side-band spur of caused by the
device mismatches and layout asymmetry of the single-gate
mixers employed in the dual-mode fractional divider. Further-
more, the non-linearity of the single-gate mixer, which also
causes the spur, is low in spite of the low-voltage operation
[23]. Thus, the spur of is low enough to be filtered out
DEGUCHI et al.: A FULLY INTEGRATED 2 1 DUAL-BAND DIRECT-CONVERSION MOBILE WiMAX TRANSCEIVER 2781

Fig. 13. Measured and simulated noise suppression ratio at 1 kHz.

Fig. 15. Wide-band spectrum measured at transmitter output.

Fig. 14. Layout of dual-mode fractional divider.

by the LC-BPFs in the receiver and the transmitter paths, as is

the case for the conventional “fractional-then-distribute” plan
[17]. As a result, the spurs of , and caused Fig. 16 Spur levels measured at transmitter output in 40 samples.
by the non-linearity of the passive mixers in the transmitter
path also become very low. The wide-band spectrum measured
at the transmitter output is shown in Fig. 15. All the spur levels
are below 60 dBc. Furthermore, the design is robust to the
process variation, resulting in the levels of the spurs in 40
samples being less than 60 dBc as shown in Fig. 16. The
results satisfy the spurious specification of mobile WiMAX
with a sufficient margin. Fig. 17 shows the measured phase
noise at the transmitter output. In this measurement, the VCO
is operating at 10 GHz which is then divided by two. The LO
signal of 5 GHz is distributed through the inductor-less LO
distribution path. For the high-band operation, the LO signal of
5 GHz is divided by 4/3 at the proposed divider and the carrier
Fig. 17. Measured phase noise at high-band and low-band of 3.75 GHz and 2.5
frequency becomes 3.75 GHz. For the low-band operation, the GHz.
LO signal of 5 GHz is divided by 2 at the proposed divider and
then the carrier frequency becomes 2.5 GHz. The integrated
phase noise from 1 kHz to 5 MHz is 38.8 dBc and 42.5 dBc of 10 MHz. The two receivers consume 214.1 mW and 247.7
in the high-band and the low-band operations, respectively. mW at the low-band and the high-band operations, respec-
The difference of the integrated phase noise is 3.7 dB. It is the- tively. The transmitter consumes 214.8 mW and 229.7 mW at
oretically equal to 3.5 dB which corresponds to the difference the low-band and the high-band operations, respectively. The
of the frequency division ratio. It is calculated by of 3.75 power consumption includes the PLL, the inductor-less LO
over 2.5. It proves that the noise contribution of the proposed distribution path, the dual-mode fractional dividers and ADCs
dual-mode fractional divider is negligible. The constellation or DACs. The power consumption of the receiver per path is
plots measured at 1 dBm transmitter output are shown in lower than that of the mobile WiMAX transceivers reported
Fig. 18. The error vector magnitudes (EVM) in 2.5 GHz and previously [4], [7], [8]. In spite of such low power consump-
3.5 GHz bands are 34.0 dB and 31.0 dB, respectively. tion, the receiver achieves the total NF of 3.8 dB and 4.5 dB
Table I summarizes the measured total performance of the in the low-band and the high-band operations by virtue of the
transceiver. The results are measured at the channel bandwidth proposed noise-shaping TIA. Fig. 19 shows the die micrograph
2782
Fig. 18. TX constellation plots measured at +1 dBm output.
TABLE I
PERFORMANCE SUMMARY OF MOBILE WIMAX TRANSCEIVERS
1 Analog I/Q mode
2 External local mode
Fig. 19. Die micrograph of test chip.
of the test chip. The transceiver occupies 2.3 mm 6.72 mm.
The on-chip inductors are used only in the RF front-end circuits
of the transceiver.
VI. CONCLUSIONS
A fully integrated 2 RX 1 TX dual-band direct-conver-
sion mobile WiMAX transceiver in 65 nm CMOS technology
was presented. The “distribute-then-fractional” frequency plan
is proposed, which employs the inductor-less LO distribution
with the compact dual-mode fractional dividers. The frequency
plan provides higher flexibility for the floor planning of the
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 12, DECEMBER 2010
long LO distribution path. Furthermore, in order to mitigate the
flicker noise of scaled CMOS devices, the noise-shaping TIA
with the negative conductance cell is proposed. By enabling the
noise-shaping function, while the signal transfer function of the
TIA remains the same, the flicker noise from the op-amp is sup-
pressed. Although the power consumption of the receiver em-
ploying the noise-shaping TIA is lower than that of the mobile
WiMAX transceivers reported previously, total NF of 3.8 dB
and 4.5 dB is achieved in the low-band and the high-band oper-
ations, respectively.
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Jun Deguchi (M’10) received the B.S. and M.S.
degrees in machine intelligence and systems engi-
neering, and Ph.D. degree in bioengineering and
robotics from Tohoku University, Sendai, Japan, in
2001, 2003 and 2006, respectively.
In 2006, he joined the Center for Semiconductor
Research and Development, Toshiba Corporation,
Kawasaki, Japan. Since then he has been engaged
in the design of analog and RF circuits for wireless
communications. In 2004, he was a Visiting Scholar
at the University of California, Santa Cruz.
Daisuke Miyashita (M’10) received the B.E. and
M.E. degrees in electronic engineering from the
University of Tokyo, Tokyo, Japan, in 2001 and
2003, respectively.
In 2003, he joined the Center for Semiconductor
Research and Development, Toshiba Corporation,
Kawasaki, Japan, where he has been engaged in
the design of RF and analog circuits for wireless
communications.
Yosuke Ogasawara received the B.E degree from
Chuo University, Tokyo, Japan, in 2003.
From 2003 to 2006, he was with 1st SoC Design
Division, NEC Micro Systems, Ltd., Kanagawa,
Japan, as an Analog RFIC Designer. In 2006, he
joined the Analog Device Design Department,
Semiconductor Company, Toshiba Corporation,
Kawasaki, Japan, where he is working on the design
of RF front circuit for wireless communications.
Gaku Takemura received the B.E. degree in elec-
trical engineering and the M.E. degree in electronic
communication engineering from Kyoto University,
Kyoto, Japan, in 1995 and 1997, respectively.
In 1997, he joined the Wireless and Multimedia
LSI Development Department, Semiconductor
Company, Toshiba Corporation, Kawasaki, Japan.
Since then, he has been engaged in the development
of wireless communication circuits.
2784
Masaomi Iwanaga received the B.E. and the M.E.
degrees in electrical and electronic engineering from
Kobe University, Kobe, Japan, in 1996 and 1998, re-
spectively.
In 1998, he joined the Wireless & Multimedia LSI
Development Department, Semiconductor Company,
Toshiba Corporation, Kawasaki, Japan. Since then,
he has been engaged in the development of wireless
communication circuits.
Kenichi Sami received the B.E. degree in electrical
engineering from Tokyo University, Tokyo, Japan, in
1997.
Since then, he joined the Toshiba Corporation,
Kawasaki, Japan, in 1997 and has been engaged in
the development of wireless communication circuits.
Rui Ito received the B.E and M.E degrees from
Kanagawa University, Yokohama, Japan, in 2000
and 2002, respectively.
In 2002, he joined the Corporate Research & De-
velopment Center, Toshiba Corporation, Kanagawa.
He is now with the Toshiba Corporation Semicon-
ductor Company, Kawasaki, Japan. His research in-
terests include analog IC design for telecommunica-
tion and LCD driver ICs.
Junji Wadatsumi received the B.E. and M.E. de-
grees from the Tokyo Institute of Technology, Tokyo,
Japan, in 2003 and 2005, respectively.
In 2005, he joined the Center for Semiconductor
Research and Development, Toshiba Corporation,
Kawasaki, Japan, where he has been engaged in
the design of RF and analog circuits for wireless
communications.
Yuki Tsuda received the B.E. degree and the M.E.
degree in electrical engineering from Kyushu Univer-
sity, Fukuoka, Japan, in 2003 and 2005, respectively.
In 2005, he joined the Wireless & Multimedia LSI
Development Department, Semiconductor Company,
Toshiba Corporation, Kawasaki, Japan. Since then,
he has been engaged in the development of wireless
communication circuits.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 12, DECEMBER 2010
Shoko Oda received the B.E. and the M.E. degrees
in electrical engineering from Kyushu University,
Fukuoka, Japan, in 2005 and 2007, respectively.
In 2007, she joined the Center for Semiconductor
Research and Development, Toshiba Corporation,
Kawasaki, Japan. Since then, she has been engaged
in the design of RF and analog circuits for wireless
communications.
Shunji Kawaguchi was born in Hyogo, Japan, in
1959. He received the B.S. degree in electronic
engineering from Kobe University, Kobe, Japan, in
1983.
In 1983, he joined the Toshiba Corporation,
Kawasaki, Japan, where he has been engaged in the
design and development of bipolar LSI’s, especially
for wireless communications. He is currently the
Chief Specialist of the Analog Device Design
Department, Toshiba Corporation Semiconductor
Company.
Nobuyuki Itoh (M’03) was born in Tokyo, Japan,
in 1960. He received the B.S. and M.S. degrees in
chemistry from Tokyo University of Science, Tokyo,
Japan, in 1983 and 1985 respectively, and the Ph.D.
degree in physical electronics from Tokyo Institute of
Technology, Tokyo, Japan, in 2006.
In 1985, he joined the Research and Development
Center, Toshiba Corporation, Kawasaki, Japan,
where he was engaged in the research and develop-
ment of CMOS device technologies, bipolar device
technologies, bipolar circuits design and RFCMOS
circuit design. He had been a Visiting Scientist at Katholieke Universiteit
Leuven, ESAT-MICAS, Leuven, Belgium, from 1996 to 1998, where he had
worked on design of fully integrated VCOs and PLLs using RFCMOS. He has
been engaged in the research and development of high-frequency analog circuit
at Semiconductor Company of Toshiba Corporation since 1998. He is also a
part-time lecturer of Chuo University, Tokyo, Japan, since 2009. His current
research interests are high-frequency integrated circuit for telecommunications.
Dr. Itoh is a member of the Institute of Electronics and Communication En-
gineers (IEICE). He received the Asia-Pacific Microwave Conference (APMC)
Prize in 2007. He has been a member of TPC of CICC, BCTM, and ESSCIRC,
was a secretary of IEEE MTT-S Japan Chapter, is a secretary of URSI-C Japan
Committee, and is the Publicity Chair of APMC 2010.
Mototsugu Hamada (M’03) was born in Nara,
Japan, in 1968. He received the B.S., M.S., and
Ph.D. degrees in electronic engineering from the
University of Tokyo, Tokyo, Japan, in 1991, 1993,
and 1996, respectively.
In 1996, he joined Toshiba Corporation and has
been engaged in wireless and low-power electronic
circuits design with Toshiba’s Center for Semicon-
ductor Research and Development, Kawasaki, Japan.
From 2002 to 2004, he was a Visiting Scholar with
Stanford University.
Dr. Hamada was the recipient of the 2007 IEEE International Conference on
Computer Design (ICCD) Best Paper Award and the co-recipient of the Design
Automation Conference (DAC) 2010 Best User Track Poster Award. He has
served as a member of the technical program committee of International Solid-
State Circuits Conference (2003–2009, 2011) and Asian Solid-State Circuits
Conference (2005–2010). He was the Technical Program Committee Vice-Chair
of A-SSCC2009.