Microprocessor Development Tools

CSE 466-02au-
Tool Types

Software Tools

! Assembler
! Linker
! Loader
! Compiler
! Libraries
! Pre-compiled IP
! Simulator
! IDE

CSE466 - Fall 2002- 2

Hardware Tools

In Circuit Emulator (ICE)

Logic Analyzer
Microprocessor
Development Systems
System Development
Systems

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Atmel AVR Architecture

CSE466 - Fall 2002- 4

ATmega16

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AVR CPU

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Simple Princeton Architecture

I/O Port
Timer, SFR’s PC IR GPRs SP
RAM
address
Reset Vector
Interrupt Vect ALU
ROM
IR
Linear
Address mux
Space data
Status
W/ Mem
Mapped Control
IO

CSE466 - Fall 2002- 7

Analysis

Bottleneck into and out of memory for data and code

Use of critical 8-bit address space (256) for memory mapped I/O and
special function registers (timers and their controllers, interrupt
controllers, serial port buffers, stack pointers, PC, etc). For example,
the Motorola 6805 processor has only 187 RAM locations.

But, easy to program and debug. Compiler is simple too.

CSE466 - Fall 2002- 8

8051: Modified Harvard Architecture
PC
mux
address
Reset Vector Internals
Interrupt Vect Usually
SFR’s
Interrupt Vect Stack ALU
Interrupt Vect (indirect) (direct)

RAM
(indirect or 8051 standard +
Enhancements
Direct)
Bit Addressable

Reg. Banks
Status
PSW – 2-bits bank sel.
data instruction 3 bits reg sel
------------------
Control 4x8 5 bits of reg. addr

CSE466 - Fall 2002- 9

8051 Memory Architecture

Advantages
! Simultaneous access to Program and Data store
! Register banks great for avoiding context switching on
interrupt and for code compression
! 8-bit address space extended to 256+128 = 384 registers by
distinguishing between direct and indirect addressing for
upper 128 bytes. Good for code compression
! Bit addressable great for managing status flags

Disadvantage
! A little bit confusing, with potential for errors.

CSE466 - Fall 2002- 10

Motorola 56367 DSP

CSE466 - Fall 2002- 11

Motorola 56367 DSP

Advantages

! Three memory spaces allow ALU op and two moves simultaneously

" Macc x1,y1,a x1,x:(r3)+ y:(r6)+,y1 ; in one cycle

" Really, really,really fast

Disadvantages

! frightening to program

! Very difficult to write a good compiler

CSE466 - Fall 2002- 12

AVR CPU

CSE466 - Fall 2002- 13

Registers

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Register Mapping

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ALU Opcode Timing

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Pipeline

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SRAM access

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Instructions by Type

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