FPGA Assignment 3

(Total Marks 25)

1. Write a Verilog HDL code to infer 256 x 8 Distributed RAM with

Simple Dual Port Configuration and Report the utilization of the
number of LUTs

Simple dual port

• One port for synchronous writes (no data out/read port from the write
port)
• One port for asynchronous reads

Refer Xilinx User Guide / Data Sheet for more information

2. Write a Verilog HDL code to infer 1024 x 32 Distributed RAM with

Single Port Configuration with Synchronous Read and Report the
utilization of the number of LUTs.

3. Write a Verilog HDL code to infer 128-Bit Shift Register and Report
the utilization of the number of LUTs.

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