MC14016B

Quad Analog Switch/

Quad Multiplexer

The MC14016B quad bilateral switch is constructed with MOS

P–channel and N–channel enhancement mode devices in a single
monolithic structure. Each MC14016B consists of four independent
switches capable of controlling either digital or analog signals. The http://onsemi.com
quad bilateral switch is used in signal gating, chopper, modulator,
demodulator and CMOS logic implementation. MARKING
• Diode Protection on All Inputs DIAGRAMS
• Supply Voltage Range = 3.0 Vdc to 18 Vdc 14
PDIP–14
• Linearized Transfer Characteristics P SUFFIX MC14016BCP
• Low Noise — 12 nV/√Cycle, f ≥ 1.0 kHz typical CASE 646 AWLYYWW

• Pin–for–Pin Replacements for CD4016B, CD4066B (Note improved 1

transfer characteristic design causes more parasitic coupling 14
capacitance than CD4016) SOIC–14
• For Lower RON, Use The HC4016 High–Speed CMOS Device or D SUFFIX
14016B
AWLYWW
The MC14066B CASE 751A

• This Device Has Inputs and Outputs Which Do Not Have ESD 1

Protection. Antistatic Precautions Must Be Taken. 14

SOEIAJ–14
F SUFFIX MC14016B
CASE 965 AWLYWW
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
1
Symbol Parameter Value Unit
A = Assembly Location
VDD DC Supply Voltage Range – 0.5 to +18.0 V WL or L = Wafer Lot
YY or Y = Year
Vin, Vout Input or Output Voltage Range – 0.5 to VDD + 0.5 V
WW or W = Work Week
(DC or Transient)
Iin Input Current (DC or Transient) ± 10 mA
per Control Pin
ORDERING INFORMATION
ISW Switch Through Current ± 25 mA
Device Package Shipping
PD Power Dissipation, 500 mW
per Package (Note 3.) MC14016BCP PDIP–14 2000/Box
TA Ambient Temperature Range – 55 to +125 °C MC14016BD SOIC–14 55/Rail
Tstg Storage Temperature Range – 65 to +150 °C
MC14016BDR2 SOIC–14 2500/Tape & Reel
TL Lead Temperature 260 °C
(8–Second Soldering) MC14016BF SOEIAJ–14 See Note 1.

2. Maximum Ratings are those values beyond which damage to the device MC14016BFEL SOEIAJ–14 See Note 1.
may occur.
3. Temperature Derating: 1. For ordering information on the EIAJ version of
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C the SOIC packages, please contact your local
ON Semiconductor representative.
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) vVDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.

 Semiconductor Components Industries, LLC, 2000 1 Publication Order Number:

March, 2000 – Rev. 3 MC14016B/D
 MC14016B

PIN ASSIGNMENT

IN 1 1 14 VDD
OUT 1 2 13 CONTROL 1
OUT 2 3 12 CONTROL 4
IN 2 4 11 IN 4
CONTROL 2 5 10 OUT 4
CONTROL 3 6 9 OUT 3
VSS 7 8 IN 3

BLOCK DIAGRAM
13
CONTROL 1 2
1 OUT 1
IN 1
5
CONTROL 2 3
4 OUT 2
IN 2
6
CONTROL 3 9
OUT 3
8
IN 3
12
CONTROL 4 10
OUT 4
11
IN 4

VDD = PIN 14
VSS = PIN 7

Control Switch
0 = VSS Off
1 = VDD On

LOGIC DIAGRAM
(1/4 OF DEVICE SHOWN)
OUT

CONTROL

LOGIC DIAGRAM RESTRICTIONS IN

VSS ≤ Vin ≤ VDD
VSS ≤ Vout ≤ VDD

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2
 MC14016B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
Î ÎÎ
ÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ VDD
– 55_C 25_C 125_C

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Characteristic Figure Symbol Vdc Min Max Min Typ (4.) Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Voltage 1 VIL 5.0 — — — 1.5 0.9 — — Vdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Control Input 10 — — — 1.5 0.9 — —
15 — — — 1.5 0.9 — —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
VIH 5.0
10
—
—
—
—
3.0
8.0
2.0
6.0
—
—
—
—
—
—
Vdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — — 13 11 — — —
± 0.1 ± 0.00001 ± 0.1 ± 1.0 µAdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
Input Current Control — Iin 15 — — —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
Input Capacitance — Cin pF
Control — — — — 5.0 — — —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
Switch Input — — — — 5.0 — — —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
Switch Output — — — — 5.0 — — —
Feed Through — — — — 0.2 — — —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
Quiescent Current
ÎÎÎ
ÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
(Per Package) (5.) ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
2,3 IDD 5.0
10
—
—
0.25
0.5
—
—
0.0005
0.0010
0.25
0.5
—
—
7.5
15
µAdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
15 — 1.0 — 0.0015 1.0 — 30

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
“ON” Resistance 4,5,6 RON — — Ohms
(VC = VDD, RL = 10 kΩ) — —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
(Vin = + 5.0 Vdc) — 600 — 300 660 — 840

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
(Vin = – 5.0 Vdc) VSS = – 5.0 Vdc — 600 — 300 660 — 840
(Vin = ± 0.25 Vdc) 5.0 — 600 — 280 660 — 840

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
(Vin = + 7.5 Vdc)

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎ
ÎÎÎ
(Vin = ± 0.25 Vdc)
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = – 7.5 Vdc) VSS = – 7.5 Vdc
7.5
—
—
—
360
360
360
—
—
—
240
240
180
400
400
400
—
—
—
520
520
520

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
(Vin = + 10 Vdc)

ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
— 600 — 260 660 — 840

ÎÎ ÎÎ
(Vin = + 0.25 Vdc) VSS = 0 Vdc — 600 — 310 660 — 840

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = + 5.6 Vdc) 10 — 600 — 310 660 — 840
(Vin = + 15 Vdc) — 360 — 260 400 — 520

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
(Vin = + 0.25 Vdc) VSS = 0 Vdc

ÎÎÎ
ÎÎÎ
— 360 — 260 400 — 520

ÎÎ ÎÎ
(Vin = + 9.3 Vdc) 15 — 360 — 300 400 — 520

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
∆ “ON” Resistance — ∆RON Ohms
Between any 2 circuits in a common

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
package

ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ ÎÎ
(VC = VDD)
(Vin = ± 5.0 Vdc, VSS = – 5.0 Vdc) 5.0 — — — 15 — — —

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ
Input/Output Leakage CurrentÎÎ
ÎÎÎ
ÎÎ ÎÎÎ
(Vin = ± 7.5 Vdc, VSS = – 7.5 Vdc)

ÎÎÎ
ÎÎÎ — —
7.5 — — — 10 — — —
µAdc

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎ ÎÎÎ
(VC = VSS)
(Vin = + 7.5, Vout = – 7.5 Vdc) 7.5 — ± 0.1 — ± 0.0015 ± 0.1 — ± 1.0

ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
(Vin = – 7.5, Vout = + 7.5 Vdc) 7.5 — ± 0.1 — ± 0.0015 ± 0.1 — ± 1.0
NOTE: All unused inputs must be returned to VDD or VSS as appropriate for the circuit application.
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. For voltage drops across the switch (∆Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e., the
current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the
Maximum Ratings are exceeded. (See first page of this data sheet.) Reference Figure 14.

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 MC14016B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (6.) (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
Characteristic Figure Symbol Vdc Min Typ (7.) Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
Propagation Delay Time (VSS = 0 Vdc) 7 tPLH, 5.0 — 15 45 ns
Vin to Vout tPHL 10 — 7.0 15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VC = VDD, RL = 10 kΩ) 15 — 6.0 12

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
Control to Output 8 tPHZ, ns
v
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
(Vin 10 Vdc, RL = 10 kΩ) tPLZ, 5.0 — 34 90
tPZH, 10 — 20 45

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
tPZL 15 — 15 35

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
Crosstalk, Control to Output (VSS = 0 Vdc) 9 — 5.0 — 30 — mV
(VC = VDD, Rin = 10 kΩ, Rout = 10 kΩ, 10 — 50 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
f = 1.0 kHz)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
Crosstalk between any two switches (VSS = 0 Vdc) — —
15
5.0
—
—
100
– 80
—
— dB

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
(RL = 1.0 kΩ, f = 1.0 MHz,

+ V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
crosstalk 20 log10 out1)
Vout2

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
Noise Voltage (VSS = 0 Vdc)

ÎÎÎÎ
(VC = VDD, f = 100 Hz)
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
10,11 — 5.0
10
15
—
—
—
24
25
30
—
—
—
nV/√Cycle

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
(VC = VDD, f = 100 kHz)

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
5.0
10
—
—
12
12
—
—

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
15 — 15 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
Second Harmonic Distortion (VSS = – 5.0 Vdc) — — 5.0 — 0.16 — %
(Vin = 1.77 Vdc, RMS Centered @ 0.0 Vdc,

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
RL = 10 kΩ, f = 1.0 kHz)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
Insertion Loss (VC = VDD, Vin = 1.77 Vdc, 12 — 5.0 dB
VSS = – 5.0 Vdc, RMS centered = 0.0 Vdc, f = 1.0 MHz)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
+Iloss
ÎÎÎ
(RL = 1.0 kΩ)
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
V

ÎÎÎÎ ÎÎÎÎ
20 log10 out)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vin ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
—
—
2.3
0.2
—
—

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
(RL = 10 kΩ)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ
(RL = 100 kΩ)
(RL = 1.0 MΩ)
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
—
—
0.1
0.05
—
—

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
Bandwidth (– 3.0 dB)

ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VC = VDD, Vin = 1.77 Vdc, VSS = – 5.0 Vdc,
12,13 BW 5.0 MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
RMS centered @ 0.0 Vdc)
(RL = 1.0 kΩ) — 54 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
(RL = 10 kΩ) — 40 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
(RL = 100 kΩ) — 38 —
(RL = 1.0 MΩ) — 37 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
ÎÎÎ ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
(VSS = – 5.0 Vdc)
+
ÎÎÎÎ
ÎÎÎ ÎÎÎ
ÎÎÎÎ
Vout
ÎÎÎÎ
OFF Channel Feedthrough Attenuation

ÎÎÎ
ÎÎÎÎ
— — 5.0 kHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
(VC = VSS, 20 log10 –50 dB)
Vin — 1250 —
(RL = 1.0 kΩ)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
— 140 —
(RL = 10 kΩ)
— 18 —

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎ
(RL = 100 kΩ)
— 2.0 —
(RL = 1.0 MΩ)
6. The formulas given are for typical characteristics only at 25_C.
7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

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 MC14016B

VC IS

Vin Vout

VIL: VC is raised from VSS until VC = VIL.

VIL: at VC = VIL: IS = ±10 µA with Vin = VSS, Vout = VDD or Vin = VDD, Vout = VSS.
VIH: When VC = VIH to VDD, the switch is ON and the RON specifications are met.

Figure 1. Input Voltage Test Circuit

10,000
VDD = 15 Vdc 10 Vdc

PD , POWER DISSIPATION (µW)

VDD TA = 25°C
5.0 Vdc
1000

ID
100

VDD Vout
TO ALL
10 k 10
PULSE 4 CIRCUITS CONTROL
GENERATOR INPUT
fc

VSS Vin 1.0

PD = VDD x ID 5.0 k 10 k 100 k 1.0 M 10 M 50 M
fc, FREQUENCY (Hz)

Figure 2. Quiescent Power Dissipation Figure 3. Typical Power Dissipation per Circuit
Test Circuit (1/4 of device shown)

TYPICAL RON versus INPUT VOLTAGE

700 700
RL = 10 kΩ VSS = 0 Vdc
600 TA = 25°C 600 RL = 10 kΩ
R ON, “ON” RESISTANCE (OHMS)

R ON, “ON” RESISTANCE (OHMS)

TA = 25°C
500 500

400 VC = VDD = 5.0 Vdc 400

VSS = – 5.0 Vdc VC = VDD = 10 Vdc
300 300

200 200 VC = VDD = 15 Vdc

VC = VDD = 7.5 Vdc
100 VSS = – 7.5 Vdc 100

0 0
– 10 – 8.0 – 4.0 0 4.0 8.0 10 0 2.0 6.0 10 14 18 20
Vin, INPUT VOLTAGE (Vdc) Vin, INPUT VOLTAGE (Vdc)

Figure 4. VSS = – 5.0 V and – 7.5 V Figure 5. VSS = 0 V

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 MC14016B

Vout

RL CL

Vin

Vout 20 ns 20 ns
RL VDD
Vin 90%
VC 50% 10%
VSS
tPLH tPHL

Vout 50%
Vin

Figure 6. RON Characteristics Figure 7. Propagation Delay Test Circuit

Test Circuit and Waveforms

Vout
VC RL CL

Vin VX
20 ns
VDD Vout
90%
VC 50%
10% VC 10 k 15 pF
VSS
tPZH tPHZ
Vin = VDD
90% Vx = VSS
Vout 10% Vin
tPZL tPLZ
90% 1k
Vout Vin = VSS
10%
Vx = VDD

Figure 8. Turn–On Delay Time Test Circuit Figure 9. Crosstalk Test Circuit
and Waveforms

35

30
VDD = 15 Vdc
NOISE VOLTAGE (nV/ CYCLE)

25
10 Vdc
20
5.0 Vdc
15
OUT QUAN–TECH 10
MODEL
VC = VDD
2283
5.0
IN OR EQUIV
0
10 100 1.0 k 10 k 100 k
f, FREQUENCY (Hz)

Figure 10. Noise Voltage Test Circuit Figure 11. Typical Noise Characteristics

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 MC14016B

2.0
RL = 1 MΩ AND 100 kΩ
0
TYPICAL INSERTION LOSS (dB)

10 kΩ
– 2.0
1.0 kΩ
– 4.0 – 3.0 dB (RL = 1.0 MΩ )
Vout
– 6.0 – 3.0 dB (RL = 10 kΩ ) RL
VC
– 3.0 dB (RL = 1.0 kΩ )
– 8.0

– 10 + 2.5 Vdc
Vin 0.0 Vdc
– 12 – 2.5 Vdc
10 k 100 k 1.0 M 10 M 100 M
fin, INPUT FREQUENCY (Hz)

Figure 12. Typical Insertion Loss/Bandwidth Figure 13. Frequency Response Test Circuit
Characteristics

ON SWITCH

CONTROL
SECTION
OF IC

LOAD
V

SOURCE

Figure 14. ∆V Across Switch

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 MC14016B

APPLICATIONS INFORMATION

Figure A illustrates use of the Analog Switch. The 0–to–5
V Digital Control signal is used to directly control a 5 Vp–p
analog signal.
The digital control logic levels are determined by VDD
and VSS. The VDD voltage is the logic high voltage; the VSS
voltage is logic low. For the example, VDD = + 5 V logic high
at the control inputs; VSS = GND = 0 V logic low.
The maximum analog signal level is determined by VDD
and VSS. The analog voltage must not swing higher than
VDD or lower than VSS.
The example shows a 5 Vp–p signal which allows no
margin at either peak. If voltage transients above VDD
and/or below VSS are anticipated on the analog channels,
external diodes (Dx) are recommended as shown in Figure
B. These diodes should be small signal types able to absorb
the maximum anticipated current surges during clipping.
The absolute maximum potential difference between
VDD and VSS is 18.0 V. Most parameters are specified up to
15 V which is the recommended maximum difference
between VDD and V SS.

+5 V

VDD VSS
+ 5.0 V

+5 V 5 Vp–p SWITCH
ANALOG SIGNAL IN
SWITCH 5 Vp–p
+ 2.5 V
OUT ANALOG SIGNAL
EXTERNAL
CMOS 0–TO–5 V DIGITAL
GND
DIGITAL CONTROL SIGNALS MC14016B
CIRCUITRY

Figure A. Application Example

VDD VDD

Dx Dx

SWITCH SWITCH
IN OUT
Dx Dx

VSS VSS

Figure B. External Germanium or Schottky Clipping Diodes

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 MC14016B

PACKAGE DIMENSIONS

P SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE M NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14 8 2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 7 5. ROUNDED CORNERS OPTIONAL.

INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 18.80
F L B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
N F 0.040 0.070 1.02 1.78
C G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
–T– J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
SEATING
PLANE L 0.290 0.310 7.37 7.87
K J M ––– 10_ ––– 10_
H G D 14 PL M N 0.015 0.039 0.38 1.01

0.13 (0.005) M

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 MC14016B

PACKAGE DIMENSIONS

D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
–A– Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
14 8 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
–B– P 7 PL 5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
1 7
0.25 (0.010) M B M PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
MILLIMETERS INCHES
G R X 45 _ F DIM MIN MAX MIN MAX
C A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
–T– F 0.40 1.25 0.016 0.049
K M J G 1.27 BSC 0.050 BSC
SEATING D 14 PL
PLANE J 0.19 0.25 0.008 0.009
0.25 (0.010) M T B S A S K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

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 MC14016B

PACKAGE DIMENSIONS

F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 965–01
ISSUE O NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
14 8 LE MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
Q1 OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
E HE M_ 4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
1 7 L DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DETAIL P DIMENSION AT MAXIMUM MATERIAL CONDITION.
Z DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
D BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
VIEW P
A MILLIMETERS INCHES
e DIM MIN MAX MIN MAX
c A ––– 2.05 ––– 0.081
A1 0.05 0.20 0.002 0.008
b 0.35 0.50 0.014 0.020
c 0.18 0.27 0.007 0.011
b A1 D 9.90 10.50 0.390 0.413
E 5.10 5.45 0.201 0.215
0.13 (0.005) M 0.10 (0.004) e 1.27 BSC 0.050 BSC
HE 7.40 8.20 0.291 0.323
0.50 0.50 0.85 0.020 0.033
LE 1.10 1.50 0.043 0.059
M 0_ 10 _ 0_ 10 _
Q1 0.70 0.90 0.028 0.035
Z ––– 1.42 ––– 0.056

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 MC14016B

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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