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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
A Statistical Design Approach Using Fixed
and Variable Width Transconductors for
Positive-Feedback Gain-Enhancement OTAs
Andrew Peter Nicholson, Astria Nur Irfansyah, Julian Jenkins, Tara Julia Hamilton, Member, IEEE,
and Torsten Lehmann, Senior Member, IEEE
Abstract— The positive-feedback gain-enhancement opera-
tional transconductance amplifier (OTA) design is a promising
architecture to scale into deep submicron CMOS. Ever smaller
CMOS process nodes require analog circuit designs that can
overcome the area–power-matching relation. We introduce a
Nauta OTA with a split architecture consisting of fixed width and
digitally programmable variable width transconductors utilizing
the minimum grid-spacing of the CMOS process enabling an
active mismatch cancelation technique. A variation-aware sta-
tistical design practice is introduced to analyze the sizing of
transconductors, computing code-word solutions for statistically
likely solutions, and estimating average maximum dc gain over
the entire code-space of many simulated OTAs. Prototypes of
a 8-bit differential OTA in 180-nm CMOS designed using the
Nauta structure fixed width and digitally programmable variable
width architecture achieves an average maximum dc gain of
60 dB, simulated unity gain frequency of 4.6 GHz, and a
figure-of-merit of 1 GHz/mW.
Index Terms— Deep submicron CMOS, digitally assisted
analog design, positive-feedback gain-enhancement operational
transconductance amplifier (OTA).
I. I NTRODUCTION
A NALOG designers are faced with numerous challenges
to scaling down circuit designs into deep submicron
CMOS—increasing output conductance of short-channel
devices implies decreasing intrinsic gain, low voltage
headroom as voltage supply decreases faster than threshold
voltages, and increased nonlinearities [1]–[3]. In 90 nm and
below, the traditional analog designs will not be able to break
the area–power-matching relation, and simply scaling up width
and length to overcome mismatch is limited by gate leakage
effects. Thus, active mismatch cancelation techniques are
Manuscript received July 25, 2016; revised November 30, 2016; accepted
January 3, 2017. This work was supported by the Australian Research Council
Industry Linkage under Grant LP100200275.
A. P. Nicholson and T. Lehmann are with the School of Electrical
Engineering and Telecommunications, University of New South Wales,
Sydney, NSW 2033, Australia.
A. N. Irfansyah is with the School of Electrical Engineering and
Telecommunications, University of New South Wales, Sydney, NSW 2033,
Australia, and also with the Department of Electrical Engineering, Institut
Teknologi Sepuluh Nopember, Surabaya 60117, Indonesia.
J. Jenkins is with Perceptia Devices Inc., Sydney, NSW 60117, Australia.
T. J. Hamilton is with The MARCS Institute, Western Sydney University,
Penrith, NSW 2150, Australia.
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TVLSI.2017.2657885
1063-8210 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
1
required to maintain low area (high unity gain frequency), low
power and high gain [4], [5]. Digitally assisted analog circuits
are a solution for active mismatch cancelation, however,
this introduces new challenges, such as the classification of
errors (time dependence and monotonicity) and the design of
calibration and linearization techniques [6], [7].
To design operational transconductance amplifiers (OTAs)
further into deep submicron CMOS using positive-feedback
gain-enhancement techniques that rely upon device matching,
we need to proceed with a mismatch tolerant architecture.
The Nauta OTA is a high-speed single-stage design, which
is suitable for digitally assisted variation-aware techniques
to scale down into deep submicron CMOS [8]–[10]. In
this paper, we introduce a circuit architecture and statistical
design procedure for digitally assisted positive-feedback gain-
enhancement OTAs. The OTA is split into fixed width and
digitally programmable variable width components using a
statistical approach of designing the sizes of each transconduc-
tor for high-gain solutions. A Monte Carlo-based simulation
method of quantifying our various yields and average dc gains
is outlined, and then compared with the experimental results
of prototypes fabricated in 180-nm CMOS.
Our motivation for designing with a statistical frame-
work for a mismatch tolerant architecture is that the gain-
enhancement technique used in the Nauta OTA architecture
relies upon device matching. However, in deep submicron
CMOS, minimum-sized device matching is becoming statis-
tically worse, for instance, as measured by comparing the
standard deviation of drain currents between two minimum
sized identical devices within the same die [11], [12]. Our
design presented here is informed by statistical techniques
to enhance mismatch tolerance through the availability of a
series of transconductance values implemented as digitally
programmable analog components whose width differences are
defined by a function of the minimum CMOS grid-spacing.
Recent work on mismatch tolerant analog design includes
Maunu et al. [13] who present a design of a self-calibrating
current source utilizing the inherent variations within an array
of minimum-sized devices. Ragab et al. [14] introduce a
component redundancy and random diversity architecture to
harness randomness to calibrate a positive-feedback amplifier
utilizing minimum-sized devices biased in subthreshold.
This paper will detail the statistical design process showing
how we can partition the transconductors into fixed width and
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2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Fig. 1. Nauta differential OTA schematic.
variable width components, size the individual components of
the variable width transconductors for the highest likelihood
of combinatorial matching, and estimate the statistical average
of the maximum dc gain achievable for the digital Nauta OTA.
It can achieve higher gains than traditional analog multistage
OTA designs whilst using a comparable silicon die area but
achieves higher unity gain frequencies. In terms of a figure-of-
merit (FoM) as measured in a unity gain frequency per power
consumption ratio (GHz per mW) our designs are competitive
to the state-of-the-art. Further into deep submicron CMOS,
the digital Nauta OTA increases unity gain bandwidth and
decreases silicon area whilst still delivering high dc gains.
This paper is organized as follows. Section II is the
mathematical analysis of the design process for the fixed
width and variable width components of the positive-feedback
gain-enhancement OTA and expectation of calibrated dc gain,
Section III is a model of the unity gain frequency of the OTA,
Section IV is a statistical analysis over the entire code-space,
which can quantify the performance metrics of the OTA,
Section V is a description of the calibration strategy of the
digital Nauta OTA, Section VI is the experimental results
obtained from ten prototype digital OTAs in 180-nm CMOS,
Section VII is a comparison with a traditional analog amplifier
design, and Section VIII is the conclusions of the research.
II. S IZING S TRATEGY OF T RANSCONDUCTORS
IN D IGITAL NAUTA OTA
The width sizing strategy for transconductors is based on
the method of gain enhancement used in the Nauta OTA [15].
This is achieved using positive feedback to form a negative
transconductance, which cancels the output conductance of the
circuit and produces large gain. Gain is therefore restricted to
transconductance (or width) matching resolution. We assume
minimum length for all transistors in our structure as we are
targeting the highest unity gain frequency possible.
Referring to Fig. 1, the cross-coupled (Inv3, Inv6)
transconductors’ width should be larger than the self-coupled
(Inv4, Inv5) transconductors’ widths, to form the negative
transconductance, and this should be equal to the sum of
output conductance of all transconductors. Assuming a
symmetrical architecture for both paths in the differential
circuit, we can find the result of ideal width difference
between self-coupled and cross-coupled transconductors by
considering just three transconductors in one path and an
assumption of a constant ratio of transconductance to output
conductance operating point [8], [16].
In Sections III-A–III-D, we define a code-word as the setting
of the digital control lines for the digital OTA, refer to Fig. 2.
P is the control line to power-up the OTA. P, E N[7 : 0] is
in bus notation, indicating a 9-bit bus composed of powerup
control line for the fixed width self-coupled transconductor
and the 8-bit variable width transconductor programming bus.
As a simplifying assumption in this paper, we assume that
the code-word is symmetrical across both the paths, and the
active low control lines are always the inverse of the active
high lines. This means that the total size of the code-space
is 2 N for a Nauta differential OTA using N-bit digital-to-
transconductance converters [17].
Our architecture for the digital Nauta OTA that follows is an
improvement over full programmability of transconductance
in all components [8] with a computationally feasible size of
the code-space. We have only fixed-width components for the
feedforward and cross-coupled transconductors, and for the
self-coupled transconductors, we use a parallel fixed width and
variable width transconductor design. This new architecture
provides a small code-space that is easily traversable by a
calibration algorithm combined with a statistical technique of
choosing design parameters based on a grid-spacing design of
digitally controllable transconductor width.
We acknowledge the inherent device mismatch in the design
of the programmable width transconductor architecture by
using a certain number of tristate-able parallel connected
minimum-length transconductors of varying widths. Starting
with a minimum width transconductor, the sequence is defined
relative to the previously defined device width plus a width
increment that is a multiple of the grid-spacing resolution
of the CMOS process. In this way, we combine the idea
of redundancy—using multiple transconductors varying in
width by only by a single grid-spacing resolution—with the
statistical benefits produced by a combinatorial space of the
digitally programmable transconductors with width differences
at integer multiples of the grid-spacing resolution. We define
the parameter M as the number of devices in the series starting
from a minimum length, minimum width device that are sized
apart in width only by a single CMOS grid-spacing. The
parameter N is the total number of independent devices in
the series, inclusive of M.
A. Fixed Width Feedforward and
Cross-Coupled Transconductors
The feedforward fixed width component is derived from
the transconductance requirements, gm , and dc gain speci-
fication, A V . We illustrate our argument with an example
specifications of 4-mS transconductance minimum, gm,spec,
(relative to a single-ended transconductor) and at least a linear
dc gain of 64 (36 dB) that can be used within a sigma–delta
modulator [10].
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NICHOLSON et al.: STATISTICAL DESIGN APPROACH USING FIXED AND VARIABLE WIDTH TRANSCONDUCTORS 3

Fig. 2. Digital Nauta differential OTA using two 8-bit digital-to-transconductance converters for the two variable width components of the self-coupled
transconductors (Inv4, Inv5). This OTA has values N = 8, M = 2. P is the control line to power-up the OTA. P, E N [7 : 0] is in bus notation, indicating a
9-bit bus composed of power-up control line for the fixed width self-coupled transconductor and the 8-bit variable width transconductor programming bus.

To a first order, the width matching considerations require We have

that in a digitally programmable Nauta structure, the feed-
forward transconductor’s width is at least half the linear dc
gain as large as the smallest width transconductor, Wmin [8].
This accounts for the first estimate in (1). This lower bound
on feedforward transconductor width, WFF , can then be con-
firmed to match gm,spec specifications through transconduc-
tance measurements across process variation-only Monte Carlo
simulations (using 4096 trials) to ensure that it is greater than
the gm,spec specification to within 3σ . E[] is the expectation
operator
1 coupled transconductors for the condition of maximum dc
WFF = · E[ A V ] · Wmin .
2
Next, this transconductor is statistical sampled via process
variation and mismatch Monte Carlo trials to find the mean
and standard deviation of transconductance, gm , and output
conductance, gds . These parameters will be used to estimate
the range of width differences between self- and cross-coupled
transconductance needed to establish maximum dc gain
conditions.
The cross-coupled fixed width, WCC , component is defined
as a fraction, k, of WFF . Total self-coupled transconductor
width (fixed and variable components) is defined as WSC .
A tradeoff for the selection of this fraction exists between min-
imizing for power, area, and hysteresis effects (smaller k) and
the requirement of the common mode stability condition [18],
that is, WSC + WCC > WFF (larger k).
WCC = k · WFF 0 < k < 1. (2)
The self-coupled transconductor’s width can be determined
by the necessity of setting the transconductance difference
between self-coupled and cross-coupled transconductors equal
to the sum of output conductance of all transconductors for
maximum dc gain. Thus
|(WSC − WCC ) · gm | = (WSC + WCC + WFF ) · gds. (3)
Following from (3), we solve for the width of the self-
(1) gain as:
WSC · (gm + gds) = WCC · (gm − gds) − WFF · gds
WSC = (ζ − ξ ) · WCC − ξ · WFF (4)
where ζ −1 = 1 + μ(gds/gm ) and ξ = ζ · μ(gds/gm ). We
define μ(gds/gm ) as the mean of the ratio of the output
conductance to transconductance.
Substituting (2) into (4) allows us to solve for the ideal self-
coupled width (in the absence of device mismatch) solely in
terms of cross-coupled width to establish maximum dc gain.
We have
WSC = (ζ − (k −1 + 1) · ξ ) · WCC . (5)
Defining W as the ideal width difference between
cross-coupled and self-coupled transconductors for maximum
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4 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
TABLE I
F IXED C OMPONENTS S UMMARY FOR D IGITAL N AUTA OTA
dc gain, and using (5), we find
W = WCC − WSC
W = WCC · (1 − (ζ − (k −1 + 1) · ξ )).
From (2) and (5), we can determine if the common mode
stability condition is met, that is, if WSC + WCC > WFF holds
at the condition of maximum dc gain
WSC > WFF − WCC
WSC > WCC · (k −1 − 1)
ζ − (k −1 + 1) · ξ > k −1 − 1.
We start our numerical calculations using the smallest width
transconductor available in the 180-nm CMOS process—a
220 nm:180 nm (W : L) nMOS device with an nMOS:pMOS
ratio of 1:4. Using Wmin = 220 nm and E[ A V ] = 64 with (1),
we obtain
64
WFF = · 220 nm = 7.04 μm. (8)
2
Substituting this result for WFF and using k = (5/7) into (2),
we obtain WCC = 5.03 μm. Finally, using the values for
the mean ratio of transconductance to output conductance
and values for ζ, ξ as shown in Table I, obtained from the
simulated single-ended feedforward transconductor, we can
use (5) and (6) to derive the final values we need for the
design, arriving at WSC = 4.135 μm and W = 895 nm.
Table I summarizes the state of the fixed components
parameter values as discussed so far, especially the ideal values
of WFF , WCC , and WSC as derived from (1), (2), and (5). We
can also use this data to confirm that (7) is satisfied.
In the next part, we analyze the self-coupled transconductor
width, WSC , and show how to split this component into fixed
and variable components (WSC,fixed ,WSC,variable ).
B. Variable Width Self-Coupled Transconductors
The self-coupled transconductor fixed component, WSC,fixed ,
needs to be a smaller width value than the ideal width, WSC ,
found using (5) so as to allow our variable width self-coupled
transconductors to combine with the fixed component to form
the overall ideal width. For a first approximation, the fixed
width component of the self-coupled transconductors can be
estimated by subtracting a value greater than W from WCC .
We cannot determine a satisfactory value exactly until after
we also choose sizes for the variable components and conduct
parametric evaluations of the entire OTA and simulate the
achievable parametric yields.
The variable component for the self-coupled transconduc-
tors, WSC,variable , is composed of a set of N parallel-connected
tristate transconductors varying in width. Each transconductor
is independently digitally controllable via the tristate switches,
which are sized the same as the corresponding signal carrying
transistors.
Given a particular programming code-word, C, for the vari-
able width self-coupled transconductors, 0 ≤ C ≤ 2 N − 1, in
combination with the fixed width self-coupled transconductor,
for the maximum dc gain condition, we have

N
WSC,fixed + WSC,variable,i · F(C, i ) = WSC (9)
i=1
(6) where F(C, i ) is a function, which is one only if the i th digit
of the binary form of the code-word C is one, otherwise zero.
As (9) reveals that the value we ultimately chose for
WSC,fixed will be a tradeoff between having a larger fixed com-
ponent to minimize mismatch error in the fixed components
and fewer N bits needed to cover a smaller width range—
versus a smaller fixed component and larger width range,
allowing increased coverage of grid-spaced width solutions at
(7) the expense of more N bits.
Given an N-bit implementation of the variable width self-
coupled transconductors there are N transconductors with the
width of the xth device defined via a first-order difference
between successive transconductors’ width, as so
WSC,variable,x − WSC,variable,x−1 = f (x) ·  for 1 < x ≤ N
(10)
where  is the grid-spacing—the minimum increment for
width in the CMOS process.
The discrete-valued function f (x) is defined for 1 < x ≤ N,
given a programmable transconductor architecture with N bits
containing M bits of redundancy. It has the following form:
f (x) = 1 for 1 < x ≤ (M + 1)
f (x) = 2 · (x − M) for (M + 1) < x ≤ N. (11)
The first M values encode redundancy into the achieved
matching estimate of —the minimum unit of grid-spacing.
These transconductors are a variation on the idea of an array
of identical minimum sized devices, which are available for
combination to achieve matching. However, they are a single
grid-spacing larger than each other, starting from the minimum
sized device. This allows for combinatorial solutions that
can resolve width to within the grid-spacing resolution. The
remaining N −M devices in the design are sized with multiples
of the grid-spacing to achieve a large overall width range with
fewer overall components.
In general, the choice of the N −1 values for f (x) is design
decisions to be chosen after a process involving tradeoffs
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NICHOLSON et al.: STATISTICAL DESIGN APPROACH USING FIXED AND VARIABLE WIDTH TRANSCONDUCTORS
Fig. 3. Monte Carlo-based simulations of code yields estimated from
1024 8-bit OTAs in 180-nm CMOS.
for resolution of matching, redundancy, and width range.
In the 180-nm CMOS process, our prototype was fabricated
in the minimum grid-spacing is  = 5 nm, and the size of
WSC,variable,1 = 220 nm corresponding to the minimum sized
transconductor available.
C. Choice of the Number of Bits (N) and Redundancy (M)
A tradeoff can be found between WSC,fixed and the num-
ber of bits N chosen in the design of the self-coupled
transconductors. Fewer bits means a smaller code-space and
a restricted width tuning range requiring a larger WSC,fixed .
More bits allows more possible grid-spaced (and overlapping
redundant) width solutions, more width tuning range and a
smaller WSC,fixed at the expense of a larger code-space. After
settling upon values of N, M, and WSC,fixed , we can use (9),
(10), and (11) to calculate the solutions for the variable width
component and the associated high gain code-words.
In our presented design, we have chosen to use N = 8,
which corresponds to a code-space size of 256 possible code-
words. In practice, these decisions are the result of an iterative
design approach. During such a design process, and assuming
a relatively small code-space, we can conduct Monte Carlo
mismatch and process variation statistical trials over the entire
code-space, iterating over the values of WSC,fixed and M to see
the effects of varying the fixed component and redundancy
upon total parametric yield and statistical metrics of average
number of yielding code-words for a given dc gain specifica-
tion and the average maximum dc gain.
We simulate four different OTA designs using N = 8,
1 ≤ M ≤ 4, and WSC,fixed = 3 μm, across the entire
code-space using Monte Carlo mismatch and process trials,
establishing 1024 virtual OTAs. We define code-word yield as
the number of OTAs that this particular code-word achieves the
dc gain specifications on. Fig. 3 shows the code-word yields
simulated for each of the four possible design decisions for
the variable width self-coupled transconductors. The N = 8,
M = 2 design has 25 code-words, which achieve a 15% or
higher yield, which is only surpassed by N = 8, M = 3,
which has 29 code-words above 15%.
Dead-zones in Fig. 3 are related to the fact that
either these code-words do not produce enough dc gain
5
Fig. 4. Histograms of maximum dc gains obtained across 1024 simulated
OTAs.
(negative transconductance not close enough to output
conductance) or they give a nonzero phase response at dc
(negative transconductance larger in magnitude than output
conductance). Given the code-words do not map linearly to
width, the dead-zones are distributed on the code-word axis
in a nonlinear fashion.
Fig. 4 shows the distributions of maximum dc gains sim-
ulated for all four design variants. The M = 2 design has
the longest tail of all the distributions, with more nonzero
bins above 60 dB than any other option. Specifically, it has
a 2.94% probability for gains above 60 dB compared with a
3.09% probability for M = 3, and the highest probability for
gains above 65 dB at 1.05%. The M = 2 design has average
maximum dc gain of 46.9 dB, whilst the M = 3 design has
an average maximum dc gain of 47.4 dB.
D. Estimation of Width Range of High Gain Solutions
and Expectation of Grid-Spaced DC Gain
Estimating the 99.9% confidence interval (CI) of the mean
of the ratio of output conductance to transconductance,
μ(gds/gm ), allows us to derive the range of possible width
differences that correspond to solutions for the maximum
dc gain for the digital Nauta OTA. We can derive the CI
from the ratio of the mean of two random variables using
Fieller’s theorem, from the mean and variance of the two sets
of simulated data (output conductance and transconductance
curves). Note that this analysis for uncertainty in the ideal
width is only considering variations in a single feedforward
transconductor relative to the entire circuit.
We can then derive from (6) two sets of equations to
determine the maximum and minimum ideal width difference
from the maximum and minimum values of ζ, ξ
  
gds
Wmax : ζ −1 = 1 + max μ
g
  m
gds
ξ = ζ · max μ
g
  m 
gds
Wmin : ζ −1 = 1 + min μ
g
  m
gds
ξ = ζ · min μ . (12)
gm
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6 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

TABLE II III. U NITY-G AIN F REQUENCY M ODEL

PARAMETER VALUES FOR E STIMATION OF R ANGE OF H IGH G AIN
S OLUTIONS AND E XPECTATION OF G RID -S PACED DC G AIN Following the treatment in [8], we provide a model of the
unity gain frequency from the analysis of the capacitance of
the transconductors. Unlike with a digital Nauta OTA made
completely from programmable DTCs from the previously
cited 60-bit 65-nm OTA, the fixed width transconductors used
here provide a simpler analysis. The fixed width transconduc-
tor capacitance model can be written as follows, for nMOS
transistors only, without the disabled state given that the
TABLE III entire OTA is powered OFF when the P signal is low. In the
VARIABLE C OMPONENTS S UMMARY FOR P RESENTED OTA D ESIGN following, we write capacitances Cgd , Cdb , Cgs in terms of
unit transistor widths, that is, normalized to total FF device
width, WFF . We use the definition of k from (2)
WCC
Ctotal,nMOS,fixed = (Cgd + Cdb ) + (2 · Cgd + Cgs ) ·
WFF
WSC,fixed
+ (Cgs + Cdb ) ·
W
 FF 
WSC,fixed
Ctotal,nMOS,fixed = (1 + 2 · k) · Cgd + k + · Cgs
WFF
 
WSC,fixed
+ 1+ · Cdb . (14)
WFF
This range of solutions for the width difference means that
there is a corresponding range of optimal WSC,variable . Given Using our nMOS:pMOS ratio of 1:4 as previously given, our
we have a known range for the ideal width difference, we total capacitance for fixed width transconductors is as follows:
can know write an expression for dc gain in terms of the
Ctotal,fixed = 5 · Ctotal,nMOS,fixed
minimum unit of transconductance uncertainty relative to the  
feedforward transconductors. That is, we estimate the tunable WSC,fixed
Ctotal,fixed = 5 · (1 + 2 · k) · Cgd + 5 · k + · Cgs
transconductance error in our grid-spaced system as the differ- WFF
 
ence between the estimated largest and smallest optimal width WSC,fixed
+5· 1+ · Cdb . (15)
difference between self- and cross-coupled transconductors. WFF
Following on from (1), we find that:
The equation for unity gain frequency follows:
2 · WFF
E[ Av ] = . (13)
Wmax − Wmin f T = gm,unit
   
Inspecting the width range for the variable component of WSC,fixed
· 2π · 5 · (1+ 2 · k) · Cgd + 5 · k + · Cgs
the N = 8, M = 2 design we find that the coverage of WFF
widths that is produced by sizing the transconductors using   −1
WSC,fixed
(10) and (11) provides eight code-word solutions mapping +5· 1+ · Cdb . (16)
WFF
continuously between 1.125 and 1.145 μm in  nm steps.
WSC,fixed =3 μm combines with a value within this range to We combine our values from Table I, estimates for the
form an exact solution to (9). smallest-width transistor capacitances on our 180-nm CMOS
We show the values of the maximum and minimum estimate process at Cgd = 155 aF, Cdb = 195 aF, and Cgs =
for μ(gds/gm ) for a 99.9% CI, the range of W this corre- 222 aF, assuming Cox = 8.4 fF/μm2 ,C j = 0.96 fF/μm2 ,
sponds to, and the expected high gain using the grid-spacing Cjsw = 0.27 fF/μm and unit transconductance estimated at
resolution matching from (13) in Table II. gm,unit = 136 μS. Using these values (16) gives 4.7 GHz for
Our design calculations are completed with this analysis— the maximum unity gain frequency. This result does not take
concluding that the N = 8, M = 2 option is a satisfactory into account the grid-spaced DTCs, as these are much smaller
tradeoff in terms of redundancy and width range of the four than the fixed components, and thus will overestimate the
options—it has a continuous mapping of widths around the maximum unity gain frequency. The ideal matched simulation
estimated range of possible solutions, is expected to achieve of the entire OTA’s unity gain frequency gives a figure of
high average maximum dc gains and has a large number of 4.6 GHz—refer to Fig. 5 showing the simulated gain and
high-yielding code-word solutions. Table III summarizes the phase response at code-word 202—a representative code-word
variable component design decisions thus far, and gives the of high dc gain and stable phase response. The gain curve is
high gain code-words (in decimal format) as found by (9) at the top curve, the phase curve is the bottom curve, showing a
the ideal width (no mismatch effects) and the width range simulated −3 dB gain of 80 dB at 304 kHz and a unity gain
found via (12). frequency of 4.6 GHz.
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NICHOLSON et al.: STATISTICAL DESIGN APPROACH USING FIXED AND VARIABLE WIDTH TRANSCONDUCTORS
Fig. 5. Open-loop dc gain and phase response for 8-bit 180-nm digital
OTA—simulated at SC code-word 202.
TABLE IV
S IMULATED C ODE -W ORD Y IELDS W ITHIN THE P REDICTED
I DEAL VARIABLE W IDTH R ANGE
IV. S IMULATED C ODE -S PACE S TATISTICS
OF N = 8, M = 2 D IGITAL OTA
We analyze the digital Nauta OTA as presented in Fig. 2
using statistical techniques – Monte Carlo process variation
and mismatch simulations – from which we can quantify the
performance across code-space over a large number of sim-
ulated OTAs. This allows us to make statistically significant
statements about total parametric yield, individual code-
word yield, and average number of code-word solutions per
OTA—as estimated across the entire code-space. Furthermore,
we can contrast our statistically estimated best code-word
solutions with our high gain codes found via mathematical
analysis in Section III, and give average minimum and
maximum dc gains achievable in the code solution set
according to the specifications found across all OTAs.
We conducted 1024 Monte Carlo trials for every code-word
in the code-space (256), for a total of 262 144 mismatch and
process variation simulations. Due to our control over the mis-
match run sequence, we can ensure that we can equivalently
treat this as simulating every code-word over 1024 different
OTAs. First, total yield is calculated from the number of OTAs
that had no code-words that satisfied the dc gain specification.
With 15 from 1024 OTAs with no code-words achieving the
gain specification, we estimate total yield at 98.5%. Second,
individual code-word yield can be calculated from the number
of OTAs that this particular code-word achieves the gain speci-
fications on. Table IV shows the code-word yields correspond-
ing to the predicted ideal self-coupled width range identified
in Table III. The ideal solution (code-word 99) calculated
analytically under no mismatch conditions is in the middle of
this range, with a high yield, and as shown in Fig. 3, second
top panel is in the middle of a cluster of high yield code-words.
7
Fig. 6. Distribution of dc gains from fixed width Nauta OTA simulated from
1024 Monte Carlo mismatch and process variation trials in 180-nm CMOS.
We find that each yielding OTA has on average ten-code
solutions, with an average minimum dc gain of 37 dB, with a
standard deviation of 1 dB, and an average maximum dc gain
of 47 dB, with standard deviation of 5 dB, as sampled over the
code-word solution set for all yielding OTAs. The maximum
dc gain achieved was 74 dB. This average maximum dc gain
of 47 dB is an 11-dB increase over the prediction in (1),
whilst the average minimum is the just above the value of the
initial gain specification of 36 dB, which was used to size the
feedforward transconductors. The width range of maximum
gain code-words corresponds to an implied WSC,variable in the
range from 620 to 1300 nm. This range covers the ideal value
of WSC,variable found in the Table III of 1135 nm.
Finally, by the way of comparison, we note that a nonpro-
grammable fixed width version of the OTA using the values
of WFF , WCC , WSC as listed in Table I only achieves a mean
dc gain of 44 dB with standard deviation of 10 dB, across
1024 Monte Carlo mismatch and process variation trials, with
a yield of 79% for the given gain specification of 36 dB.
This yield result assumes that no active biasing solutions are
used—which, however, can be attempted using a separate
tunable power supply for certain transconductors to tune the
transconductance and maximize gain. Fig. 6 shows the distrib-
utional shape of dc gains in this fixed width nonprogrammable
Nauta OTA.
V. C ALIBRATION OF THE P OSITIVE -F EEDBACK
G AIN -E NHANCEMENT OTA
Our approach to calibrating the digital Nauta OTA is
presented previously in [8] and [19]. This digital approach
requires on-chip calibration devices, which can locate the
maximum dc gain through a test voltage sweep, which detects
for the presence and width of hysteresis. The presence of
hysteresis is co-located with the point of maximum dc gain,
and the digital procedure finds the maximum acceptable
dc gain, whilst minimizing for the presence of hysteresis.
Currently, this requires the OTA to be calibrated in the
foreground periodically.
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8 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Fig. 7. Layout of the 180-nm digital Nauta OTA occupying 2400 μm2 , not
including the digital registers.
In contrast, the calibration approach in
Mondal and Krishnapura [20] introduces automatic on-chip
conductance tracking using test voltages and a differential
difference error amplifier. This introduces another feedback-
path into the positive-feedback gain-enhancement OTA
architecture that of the addition of a feedback path between
the differential output currents and the negative conductance
load. It requires a clocked chopper operation on the new
feedback path to alleviate device mismatch effects in the
threshold voltage of all the transconductors. This online
style of calibration is attractive option; however, a clocked
averaging circuit to reduce threshold voltage mismatch effects
can only achieve a modest increment in average dc gain,
since it is a passive mismatch cancelation technique [20].
Future work on digital calibration includes strategies for
classifying the gain directly, rather than assuming colocation
with hysteresis, and methods of comparing code-words.
Further techniques for background calibration will be required
for continuous output availability and linearization of voltage
to current conversion will be beneficial in the embedding of
the OTA into larger digitally assisted analog circuits.
VI. E XPERIMENTAL R ESULTS OF N = 8, M = 2
D IGITAL NAUTA OTA P ROTOTYPES
We show the layout of the prototype digital OTA in Fig. 7
in lieu of a micrograph of the die. This shows the analog
components only, without the digital registers holding the
programming code-word. Visible on the left are the three fixed
width transconductor components, and on the right is the array
of eight digitally programmable transconductors. The chips
were supplied with a power supply of VDD = 1.8 V.
Transconductance and output conductance curves were
measured on each prototype chip’s OTA (refer to Fig. 2)
via a programmable two-panel source measurement unit
utilizing a six-wire interface—four wires for the differential
input and ground and two wires for the differential output.
Transconductance was measured with the differential input
being swept across a range of voltages around the common
mode, (VDD /2), whilst keeping the differential output voltage
floating and measuring the differential output current. The
slope of the differential output current relative to the input
voltage range is the estimated transconductance.
Output conductance is measured by keeping the differential
input voltage at the common mode, sweeping the differential
output voltage around the common mode, and measuring the
output current. The slope of the differential output current rel-
ative to the output voltage is the estimate output conductance.
Both of these curves are interpolated by a linear regression
giving the estimated slopes and their standard errors.
We report the achieved open-loop dc gain from these two
derivatives and the standard error of the output conductance
using a conservative estimation function, to give the lower
bound of a 95% CI
 
μgm σgds
Av = 1− (17)
μgds μgds
where μgm is the measured mean transconductance, μgds is the
measured mean output conductance, and σgds is the standard
deviation of the output conductance as measured by the stan-
dard error reported by the linear regression function. We ignore
the standard error of the transconductance as in practice,
and this is much smaller relative to its mean that the output
conductance. This is due to the fact that the transconductance
values are not being changed appreciably over code-space,
since we have a large fixed width feedforward transconductor
irrespective of code-word, and second, that output conduc-
tance, as we approach the condition of maximum gain, is
approaching a theoretical value of zero. This measurement
in practice contains more variance than the transconductance,
as we approach the noise floor of measurement setup.
Transconductance and output conductance measurements
were conducted across the entire code-space of each OTA and
repeated three times. Linear dc gain is calculated by (17), then
averaged across the three experiments for each code.
Average power consumption when driven by a VDD /2
peak-to-peak differential sine wave in open-loop configuration
was 2.4 mA. This type of OTA structure has bias currents
dependent on the input signal. Thus, we estimate power at
the maximum expected range of the input signal amplitude.
Measured differential transconductance over ten prototype
chips had a mean of 1.9 mS, standard deviation of 22 μS,
at the maximum gain code-word, implying a single-ended
transconductance of the feedforward transconductors of
3.8 mS as compared with the design specification of 4 mS.
Maximum standard error of any individual mean
transconductance measurement across the maximum gain
code-word was 0.03%.
Average maximum dc gain across the ten chips was 60 dB
with the 95% CI calculated to be 54–64 dB. The maximum
gain codes corresponded to an ideal total variable width
solution range of 1070–1475 nm, compared with the analytical
solution of 1135 nm. The ten prototype chips had an average
of 25 code-words per OTA satisfying the gain requirement,
compared with our simulated average value of ten code-words.
Figs. 8 and 9 show a heat-map of dc gains measured
across all ten prototype chips, for two ranges of code-space.
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NICHOLSON et al.: STATISTICAL DESIGN APPROACH USING FIXED AND VARIABLE WIDTH TRANSCONDUCTORS
Fig. 8. Heat-map showing measured dc gains across ten prototype chips, inset 1280 nm to 1590 nm.
These heat-maps have been converted from code-word to
implied total variable transconductor width and sorted for
nonmonotonic increasing width. In some cases, due to the
nature of the encoding, some widths are duplicated, since some
code-words map to the same total variable transconductor
width, and in other cases, there are gaps. These heat-maps
clearly show the two bands of high dc gains around widths
1475 and 1135 nm. This shows that there are horizontal bands
of high dc gain solutions across the sampled prototype chips,
which indicates consistent code-word solutions across any
particular tape-out of the OTA.
Fig. 10 shows the estimated code yield across code-space as
measured across ten prototype chips. Due to the small sample
size, these code yields may be overestimating the achievable
code yields. To more accurately statistically quantify code
yield and overall chip yield, we would need to test more
prototype chips to build up confidence though a larger sample
size. However, the overall shape of the curve is similar to
the simulated one as shown in Fig. 3 second panel from
the top (M = 2). The two codes that are shown as 100%
yield correspond to code-word 99 (width 1135 nm), which
is the ideal code-word predicted from analysis in Section III
(Table IV) as well as code-word 199 (width 1475 nm). Both
of these codes we measured as having dc gain greater than the
specification across all ten chips.
Finally, we give the histogram of experimentally measured
open-loop dc gains across all ten prototype digital OTAs
9
in Fig. 11. Fig. 11 shows the long tail distribution of gains as
we see in the simulated digital OTAs represented in Fig. 4 and
in the fixed width Nauta OTA simulated by process variation
and mismatch Monte Carlo trials represented in Fig. 6. This
long tail is the behavior we want and expect such that a
calibration procedure can trim the amplifier into a high gain
code-word.
VII. T RADITIONAL OTA C OMPARISON
As a reference point to compare against our variation-aware
OTA architecture, we simulate an ac optimized traditional
analog OTA design in the 180-nm CMOS process as the digital
Nauta OTAs presented. The circuit is given by Binkley and the
OTA schematic is given in Fig. 12 [11].
All devices are minimum length as similar to the digital
Nauta OTAs under consideration, with widths chosen for the
fastest traditional OTA circuit. This standard input differential,
single-ended output OTA design has a mean of 2.9 GHz unity
gain bandwidth, a mean dc gain of 49 dB with standard
deviation of 2 dB—as simulated across 1024 mismatch and
process variation Monte Carlo statistical trials, refer to Fig. 13.
Fig. 13 shows the yield as measured by a gain specification
of 36 dB corresponding to the example in Section II. Note
that in comparison with the shape of dc gain distribution for
the Nauta OTA, the traditional distribution is approximately
normally distributed around the mean gain—there is no long
tail of high dc gains like in Figs. 4 and 6.
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10 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Fig. 9. Heat-map showing measured dc gains across ten prototype chips, inset 1030 nm to 1205 nm.

Fig. 10. Code yields as experimentally measured across the ten prototype Fig. 11. Histogram of experimentally measured open loop dc gains across
chips. all ten 8-bit 180 nm digital Nauta OTAs.

Core power consumption is 810 μW using a 1.8 V supply,

including voltage reference circuits, with an external current
reference at 50 μA. Silicon area is estimated at 1305 μm2 —
not including the required current reference and voltage
bias generation circuits. Binkley reported tape-out area at
1900 μm2 . Slew rate is limited by the small maximum output
current of twice the bias current set—in this example 100 μA.
Usable output voltage range is approximately 600 mV. This
design can only be calibrated for process variations postlayout
via adjusting dc bias conditions, and mismatch variations
cannot be corrected.
This contrasts against our digital Nauta OTA, which con-
sumes 4.5 mW using a 1.8 V supply, occupies 2400 μm2 in
total (not including the digital registers), has a 4.6 GHz unity
gain bandwidth and an average maximum dc gain of 60 dB.
This is a five times higher gain-bandwidth product than the
traditional OTA design. Expected differential output voltage
range is approximately 1 V using (2·VDD −4·VT −4·VDS,sat)—
this is enough voltage headroom to maintain both pMOS and
nMOS drivers turned ON whilst keeping the tristate transistors
still in strong inversion, using nominal values of VT = 420 mV
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
NICHOLSON et al.: STATISTICAL DESIGN APPROACH USING FIXED AND VARIABLE WIDTH TRANSCONDUCTORS
Fig. 12. Traditional OTA design in 180 nm CMOS simulated as comparative
reference design. From [11] © Wiley 2008. Reproduced with permission.
Fig. 13. DC gain distribution in Monte Carlo mismatch and process variation
trials of a traditional analog OTA design (given in Fig. 12) as simulated in
180-nm CMOS.
and VDS,sat = 200 mV for 180-nm CMOS. It can be calibrated
for mismatch and process variations postlayout by digital
programming and by adjusting dc bias conditions if required.
Thus, our digital Nauta OTA is capable of faster slew rates,
higher output voltage ranges, higher dc gains, and higher unity
gains at similar silicon areas with these advantages improving
in finer line-widths as the CMOS process scales down.
VIII. C ONCLUSION
The positive-feedback gain-enhancement OTA produced
using a statistical design framework to enable variation-aware
digital programmability is shown to be a viable solution
for digitally assisted analog circuit design scaling into deep
submicron CMOS. The digital Nauta OTA presented here is
a high-speed single-stage OTA capable of high dc gains, high
unity gain frequencies, and well placed for scaling into smaller
process nodes.
Our technique of using a tradeoff between redundancy and
range, through grid-spacing width differences in the design
11
TABLE V
C OMPARISON OF P UBLISHED CMOS OTAs W ITH T HIS PAPER . * N EXT TO
FoM VALUE I NDICATES A S IMULATION -O NLY R ESULT
of the digitally programmable variable width transconductor
ensures that we are robust to variations, and gives the calibra-
tion circuit enough code-space to find solutions to the device
matching problem.
Our results show that the grid-spacing strategy implies an
order of magnitude matching resolution improvement in max-
imum dc gain compared with the first-order dc gain estimate.
The prototype chip results show an average maximum gain
of 60 dB compared with the first-order dc gain estimate of
36 and 47 dB average maximum as simulated across process
and mismatch Monte Carlo trials.
Table V shows our measured results against previously
published work. The digital Nauta OTA is a high-speed, high
dc gain, and scalable solution for digitally assisted analog
OTA design with a state-of-the-art FoM.
R EFERENCES
[1] B. Murmann, P. Nikaeen, D. J. Connelly, and R. W. Dutton, “Impact of
scaling on analog performance and associated modeling needs,” IEEE
Trans. Electron Devices, vol. 53, no. 9, pp. 2160–2167, Sep. 2006.
[2] T. Ytterdal and C. Wulff, “On the energy efficiency of ana-
log circuits in nanoscale CMOS technologies,” in Proc. Int. Conf.
Microelectron. (ICM), Dec. 2008, pp. 240–243.
[3] P. G. Drennan and C. C. McAndrew, “Understanding MOSFET mis-
match for analog design,” IEEE J. Solid-State Circuits, vol. 38, no. 3,
pp. 450–456, Mar. 2003.
[4] A.-J. Annema, B. Nauta, R. van Langevelde, and H. Tuinhout, “Analog
circuits in ultra-deep-submicron CMOS,” IEEE J. Solid-State Circuits,
vol. 40, no. 1, pp. 132–143, Jan. 2005.
[5] P. R. Kinget, “Device mismatch and tradeoffs in the design of analog
circuits,” IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1212–1224,
Jun. 2005.
[6] B. Murmann, “Digitally assisted analog circuits,” IEEE Micro, vol. 26,
no. 2, pp. 38–47, Mar. 2006.
[7] A. N. Irfansyah, A. P. Nicholson, A. Iberzanov, J. Jenkins, T. Lehmann,
and T. J. Hamilton, “Automatic tuning of digitally-controllable positive-
feedback OTAs in continuous-time sigma–delta modulators,” Analog
Integr. Circuits Signal Process., vol. 89, no. 2, pp. 469–483, Nov. 2016.
[8] A. P. Nicholson, A. Iberzanov, J. Jenkins, T. J. Hamilton, and
T. Lehmann, “A statistical design approach for a digitally programmable
mismatch-tolerant high-speed Nauta structure differential OTA in 65-nm
CMOS,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 24,
no. 9, pp. 2899–2910, Sep. 2016.
[9] A. Nicholson et al., “A 0.3mm2 10-b 100MS/s pipelined ADC using
Nauta structure op-amps in 180nm CMOS,” in Proc. IEEE Int. Symp.
Circuits Syst. (ISCAS), May 2013, pp. 1833–1836.
[10] A. N. Irfansyah, L. Pham, A. Nicholson, T. Lehmann, J. Jenkins, and
T. J. Hamilton, “Nauta OTA in a second-order continuous-time delta-
sigma modulator,” in Proc. IEEE 57th Int. Midwest Symp. Circuits
Syst. (MWSCAS), Aug. 2014, pp. 849–852.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
12
[11] D. Binkley, Tradeoffs and Optimization in Analog CMOS Design.
Hoboken, NJ, USA: Wiley, 2008.
[12] T. McConaghy, K. Breen, J. Dyck, and A. Gupta, Variation-Aware
Design of Custom Integrated Circuits: A Hands-on Field Guide.
New York, NY, USA: Springer, 2012.
[13] J. Maunu, M. Pankaala, J. Marku, J. Poikonen, M. Laiho, and A. Paasio,
“Current source calibration by combination selection of minimum sized
devices,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2006,
pp. 549–552.
[14] K. Ragab, R. Gharpurey, and M. Orshansky, “Embracing local variability
to enable a robust high-gain positive-feedback amplifier: Design method-
ology and implementation,” in Proc. 13th Int. Symp. Quality Electron.
Design (ISQED), Mar. 2012, pp. 143–150.
[15] B. Nauta, Analog CMOS Filters for Very High Frequencies (The Kluwer
international series in engineering and computer science: Analog circuits
and signal processing). Norwell, MA, USA: Kluwer, 1993.
[16] A. N. Irfansyah, A. Nicholson, J. Jenkins, T. J. Hamilton, and
T. Lehmann, “Subthreshold operation of Nauta’s operational transcon-
ductance amplifier,” in Proc. IEEE 13th Int. New Circuits Syst.
Conf. (NEWCAS), Jun. 2015, pp. 1–4.
[17] A. Nicholson, J. Jenkins, A. van Schaik, T. J. Hamilton, and T. Lehmann,
“A digital to transconductance converter for Nauta structure op-amps
in 65nm CMOS,” in Proc. IEEE 57th Int. Midwest Symp. Circuits
Syst. (MWSCAS), Aug. 2014, pp. 173–176.
[18] B. Nauta, “A CMOS transconductance-C filter technique for very high
frequencies,” IEEE J. Solid-State Circuits, vol. 27, no. 2, pp. 142–153,
Feb. 1992.
[19] A. Iberzanov, A. Nicholson, J. Jenkins, T. Lehmann, and T. J. Hamilton,
“Calibration of the Nauta structure differential OTA,” in Proc. IEEE Asia
Pacific Conf. Circuits Syst. (APCCAS), Nov. 2014, pp. 189–192.
[20] I. Mondal and N. Krishnapura, “Gain enhanced high frequency OTA
with on-chip tuned negative conductance load,” in Proc. IEEE Int. Symp.
Circuits Syst. (ISCAS), May 2015, pp. 2085–2088.
[21] S. Chen, L. He, and L. Zhang, “High gain, high speed OTA for S/H
circuit in 14-b 100-MS/s pipeline ADC,” in Proc. 13th Int. Symp. Integr.
Circuits (ISIC), Dec. 2011, pp. 254–257.
[22] W. Yan, R. Kolm, and H. Zimmermann, “A low-voltage low-power fully
differential rail-to-rail input/output opamp in 65-nm CMOS,” in Proc.
IEEE Int. Symp. Circuits Syst. (ISCAS), May 2008, pp. 2274–2277.
[23] H. Uhrmann, F. Schlogl, K. Schweiger, and H. Zimmermann,
“A 1GHz-GBW operational amplifier for DVB-H receivers in 65nm
CMOS,” in Proc. 12th Int. Symp. Design Diagnostics Electron. Circuits
Syst. (DDECS), Apr. 2009, pp. 182–185.
[24] O. Abdelfattah, G. W. Roberts, I. Shih, and Y.-C. Shih, “An ultra-
low-voltage CMOS process-insensitive self-biased ota with rail-to-rail
input range,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 10,
pp. 2380–2390, Oct. 2015.
Andrew Peter Nicholson received the B.Eng.
degree (Hons.) in computer engineering from the
University of Newcastle, Callaghan, NSW, Australia,
the M.Eng. degree in electrical engineering from
the University of Sydney, Sydney, with specializing
in wireless. He is currently pursuing the Ph.D.
degree with the School of Electrical Engineering
and Telecommunications, at the University of
New South Wales, Australia, with a focus on
researching alternative analog design strategies in
nanometer CMOS.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Astria Nur Irfansyah received the B.Eng. degree in
electrical engineering from Gadjah Mada University,
Yogyakarta, Indonesia, in 2004, the M.Eng. degree
in electrical engineering from the University of
New South Wales, Sydney, NSW, Australia, where
he is currently pursuing the Ph.D. degree with the
School of Electrical Engineering and Telecommuni-
cations, with a research focus on digitally-assisted
sigma delta modulation circuits.
He has been on leave from the Institut Teknologi
Sepuluh Nopember, Surabaya, Indonesia, where he
is currently an Academic Staff with the Department of Electrical Engineering.
Julian Jenkins received the B.Sc. degree in
computer science and the B.Eng. degree in
electrical engineering from the University of
New South Wales, Sydney, NSW, Australia, in
1996 and 1997, respectively, where he is currently
pursuing the Ph.D. degree.
From 1997 to 2000, he was with Quality
Semiconductor Australia, Sydney, where he is
involved in working on 100-Mbps Ethernet.
In 2000, he joined Hiband Semiconductor, later
acquired by Cypress Semiconductor to focus on
3.5 Gbps SerDes. In 2005, he co-founded Perceptia Devices with a focus
on SerDes and PLLs in the 10-28-Gbps range. His current research interests
include designing analog circuits in sub 65-nm technologies with a focus on
SerDes, PLLs, DCOs, CDRs, and filters.
Tara Julia Hamilton (S’97–M’00) received the
B.E. degree (Hons.) in electrical engineering and
the B.Com. degree from the University of Sydney,
Sydney, NSW, Australia, in 2001, the M.Sc. degree
in biomedical engineering from the University of
New South Wales, Sydney, in 2003, and the Ph.D.
degree from the University of Sydney in 2008.
She is currently a Senior Research Lecturer in
biomedical engineering and neuroscience, MARCS
Institute, Western Sydney University, Penrith, NSW,
Australia. Her current research interests include neu-
romorphic engineering, mixed-signal integrated circuit design, and biomedical
engineering.
Torsten Lehmann (M’94–SM’06) received the
M.Sc. and Ph.D. degrees in electrical engineering
from the Technical University of Denmark, Lyngby,
Denmark, in 1991 and 1995, respectively, with a
focus on selflearning VLSI neural networks.
He spent two years as a Research Fellow with
the University of Edinburgh, Edinburgh, Scotland,
where he was with biologically inspired artificial
neural systems. From 1997 to 2000, he was an
Assistant Professor in electronics with the Technical
University of Denmark, where he was involved in
low-power, low-noise, low-voltage analog, and mixed analog-digital integrated
circuits. From 2001 to 2003, he was a Principal Engineer with Cochlear Ltd.,
Sydney, NSW, Australia, where he was involved in the design of the world’s
first fully implantable cochlear implant. He is currently an Associate Professor
in microelectronics with the University of New South Wales, Sydney, NSW,
Australia. He has authored over 100 journal papers, conference papers, book
chapters, and patents in integrated circuit design for a range of applications.
His current research interests are in solid-state circuits and systems (analog
and digital), biomedical microelectronics, ultralow temperature electronics,
nanometer CMOS, and green electronics.