Presented by

G NAVEEN KUMAR
(13011D0614)
DSCE
JNTU-CEH
CONTENTS
INTRODUCTION

WHY 3D IC

LIMITED PERFORMANCE OF 2D IC

COMPARISION OF 2D,3D

EVOLUTION IN 3D IC’S

3D IC ARCHITECTURE

MANUFACTURING TECHNOLOGY OF 3D IC’S

PERFORMANCE CHARACTERISTICS

CONCERNS IN 3D CIRCUITS

ADVANTAGES

 CONCLUSION
 INTRODUCTION

 A chip in three-dimensional integrated circuit (3D-

IC) technology is composed of two or more layers
of active electronic components, integrated both
vertically and horizontally into a single circuit.
Why 3D IC ?
 The large growth of computer and information
technology industry is depending on VLSI circuits
with increasing functionality and performance at
minimum cost and power dissipation and 2D ICs
generate various gate delays and interconnection
delay.
 So to reduce these delays and total power
consumption, 3D IC technology is introduced.
LIMITED PERFORMANCE OF 2D
ICs

 As we try to increase the performance and

efficiency of chip, the complexity of chip design
increases and this requires more and more
transistors. So the final size of the circuit and
delays increases.
 The losses increases with large interconnection
because the capacitance and resistances are
generated in between the clad and copper.
 COMPARISION OF 2D,3D

Metric 2D 3D Change

Total Area (mm2) 31.36 23.4 -25.3%

Total Wire Length 19.107 8.238 -56.9%

(m)
Max Speed (Mhz) 63.7 79.4 +24.6%

Power (mW) 340.0 324.9 -4.4%

3D IC ARCHITECTURE
What does it say
3D IC is a concept that can significantly :
 Improve interconnect performance

 Increase transistor packing density

 Reduce chip area

 Power dissipation

In 3D design structure the entire chip ‘Si’ is divided

by number of layers of oxide and metal, to form
transistors.
Manufacturing Technologies

There are four ways to built 3D IC

• Monolithic

• Wafer on wafer

• Die on wafer

• Die on die
Monolithic

Electronic components and their connections (wiring) are built

in layers on a single semiconductor wafer, which is then diced
into 3D ICs. There is only one substrate, hence no need for
aligning, thinning, bonding, or through-silicon vias.
2. Wafer on wafer
 Electronic components are built on two or more
semiconductor wafers, which are then aligned,
bonded, and diced into 3D ICs.
3. Die on wafer
Electronic components are built on two semiconductor wafers.
One wafer is diced aligned and bonded onto die sites of the
second wafer.
4.Die on die
Electronic components are built on multiple dice, which are
then aligned and bonded.
One advantage of die-on-die is that each component die can
be tested first, so that one bad die does not ruin an entire stack
PERFORMANCE
CHARACTERISTICS

1. TIMING
2. ENERGY

With shorter interconnects in 3D ICs, both switching

energy and cycle time are expected to be reduced
Benefits
 Foot Print
 Cost
 Heterogeneous Integration
 Shorter Interconnect
 Power
 Circuit Security
 Bandwidth
Advantages
 3D integration can reduce the wiring, thereby reducing
the capacitances, power dissipation and chip area
improves performance.
 Digital , analog circuits can be formed with better noise
performance.
 Reduced interconnect delays(R,L,C) and high clock rates
 High integration density (may go heterogeneous)
 High band width μ-processors and advanced focal planes
 The cost of a 3-D IC will be 10 times less than the
present ones.
Concerns In 3D Circuit

 Thermal Issues in 3D-circuits

 Reliability Issues
CONCLUSION

Many companies like MIT (USA), IBM are doing research

on 3D IC technology and they are going to introduce cheaper
chips for certain applications, like memory used in digital
cameras, cell phones, handheld gaming devices etc.

The original cost will be 10 times lesser than the current

ones.

3D ICs will be the first of a new generation of dense,

inexpensive chips having less delay and interconnection losses
that will replace the conventional storage and recording media.
QUERIES
THANK YOU