Professional Documents
Culture Documents
Mod 2
Mod 2
CIRCUIT DESIGN
PROCESSES
INTRODUCTION
• Objectives:
– To know MOS layers
– To understand the stick diagrams
– To learn design rules
– To understand layout and symbolic diagrams
• Outcome:
– At the end of this, will be able draw the stick
diagram, layout and symbolic diagram for simple
MOS circuits
• Objectives:
– To know what is meant by stick diagram.
– To understand the capabilities and limitations of
stick diagram.
– To learn how to draw stick diagrams for a given
MOS circuit.
• Outcome:
– At the end of this module the students will be able
draw the stick diagram for simple MOS circuits.
Metal 1
poly
ndiff
pdiff
Can also draw
in shades of
gray/line style.
Buried Contact
Contact Cut
NMOS ENCODING
UNIT – II CIRCUIT DESIGN PROCESSES
STICK DIAGRAMS
CMOS
ENCODING
Vdd = 5V Vdd = 5V
pMOS
Vin Vout Vin Vout
nMOS
X
x x x
x X
Gnd Gnd
Vdd = 5V
Vout
Vin
“Micron” rules
Problems in Manufacturing
• Photoresist shrinking / tearing
• Variations in material deposition
• Variations in temperature
• Variations in oxide thickness
• Impurities
• Variations between lots
• Variations across the wafer
Problems in Manufacturing
• Variations in threshold voltage
– oxide thickness
– ion implantation
– poly variations
• Diffusion - changes in doping (variation in R, C)
• Poly, metal variations in height and width
• Shorts and opens
• Via may not be cut all the way through
• Undersize via has too much resistance
• Oversize via may short
UNIT – II CIRCUIT DESIGN PROCESSES
DESIGN RULES
Metal
Diffusion
3λ
2λ 2λ Polysilicon
Metal
2λ
Diffusion
2λ 3λ Polysilicon
Metal
Diffusion
Metal
λ
Polysilicon
• Recall
– poly-poly spacing 2λ
– metal-metal spacing 2λ
– diff-poly spacing λ
Advantage:
No buried contact mask required and avoids associated processing.
Metal
Insulating
Oxide
n+ n+
PolySi
λ 2λ λ Channel length ±λ
Buried contact 2λ
Diffusion
UNIT – II CIRCUIT DESIGN PROCESSES
DESIGN RULES
Contact Cut
• Metal connects to polySi/diffusion by contact cut.
• Contact area: 2 λ X 2 λ
• Metal and polySi or diffusion must overlap this contact
area by l so that the two desired conductors encompass the
contact area despite any mis-alignment between
conducting layers and the contact hole
4λ
4λ
2λ
2λ
3λ
6λ
6λ
2λ
2λ
All device mask dimensions are based on multiples of λ, e.g., polysilicon minimum
width = 2λ. Minimum metal to metal spacing = 3λ
Metal 1
n-diffusion p-diffusion
3λ
2λ
3λ 3λ
2λ 3λ
Metal 2
2λ
4λ
2λ
2λ 4λ
Polysilicon
4λ
• Layer Types
– p-substrate
– n-well
– n+
– p+
– Gate oxide
– Gate (polysilicon)
– Field Oxide
• Insulated glass
• Provide electrical isolation
N+ N+
n+ n+ n+ n+ p+ p+ p+ p+
n-well
Shared drain/
source
Gnd
UNIT – II CIRCUIT DESIGN PROCESSES
LAYOUTS
Metal Interconnect Layers
• Metal layers are electrically isolated from each other
• Electrical contact between adjacent conducting layers requires contact cuts
and vias
Ox3
Via
Metal2
Active Ox2
contact
Metal1
Ox1
n+ n+ n+ n+
p-substrate
Metal1
Metal2
Metal1
MOS
Active contact
x y
A B C
x
UNIT – II CIRCUIT DESIGN PROCESSES
LAYOUTS
Parallel Connected MOS Patterning
x x
A B
A B
X X X
y
y
X X
A B
A B
X X
y y
UNIT – II CIRCUIT DESIGN PROCESSES
LAYOUTS
Basic Gate Design
• Both the power supply and ground are routed using the Metal
layer
• n+ and p+ regions are denoted using the same fill pattern. The
only difference is the n-well
• Contacts are needed from Metal to n+ or p+
X
x x
x X
X
Gnd
Gnd
X X
x x
X X
Gnd
x Gnd
x
Vp Vp
X X X
a.b
Gnd
a.b
a b
X X
a b
Gnd
Vp
Vp
X X
a+ b
a +b
a b X
Gnd X X
a b
Gnd
• Efficient routing space usage. They can be placed over the cells
or even in multiple layers.
4. Floor Planning
5. Routing, Placement
6. On to Silicon
UNIT – II CIRCUIT DESIGN PROCESSES
ANY Qs?