Computer Engineering 200280107139

Practical-1

AIM: Implement Register transfer operation in Logisim simulator.

Computer registers are designated by capital letters (sometimes

followed by numerals) to denote the function of the register. For
example, the register that holds an address for the memory unit is
usually called a memory address register and is designated by the
name MAR. Other designations for registers are PC (for program
counter), IR (for instruction register, and R1 (for processor register).
For data to be processed it has to first be transferred through
several registers.

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Practical-2

AIM: Implement ALU Circuit in Logisim simulator.

The arithmetic logic unit (ALU) performs the required

microoperations for executing the instructions. The control unit
supervises the transfer of information among the registers and
instructs the ALU as to which operation to perform.

The operation selected in the ALU determines the arithmetic or

logic microoperation that is to be performed. The result of the
microoperation is available for output data and also goes into the
inputs of all the registers. The register that receives the information
from the output bus is selected by a decoder. The decoder activates
one of the register load inputs, thus providing a transfer path
between the data in the output bus and the inputs of the selected
destination register. The control unit that operates the CPU bus
system directs the information flow through the registers and
ALU by selecting the various components in the system.

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L. D. College of Engineering
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Practical-3
AIM: Implement Common Bus System in Logisim simulator.
A typical digital computer h a s many registers, and paths must b e
provided to transfer information from one register to another. The
number of wires will be excessive if separate lines are used
between each register and all other registers in the system. A more
efficient scheme for transferring information between registers in a
multiple-register configuration is a common bus system. A bus
structure consists of a set of common lines, one for each bit of a
register, through which binary information is transferred one at
a time. Control signals determine which register is selected by the
bus during each particular register transfer.

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Practical-4

Aim: Write Assembly language Program to implement subtraction

between two number using 2's complement - in GNU Simulator

Theory: In 8085, the SUB instruction is used 2’s complemented

method for subtraction. When the first operand is larger, the result
will be positive. It will not enable the carry flag after completing the
subtraction. When the result is negative, then the result will be in
2’s complemented form and carry flag will be enabled. 
We are using two numbers at location 8000H and 8001H. When the
numbers are 78H and 5DH, then the result will be (78 – 5D = 1B)
and when the numbers are 23H and CFH, then the result will be (23
– CF = 154) Here 1 indicates the number is negative. The actual
result is 54H. It is in 2’s complemented form.

Instructions:

LDA 2050H
MOV B,A
LDA 2051H
CMA
INR A
ADD B
STA 2052H
HLT

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L. D. College of Engineering
 Computer Engineering 200280107139

Practical-5
Aim: Write Assembly language Program to implement
Multiplication Algorithm between two numbers - in GNU Simulator
(Using Circular Right and Circular Left Instruction)
Theory:
1. Set the Multiplicand and Multiplier binary bits as M and Q,
respectively.
2. Initially, we set the AC and Qn + 1 registers value to 0.
3. SC represents the number of Multiplier bits (Q), and it is a
sequence counter that is continuously decremented till equal to the
number of bits (n) or reached to 0.
4. A Qn represents the last bit of the Q, and the Qn+1 shows the
incremented bit of Qn by 1.
5. On each cycle of the booth algorithm, Qn and Qn + 1 bits will
be checked on the following parameters as follows:
0. When two bits Qn and Qn + 1 are 00 or 11, we simply
perform the arithmetic shift right operation (ashr) to the partial
product AC. And the bits of Qn and Qn + 1 is incremented by 1 bit.
i. If the bits of Qn and Qn + 1 is shows to 01, the multiplicand
bits (M) will be added to the AC (Accumulator register). After that,
we perform the right shift operation to the AC and QR bits by 1.
ii. If the bits of Qn and Qn + 1 is shows to 10, the multiplicand
bits (M) will be subtracted from the AC (Accumulator register).
After that, we perform the right shift operation to the AC and QR
bits by 1.
6. The operation continuously works till we reached n - 1 bit in
the booth algorithm.
7. Results of the Multiplication binary bits will be stored in the
AC and QR registers.

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Instructions:
MVI C,08H
LXI H,2052H
UP: STC
CMC
LDA 2051H
RAR
STA 2051H
JNC ZRO
LDA 2050H
ADD M
STA 2052H
STC
CMC
ZRO: LDA 2050H
RAL
STA 2050H
DCR C
JNZ UP
HLT

L. D. College of Engineering
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 Computer Engineering 200280107139

Practical-6

Aim: Implement the flowchart of signed magnitude addition and

subtraction in logisim Simulator
• The two signs A, and B, are compared by an
• exclusive-OR gate.
• If the output of the gate is 0 the signs are identical;
• If it is 1, the signs are different.
• For an add operation, identical signs dictate that the magnitudes
be added. For a subtract operation, different signs dictate that the
magnitudes be added.
• The magnitudes are added with a microoperation EA  A + B,
where EA is a register that combines E and A. The carry in E after
the addition constitutes an overflow if it is equal to 1. The value of
E is transferred into the add-overflow flip-flop AVF.

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• The two magnitudes are subtracted if the signs are different for
an add operation or identical for a subtract operation. The
magnitudes are subtracted by adding A to the 2's complemented B.
No overflow can occur if the numbers are subtracted so AVF is
cleared to 0.
• 1 in E indicates that A >= B and the number in A is the correct
result. If this numbs is zero, the sign A must be made positive to
avoid a negative zero.
• 0 in E indicates that A < B. For this case it is necessary to take
the 2's complement of the value in A. The operation can be done
with one microoperation A A' +1.
• However, we assume that the A register has circuits for
microoperations complement and increment, so the 2's complement
is obtained from these two microoperations.
• In other paths of the flowchart, the sign of the result is the same
as the sign of A. so no change in A is required. However, when A <
B, the sign of the result is the complement of the original sign of A.
It is then necessary to complement A, to obtain the correct sign.
• The final result is found in register A and its sign in As. The
value in AVF provides an overflow indication. The final value of E
is immaterial.
• Figure shows a block diagram of the hardware for implementing
the addition and subtraction operations.
• It consists of registers A and B and sign flip-flops As and Bs.
• Subtraction is done by adding A to the 2's complement of B.
• The output carry is transferred to flip-flop E , where it can be
checked to determine the relative magnitudes of two numbers.
• The add-overflow flip-flop AVF holds the overflow bit when A
and B are added.
• The A register provides other microoperations that may be
needed when we specify the sequence of steps in the algorithm.

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Practical-7
Aim: Implement the flowchart of signed magnitude multiplication
in logisim Simulator

 When multiplication is implemented in a digital computer, it is

convenient to change the process slightly.
First, instead of providing registers to store and add
simultaneously as many binary numbers as there are bits in the
multiplier, it is convenient to provide an adder for the summation of
only two binary numbers and successively accumulate the partial
products in a register.
Second, instead of shifting the multiplicand to the left, the
partial product is shifted to the right, which results in leaving the
partial product and the multiplicand in the required relative
positions.
Third, when the corresponding bit of the multiplier is 0,
there is no need to add all zeros to the partial product since it will
not alter its value. The hardware for multiplication consists of the
equipment shown in Fig. plus two more registers. These registers
together with registers A and B are shown in Fig. The multiplier is
stored in the Q register and its sign in Q.
The sequence counter SC is initially set to a number equal
to the number of bits in the multiplier. The counter is decremented
by 1 after forming each partial product. When the content of the
counter reaches zero, the product is formed and the process stops.
Initially, the multiplicand is in register B and the multiplier in Q.
The sum of A and B forms a partial product which is transferred to
the EA register. Both partial product and multiplier are shifted to the
right. This shift will be denoted by the statement shr EAQ to

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designate the right shift depicted in the given figure.

Least significant bit of A is shifted into the most significant

position of Q, the bit from E is shifted into the most significant
position of A, and 0 is shifted into E. After the shift, one bit of the
partial product is shifted into Q, pushing the multiplier bits one
position to the right. In this manner, the rightmost flip-flop in
register Q, designated by Q., will hold the bit of the multiplier,
which must be inspected next.

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Practical-8

Aim: Implement of General Register Organisation in LOGISIM.

A set of flip-flops forms a register. A register is a unique high-speed
storage area in the CPU. They include combinational circuits that
implement data processing. The information is always defined in a
register before processing. The registers speed up the
implementation of programs. Registers implement two important
functions in the CPU operation are as follows It can support a
temporary storage location for data. This supports the directly
implementing programs to have fast access to the data if required. It
can save the status of the CPU and data about the directly
implementing program.

Example: Address of the next program instruction, signals get from

the external devices and error messages, and including different data
is saved in the registers. If a CPU includes some registers, therefore
a common bus can link these registers. A general organization of
seven CPU registers is displayed in the figure.

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L. D. College of Engineering
 Computer Engineering 200280107139

Practical-9

Aim: To explore various types of Addressing Modes in GNU

Simulator 8085

The addressing mode specifies a rule for interpreting or modifying

the address field of the instruction before the operand is actually
referenced. Computers use addressing mode techniques for the
purpose of accommodating one or both of the following provisions:
To give programming versatility to the user by providing such
facilities as pointers to memory, counters for loop control, indexing
of data, and program relocation. To reduce the number of bits in the
addressing field of the instruction. There are basic 10 addressing
modessupported by the computer.
1. Implied Mode
2. Immediate Mode
3. Register Mode
4. Register Indirect Mode
5. Autoincrement or Autodecrement Mode
6. Direct Address Mode
7. Indirect Address Mode
8. Relative Address Mode
9. Indexed Addressing Mode
10.Base Register Addressing Mode

1. Implied Mode
Operands are specified implicitly in the definition of the
instruction.
For example, the instruction “complement accumulator (CMA)” is
an implied-mode instruction because the operand in the accumulator
register is implied in the definition of the instruction. In fact, all

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register reference instructions that use an accumulator and zero

address instructions are implied mode instructions.

2. Immediate Mode
Operand is specified in the instruction itself. In other words, an
immediate-mode instruction has an operand field rather than
an address field. The operand field contains the actual operand to be
used in conjunction with the operation specified in the instruction.
Immediate mode of instructions is useful for initializing register to
constant value. E.g. MOV R1, 05H instruction copies immediate
number 05H to R1 register.

3. Register Mode
Operands are in registers that reside within the CPU. The
particular register is selected from a register field in the instruction.
E.g. MOV AX, BX move value from BX to AX register

4. Register Indirect Mode

In this mode the instruction specifies a register in the CPU
whose contents give the address of the operand in memory.
Before using a register indirect mode instruction, the programmer
must ensure that the memory address of the operand is placed in the
processor register with a previous instruction. The advantage of this
mode is that address field of the instruction uses fewer bits to select
a register than would have been required to specify a memory
address directly. E.g. MOV [R1], R2 value of R2 is moved to the
memory location specified in R1.

5. Autoincrement or Autodecrement Mode

This is similar to the register indirect mode expect that the
register is incremented or decremented after (or before) its value is

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used to access memory. When the address stored in the register

refers to a table of data in memory, it is necessary to increment or
decrement the register after every access to the table. This can be
achieved by using the increment or decrement instruction.

6. Direct Address Mode

In this mode the effective address is equal to the address part of
the instruction. The operand resides in memory and its address is
given directly by the address field of the instruction. E.g. ADD 457

7. Indirect Address Mode

In this mode the address field of the instruction gives the
address where the effective address is stored in memory. Control
fetches the instruction from memory and uses its address part to
access memory again to read the effective address. The effective
address in this mode is obtained from the following computational:
Effective address = address part of instruction + content of CPU
register

8. Relative Address Mode

In this mode the content of the program counter is added to the
address part of the instruction in order to obtain the effective
address. The address part of the instruction is usually a signed
number which can be either positive or negative.
Effective address = address part of instruction + content of PC

9. Indexed Addressing Mode

In this mode the content of an index register is added to the
address part of the instruction to obtain the effective address. The
indexed register is a special CPU register that contain an index
value. The address field of the instruction defines the beginning

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address of a data array in memory. Each operand in the array is

stored in memory relative to the beginning address.
Effective address = address part of instruction + content of index
register
10. Base Register Addressing Mode
In this mode the content of a base register is added to the
address part of the instruction to obtain the effective address. A base
register is assumed to hold a base address and the address field of
the instruction gives a displacement relative to this base address.
The base register addressing mode is used in computers to facilitate
the relocation of programs in memory. Effective address = address
part of instruction + content of base register

Types of Addressing Modes

MVI A, 09H
; Immediate Mode of Addressing
MVI B, 10H
ADD B
; Register Mode of Addressing
STA 2050H
; Direct Mode of Addressing
MVI A, 99H
MVI D, 50H
MVI E, 00H
STAX D
; Indirect Mode of Addressing
LXI H, 3000H
MOV A, M
; Register Indirect Mode of Addressing
INX H

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MOV B, M
; Register Indirect Mode of Addressing
ADD B
HLT

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Practical-10

Aim: To explore various types of Flags in GNU Simulator 8085

1. Sign Flag (S) - After any operation if the MSB (B(7)) of the
result is 1, it indicates the number is negative and the sign flag
becomes set, i.e. 1. If the MSB is 0, it indicates the number is
positive and the sign flag becomes reset i.e. 0. from 00H to 7F, sign
flag is 0 from 80H to FF, sign flag is 1 1- MSB is 1 (negative) 0 -
MSB is 0 (positive) Example: MVI A 30 (load 30H in register A)
MVI B 40 (load 40H in register B) SUB B (A = A - B) These set of
instructions will set the sign flag to 1 as 30 - 40 is a negative
number. MVI A 40 (load 40H in register A) MVI B 30 (load 30H in
register B) SUB B (A = A - B) These set of instructions will reset
the sign flag to 0 as 40 - 30 is a positive number.

SIGN Flag
MVI A, 80H
MVI B, 09H
ADD B
HLT

2. Zero Flag (Z) - After any arithmetical or logical operation if the

result is 0 (00)H, the zero flag becomes set i.e. 1, otherwise it
becomes reset i.e. 0. 00H zero flag is 1. from 01H to FFH zero flag
is 0 1- zero result 0- non-zero result Example: MVI A 10 (load 10H
in register A) SUB A (A = A - A) These set of instructions will set
the zero flag to 1 as 10H - 10H is 00H

ZERO Flag
MVI A, 10H

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MVI B, 10H
SUB B
HLT

3. Auxiliary Carry Flag (AC) - This flag is used in BCD number

system(0-9). If after any arithmetic or logical operation D(3)
generates any carry and passes on to D(4) this flag becomes set i.e.
1, otherwise it becomes reset i.e. 0. This is the only flag register
which is not accessible by the programmer 1-carry out from bit 3 on
addition or borrow into bit 3 on subtraction 0-otherwise Example:
MOV A 2B (load 2BH in register A) MOV B 39 (load 39H in
register B) ADD B (A = A + B) These set of instructions will set the
auxiliary carry flag to 1, as on adding 2B and 39, addition of lower
order nibbles B and 9 will generate a carry.

AUXILLARY CARRY Flag

MVI A, 88H
MVI B, 98H
ADD B
HLT

4. Parity Flag (P) - If after any arithmetic or logical operation the

result has even parity, an even number of 1 bits, the parity register
becomes set i.e. 1, otherwise it becomes reset i.e. 0. 1-accumulator
has even number of 1 bits 0-accumulator has odd parity Example:
MVI A 05 (load 05H in register A) This instruction will set the
parity flag to 1 as the BCD code of 05H is 00000101, which
contains even number of ones i.e. 2.

PARITY Flag
MVI A, 80H

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MVI B, 08H
ADD B
HLT

5. Carry Flag (CY) - Carry is generated when performing n bit

operations and the result is more than n bits, then this flag becomes
set i.e. 1, otherwise it becomes reset i.e. 0. During subtraction (A-
B), if A>B it becomes reset and if (A<B) it becomes set. Carry flag
is also called borrow flag. 1-carry out from MSB bit on addition or
borrow into MSB bit on subtraction 0-no carry out or borrow into
MSB bit Example: MVI A 30 (load 30H in register A) MVI B 40
(load 40H in register B) SUB B (A = A - B) These set of instructions
will set the carry flag to 1 as 30 - 40 generates a carry/borrow. MVI
A 40 (load 40H in register A) MVI B 30 (load 30H in register B)
SUB B (A = A - B) These set of instructions will reset the sign flag
to 0 as 40 - 30 does not generate any carry/borrow.

Carry Flag
MVI A, 80H
MVI B, 99H
ADD B
HLT

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