Velagapudi Ramakrishna Siddhartha Engineering College::Vijayawada

(Autonomous)
II/IV B Tech Degree Examination VR20
Third Semester 0
Department of Electronics and communication Engineering
20EC3302 – Analog Electronics
Time: 3Hrs MODEL QUESTION PAPER Max Marks: 70

Part – A is Compulsory
Answer one (01) question from each unit of Part – B
Answers to any single question or its part shall be written at one place only
Cognitive Levels(K): K1-Remember; K2-Understand; K3-Apply; K4-Analyze; K5-Evaluate; K6-Create
Q. No Question Marks Course Cog.
Outcome Level
Part - A 10X1=10M
1 a Define ℎ-parameters of a transistor in CC configuration. 1M CO1 K1

b What are the harmonic components in rectifier? 1M CO1 K1

c Compare enhancement and depletion MOSFET. 1M CO1 K2

d What is the need of biasing? 1M CO2 K1

e Explain the importance of bypass capacitor in CE amplifier. 1M CO2 K2

f Classify different types of couplings used in multistage 1M CO3 K2

amplifiers.

g What is the relationship between 𝐴, 𝛽, and 𝐴𝑓 for negative 1M CO3 K1

feedback amplifiers.

h What is the need of multistage amplifiers? 1M CO3 K1

I Summarize the advantages of power amplifier in class-B 1M CO4 K2

operation mode.

j Why RC Phase shift oscillators are not used at high 1M CO4 K1

frequencies.

Part - B 4X15
=60M
UNIT - I
2 a A sinusoidal voltage whose vm = 12V is applied to half-wave 7M CO1 K4
rectifier. The diode may be considered to be ideal and 𝑅𝐿 =
1.5 𝐾𝛺 is connected as load. Examine the peak value of
current, RMS value of current, DC value of current and ripple
factor.

b Relate the expressions for ripple factor and efficiency with 8M CO1 K2
 respect to full wave bridge rectifier.

(OR)
3 a Demonstrate the input & output characteristics of a BJT in 7M CO1 K2
Common-emitter configuration.

b Analyze the construction and operation of an n-channel depletion 8M CO1 K4

MOSFET with the help of characteristics

UNIT – II
4 a Justify statement “Potential divider bias is the most commonly 7M CO2 K5
used biasing method” for BJT circuits. Explain how bias
compensation can be done in such biasing through diodes.

b Build a self-bias circuit for the following specifications: 8M CO2 K3

V = 12 V; V = 2V; I = 4mA; h = 80. Assume any other
CC CE C fe
design parameters required. Draw the designed circuit.
(OR)
5 a Model the common emitter amplifier using h-parameter model 7M CO2 K3
and derive the expressions for voltage gain, current gain, input
impedance and output impedance.

b The h-parameters of the transistor in CE amplifier circuit with 8M CO2 K5

RE are hie=1.1kΩ, hfe=50, hoe=25*10-6 A/V, hre=2.5*10-4 and
the circuit parameters are R1=100KΩ, R2=10KΩ, RE=1KΩ,
RL=5KΩ. Evaluate AI, AV, Ri, Ro.

UNIT – III
6 a Construct a two stage cascaded CE amplifiers and model the 8M CO3 K3
expression for overall gain in multistage amplifiers.

b Analyze the two stage cascaded amplifier circuit using an 7M CO3 K4

approximate model and obtain the value for the overall voltage
gain if ℎ𝑖𝑒 = 1𝐾Ω, ℎ𝑓𝑒 = 50, ℎ𝑟𝑒 = ℎ𝑜𝑒 = 0.

(OR)
7 a Analyze the concept of feedback and its effect on the 7M CO3 K4
characteristics of amplifiers.

b Find the voltage gain, input and output impedance of negative 8M CO3 K1
feedback amplifier having 𝐴𝑉 = 100, 𝑅𝑖 = 10𝐾Ω, and𝑅𝑜 =
20𝐾Ω, with a feedback factor 𝛽 = 0.1.

UNIT – IV
8 a Select the basic circuit of LC oscillator and find the general 7M CO4 K1
condition for frequency of oscillation.

b Discover the capacitor C and hfe for the transistor to provide a 8M CO4 K4
 resonating frequency of 10KHz with RC phase shift oscillator.
Given parameters are 𝑅𝑖 = 25 𝐾Ω, 𝑅2 = 60 𝐾Ω, 𝑅𝑐 =
40 𝐾Ω, 𝑅 = 7.1 𝐾Ω 𝑎𝑛𝑑 ℎ𝑖𝑒 = 1.8𝐾 Ω.

(OR)
9 a A single transistor is acting as ideal Class B amplifier with 7M CO4 K3
load of 1KΩ, if DC collector current is 15mA, VCC=20V.
Solve its efficiency.

b Infer the conversion efficiency of a class A transformer 8M CO4 K4

coupled power amplifier is 50%.

Designation Name in Capitals Signature with Date

Course Coordinator Dr. G. Suryanarayana
Program Coordinator Dr. M. Padmaja
Head of the Department Dr. D. Venkata Rao
 VELAGAPUDI RAMAKRISHNA
SIDDHARTHA ENGINEERING COLLEGE::VIJAYAWADA
(AUTONOMOUS)
Dt.12-06-2019

GUIDELINES FOR FRAMING MODEL QUESTION PAPER

The model papers for all subjects in a semester are gathered from the departments whenever a
course is offered for the first time adopting new regulation. All the Heads of the Departments are
requested to direct their faculty to strictly adhere to the following guidelines while framing the model
question papers for the subjects of UG and PG courses in the new curriculum.

1. Questions must be covered unit-wise uniformly as per the syllabus without missing the
competency.

2. The question paper shall reflect the Bloom’s Cognitive Levels of Learning.
Cognitive Levels (K): K1-Remember; K2-Understand; K3-Apply; K4-Analyze; K5-Evaluate; K6-Create

 The composition of question paper shall have questions at different complexity levels as listed
below:
 Questions that can be attempted by an average student (K1 & K2) 40%
 Questions of intermediate complexity (K3 & K4) 40-50%
 Questions of design and application oriented nature (K5 & K6) 10-20%

3. Question paper is to be set conforming to the OBE pattern clearly mentioning the Course Outcomes
and Bloom’s Cognitive Levels against each question.

4. The questions are to be set with minimum 2 sub-questions (a) & (b) for each main question
to the extent possible covering entire syllabus in the unit.

5. Specify the marks against each question / part of a question in Part B.

6. The figures, if any, may be computer aided or neatly drawn with black pen indicating clearly the
values/dimensions.

7. Prepare the one mark questions in only sentence form. Answers to these questions must be unique
and having short answers limited to three/four lines.

PRINCIPAL