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Tulsiramji Gaikwad-Patil College of Engineering and Technology
Tulsiramji Gaikwad-Patil College of Engineering and Technology
Tulsiramji Gaikwad-Patil College of Engineering and Technology
A. 1 B. 2 C. 3 D. 4
A. Is the simplest of semiconductor devices B. Has characteristics that closely match those of a simple
switch C. Is a two terminal device D. All the above
Q3. Which of the following elements are most frequently used for doping pure Ge or Si ?
Q4. In which of the following state does the silicon diode has the voltage drop of 0.7V
Q5. ________are electronic circuits which give constant DC output voltage, irrespective of variations in Input
Voltage V, current drawn by the load I from output terminals
Q6. _____ is a device in which there is a transfer of resistance from input side which is forward biased (low
resistance) to output side which is reverse biased (high resistance)
Q7. Which of the following regions are part of the output characteristics of a transistor?
Q8. In which of the following region, both the collector base & base emitter junctions are forward biased ?
Q9. In which of the following region, the collector base junction is reverse biased & base emitter junction is
reverse biased
Q11. The decrease in base width with increase in collector reverse bias voltage is known as ____
Department of EE
TGPCET/EE
Q14. _________ is a semiconductor device which depends for its operation on the control of current by an
electric field
A. Oscillators
B. Filters
C. Instrumentation circuits
A. Oscillators
B. Filters
C. Instrumentation circuits
Department of EE
TGPCET/EE
Q19. A voltage-follower amplifier comes to you for service. You find the voltage gain to be 5.5 and the input
impedance 22 k. The probable fault in this amplifier, if any, is
D. none of these
Q20. For an op-amp having a slew rate SR = 5 V/ms, what is the maximum closed-loop voltage gain that can be
used when the input signal varies by 0.2 V in 10 ms?
A. 150
B. 200
C. 250
D. 300
Q21. An op-amp has an open-loop gain of 100,000 and a cutoff frequency of 40 Hz. Find the open-loop gain at a
frequency of 30 Hz.
A. 800
B. 8,000
C. 80,000
D. 100,000
Q22. What is the level of the voltage between the input terminals of an op-amp?
A. Virtually zero
B. 5V
C. 18 V
D. 22 V
Q23. An op-amp has an open-loop gain of 75,000 and a cutoff frequency of 100 Hz. At 1 kHz the open-loop gain
is down by
A. 10 dB.
B. 6 dB.
C. 20 dB.
Department of EE
TGPCET/EE
D. 3 dB.
Q24. What is the difference output voltage of any signals applied to the input terminals?
C. The sum of the differential gain times the difference input voltage and the common-mode gain times
the common input voltage.
D. The difference of the differential gain times the difference input voltage and the common-mode gain
times the common input voltage.
Q25. _________ circuit converts the electrical energy in the form of DC into electrical energy in the form of AC
Q26. Which of the following expressions represents the correct distribution of the electrons in the conduction
band? (gc(E)=density of quantum states, fF(E)=Fermi Dirac probability
Q27. In a semiconductor which of the following carriers can contribute to the current?
A. True
B. False
Q28. What is the open-loop gain of an op-amp at the gain-bandwidth product of the op-amp?
A. 200,000
B. 50,000
C. 200
D. 1
A. 154 Hz
B. 1540 Hz
C. 1.54 Hz
Department of EE
TGPCET/EE
D. 15.4 Hz
A. 154 Hz
B. 1540 Hz
C. 1.54 Hz
D. 15.4 Hz
Q31. Calculate the ripple voltage of a full-wave rectifier with a 75-F filter capacitor connected to a load drawing
40 mA.
A. 1.20 V
B. 1.28 V
C. 1.32 V
D. 1.41 V
Q32. In which period is the capacitor filter discharged through the load in a full-wave rectifier?
Q33. Calculate the voltage regulation of a power supply having VNL = 50 V and VFL = 48 V.
A. 4.17%
B. 5.2%
C. 6.2%
D. 7.1%
A. 60
B. 70
C. 80
Department of EE
TGPCET/EE
D. 90
Q35. If a peak rectified voltage for the full-wave filter circuit is 40 V, calculate the filter dc voltage if C = 75 F and
load current is 40 mA.
A. 27.9 V
B. 32.12 V
C. 37.78 V
D. 40 V
Q36. The code where all successive numbers differ from their preceding number by single bit is
__________
a) Alphanumeric Code
b) BCD
c) Excess 3
d) Gray
Q37. The NOR gate output will be high if the two inputs are __________
a) 00
b) 01
c) 10
d) 11
Q38. A universal logic gate is one which can be used to generate any logic function. Which of the
following is a universal logic gate?
a) OR
b) AND
c) XOR
d) NAND
Department of EE