Lesson 37

Digital arithmetic operations and circuits

Representation of binary numbers in hardware
In binary machines, the binary numbers are represented
by a set of binary storage devices, usually FFs. Each FF
represents one bit. Numbers have a magnitude as well as
a sign (positive or negative). Since most digital
computers and calculators handle positive as well as
negative numbers, some means is required for
representing the sign of the number. This is usually done
by adding another bit, called sign bit, to the number at its
leftmost position. The common convention which has
been adopted is that a 0 in the sign bit represents a
positive number, and a 1 in the sign bit represents a
negative number. This is illustrated in the Figure 1.

Here the leftmost bit is the sign bit. The six bits A0 -A5
or B0 – B5 are the magnitudes of the number 1101102
which is equal to 52 in decimal. In positive numbers,
the rest of the bits always represent the magnitude of
the number in binary form.
In negative numbers, however, there are three possible
ways in representing the magnitude: They are,
True-magnitude form,
1’s-complement form, and
2’s-complement form.

True-magnitude form
When representing numbers in true magnitude form, the
magnitude bits represent the true equivalent of the
decimal values whether it is a positive or a negative
number. We call this the true-magnitude form for
representing sign numbers. However, this true magnitude
form is not as useful as the other two systems (i.e. 1’s-
complement form, and 2’s-complement form) for
representing negative numbers.
1’s-Complement form
1’s-complement of any number is obtained by changing
each 0 in the number to a 1and each 1 in the number to a
0. In other words, change each bit to its complement.
Example: 1’s-complement of 101101 is 010010.
When negative numbers are presented in 1’s-
complement form, the sign bit is made a 1, and
magnitude is converted from true-magnitude form to its
1’s-complement.
This can be illustrated with the decimal number – 57 as
follows.

Note that sign bit is not complemented but kept as 1 to

indicate that it is a negative number.
2’s-Complement form
The 2’s-complement form of a binary number is formed
by taking the 1’s-complement of the number first and
then adding 1 to the least significant bit (LSB) position.
The procedure is illustrated below by converting 111001
(decimal 57) to its 2’s-complement

All three forms are currently used in digital systems.

However, when performing mathematical operations
with modern digital systems, the negative numbers are
always represented in either 1’s- or 2’s- complement
form.
The 2’s-complement representation, however, has one
more advantage that it allows us to perform the operation
of subtraction also as an operation of addition. This is
significant because it means that the same digital
hardware can be used to perform both addition and
subtraction.
As a summary, the three systems for representing
signed binary numbers are given below.

Note that all three systems are identical when

representing positive numbers

Addition in the 2’s- complement system

Some examples
Addition of -9 and +4
Remember 2’s- complement of +4 is equal to its true-
magnitude, but 2’s-complemet of -9 must be worked
out since it is a negative number. When converted, the
2’s- complement of -9 will become 1 0111

To find out the true magnitude of the 2’s- complement of

the negative number 1011, first convert it to 1’s-
complement form and then add 1 to the LSB position.

Since it is a negative number, answer is -5.

Addition of two negative numbers -9 and -4

Subtraction in 2’s-complement system
As mentioned earlier, the subtraction operation using the
2’s-complement actually involves the operation of
addition. When subtracting one binary number (called
the subtrahend) from another binary number (called the
minuend), first take the 2’s-complement of the
subtrahend. This will change it to a negative number in
2’s-complement form.
If the subtrahend is a negative number, this will
change it to a positive number in true-binary form.
After taking the 2’s-complement of the subtrahend, it is
added to the minuend.
Subtraction of +4 from +9
Arithmetic circuits
One essential function of computers and calculators is
the performance of arithmetic operations. These
operations are performed in the arithmetic unit of the
computer, where logic gates and FFs are combined so
that they can add, subtract, multiply and divide binary
numbers.

Lesson 38
Arithmetic Unit
Figure 2 is a block diagram showing the major elements
included in a typical arithmetic unit. The main purpose
of the arithmetic unit is to accept binary data that are
stored in the memory and to execute arithmetic
operations on these data according to the instructions
from the control unit.
The arithmetic unit contains at least two flip-flop
registers; the B register and the accumulator which is
also called A register. It also contains combinational
logic circuit which performs arithmetic operations on the
binary numbers that are stored in the B register and the
accumulator.
A typical sequence of operations may occur as follows.
(a) The control unit receives an instruction (from the
memory unit) specifying that a number stored in a
memory location (address) is to be added to the
number presently stored in the accumulator
register (A register).
(b) The number to be added is transferred from the
memory to the B register.
(c) The number in the B register and the number in
the accumulator register are added together in the
logic circuits. The resulting sum is then sent to the
accumulator to be stored.
(d) The new number in the accumulator can remain
there so that another number can be added to it, or
 if the arithmetic process is finished, it can be
transferred to memory for storage.

Combinational logic circuits which perform basic

functions in the arithmetic unit
Adder circuits
The half Adder
The half adder is used in cases where a circuit is needed
that can add only 2 input bits, to produce a sum and a
carry output. A special logic circuit can be designed to
take two input bits, A and B, and to produce sum (S) and
carry (Cout) outputs. It is called half adder. The design of
a half adder is left as an exercise at the end of the lesson.
Full Adder

(Full adder) 4-bit parallel adder

When we add two 4-bit binary numbers 𝐴3 𝐴2 𝐴1 𝐴0 and
𝐵4 𝐵2 𝐵1 𝐵0, the addition process begins with addition of
the two least significant bits 𝐴0 and 𝐵0 . This may
generate a carry bit that has to be added to the next bit
position and so on. In general, each step in this addition
process, we are performing the addition of 3 bits; the
augend bit, the addend bit and a carry bit coming from
the previous position. Addition at each position will
result in a sum (S), and a carry (C) that must be added
to the next position. This is part of a process occurring in
the logic circuit of the arithmetic unit shown in Figure 2.
Figure 3 shows the block diagram of such a 4-bit parallel
adder. It consists of 4 full Adder (FA) units receiving
binary information from B register and A register
(accumulator) in the parallel manner.

𝐶4 𝐶3 𝐶2 𝐶1 and 𝐶0 represent the carry bits generated from

each position. In this diagram the binary number
𝐴3 𝐴2 𝐴1 𝐴0 represents bits of the augend that are stored
in the accumulator (which is called the A register), and
𝐵3 𝐵2 𝐵1 𝐵0 represent the bits of the addend stored in the
B register. 𝑆3 𝑆2 𝑆1 𝑆0 are the sum output bits generated by
the FAs once the addition is completed.

Construction of a basic full adder (FA) unit

Block diagram of a basic full adder unit which adds nth
bit of the two binary numbers A and B, and the carry bit
coming from the addition of n-1th column is shown
below.

The truth table needed for the construction of the above

FA is shown below.
𝐴𝑁 𝐵𝑁 𝐶𝑁−1 𝑆𝑁 𝐶𝑁
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Logic expression for 𝑆𝑁
𝑆𝑁 = ̅̅̅̅ 𝐵𝑁 𝐶𝑁−1 + ̅̅̅̅
𝐴𝑁 ̅̅̅̅ 𝐴𝑁 𝐵𝑁 ̅̅̅̅̅̅ 𝐵𝑁 ̅̅̅̅̅̅
𝐶𝑁−1 +𝐴𝑁 ̅̅̅̅ 𝐶𝑁−1 +𝐴𝑁 𝐵𝑁 𝐶𝑁−1

= ̅̅̅̅ 𝐵𝑁 𝐶𝑁−1 + 𝐵𝑁 ̅̅̅̅̅̅

𝐴𝑁 (̅̅̅̅ ̅̅̅̅
𝐶𝑁−1 ) + 𝐴𝑁 (𝐵 ̅̅̅̅̅̅
𝑁 𝐶𝑁−1 + 𝐵𝑁 𝐶𝑁−1 )

= ̅̅̅̅ ̅̅̅̅
𝐴𝑁 (𝐵𝑁 ⊕ 𝐶𝑁−1 ) + 𝐴𝑁 (𝐵 ̅̅̅̅̅̅
𝑁 ⊕ 𝐶𝑁−1 )

= 𝐴𝑁 ⊕ (𝐵𝑁 ⊕ 𝐶𝑁−1 )

Logic expression for 𝐶𝑁

𝐶𝑁 = ̅̅̅̅ 𝐵𝑁 𝐶𝑁−1 + 𝐴𝑁 𝐵𝑁 ̅̅̅̅̅̅
𝐴𝑁 𝐵𝑁 𝐶𝑁−1 + 𝐴𝑁 ̅̅̅̅ 𝐶𝑁−1 + 𝐴𝑁 𝐵𝑁 𝐶𝑁−1
= 𝐵𝑁 𝐶𝑁−1 (̅̅̅̅
𝐴𝑁 + 𝐴𝑁 ) + 𝐴𝑁 𝐶𝑁−1 (̅̅̅̅ ̅̅̅̅̅̅
𝐵𝑁 + 𝐵𝑁 ) + 𝐴𝑁 𝐵𝑁 (𝐶 𝑁−1
+ 𝐶𝑁−1 )
= 𝐵𝑁 𝐶𝑁−1 + 𝐴𝑁 𝐶𝑁−1 + 𝐴𝑁 𝐵𝑁

Complete logic circuit for the full adder

A complete 4-bit parallel adder including storage
registers are shown in Figure 4.
The augend bits A3 – A0 are stored in the A register
(accumulator) and the addend bits are stored in the B
register bits B3 – B0. Note that, since the outputs of A and
B registers are already available at the relevant inputs of
the FAs, the addition will take place automatically and
the sum will be available at the S3 – S0 outputs. This is
because the FAs are combinational logic circuits, and no
command is necessary for them to execute the operation
of addition. Note C4 is the carry output to a fifth FA or it
can be used to indicate that the sum has exceeded 1111.
The sum outputs (S3, S2, S1, S0) are connected to the D
input of the Accumulator. The sum outputs are then
parallel transferred into the accumulator on the PGT of
the add command pulse. In this way sum can be stored
in the A register until it is transferred to a permanent
memory location.
Question. What will happen if the sum outputs are not transferred
immediately to the A register?
Sequence of operations
Register notation
Before we go through the complete process of how this
circuit adds two binary numbers, let us define some
notations that make it easy to describe the contents of a
register and a data transfer operation.
(1) Use a square bracket with register label to
represent the content in the register. For example,
the notation, [A] = 1011 represents the content
1011 in the A register.
(2)

We will now describe the process by which the circuit in

Figure 4 can be used to add the two binary numbers 1001
and 0101 which are in the memory. Assume C0 = 0.
Sequence of operation
0 1 0 1
0 0 0 0
1 0 0 1
 0 0 0 0
1 0 0 1
1 1 1 0

If the addition process is completed, the content in A

register must be transferred to the memory for storage.
Then the adder circuit can be used for another operation.
Note that the circuitry needed to perform the final
transfer from A register to the memory is not included in
the diagram.
Exercises
(1) Suppose we need to add four different numbers which are
located at the memory. How many (a) ‘clear’ pulses, (b)
 ‘Transfer pulses’ and (c) ‘Add command’ pulses are needed to
complete this process?
(2) Determine the content in the A register after completing the
following process.

Lesson 39
Carry propagation
Parallel adders (FAs) are expected to be fast, as all the
required data are received in the parallel manner and, the
additions in all the FAs take place simultaneously.
However, their overall speed is greatly reduced due to an
effect called ‘carry propagation’ delay. It arises due to
the time taken by each FA to generate its carry bit after
receiving the two relevant input bits from A and B
registers. It is about 40 ns per FA. This is a cumulative
delay process and each FA must wait 40 ns until the carry
is generated by the previous FA. The carry signals thus
generated, must propagate (ripple) all the way through
FAs to generate the final FA before producing the correct
sum. For the above 4-bit adder this delay time is about
4×40 = 160 ns. In other words, the Add command
cannot be applied until 160 ns has elapsed. This
situation will get worsen with the number of FAs. For
example, if a 32-bit parallel adder is used, the carry
propagation delay would be about 1.28 µs. Therefore, the
carry propagation delay will adversely affect the speed
of the addition process.
There are ways to minimize this propagation delay. One
mechanism to reduce this delay is to generate carry bits
using faster external circuits and introduce them at
intermediate positions of the adder circuit as shown in
the following figure. Such circuits are called ‘Look
ahead carry’ circuits.

For example, as shown in the figure a combinational

logic circuit can be employed for ‘Look ahead carry
circuitry 1’by considering A0, B0, A1, B1, A2, B2, as inputs
and C3 as the output. If a logic expression is generated for
example, in sum of product form and implemented with
2-level NAND gates in the usual manner, a propagation
delay of 10× 2 =20 ns per ‘look ahead carry’ would be
achieved. (Note: Propagation delay of each NAND gate
is about 10 ns). This way the carry propagation delay of
parallel adder circuits can be reduced to a large extent.
This method would require large amount of extra
circuitry, but it is not a drawback as it yields high speed
adders.
Exercise
Construct a look ahead carry circuit to generate C2 for the above circuit
using NAND gates
Hints
The truth table for the circuit
𝐴1 𝐴2 𝐵1 𝐵2 𝐶2
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1 √
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1 √
1 0 1 1 1 √
1 1 0 0 0
1 1 0 1 1 √
1 1 1 0 1 √
1 1 1 1 1 √

IC parallel adders
A popular 4-bit parallel adder with look ahead carry
circuitry is TTL 7483 or 74283 (an improved version).
The inputs, outputs, and the carry in/out shown in the IC
are self-explanatory. They conform with the adder circuit
together with look ahead carry that we learnt before.
Circuit symbol of TTL7483

Cascading two 7483 to produce an 8-bit parallel

adder

Question
Is it possible to extend the above idea to construct a 32-bit parallel
adder?
Subtraction
Subtraction in 2’s- complement system
When the subtraction is done in 2’s- complement system,
the number to be subtracted (the subtrahend) is 2’s-
complemented and then added to the minuend. Let us
assume that minuend is already in the A register.

Hardware to Convert subtrahend to 2’s-complement

system
In order to convert a given binary number to a 2’s-
complement number, first we need to complement each
bit of the number to generate its 1’s-complement, and
then add 1 to the LSB of the complemented number to
produce the 2’s-complement number.
If we look at carefully, we can realize that, both the
above-mentioned facilities are available in FF registers
and FAs. For example, consider the circuit diagram of
the 4-bit parallel adder that was given in Figure 4. The
relevant part of the diagram is reproduced below.
 Note that each FF in the B register has two outputs, the
B output and the 𝑩 ̅ output which is the complement of
the B output. See figure above.
If we use the B register to store the substrahend, then the
1’s-complement of that number can be obtained straight
from the 𝐁̅ outputs of the D type FFs. Addition of 1 to
the LSB of the1’s-complemented number can be achievd
by making C0 = 1, then the 1’s complement number
automatically gets converted to the 2’s- complement
number.
Complete circuit diagram of an Adder / Subtracter
using 2’s-complement system
The circuit shown in Figure 5 can be used to add as well
as subtract 4-bit numbers. The circuit is controlled by
two command signals ADD and SUB.
When ADD = 1 and SUB = 0, AND gates 1, 3, 5, and 7,
will be enabled, and the bits B0, B1, B2, and B3 will be
selected and transmitted to the 7483 4-bit parallel adder.
Note that under this condition C0 = 0, and normal
addition will take place with the number in the A register.
When SUB = 1 and ADD = 0, AND gates 2, 4, 6, and 8
will be enabled, and the 1’s-complement values of B (i.e.
̅̅̅0 ……𝐵
𝐵 ̅̅̅3 ) will be selected and transmitted to 7483
adder. Note that since C0 = 1 under this situation, the 1’s-
complement value of B is automatically converted to its
2’s- complement value inside the FA. Then the addition
of two numbers takes place in the 4-bit parallel adder.
Though it is an addition, the overall effect under this
condition is a subtraction of the binary number in B
register from the binary number in A register. The
sequence of operation in this case is similar to that is
taking place in the 4-bit parallel adder described earlier.
Exercise
1. Write down sequence of steps to transfer a binary number from the
memory to A register in the circuit shown in Figure 5
2. Suppose the two numbers 1101 and 0011 are in the memory. Write
down detail sequence of steps to
(a) Add 1101 and 0011
(b) Subtract 0011 from 1101
Note that in both cases, the final result must be transferred to
the A register.

Binary multiplication
Multiplication of two binary numbers is done manually
on paper by performing successive addition and
shifting.
For example, 1011× 1101 is done as follows.

The above multiplication process basically amounts to

writing the multiplicand whenever the multiplier bit is 1
and shifting the multiplicand value by one position at
each stage. When the multiplier bit is 0, only the shifting
takes place. Addition is done at the end.
The binary multiplication is done in computers in the
similar manner, but a partial addition is done at each
stage. This is simply because adder circuit cannot add
more than two numbers at a time. The same example is
done again to show how a digital system performs the
same multiplication.
This example illustrates how a digital system performs
multiplication. It is unable to add more than two numbers
at a time. The entire multiplication process can be
considered as a shifting and addition exercise. In a
computer, shifting is done by a shift register and the
addition by a parallel adder. The result can be found in
the A register
The following diagram shows such a multiplication
circuit and it is only for your information. You may
realize that both multiplicand (B register) and the
multiplier operates as shift registers upon receiving clock
pulses. A register is initially zero. Sum outputs, 𝑆0 − 𝑆8
are transferred to the A register only when X bit is equal
to 1.
Exercises
1.Write a truth table for a half adder (inputs A and B; outputs SUM and
CARRY). From the truth table design a logic circuit that will act as
a half adder.
2. The figure below shows how one may construct a full adder from
two half adders. Construct a truth table for this arrangement and
verify that it operates as a FA.

3. Design a look-ahead carry circuitry 1 of the adder shown in figure

below.
(Hint: Begin by writing a expression for C1 in terms of A0, B0, and
C0. Then write the expression for C2 in terms of A1, B1, and C1.
Substitute the expression for C1 into the expression for C2. Then
write the expression for C3 in terms of A2, B2, and C2. Substitute the
expression for C2 into the expression for C3. Simplify the final
expression for C3 and put it in sum of products form.)