Ex. No.

: 3a HDL BASED DESIGN ENTRY AND SIMULATION OF

4-BIT SYNCHRONOUS COUNTER
Date:

AIM

To perform HDL based design entry and simulation of4-bit Asynchronous Counter.

SOFTWARE REQUIRED:

Simulation tool: Xilinx Vivado 2015

PROCEDURE:

1. Design the Logic circuit (Schematic / logic diagram) and write the Boolean function/ expressions.
2. Create new RTL project in Xilinx Vivado.
3. Choose the HDL language (Verilog) and the device (Zedboard).
4. Write the Verilog module for the designed logic circuitusing three modeling styles in the Code editor.
5. Simulate the source program using Xilinx Simulator tool. Run behavioural Simulation.
6. Force the inputs (and clock if any) in the object window and Run simulation.
7. Verify the output in the obtained simulation waveform .

PROGRAM CODE:
SIMULATION WAVEFORM:

RESULT:
Thus the Verilog program for 4-bit Asynchronous Counter.was written, simulated and the output
was verified from the simulation waveform.
Ex. No.:3b SYNTHESIS, P&R AND POST P&R SIMULATION OF
4-BIT SYNCHRONOUS COUNTER
Date :

AIM:
To synthesize, implement and perform post implementation simulation of Universal Shift Register.

SOFTWARE/HARDWARE REQUIRED:
Simulation tool: Xilinx Vivado 2015
Zedboard Zynq 7000 Development Board

PROCEDURE:

1. After simulation, Click on Run Synthesis under the flow navigatorpane.

2. Open Synthesized Designand view the Elaborated Synthesized Design.
3. Examine the resources utilised in the synthesized design from the project summary.
4. Perform IO pin assignment for each of the inputs and outputs as per board configuration and save
constraints.
5. Re-run the synthesis.
6. Click on Run Implementation under the Flow Navigatorpane. Open and view the implemented
design.
7. Examine the resources utilised in the implemented design from the project summary.
8. Run Post-Implementation Timing Simulation under the Simulation tasks in the Flow Navigator
pane and obtain the waveform by giving test vector inputs.

OUTPUT:

1. Constraints Files
2. Elaborated Design

3. Implemented Design

4. Utilisation after synthesis

5. Utilisation after Implementation

6. Utilisation Report
 7. Post – implementation Simulation

RESULT:
Thus Verilog program for 4-bit Asynchronous Counter.was synthesized, implemented and post
implementation simulation was performed.
Ex. No.:3c HARDWARE FUSING AND TESTING OF
4-BIT SYNCHRONOUS COUNTER

AIM:

To perform hardware fusing and testing of Universal Shift Register in Zedboard using Xilinx Vivado.

SOFTWARE/HARDWARE REQUIRED:

Simulation tool: Xilinx Vivado 2015

Zedboard Zynq 7000 Development Board

PROCEDURE:

1. Connect the Zedboard to the PC and power ON.

2. Click on Generate Bit stream entry under the Program and Debugtasks of the Flow Navigator
pane.
3. Click on “Open Hardware Manager”. Click on “Open Target” and select “Auto Connect”.
4. Program the Device xc7z020_1.
5. Once the program is downloaded into the Zedboard, verify the functionality by varying the input
switches and checking the output LEDs.

RESULT:

Thus the hardware fusing and testing of 4-bit Asynchronous Counter.was performed in Zedboard
using Xilinx Vivado.