Microelectronics Journal 82 (2018) 62–70

Contents lists available at ScienceDirect

Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo

Power and area-efficient design of VCMA-MRAM based full-adder using

approximate computing for IoT applications
Ali Zarei, Farshad Safaei *
Faculty of Computer Science and Engineering, Shahid Beheshti University G.C., Evin, 1983963113, Tehran, Iran

A R T I C L E I N F O A B S T R A C T

Keywords: The next generation in computing era will be within the realm of internet of things (IoT). High density, near-zero
Approximate computing leakage, and high endurance are some of the important properties of magnetic RAM (MRAM) which makes it
Internet of things (IoT) attractive for many IoT applications. As in many of these applications, the computational error is tolerable to some
Magnetic tunnel junction (MTJ)
extent; therefore, it is reasonable to use approximate computing to have significant gain in terms of area and
Non-volatile full-adder
Voltage-controlled magnetic anisotropy
power. Full-adder is one of the main parts of CPU for basic operations. In this paper, we utilize voltage-controlled
(VCMA) magnetic anisotropy spin transfer torque (VCMA-STT) magnetic tunnel junction (MTJ) as a memory element in
Low-power computing accurate non-volatile full-adder and present the corresponding writing circuit that improves 7.6x power con-
sumption compared to the state-of-the-art work. We also propose several approximate magnetic full-adders
(AMFs) based on STT-assisted precessional VCMA that are very cost-effective. Some proposed AMFs in this
work have improved more than 50% of area and 9.5x of power consumption.

1. Introduction
By emerging Internet of Things (IoT), the number of smart devices
around the world is increasing and it is anticipated to be doubled by 2020
[1]. Therefore, the speed of the data generation rate will be so high that
the current computing systems cannot process them and need high-speed
technology. Also, despite the advancements in semiconductor technology
and the developments of low-power design, the power consumption of a
processing system has been increased dramatically due to larger amounts
of data [2].
Approximate computing is one of the most important methods for
reducing power consumption in IoT in which fewer resources are used
[3]. In approximate computing, it is possible to reduce the area, power,
and delay effectively without affecting the output quality significantly
[4–6]. The approximate computing is very important in applications such
as image and signal processing, voice recognition, data analysis, machine
learning, and global positioning system (GPS); because one of the com-
mon points of these applications is their ability to tolerate a certain
amount of computational errors [5–7]. In addition, with the increasing
popularity of smart devices that support multimedia applications, the
demand for video and image processing with a very small budget has
been increased [8].
Numerous IoT applications are naturally dealing with the
approximation since they are interacting with noisy input data [9]. These
applications endure some errors but the final output should be in a se-
mantic range. Various hardware components such as data processing and
data storage can exploit the tolerable error [10]. In Ref. [11] authors
studied the use of MRAM to design a non-volatile processor for IoT de-
vices and concluded that in most cases it will lead to better energy effi-
ciency. Emerging memory technologies can potentially make IoT devices
energy-efficient, and approximate computing can increase the battery of
these devices [12]. For example, in a European project, STT-MRAM uti-
lized for analog and digital sub-systems of IoT platforms that led to better
integration and power efficiency of embedded and mobile communica-
tion systems [13].
The full-adder (FA) is the main element in the computational circuits
used in the arithmetic logic unit (ALU) of each processor for addition and
other operations such as subtraction, division, and multiplication.
Additionally, full-adders are also used in floating point units (FPU) and in
address generation to access cache and main memory [14]. Recently,
non-volatile magnetic full-adders (MFA) have been designed and
implemented, which use memory elements to store data values and
almost have no static power consumption [15–17].
International Technology Roadmap for Semiconductor (ITRS) re-
ported static power consumption would have a considerable portion of
the whole power consumption in the future [18]. Power consumption,

* Corresponding author.
E-mail addresses: a_zarei@sbu.ac.ir (A. Zarei), f_safaei@sbu.ac.ir (F. Safaei).

https://doi.org/10.1016/j.mejo.2018.10.010
Received 14 June 2018; Received in revised form 3 October 2018; Accepted 24 October 2018
Available online 27 October 2018
0026-2692/© 2018 Elsevier Ltd. All rights reserved.
A. Zarei, F. Safaei
particularly static power is one of the major challenges in conventional
memory based on semiconductors. Nevertheless, emerging non-volatile
memory makes it possible to have a suitable option to solve this chal-
lenge since its static power consumption is almost zero [19,20].
Spin transfer torque magnetic random access memory (STT-MRAM)
in emerging non-volatile memories, is one of the most important solu-
tions that can be employed instead of SRAM in the cache thanks to its
high density, low static power consumption, and high endurance.
Accordingly, researchers have been also designed flip-flop and MFA
circuits with this technology [21,22]. However, STT-MRAM write power
and delay is less efficient than conventional SRAMs due to the need to
higher charge currents for switching [19]. An appropriate solution for
reducing energy is using an electric field instead of a charge current,
which has much lower power consumption [23].
Controlling magnetic field by an electric field can be a useful and
effective method rather than STT for high-speed, low-power MRAM ap-
plications. Voltage controlled magnetic anisotropy (VCMA) allows using
an electric field or voltage to switch the magnetic tunnel junction (MTJ).
To take benefit of the VCMA effect, there are several switching ap-
proaches that the STT-assisted precessional VCMA is generally optimal in
terms of dynamic power consumption, design complexity, and latency
[24]. By employing STT-assisted precessional VCMA, a low-power
non-volatile flip-flop was designed for data backup operation, as well
as an MRAM-backed SRAM cell for reconfigurable memory units of
FPGAs [25,26]. The key contributions of our work are:

We introduce STT-assisted precessional VCMA based full-adder that is
very cost-effective in comparison to other types of full-adders that
makes it particularly suitable for IoT applications.

We provide write circuits with only one supply voltage in order to be
employed in STT-assisted precessional VCMA MTJ.

We propose several approximate full-adders based on STT-assisted
precessional VCMA MTJ that are very power and area-efficient.

Circuit and application level evaluation is considered for the pro-
posed accurate and approximate full-adders design. To evaluate our
approximate designs at application level, we apply these methods into
the Sobel edge detection algorithm.
The rest of this paper is organized as follows: first, we review MTJ and
explain the STT-assisted precessional VCMA strategy in Section 2. In
section 3, we present magnetic full-adder based on STT-assisted preces-
sional VCMA. Related work and our proposed approximate full-adders
and its application on Sobel edge detection algorithm are introduced in
section 4. Simulation results are presented in Section 5. Finally, Section 6
summarizes and concludes this paper.
2. VCMA-MTJ
MTJ is an essential element in MRAM. Each MTJ composed of two
ferromagnetic layers called free layer and fixed layer (CoFeB) with an
oxide tunnel barrier (MgO) that is sandwiched between them as an
insulator. Two directions can be considered for the free layer: parallel (P)
or anti-parallel (AP) with a fixed layer, which ascertains the MTJ resis-
tance. When the magnetic direction of the free layer and fixed layer are
parallel, the resistance is low; in contrast, if the directions are anti-
parallel, the resistance is high.
The difference between the resistance in both parallel and anti-
parallel modes is determined by the ratio of the tunnel magnetic reso-
nance (TMR) shown in Eq. (1) [20]. RP and RAP are MTJ resistances in
parallel and anti-parallel states, respectively. Since the larger TMR ratio
represents a more difference between the resistance of parallel and
anti-parallel, the TMR ratio is a proper measure for distinguishing two
states in MTJ.
RAP  RP
TMR ¼ (1)
RP
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Microelectronics Journal 82 (2018) 62–70
With the VCMA effect, the magnetization dynamics of the free layer of
an MTJ can be defined by a modified Landau-Lifshitz-Gilbert (LLG)
equation, as [23]
d!m ! d!m
¼  γ!
m  H eff þ α!
m  ρstt !
m  ð!
m !
m rÞ (2)
dt dt
where γ is the gyromagnetic ratio, ! m is the magnetization vector of the
free layer, !m r is the polarization vector, α is the Gilbert damping factor,
!
H eff is the effective magnetic field, and ρstt is the STT factor. The effective
magnetic field comprises of external field, demagnetization field, thermal
!
noise field, and voltage-dependent anisotropy field (H ani ðVb Þ) that is
expressed as [27]
 
! 2ki ð0Þtox  2ξVb
H ani ðVb Þ ¼ mz (3)
μ0 Ms tf tox
In Eq. (3), ξ is the VCMA coefficient, tf is the thickness of the free
layer, tox is the thickness of the oxide barrier, and ki ð0Þ is the
perpendicular-anisotropy under zero voltage.
The magnetization vector of a ferromagnetic layer is aligned along an
axis in the steady state that is called easy axis, which is most desirable
from the minimum potential energy point of view. The orientation of the
free layer or fixed layer easy axis gives two different types of MTJs ac-
cording to the geometry of the ferromagnetic layers: In-Plane Anisotropy
(IPA) devices and Perpendicular-to-Plane Anisotropy (PPA) devices [28].
PPA device relative to IPA consumes less energy, has higher thermal
stability, and better scalability [23]. Hence, we consider PPA in this
paper.
In PPA MTJ (P-MTJ), a voltage is applied for increasing the switching
speed by creating an electric field across the oxide barrier. Fig. 1.a shows
the p-MTJ device based on STT-assisted precessional VCMA and Fig. 1.b
depicts the writing signal along it. Writing signal for STT-assisted pre-
cessional VCMA p-MTJ includes a VCMA effect voltage pulse (1.2 V) that
is applied at time t (in pre-charge phase) for 0.2ns that follows by an STT
voltage pulse (0.8 V or 0.8 V) within 0.4 ns [25]. In fact, VCMA effect
can be used to assist STT for MTJ switching. If STT voltage pulse is
positive (T1 – T2 ¼ 0.8), '00 is written in the p-MTJ, otherwise if the STT
voltage is negative (T1 – T2 ¼  0.8), '10 is written in the p-MTJ.
To switch MTJ from '1' (P) to '0' (AP) or vice-versa, a number of
transistors are needed to control the VCMA effect and STT current.
Fig. 2.a shows the write driver for the STT. If the write signal (En-write) is
active, an input ('10 or '00 ) can be written in the MTJ. Fig. 2.b and c depict
the STT-assisted precessional VCMA MTJ proposed write circuit and
switching waveforms, respectively. When the P0 transistor is turned on,
i.e. the VCMA signal is '00 , source voltage pulse (1.2 V) applies the VCMA
effect during 0.2ns on MTJ (purple solid path).
Afterward, if En-write is set to '10 , N0 and N1 transistors are activated
by STT signal to write '0' (red dashed path) or '1' (green dotted path).
Fig. 1. (a) STT-assisted precessional VCMA p-MTJ device. (b) write signal in-
cludes VCMA effect followed by STT for writing '00 in STT-assisted precessional
VCMA MTJ [25].
A. Zarei, F. Safaei
Fig. 2. (a) write driver (b) proposed write circuit (c) MTJ switching waveforms for STT-assisted precessional VCMA p-MTJ.
When the source voltage passes through the NMOS transistor (N0, N1), it
will be about 0.8 V, having reduced by the amount of NMOS threshold
voltage (Vth, n ~0.4 V). This issue will result in the write circuit of MTJ to
be powered by a 1.2 V supply voltage instead of two different voltage
amplitudes. Subsequently, STT current is applied to the MTJ during
0.4 ns. As illustrated in Fig. 2.b, P3 and N2 transistors are turned on to
pass STT current across MTJ if the input is '0'. Therefore, the magneti-
zation of the free layer is anti-parallel with the fixed layer. In contrast, if
the input is '10 , P2 and N3 transistors will be turned on that makes the
magnetization of the free layer parallel to the fixed layer.
3. Non-volatile STT-assisted precessional VCMA based magnetic
full-adder
As illustrated in Fig. 3, the MFA structure contains a pre-charge sense
amplifier (PCSA), CMOS logic, and MTJ memory elements. A pair of
MRAM cells is on the contrary state which is related to non-volatile input
data [15]. In this paper we implemented a non-volatile magnetic
full-adder based on STT-assisted precessional VCMA MTJ. Compared to
STT-MTJ based MRAM, the STT-assisted precessional VCMA gains a
lower power consumption and faster writing switching. By using the
STT-assisted VCMA-MRAM, the dynamic writing energy can be reduced
significantly, whereas STT-MRAM has 30x higher energy consumption
[29].
In this paper, we suppose that input 'B0 is the only non-volatile datum.
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Microelectronics Journal 82 (2018) 62–70
Hence, the 'B0 is written in the 'MTJ-L0 and 'MTJ-R0 as complementary. A
PCSA comprises a pre-charge sub-circuit, a discharging sub-circuit, and a
pair of inverters. PCSA works in two phases: In the first phase, 'CLK0 is set
to '00 to pre-charge complementary outputs such as 'SUM0 and '/SUM0 ,
'Cout', and '/Cout'. Then in the second phase, for discharge, 'CLK0 is set to
'1'. There are two branches with non-identical resistance toward dis-
charging. The branch with fewer resistance is pulled down, which causes
the other branch to be pulled up to the 'Vdd', simultaneously. Eventually,
the branch with lower resistance settles to the 'Gnd'. CMOS logic is also
based on Eq. (4) to Eq. (7) [15]. Unlike 'Cout' CMOS logic, the CMOS logic
for 'SUM0 matches to the logic correlation between the inputs 'A0 , 'B0 and
'Ci'.
Sum ¼ A  B  Ci ¼ ABCi þ ABCi þ ABCi þ ABCi (4)
Sum ¼ ABCi þ ABCi þ ABCi þ ABC (5)
Cout ¼ AB þ ACi þ BC (6)
Cout ¼ AB þ ACi þ BCi (7)
4. Related work
There are many methods in the literature for accurate and approxi-
mate adders [30–39]. Approximate adders compared to accurate ones
A. Zarei, F. Safaei Microelectronics Journal 82 (2018) 62–70

Fig. 3. STT-assisted precessional VCMA based Magnetic Full-Adder architecture with 'SUM0 and 'Cout' outputs, 'B0 is non-volatile data.

sacrifice a percentage of accuracy for power, area, and delay reduction. to '/Cout ' and '/SUM 0 outputs, respectively. In other words, only in two
For example, in Ref. [30], OR operation was used instead of the XOR out of eight cases where 'A ¼ B ¼ Ci ¼ 00 and 'A ¼ B ¼ Ci ¼ 10 , the
operation in 'SUM0 to compute least significant bits. Several valuable calculation of 'SUM0 from '/Cout' and 'Cout' from '/SUM0 is not correct
works has been done in the approximate non-volatile magnetic (bold content in Table .1). Therefore, we can exploit this feature and
full-adders [32,37]. In Ref. [37] approximate majority gate based obtain 'SUM0 or 'Cout' approximately.
full-adder is presented that utilized current induced Domain Wall Motion Due to the fact that the number of 'Cout' sub-circuit CMOS logic
(DWM). In Ref. [32], authors reduced the supply voltage of the circuit so transistors is less than that of the 'SUM0 sub-circuit, we consider the 'Cout'
that it can be used to approximate computing (AX-MFA2). According to sub-circuit intact and manipulate the 'SUM0 sub-circuit for approxima-
the results presented, half of the 'SUM0 is erroneous and the number of tion. If 'Cout' is error-free, its advantage is that in making multi-bit adders
errors (NoE) is 4. In addition, the 'Cout' is not exactly correct and has NoE the error does not go up to higher stages and will not propagate.
of 2. In addition, they eliminate the input 'Ci' from the CMOS logic to Therefore, in AMF1, we utilized the 'Cout' sub-circuit CMOS logic instead
calculate the 'SUM0 based on 2-input XOR which has an NoE of 4, but the of the 'SUM0 sub-circuit CMOS logic. As shown in Fig. 4 the CMOS logic of
output of the 'Cout' operates correctly (AX-MFA1). In these methods, the the '/Cout' and 'Cout' sub-branches was placed in the CMOS logic of the
area of the FA circuit is not reduced significantly, while in our proposed 'SUM0 and '/SUM0 sub-branches, respectively with fewer transistors. For
method it is decreased at a much lower cost. AMF2, we removed the complete 'SUM0 sub-circuit and exploit the '/Cout'
In this paper, seven approximate magnetic full-adders (AMFs) based sub-branch in the 'Cout' sub-circuit instead of 'SUM'. AMF2 is a
on STT-assisted precessional VCMA is presented. Although VCMA effect straightforward method and efficient than AMF1, since in AMF2 a PCSA,
improves energy-delay efficiency using an electric field, for a very limited two MTJs with along write circuit and eight transistors in CMOS logic
energy budget IoT applications that can tolerate some errors, we propose will be removed which is very cost-effective in terms of power and area.
approximate full-adders that are more cost-effective than previous works Consequently, as shown in Table 2, in AMF1 and AMF2, 'Cout' is accurate,
having the same or even better accuracy. For simplicity in the remainder and 'SUM0 has an NoE of 2.
of this paper, we call these methods AMF1 to AMF7. One of the problems with MTJ is power consumption and delay in
Table .1 shows the truth table of a full-adder. According to the truth writing. Writing circuit transistors should be large enough to provide the
table, we find that the outputs of 'SUM0 and 'Cout' in most cases are equal required current for MTJ switching. Hence, in AMF3, we eliminated
writing circuit of MTJs in 'SUM0 sub-circuit, in which case the initial
states of the MTJs remained unchanged, and the NoE of 'SUM0 is 4.
Table 1 AMF4 is the same as AMF1, with the difference that MTJs in 'SUM0
Truth table of a full-adder.
sub-circuit have not write circuit. In this method, 'SUM0 has an NoE of 4.
A B Ci SUM /SUM Cout /Cout In AMF5, we only removed the CMOS logic in the 'SUM0 sub-circuit with
0 0 0 0 1 0 1 8 transistors that half of the them is correct and the NoE is 4. In AMF6, we
0 0 1 1 0 0 1 removed the entire MTJs write circuits in full-adder, which significantly
0 1 0 1 0 0 1 reduced power consumption. Note that in this method, the 'Cout' output
0 1 1 0 1 1 0
has less NoE than 'SUM0 output, which is 2 and 4, respectively.
1 0 0 1 0 0 1
1 0 1 0 1 1 0 AMF7 is a combination of AMF2 and AMF6, which has the minimum
1 1 0 0 1 1 0 cost among all proposed methods. In the AMF7, the 'Cout' sub-circuit
1 1 1 1 0 1 0 MTJs have no write circuit, and we also removed the 'SUM0 sub-circuit

65
A. Zarei, F. Safaei
Fig. 4. CMOS logic for AMF1.
Table 2
SUM and Cout outputs of accurate and approximate magnetic full-adder; proposed (AMF1 to AMF7) and previous works: (AX-MFA) [32], approximate Domain
Wall-based [37], approximate CMOS-based [38].
to exploit the '/Cout' sub-branch in the 'Cout' sub-circuit instead of 'SUM'.
In this method, a PCSA and two MTJs with the CMOS logic in the 'SUM0
sub-circuit, and four MTJs writing circuits in the full-adder circuit were
deleted while 'Cout' and 'SUM0 have NoE of 2 and 4, respectively. The
outputs of the 'SUM0 and 'Cout' for accurate full-adder are presented in
Table 2 with the proposed and previous approximate full-adders. Incor-
rect outputs in this table are bolded in gray and as we can see, AMF1 and
AMF2 have less NoE.
4.1. Sobel's edge detection algorithm
Image processing is employed in different applications and one of its
important aims is to provide images for the measurement of the features
and structure in order to extract some applicable information [40]. The
most fundamental feature of an image is its edges. Image edges are the
areas having striking contrasts. It includes the important information of
an image.
The edge detection of an image filter out unusable information and
significantly reduces the amount of data, while saving substantial
structural properties in an image [41]. Sobel is one of the most important
edge detection algorithms in image processing. Recently, image pro-
cessing algorithms especially edge detection such as Sobel, have been
implemented to monitor the environment in IoT devices [42,43]. The
motivation that we used Sobel algorithm is that, it can be implemented
with almost addition operator with an 8 bit-width addition. Then, in
order to investigate the effect of proposed AMF in the image quality of
the Sobel algorithm output, we applied approximate full-adders into
Sobel algorithm according to Table 2.
Approximate addition can be applied over a number of least-
significant bits (LSB) according to the trade-off between accuracy and
cost. We used the peak-signal-to-noise ratio (PSNR) as well as the
structural similarity index measure (SSIM) to compare performance in
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Microelectronics Journal 82 (2018) 62–70
terms of accuracy in the approximate magnetic full-adders. The PSNR (in
dB) and the SSIM are two key parameters that can be used to compare
two images [44]. PSNR equals INF and SSIM equals '10 in the accurate
case where two images are the same.
5. Simulation results and evaluation
To evaluate our proposed methods and to compare it with previous
works, we used the HSPICE simulator with a PTM-45 nm CMOS model
[45] and STT-assisted precessional VCMA Verilog-A model which was
developed in Ref. [24]. In addition, we utilized MatLab to implement
Sobel algorithm and to measure quality metrics of images after approx-
imation. In the other words, the Verilog-A model of STT-assisted VCMA is
used for device level simulation. The Hspice simulation is used for
measuring power and delay at circuit level. In addition, at application
level, the MatLab simulation is used for impact of approximate full-adder
on Sobel algorithm output quality by calculating PSNR and SSIM metrics.
For mapping Hspice simulations to MatLab, we implemented a function
in MatLab that performs approximate bitwise addition. In this function,
approximate add operation and number of LSB for approximation can be
configured.
An MTJ device with a TMR ratio of 100% is considered for all sim-
ulations and the rest of parameters are listed in Table 3. We simulate our
accurate and approximate STT-assisted VCMA-MRAM based full-adders
and compared them with the accurate and approximate CMOS-based
[34,38], MTJ-based [34], SHE-based [35] and DWM-based [36,37]
full-adders.
Fig. 5 depicts the transient simulation of a single-bit accurate and
approximate magnetic full-adders whose inputs A, B, Ci and its outputs
are 'SUM0 , 'Cout'. For instance, in accurate MFA if 'A' ¼ '10 , 'B' ¼ '10 ,
'Ci' ¼ '10 , the 'SUM0 and the 'Cout' are '10 but in MFA1 or MFA2 the 'SUM0 is
'00 and the 'Cout' is '1'.
A. Zarei, F. Safaei Microelectronics Journal 82 (2018) 62–70

Table 3 scaled our works to this process node. To do this, we used scaling
Parameters used in the model. equations for the accurate prediction (presented in Ref. [48]) of power
Default Value Description Parameter and delay from 45 nm with Vdd ¼ 1.2–180 nm node with Vdd ¼ 1 which
2 also used or scaled in previous works.
0.32 mJ/m Interfacial PMA Ki
0.625  106 A/m Saturation magnetization Ms Since instead of electric current, an electric field is utilized in VCMA
60 fJ/V.m VCMA coefficient ξ effect, compared to STT-MTJ switching it has lower dynamic power
50 nm Diameter of MTJ d consumption. Besides, STT-assisted VCMA-MTJ employed much thicker
1.4 nm Oxide layer thickness tox tunneling barrier which causes negligible static power consumption.
1.1 nm Free layer thickness tf
Additionally, STT-assisted VCMA-MTJ writing speed is faster than STT-
0.05 Gilbert Damping Factor α
40 Thermal stability at Vb ¼ 0 Δ MTJ [29]. As we expected and based on simulation results, our pro-
~100 kΩ, ~200 kΩ MTJ resistance Rp ; RAP posed accurate STT-assisted VCMA-MRAM based full-adder significantly
outperforms all previous accurate full-adders [34–37] in terms of power
consumption by 7.6x compared to state-of-the-art work. As declared in
Table 4, the proposed accurate full-adder device count (area) is almost
the same as the other accurate works. Delay corresponds to the maximum
time that inputs change and affect the 'Sum' or 'Cout' output. Due to
simulation results, the full-adder delay is obtained from 'Cout' output and
as result shows, the delay is lower than 1 ns.
As shown in Table 4, AMF7 has the lowest cost in terms of device
count, power consumption and delay compared to the other proposed
approximate methods and previous approximate works. AMF7 has
reduced device count by more than 50%, compared to AX-MFA1, AX-
MFA2 and approximate DWM-based full-adder, and has reduced power
consumption substantially by 9.5x, 3.6x and 39x respectively. Hereafter,
we want to compare the proposed and previous methods with equal NoE,
ER and MED. In the case where the NoE of the 'SUM0 is 4 and the 'Cout'
has no error, the device count (if write circuit also considered) and
especially the power consumption of AMF3 and AMF4, is better than AX-
MFA1 and AMF5.
In the case where the 'SUM0 NoE is 2 and the 'Cout' NoE is zero, device
count and power consumption of AMF2 is half of the AMF1. Furthermore,
AMF2 decreased power consumption by 9.4x and 8.4x compared to
approximate CMOS-based [38] and DWM-based [37] full-adders,
respectively. It is notable that AMF2 outperforms other methods when
'Cout' is error-free and the NoE of 'SUM0 is 2. AMF6 has better perfor-
mance compared to AX-MFA2 when 'Cout' and the NoE of 'SUM0 is 2 and
4 respectively, owing to lack of writing circuits which in turn consumes
power dramatically. In this case, AMF7 outperforms other methods.
For comparison of image quality in approximate computing, we used
PSNR and SSIM metrics to evaluate accurate and approximate full-adders
performing Sobel algorithm. According to the results in Table 4, when the
least significant bit is erroneous in computing (1-LSB), AMF5 and AX-
MFA1 have higher PSNR and SSIM. We found that in the sum of the
Fig. 5. Transient simulations STT-assisted precessional VCMA based accurate least significant bit (1-LSB), since there is no carry for the 1-LSB, one
magnetic full-adder and AMF1, 2. input is always zero (C), another one (B) is also zero in most cases and the
input A is either one or zero. According to Table 2, AMF5 and AX-MFA1
Error distance (ED) is one of the most valuable metrics for the contrast work correctly in these cases, i.e. A ¼ 0, B ¼ 0, C ¼ 0 and A ¼ 1, B ¼ 0,
between approximate FAs wherein the accurate output 'a' and inaccurate C ¼ 0, but the rest methods are erroneous in one of these two cases. In
output 'b' is compared for all feasible combinations of inputs by Eq. (8) general, AMF1, AMF2, approximate CMOS-based [38] and DWM-based
[46]. Error rate (ER) and mean error distance (MED) are also two [37] full-adders, have the best accuracy. It is noteworthy to mention
important metrics that is obtained from the ED by assuming that the that, the PSNR and SSIM for AMF7 are close to other methods in 1-LSB to
inputs are uniformly distributed. The ER is defined as the probability of 4-LSB approximation, due to smallest area and power consumption. In
producing an erroneous outputs and the MED is defined as the mean the Table 4, best values for PSNR and SSIM is bolded.
value of the ED of all possible outputs for a given set of input vectors [47]. Fig. 6 illustrates the accurate and approximate result of applying the
Sobel edge detection algorithm to the Lena image. First of all, as Fig. 6.b
 
EDða; bÞ ¼ ja  bj ¼ Σ i a½i  2i  Σ j b½j  2j  (8)
Note that the results obtained from the simulations for the proposed
method and previous works are presented in Table 4 with regard to the
number of transistors (T), number of MTJs (M), number of SHE-MTJs
(SM), number of domain walls (DM), power consumption
(dynamic þ static), number of errors (NoE) for 'SUM0 and 'Cout' outputs,
error rate (ER), mean error distance (MED) and image quality metrics
such as PSNR and SSIM for 1-LSB to 4-LSB (x-LSB means x-bit(s) with
low-order) approximate bits in 8-bit adder. Considering most previous
works were designed and evaluated in 180 nm, for a fair comparison, we
67
depicts, we perform Sobel on the original image that is the accurate
output result. Afterward, according to Table 4, we show several better
approximate Sobel results in 1-LSB and 2-LSB for all approximate
methods. As previously stated, in 1-LSB and 2-LSB, there are one and two
least significant bits in the approximate computing, respectively. As
shown in Fig. 6.c to e, g, i, and k to m; in 1-LSB or even in 2-LSB, there is
no meaningful change in the output of approximated Sobel.
6. Conclusions
In this paper, we introduced accurate magnetic full-adder based on
 A. Zarei, F. Safaei
Table 4
Comparison of the previous works and the proposed accurate and approximate STT-assisted VCMA-MRAM based full-adders.
Magnetic full-adder Device count (1) Power (2) (μW) Delay (3)
(ps) NoE (4)
ER (5) (%) MED (6)
1-LSB (7)
2-LSB 3-LSB 4-LSB

SUM Cout PSNR SSIM PSNR SSIM PSNR SSIM PSNR SSIM

accurate Proposed 32Tþ4 M 7.3 þ 0 989 0 0 0 0 INF 1 INF 1 INF 1 INF 1

CMOS [34] 42T 71.1 þ 0.001 2200
MTJ [34] 34Tþ4 M 2100 þ 0 10200
SHE [35] 23Tþ3SM 710 þ 0 7000
DWM [36] 20Tþ4 Mþ2D 85 þ 0 877
DWM [37] 28Tþ4 Mþ2D 55.6 þ 0 3000
approx CMOS [38] 14T 32.5 þ 0.002 645 2 0 25 0.25 21.95 0.91 20.70 0.88 16.13 0.76 12.21 0.66
DWM [37] 28Tþ4 Mþ2D 28.9 þ 0 2000 2 0 25 0.25 21.95 0.91 20.70 0.88 16.13 0.76 12.21 0.66
AX-MFA1 [32] 28Tþ4 M 7þ0 990 4 0 50 0.5 23.52 0.92 14.83 0.70 12.91 0.64 12.32 0.61
AX-MFA2 [32] 32Tþ4 M 2.4 þ 0 901 4 2 50 0.5 20.40 0.87 16.03 0.73 14.32 0.66 11.72 0.61
AMF1 28Tþ4 M 6.73 þ 0 990 2 0 25 0.25 21.95 0.91 20.70 0.88 16.13 0.76 12.21 0.66
AMF2 14Tþ2 M 3.43 þ 0 990 2 0 25 0.25 21.95 0.91 20.70 0.88 16.13 0.76 12.21 0.66
68

AMF3 32Tþ4 M 4.29 þ 0 990 4 0 50 0.5 21.91 0.90 18.09 0.80 14.53 0.67 12.04 0.62
AMF4 28Tþ4 M 4.38 þ 0 990 4 0 50 0.5 20.73 0.88 16.08 0.76 13.01 0.67 10.33 0.62
AMF5 26Tþ4 M 6.53 þ 0 989 4 0 50 0.5 23.52 0.92 14.83 0.70 12.91 0.64 12.32 0.61
AMF6 32Tþ4 M 1.60 þ 0 869 4 2 50 0.5 20.40 0.87 16.03 0.73 14.32 0.66 11.72 0.61
AMF7 14Tþ2 M 0.74 þ 0 868 4 2 50 0.5 21.05 0.89 17.33 0.78 14.52 0.68 11.04 0.62

Notes: AX-MFA1 and AX-MFA2 full-adders are based on STT-assisted VCMA-MRAM. Technology scaling is also utilized to achieve fair comparison. (1) T: CMOS Transistor, M: MTJ, SM: SHE-MTJ, D: DW. (2) dynamic
power þ static power. Unlike CMOS-based storage to keep data, the power of the non-volatile designs can be cut-off. (3) Worst case delay is considered in proposed accurate and approximate designs (AMF1 to AMF7) and
AX-MFA1 and AX-MFA2. (4) Number of Errors in outputs. (5) Error Rate. (6) Mean Error Distance. (7) Least Significant Bit of an 8-bit add operation in Sobel edge detection algorithm.

Microelectronics Journal 82 (2018) 62–70

A. Zarei, F. Safaei
Fig. 6. (a) Lena original image (b) accurate result of applying the Sobel to the Lena (c) AMF1, AMF2, [37] and [38] 1-LSB (d) AMF1, AMF2, [37] and [38] 2-LSB (e)
AMF3, 1-LSB (f) AMF3, 2-LSB (g) AMF4, 1-LSB (h) AMF4, 2-LSB (i) AMF5 and AX-MFA1, 1-LSB (j) AMF5 and AX-MFA1, 2-LSB (k) AMF6 and AX-MFA2, 1-LSB (l)
AMF6 and AX-MFA2, 2-LSB (m) AMF7, 1-LSB (n) AMF7, 2-LSB.
STT-assisted precessional VCMA and its corresponding write circuit. Af-
terward, we proposed seven efficient approximate magnetic full-adders
(AMFs) in terms of area and power which can be used in IoT devices.
Moreover, these approximate full-adders were mapped in Sobel image
processing algorithm at some LSB; in addition, for comparison PSNR and
SSIM metrics are used. Our simulation results demonstrate that, some of
the proposed AMFs reduced area and power consumption significantly,
with the same or even better accuracy than previous works. In the pro-
posed methods, AMF2 and AMF7 are very affordable among all methods.
AMF2 is the most cost effective method when 'Cout' is error-free while
AMF7 is most desirous when 'Cout' is erroneous.
Appendix A. Supplementary data
Supplementary data to this article can be found online at https://doi.
org/10.1016/j.mejo.2018.10.010.
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