2.

1 Introduction
active and passive components are
The term IC meansintegrated circuit where all the
are produced by the monolithic process. In
fabricated on the same chip. Most of the ICs
elements like
this process, all the active elements like transistors and all the passive
on a single piece of semiconductor material,
resistances, capacitances are fabricated
or a substrate. Such a monolithic process
generally silicon. This is called silicon water
makes low costmass production of ICs possible.
With the help of ICs the circuit design becomes very simple. The variety of useful
circuits can be built without the necessity of knowing about the complex internal
circuitry. The components used in ICs have different look than the corresponding
conventional components but their electronic functioning is same, infact more reliable.

2.1.1 Advantages of IC Technology

The integrated circuit (IC) technology offers various advantages such as,

1. Small size:
Practically size of an IC is thousands of times smaller than the discrete circuit.

2. Low cost:

Thousands of silicon wafers consisting of number of components individualiy, are

produced simultaneously, called mass production. Due to this, cost of IC is very very
low and hence millions of ICs are now in use, annually.
3. Less weight:

Number of components are fabricated on a single silicon wafer hence weight of IC is

very much less compared toa discrete circuit consisting of same number of components

4. Low supply voltages

ICs work at lower voltages which avoids the need of the large supply voltages.
5. Low power consumption
The power consumption of ICs is very very low.

6. Highly reliable
Due to absence of soldered connections and less interconnections, the ICs are
highly
reliable from the pertormance point of view. Due to low power consumption, the
temperature rise of ICs is also low which further increas s the reliability, accuracy and

the life of ICs.

7. Matched devices:
In IC technology, the characteristics of devices can be matched to a high degree or
accuracy. Such accurately matching of conventional devices is very difficult. Such
matching devices are
important in achieving functions like temperature compensation.
8. Fast speed
With ICs, the various
applications work with great This is
can
speed. mainly because
the absence of
effects like parasitic
capacitances in ICs.
Thus the ICs are used
popularly because of versatility, flexibility, dependability
alongwith the above mentioned
advantages.
The operational amplifier most commonly referred as op-amp was introduced in
1940s. Since then, op-amp is used in many electronic
application circuits. The linear IC
version of op-amp has now become an integral part of almost every electronic circuit
which uses IC technique. The IC op-amps are used in the fields of
process control,
computer systems, communication circuits, power and signal sources and displays.
The basic building block of modern linear IC
op-amp is the differential amplifier.
The differential amplifier amplifies the difference between the two
input signals. The
analysis of the differential amplifier prepares the background for the analysis and design
procedures for the IC op-amps. This chapter includes the analysis of the differential
amplifier and various circuit configurations used for linear IC op-amps.
2.2 Classification of ICs
The ICs are broadly classified as,
1. Digital ICs
2. Linear ICs
The requirements of the above two
types of ICs are different hence methods of
fabricating these two types of ICs are also ditferent. The various technologies jused to
fabrieate these ICs are,
1. Monolithic technology.
2. Thick and thin film technology.
3. Hybrid technology.
2.2.1 Monolithic Technology
In monolithic ICs all the active gs well as passive components along with
interconnections are integrated on a single crystal. The word 'monolithic is originated
from Greek word and
means
ds tne components are integrated on a
'single stone' or Lone stone'. Thus this word is appropriate
single piece of silicon crystal. The tabrication or
TECHNICAL PUBLICATIONS- An up thrust for knowledge
 different discrete devices such as diodes transistors and integrated circuits is carried out
by the same technology. The various processes involved in-the fabrication of ditterent
devices are carried out in a single plane. Hence this is also referred as a planar
technology.
The Fig. 2.1 (a) shows the 'can' type enclosure used for monolithic ICs while the
Fig. 2.1 (b) shows the 'plastic' package used for monolithic ICs.
Connecting
Silicon chip Silicon wires
Connecting chip
wire
Insulation Base
plate
Terminal Terminal
pins pins
(a) Monolithic IC in can-type enclosure (b) Monolithic IC in plastic package
Fig. 2.1 Packages used for monolithic ICs
The monolithic ICs are further classified based on the active devices
classified as used. The ICs are
bipolar 1Cs and unipolar ICs. The bipolar ICs use bipolar junction
transistors (BJTs) while the unipolar ICs use field effect transistors (FETs).
Depending upon tne isolation technique used, the
p-n junctionisolation ICs and dielectric bipolar ICs are further classified as
isolation ICs.
Depending upon the type of FET used, the
MOSFET unipolar ICs and unipolar ICs are further classified as
JFET unipolar ICs.
Key Point The monolithic ICs are
preferred for the
applications in which
circuiks ure required in large number. identical electronic
The monolithic 1Cs provide lowest per unit cost but
power limitations, monolithic ICs are reliability. highest But due to the
preferred only in low power
2.2.2 Thick and Thin Film applications.
Technology
In thin-film
integrated circuits glass, or a
ceramic surface
conducting material. Here, is used to deposit films of
width-and thickness of theresistors and
films and conductors are fabricated by controlling the
resistivity. Capacitors are fabricated by by (using different materials selected for their
Inductors are sandwiching
two conducting films. film of a
fabricated by
insulating oxide between
depositing
TECHNICAL PUBLICATIONS spiral formation of film.
a
An up thrust
for
knowledge
 In thick film integrated
Conductors
circuits, silk-screen printing
to create Resistor
technique is employed
circuit pattern on a
the desired
ceramic
substrate. This is
in the Fig. 2.2. These
illustrated
circuits are also referred to as
printed thin-film circuits. Here, Connecting lead
screens are actually made of fine
Capacitor
stainless steel wire mesh, and Substrate
the inks or pastes which have
conductive, resistive, or dielectric Fig. 2.2 Enlarged portion of thick-film IC
properties. After printing, the
in the high temperature furnace to fuse the films to the substrate.
circuits are kept
better
Key Point Integrated circuits fabricated by thin or thick film techniques usually have
than monolithic
component tolerances and they provide better high-frequency performance
integrated circuits.
2.2.3 Hybrid Technology
Hykridor multichip integrated
Connecting wire
circuits are Constructed by
interconnecting a number of individual
This is illustrated in Fig. 2.3. The
chips.
active Components are diffused Terminals
transistors or diodes. The passive
components are groups of diffused
resistors or capacitors on a single chip,
Discrete components
or they may be thin-film components.
The connections between chips are
2.3 multichip IC
metalized
Fig. Hybrid or
provided by wiring or
patterns.
The hybrid or multichip circuits also have better performance than monolithic circuits.
However, the fabrication process is too expensive for mass production, but it is
economical for small quantities.
 Package Types May-04, Dec.-041
24 IC
available in various packages. The IC packages are classified as,
The op-amp 1Cs are

IC package

P
Metal can Dual-in-tine Flat pack
(TO) (DIP
TOongist Fig

2.4.1 Metal Can Packages

12 pins. The metal sealing
The metal can packages are available with 3, 5, 8, 10 and
The plane is effective for the heat
plane is at the bottom over which the chip is bonded.
in which heat dissipation is
dissipation, hence these are well suited for power amplifiers
The
important. It also
permits the external heat sink. It is also called transistor pack.
shown in the Fig. 2.7.
various types of metal can packages are

Straight
leads

Dual-in-line
formed leads Radial formed
leads

(a) TO-5 style (b) TO-5 style

(c) TO-5 style
packagee package
(6,8, 10 and 12 lead) (8 lead) packagee
2.4.2 Dual-In-Line Package
The dual-in-line package is popular for commercial applications. In this type, the chip
is mounted inside a plastic or ceramic case. It is easy to handle and can be mounted
easily hence most widely used.
The 8 pin DIP is called miniDIP. But it is also available with 12 14, 16 and 20 pins.
As the number of components integrated on the same chip increases, the number of pins
also increases. For example on MC 68000 microprocessor chip, there are 64 pins.

The Fig. 2.8 shows DIP packages.

(a) 8, 14 and 16 lead version (b) 14 and 16 lead version

Plastic package welded seal ceramic package

Fig. 2.8 DIP packages

2.4.3 Flat Pack
For circuits where space is
the chip is
critical, the flat pack gives a compact package. In this
enclosed in a type,
the sides and ends. It is rectangular ceramic case. the terminals are taken out through
available with 8, 10, 14 or 16 leads.
The Fig. 2.9 shows 10
pin flat package.

10 lead version

Fig. 2.9 Ceramic flat

package
TECHNIÇA PLURI
2.7 Op-amp Symbol and Terminals May-04, Dec.-04

The symbol for an op-amp

Positive
supply voltage
along with terminalsS,
its various 9 +Vcc
Inverting input terminal
is shown in the Fig. 2.11 (a). o-
6) Output terminal
The op-amp is indicated OP-AMP
basically by a which triangle
points in the direction of the Non-inverting input terminal -VEE
signal flow. Negative
supply voltage
All the op-amps have atleast
Fig. 2.11 (a) Op-amp symbol
followingfive terminals:
terminal Vcc V.
i The positive supply voltage or +

terminal V EE V.
ii The negative supply voltage or
- -

i) The output terminal.

iv) The inverting input terminal, marked as negative.

v)The noninverting input terminal, marked as positive.

The input at invertingg input
terminal results in opposite polarity in
(antiphase) output. While the input
at noninverting input terminal Vcc V
results in the same polarity (phase) Vin
output. This is shown in the Op-Amp -o Vo

Fig. 2.11 (b) and (c). The input and

output are in antiphase means VEE Inverted
output with
having 180 phase difference in respect to input

between them while inphase input

and inverting terminal
output means having 0° phase Fig. 2.11 (b) Input applied to
difference in between them.
 VcC Vo
Op-Amp A -t

t VEE Noninverted
output in phase with
input

Fig. 2.11 (c) Input applied to noninverting terminal

The op-amp is fabricated on a tiny silicon chip and packaged in a suitable case. Fine
gauge wires are used to connect the chip to the external leads.

2.7.1 Power Supply

The op-amp works on a dual supply. A dual supply consists of two supply voltages
both dc., whose middle point is generally the ground terminal.
The dual supply is generally balanced i.e. +Vcc +15 V +Vcc +15 V
the voltages of the positive supply +Vcc and +

that of the negative supply - VEE are same in

magnitude. The typical commercially used

power supply voltages are t 15 V. But if the
two voltage magnitudes are not same in a
dual supply it is called as unbalanced dual
supply. The balanced and unkalanced types of -VEE -15 V -VEE -12 V
dual supply are shown in the Fig 2.12 (a) and (a) Balanced (b) Unbalanced
(b) respectively. Fig. 2.12 Types of dual supply
Practically in most of the op-amp circuits
balanced dual supply is used. The other
t9 V, t 12 V, t 22 V etc.
popular balanced dual supply voltages are
2.8 Block Diagram Representation of Op-amp May-05
As mentioned earlier, now a days op-amps are available in an integrated circuit form.
blocks. The
Commercial integrated circuit op-amps usually consists of four cascaded
block diagram of IC op-amp is shown in the Fig. 2.14.

Input 2
Intermediate Buffer and level Output Output
Input
stage stage shifting stage stage
Input1+

Fig. 2.14 Internal block schematic of an op-amp

2.8.1 Input Stage

The input stage requires high input impedance to avoid loading on the sources. It
requires two input terminals. It also requires low output impedance. All such
requirements are achieved by using the dual input, balanced output differential
amplifier as the input stage. The function of a differential amplifier is to amplify the
difference between the two input signals. The differential amplifier has high input
impedance. This stage provides most of the voltage gain of the amplifier.

2.8.2 Intermediate Stage 9 A m

The output of the input stage drives the next stage which is an intermediate stage.
This is another differential amplifier with dual input, unbalanced ie. single ended
output. The overall gain requirement of the op-amp is very high. The input stage alone
cannot provide such a high gain. The main function of the intermediate stage is to
provide an additional voltage gain required. Practically, the intermediate stage is .not a
single amplifier but the chain of cascaded amplifiers called multistage amplifiers.
2.8.3 Level Shifting Stage
All the stages directly coupled to each other. As the op-amp amplifies d.c. signals
are

also, the coupling capacitors are not used to cascade the

stages. Hence the d.c. quiescent
voltage level of previous stage gets applied as the input to the next
stage. Hence stage
by stage d.c. level increases well above ground potential. Such a
drive the
high d.c. voltage leve!
may transistors into saturation. This further
may cause distortion in the outpur
due to clipping. This may limit the maximum a.c. output voltage
distortion. Hence before the output stage, it is swing without any
necessary to bring such a high d.
voltage level to zero volts with respect to ground.
The level shifter stage brings the d.c. level down
to ground potential, when no signa
is applied at the input terminals. Then the
signal is given to the last stage which is the
output stage.

IN DOA DUDI InATIOLOM

2.8.4 Output Stage
The basic requirements of an output stage are low output impedance, large a.c.
output voltage swing and high current sourcing and sinking capability.
The push-pull complementary amplifier meets all these requirements and hence used
as an output stage. This stage increases the output voltage swing and
keeps the voltage
swing symmetrical with respect to ground. The stage raises the current supplying
capability of the op-amp.
2.13 Characteristics and Performance Specifications of Op-amp
Dec.-11
Let us study the various electrical characteristics of an op-amp which are generally

mentioned in the data sheet.

2.13.1 Input Offset Voltage

Whenever both the input terminals of the op-amp are grounded, ideally the output
a small
voltage should be zero. However, in this condition, the practical op-amp shows
non-zero output voltage. This is due to mismatching present in
the internal circuit of an
for which op-amp is
op-amp. Such a voltage can cause error in the practical application,
used.
between
1o make such a voltage zero, it is necessary to apply small difference voltage
tne two input terminals of an op-amp. This voltage is called input offset voltage.
 Ihe ditterential that must be applied between the two input terminals of
voltage an|
op-amp, to make the output voltage zero is called input offset voltage and denoted as

i0s

ViosIVdet-Vacel
Vdot
Small O Output
741
o
o output
voltage Vios 741
of 9 voltage
is zero
present
Vdc2

(a) (b)

Fig. 2.31 Concept of input offset voltage

The Vios Ccan be positive or negative hence absolute value of the Vios is mentioned in
the data sheet.
The smaller the value of Vios, better is the matching of the input terminals.
The input offset voltage depends on the temperature.
Many time voltage to one of the
input terminals is applied with the proper polarity
so as to null the
output, keeping other input terminal grounded. For ideal op-amp, Vios
is zero, hence
practical op-amp model is generally shown as in the Fig. 2.32 with the
indication of the input offset
voltage. For op-amp 741C the input offset voltage is 6 mV.

ldeal
op-amp

O-

Practical
op-amp

Fig. 2.32 Practical op-amp model

with Vios
2.13.2 Input Offset Current
The input stage of the op-amp is the dual input differential amplifier and the input
terminals are the base terminals of the two transistors as shown in the Fig. 2.33. Hence
the input currents of op-amp are the base currents of the two transistors Q1 and Q2 used
in the input stage. Ideally, Q and Q must be perfectly matched and two base currents
must be equal. But practically the two input base currents differ by small amount.

-Op-amp
Input
b1
1
Input
2

. . .

Fig. 2.33 Concept of op-amp input currents

difference between the currents flowing into the two input terminals of
The algebraic
offset current and denoted os Mathematically it is
the op-amp is called input as

expressed as,

Iios |Ib1-Ib2l
Where Ipi Current entering into noninverting input terminal.

and Ib2 = Current entering into inverting input terminal.

is while for op-amp 741C, maximum value of lios is 200 nA.

Ideally Iios zero

the output though input terminals are

This current is responsible to produce
grounded.

2.13.3 Input Bias Current

into the op-amp input terminals is
The average value of the two currents flowing
called input bias current and denoted as Ip. It is shown in the Fig. 2.34.

Mathematically it is expressed as,

I Ib1+Ib2
2
value of h, is 500 nA.
Ideally it should be zero while for op-amp 741C, maximum
2.13.4 Differential Input Resistance

It is also called input resistance of op-amp.

It is the equivalent resistance measured at either the inverting or non-inverting input

terminal with the other input terminal grounded. It is denoted as R,

it should be infinite while for op-amp 741C it is of the order of 2 M2 For

For
ldeally
.

FET input op-amps, it can be as high as few G2 (10 2).

2.13.5 Input Capacitance

It is the equivalent capacitance measured at either the inverting or non-inverting
input terminal with the other input terminal grounded. It is denoted as Ci.

For op-amp 741C, it is 14 pF.

2.13.6 Open Loop Voltage Gain

It is the ratio of output voltage to the differential input voltage, when op-amp is in
without any feedback. It is also called large signal voltage gain
open loop configuration,
and denoted as AoL

Va
AOL
Va
For op-amp 741C, it is typically 200,000.

2.13.7 CMRR
It is the ratio of differential voltage gain Ad to the common mode voltage gain A.

CMRR =Ad
Ac
the
but open loop voltage gain AoL and A, is measured by using
Now Ad is nothing
circuit as shown in the Fig. 2.35.
to both the input terminals of op-amp. Then
The common mode input Ve is applied
mode gain A. can be obtained as,
output Voc is measured. Then
common
the

VOc
 NcC
Common
Noc
741 o Output
mode input for
common

mode input
v.O NEE

Fig. 2.35 Measurement of Ac

It is generally very small and not specified in the data sheet. The CMRR is generally

for the op-amp and is expressed in dB. For op-amp 741C it is 90 dB.
specified
Key Point Higher the value of CMRR, better is the ability of the op-amp to reject the
common mode signal.

2.13.8 Output Voltage Swing

The op-amp output voltage swing is limited. It gets decided by the supply voltages. It
never exceeds the limits +Vcc and -VEE Above these values, op-amp output gets
saturated.

Thus note that the op-amp output voltage gets saurated at +Vcc and - VEE and

it can not produce output voltage more than + Vcc and - VE Practically
saturation voltages +Vsat and - Vsat are slightly less than +Vcc and - VEE

For op-amp 741C, the saturation voltages are t 13 V for supply voltages t 15 V. Thus
it can produce undistorted sine wave of the maximum amplitude 13 V, for a.c. input
applied to it.

2.13.9 Output Resistance

It is the equivalent resistance measured between the output terminal of the op-amp
and the ground.

It is denoted as R, and for op-amp 741C it is 75 2. Its value must be as low as

possible.

2.13.10Offset Voltage Adjustment Range

The op-amps like 741 are given pins for offset nulling. The pins 1 and 5 are offse
null pins for op-amp 741. A 10 k2 potentiometer can be connected between the pins
and 5. The variable end of the potentiometer is connected to
VEE By varying
the output can be adjusted
notentiometer,
P
to zero.
The range for which input offset voltage can be adjusted using the potentiometer so
as to reduce output to zero, is called offset voltage adjustment range.
+cC
741 -o Output
www-
10 k2
Potentiometer
Fig. 2.36 Offset nulling of op-amp
For op-amp 741 C, it is t 15 mV.
2.13.11 Input Voltage Range
It is the range of common mode voltages which can be applied for which op-amp
functions properly and given offset specifications apply for the op-amp. This range is
also dependent on supply voltages. Thus for t 15 V supply voltages, the input voltage
range is t 13 V for the op-amp 741C.
For voltages between t 15 V and t 13 V, the op-amp does not get damaged but does
not function properly, producing saturated output, reversal of polarity etc.
Supply Rejection Ratio
2.13.12 Power
The power supply rejection ratio (PSRR)
is defined as the ratio of the change in input
offset voltage due to the change in supply
voltage producing it, keeping other power
also called
It is Op-amp
Supply voltage constant.
power supply sensitivity (PSV).
-VEE
Now if VEE is constant and due to certain
change in Vcc, there is change in input
offset voltage then PSRR is defined as,
Fig. 2.37
2.13.15 Gain-Bandwidth Product

It is the bandwidth of op-amp Gain

when voltage gain is unity (1). It is in dB Gain reduces
as frequency
denoted as GB. The gain is generally increases

expressed in dB. Thus unity gain has

dB value 20 log 1 = 0 dB. So on the

graph of gain in dB against

f
frequency, the GB can be shown as 1 MHz Frequency
in the Fig. 2.38. It is about 1 MHz (GB)
for op-amp 741C. The GB is also
Fig. 2.38 Gain-bandwidth product
called unity gain bandwidth (UGB)
or closed loop bandwidth.
 A.C. Characteristics of Op-amnp ec.11
2.9 and 2.
The important a.c.
characteristics of op-armp are, 1. Slew rate
Frequenc
response.

2.19.1 Slew Rate

the maximum rate of change of output voltage with time

The slew rate is defined
as

in V/usec. Thus
The slew rate is specified
dVo 0)
Slew rate = S =
.

dt max

The slew rate is caused due to limited charging rate of the compensating capaciter-
of an op-amp, when a high
and current limiting and saturation 'of the internal stages
The internal capacitor voltage cannot
frequency, large amplitude signal is applied.
For large charging rate, the capacitor
change instantaneously. It is given by dt
should be small or charging current should be large.
Hence the slew rate for the op-anmp whose maximum internal capacitor charging
current is known, can be obtained as

S max ... (2)

C

for IC 741 the 1s

For example, charging current is 15 uA and the internal capacitor
30 pF, hence its slew rate is
15x10-6 0.5
S = 0.5
30x 10-12 10-6V/sec
=
V/usec
2.19.1.1 Effect of Slew Rate Input
Consider a circuit using
op-amp having unity gain. Thus
output is same as inpu If the
input is square wave, output has Nm
to be square wave. But this is
observed for certain trequency of Output (Distorted)
input. Due to slew rate of an
*m
op-amp, for a particular input \AV
t
frequency, output gets distorted
as shown in the Fig. 2.47.
Then observing such a
distorted waveform on CRO the AT
slew rate can be obtained Fig. 2.47 Effect of slew rate
S = AVo
At V/sec
The typical value of S for IC 741 op-amp is 0.5x106 V/sec ie. 0.5 V/usec. Ideally it
should be infinite.
Key Point Higher the value of S, better is the performance of op-amp.
219.1.2 Slew Rate Equation
Consider unity gain op-amp circuit with purely sinusoidal input. The output must be
same as input.
Vs Vm Sin ot (3)
Vo= Vm Sin Ot (4)
dVo = Vm(ocosot) . (5)
dt
But S = Slew rate dV . (6)
dt
al lmax
The equation (5) has maximum value when cosot = 1.
S = Vm= 27tfVm
S 27tfVm V/sec (7)
This is the required slew rete equation.
 Characteristiccs
2.15 Ideal Op-amp
ideal op-amp. It V2 =0
The Fig. 2.40 shows an AoL
has two input signals Vi V2 and applied to Vd0 OP-AMP
and inverting terminals, A
non-inverting
Vi 1 1 =0
respectively.,
following things be observed for
The can
Fig. 2.40 ldeal op-amp
the ideal op-amp shown in the Fig. 2.40.

An ideal op-amp draws no current at both

the input terminals i.e. I1 =
I2 0. Thus
=

1) no loading on
drive it and there is
its input impedance is infinite. Any source
can

the driver stage.

2) The gain of an op-amp is infinite (), hence

ideal the differential input
Vd =Vi-V2 is essentially zero for the finite output voltage Vo

3) The output voltage Vo is independent of the current drawn from the output
terminals. Thus its output impedance is zero and hence output can drive an infinte
number of other circuits.
These properties are expressed generally as the characteristics of an ideal op-amp. 1e

various characteristics of an ideal op-amp are

a) Infinite voltage gain
:
(AoL =
)
It is denoted as A oL. It is the differential open loop gain and is infinite for an ideal

op-amp.

b) Infinite input impedance (Rin = )

The input impedance is denoted as Rin and is infinite for an ideal op-amp. This
ensures that no current can flow into an ideal op-amp.

c) Zero output impedance (R = 0)

The output impedance is denoted as Ro and is zero for an ideal op-amp. This ensures
that the output voltage of the op-amp remains same, irrespective of the value of the load
resistance connected.

d) Zero offset voltage (Vios 0)

The presence of the small output voltage though V1 = V2 0 is called an offset
voltage. It is zero for an ideal op-amp. This ensures zero output for zero input signal
voltage
e) Infinite bandwidth:

The range of frequency over which the amplifier performance is satisfactory is called
its bandwidth. The bandwidth of an ideal op-amp is infinite. This means the operating
frequency range is from 0 to o This ensures that the gain of the op-amp will be
constant over the frequency range from d.c. (zero frequency) to infinite frequency. So
op-amp can amplify d.c. as well as a.c. signals.

Infinite CMRR : (p = o)

The ratio of differential_gain and common mode gain is defined as CMRR. Thus
infinite CMRR of an ideal op-amp ensures zero common mode gain. Due to this
common mode noise output voltage is zero for an ideal op-amp.

g) Infinite slew rate (S o )

This ensures that the changes in the output voltage occur simultaneously with the
changes in the input voltage.
The slew rate is important parameter of op-amp. When the input voltage applied is

step type which changes instantaneously then the output also must change rapidly as

input changes. If output does not change with the same rate as input then there occurs
distortion in the output. Such a distortion is not desirable. Infinite slew rate indicates
that output changes simultaneously with the changes in the input voltage.
The parameter slew rate is actually defined as the maximum rate of change of output

voltage with time and expressed in V/us.

 Slew rate = S = aVo
dt maximum

Its ideal value is infinite for the op-amnp.

h) No effect of temperature:
The characteristics of op-amp do not change with temperature.

i) Power Supply Rejection Ratio : (PSRR = 0)

The power supply rejection ratio is defined as the ratio of the change in input offset
voltage due to the change in supply voltage producing it, keeping other power supply
voltage constant. It is also called power supply sensitivity.
So if is constant and due to
VEE change in Vcc there is change in input offset voltage
then PSRR is expressed as,

A A Vios
PSRR A ccIVEE Constant

For fixed Vcc, if there is in

a
change VEE Causing change in input offset voltage then,

PSRR = 4 Vios
A VEE
IvC Constant
It is expressed in
mV/V or uV/V and its ideal value is zero.
These ideal characteristics of
op-amp are summarized in the Table 2.5.

Characteristics Symbol Values

Open loop voltage gain
Aou
Input impedance R in
Output impedance Ro 0
Offset voltage ** -

V
Bandwidth B.W.
C.M.R.R.
Slew rate
S
Power supply rejection ratio
PSRR 0
Table 2.5 ldeal
op-amp characteristics
2.16 Voltage Transfer Curve of Op-amp

The graph of output voltage Vo plotted against the differential input voltage Va i
aceiuming gain constant is called voltage ransfer curve or characteristics of op-amp.

2.16.1 ldeal Voltage Transfer Curve

loop gain of
Ideally open
VAoLVd
op-amp is oo,

AoL Vo
Va oc
N sat

Va Vo 0 Ao
N
Thus for zero input, the output
of op-amp is always at saturation VsattVcc
level Vsat due to infinite gain. N sa
Thus voltage transfer curve for
ideal op-amp is a vertical line as
shown in the Fig. 2.41.
Fig. 2.41 ldeal voltage transfer curve

Thus ideally range of input for

linear operation of the op-amp is zero.

2.16.2 Practical Voltage Transfer Curve

Practically AoL is finite for the op-amp. For op-amp 741C, it is 2x10°.

V = AoL Va

tVsat 2x10 Vd
The saturation voltages are almost t 15 V.

t15
Va = t 75 V
2x10

Hence practically till Va is between - 75 uV and + 75 uV, the output will vary
linearily with input. But once V exceeds t 75 uV, the output is saturated.
 is shown in the Fig. 2.42.
Thus the practical voltage transfer curve as
V
+Vsat
a b
N -+Vd
Nsat
Fig. 2.42 Practical voltage transfer curve
Thus,
i) If Va is greater than corresponding to b, the output attains +Vsat
ii) If Va is less than corresponding to a, the attains
output -
Vsat
ii)Thus range a-b is input range for which output varies linearily with the input. But
bul
as
Ao is very high, practically this range is very small.
 DIOC
op-amP
1.2 Basics of Differential Amplifier

Key Point The differential amplifier amplifies the difference between wo input voltage
signals. Hence it is also called difference amplifier.

Consider anideal differential

amplifier shown in the Fig. 1.1.
V and Vare the two input
signals while Vo is the single ended Ideal
Differential
output. Each signal is measured with Amplifier
respect to the ground.

In an ideal differential amplifier, the

is proportional to
output voltage Vo 1.1 Ideal differential amplifier
the difference between the two input Fig.

signals. Hence we can write,

..(1)
Vo (V1 -V2)

1.2.1 Differential Gain Ad

From the equation (1) we can write,

Vo = Ad (V1 - V2)
...(2)

The is the gain with which differential

is the constant of proportionality.
Aj
where Aj Hence it is called
the difference between two input signals.
amplifier amplifies
of the differential amplifier.
differential gain
Thus, Ad = differential gain
difference
V») is generally called
The difference between
the two inputs (V1
and denoted as Vd
voltage ..(3

VoAd Vd
can be expressed as,
Hence the differential gain
..(4

Vo
AdVd
 Generally the differential gain is expressed in its decibel (dB) value as,

Ad 20 Log10 (A d) in dB .(5)

1.2.2 Common Mode Gain Ac

If we apply two input voltages which are equal in all the respects to the differential
amplifier i.e. Vi = V2 then ideally the output voltage Vo = (V1 - V2) Aa must be zero.

But the output voltage of the practical differential amplifier not only depends on the
difference voltage but also depends on the average common level of the two inputs
Such an average level of the two input signals is called common mode signal denoted
as V

Ve = +V2 ...(6)
2

Practicaliy, the differential amplifier produces the output voltage proportional to such
common mode signal, also.

Key Point The gain with which it amplifies the common mode signal to produce the output
is called common mode gain of the differential amplifier denoted as A

Vo AVe ...(7)
Thus there exists some finite output for V1 =
V2 due to such mode
common gain A
in case of practical differential amplifiers.
So the total output of any differential
amplifier can be expressed
V Ad Va +Ac Ve (8)
This shows that if input is 25
one
uV and other is -25 V then the output of the
+

amplifier will not be same, with the inputs as 600 uV and 650 uV, though the difference
between the two sets of the
inputs is 50 uV.
Key Point For an ideal differential amplifier, the differential gain A4
the mode
must be infinite while
common gain must be zero. This ensures zero output for V1 =
V2
But due to mismatch in the internal circuitry, there is
output available for some
V =
V2 and gain A, is not
practically The value of zero.
such common mode
small while the value of
gain Ac is
very very the differential gain
Ad always very large.
is
At this stage, we can define ore
important parameter of the differertial amplifier
known as common mode rejection ratio
(CMRR).

TECHNICAL PUBIJCATIONG"A. 4 ,
12.3 Common Mode Rejection Ratio (CMRR)
When the same voltage is applied to both the inputs, the differential amplifier is said
operated in a
to be common mode configuration. Many disturbance signals, noise signals
appear as a common input signal to both the input terminals of the differential

amplifier. Such a common signal should be rejected by the differential amplifier.

The ability of a differential amplifier to reject a common mode
signal is expressed by
a ratio called common mode rejection ratio denoted as CMRR.

It is defined as the ratio of the differential voltage gain Aj to common mode voltage
gain Ac
CMRR =
p =| A 9)

Key Point ldeally the common mode voltage gain is zero, hence the ideal value of CMRR is

inifinite.
For a practical differential amplifier Aj is large and A is small hence the value of
CMRR is also very large.

Many a times, CMRR is also expressed in dB, as

CMRR in dB = 20 logd dB (10)

The output voltage can be expressed in terms of CMRR as below

V = Ad Va+Ac Ve = Aa Va|l+A
d d

1Ve
Vo =
1+
AaVa Ad)Va
Ac

Aa . .(11)
Vo =

Va|lCMRR Va
This equation explains that as CMRR is practically very large, though both V, and Va
components are present, the output is mostly proportional to the difference signal only.
The common mode component is greatly rejected.
 1.3 Transistorised Differential Amplifier
The transistorised ditterential
amplitier basically uses the emitter VcC
biased circuits which are identical in
characteristics. Such two identical
emitter biased cireuits are shown in
the Fig. 1.3.
Rc Rc2

The two transistors C

Q and Q
have exactly matched characteristics. B
The two collector resistances Rcand a
Rc are equal while the two emitter
E
resistances REI and RE2 are also
equal. RE RE23
Thus Re1 =
Rc2 and RE1= R E2
Themagnitudes of +Vcc and
-

VEE are also same. The differential NEE

amplifier can be obtained by using
such two emitter biased circuits. This Flg. 1.3 Emitter blased circuits
is achieved by connecting emitter E
of Q to the emitter E2 of Q2. Due to this, R1 appears in parallel with R and the
combination can be replaced by a single resistance denoted as R:. The base B, of Q is
connected to the input 1 which is VsI while the base B, of Q2 is connected to the
input
2 which is Vs2. The supply
voltages are measured with respect ground. The balanced
to
output is taken between the collector Ci of Q | and the collector C of O». Such arn
amplifier is called emitter coupled differential amplifier. The two collector resiatance
are same hence can be denoted as R(
 The
output can be taken between two collectors
or in between one of the twO
collectors and the
ground. When the output is taken between the two collectors, none ot
them is grounded
then it is called balanced output, double ended outut or floating
output.
When the output is
taken between any of the +NcC
collectors and the ground,
it is called unbalanced
output or single ended Rc 2 Ro
output. V
The complete circuit Rs1 w
R$2
diagram of such a basic
dual input, balanced
output differential s
amplifier is shown in the
Source
RE Source
Fig. 14. signal signal
As the output is taken VEE
betweenn two output Fig. 1.4 Dual input, balanced output differential amplifier
terminals, none of them is

grounded, it is called balanced output differential amplifier.

Let us study the circuit operation in the two modes namely

i) Differential mode operation

ii) Common mode operation.

1.3.1 Differential Mode Operation

In the differential mode, the +VcC
two input signals are different
from each other. Consider the Rc A
two input signals which are C2
same in magnitude but 180° out R$1 Rs2
W
of phase. These signals, with w
A
opposite phase can be obtained
from the center tap transformer. RE
The circuit used in differential -VEE
mode operation is shown in the Center tap transformer
Fig. 1.5. 0000

Souce
Fig. 1.5 Differential mode operation
 As e that the sine wave n the baNe ot Q
positive going while on the base of
gative going. Witlh a positive going ignal on the bare of Q, an amplified
atiye Hoing signal develops on the collector of Q Due to positive going signal,
vurtent thonngh R alO inereases and henee a positive going wave is developed across
R u e to negative going signal on the base of Q2, an amplified positive going signal
develops on the collector of Q. And a negative going signal develops across R
wuse ot emitter follower action of Q2
So signal voltages across R, due to the effect of Q and Q2 are equal in magnitude
and 180out of phase, due to matched pair of transistors. Hence these two signals cancel
ah other and there is no signal across the emitter résistance. Hence there is no ac.
current flowing through the emitter resistance. Hence R in this case does not
signal
intrduce negative feedback.

While Vo is the output taken across collector of Q 1 and collector of Q2. The two
outputs on collector 1 and 2 are equal in magnitude but opposite in polarity. And V is
the ditterence between these two signals, e,g. +10-(-10) = +20.

the signal voltage from either

Key Point Hence the ditference output V, is twice as large as
collector to ground.

1.3.2 Common Mode Operation

are derived from the
In this mode, the signals applied to the base of Q 1 and Q2
same source. So the two signals are equal
in magnitude as well as in phase. The circuit
is shown in the Fig. 1.6.
diagram

Re Rc
C
Rs1 Zero
Rs2
w

RE
-VEE

Fig. 1.6 Common mode operation

 In phase signal voltages the bases of Q and Q2 causes in
at 1 phase signal voltages
to appear across RE, which add together. Hence Rg carries a signal current and

provides a negative feedback. This feedback reduces the commón mode gain of
differential amplifier.
While the two signals causes in phase signal voltages of equal magnitude to appear
across the two collectors of Qi and Q2. Now the output voltage is the difference
between the two collector voltages, which are equal and also same in phase,
e.g. (10) - (10) = 0. Thus the difference output Vo is almost zero, negligibly small,
ldeally it should be zero.

1.4 Differential Amplifier Circuit Configurations

The differential amplifier, in the difference amplifier stage in the op-amp, can be used
in four configurations:
i) Dual input, balanced output differential amplifier.
ii) Dual input, unbalanced output differential amplifier
+Vcc +Vcc

Re Rc Rc2 Vo
Rs Rs Rs
ww wof
Vs Vs2Vs1 Vsz

RE RE
NEE VEE
(a) Dual input balanced output (b) Dual input unbalanced output

9+Vcc +Vcc

RcZ Rc Rc
Rs1 Rs1
wwot wwoft

RE
O
NEE EE
(c) Single input balanced output (d) Single input unbalanced output
 ii) Single input, balanced output differential amplifier.

iv Single input, unbalanced output differential amplifier

The differential amplifier uses two transistors in common emitter configuration. If
output is taken between the two collectors it is called balanced output or double ended
output. While if the output is taken between one collector with respect to ground itis
called unbalanced output or single ended output. If the signal is given to both the
input terminals it is called dual input, while if the signal is given to only one input
terminal and other terminal is grounded it is called single input or single ended input.
Out of these four configurations the dual input, balanced output is the basic
differential amplifier configuration. This is shown in the Fig. 1.7 (a). The dual input,
unbalanced output differential amplifier is shown in the Fig. 1.7 (b). The single input,
balanced output differential amplifier is shown in the Fig. 1.7 (c) and the single input,
unbalanced output differential amplifier is shown in the Fig. 1.7 (d).
The operation of dual input balanced output differential amplifier in differential mode
and common mode is already discussed in the last section. This configuration is also
called symmetrical differential amplifier.
3.2.2 Virtual Ground
This means the differential input voltage Va between the non-inverting and inverting
input terminals is essentially zero.
This is obvious because even if output voltage is few volts, due to large open loop
gain of op-amp, the difference voltage Va at the input terminals is almost zero.
 e.g. if output voltage is 10 V and the
AoL i.e. open loop gain is 10 then
Vo Va AoL
=

Vo 10
Va 1 mV
AOL 104

Hence Vd is very small. As AOL o, the difference

assumed to be zero tor analysing the circuits.
voltage Va 0 and realistically
Vo
Va = AOL

(-V2) = Vo ==00
V1 = V2
.(1)
Thus we can say that under linear range of operation there is virtually short circuit
between the two input terminals, in the sense
that their voltages are same. No current flows
R R
w w - Vo
I I
from the input terminals to the ground. The
Fig. 3.1 shows the concept of the virtual ground. v Virtual
short
I = 0

The thick line indicates the virtual short circuit

between the input terminals.
Now if the non-inverting terminal is
Fig. 3.1 Concept of virtual ground in
grounded, by the concept of short, the
virtual an op-amp
inverting terminal is also at ground potential,
though there is no physical connection between the inverting terminal and the ground.
This is the principle of virtual ground.
Key Point the equation (1), the voltage at the non-inverting input terminal
Thus from
of an op-amp can be realistically assumed to be equal to the voltage at the
op-amp can
inverting input terminal.
3.3 ldeal Inverting Amplifier
As the name suggests the output of such an amplifier Is inverled ah conpared to he

input signal. The inverled

oulput
signal means having a phase shift of ANNV
180 as compared to the input signal.
So, an amplifier which provides a R
phase shift of 180° between input and v w
T A0
output is called inverting amplifier.
The basic circuit diagram of an
inverting amplifier using op-amp is
shown in the Fig. 3.2 (a). Flg. 3.2 (a) Inverting amplifler

Derivation of closed loop gain

As nodeB is grounded, node A is also at ground potential, from the concept of
virtual ground, so VA = 0.

I = VinVA
R

I = in ... (1)
R

Now from the output side, considering the direction of current I we can write,
VA-Vo
R

I = V (2
R

Entire current I passes

through Rs as
op-amp input current is zero.
Equating equations (1) and (2) we get,
Vin Vo
R Rf

Vo R
AyF VVi in (Gain with
R feedback) . (3

The is the gain of the

cmplifier while negative sign of
R indicates that the polarity
output is opposite to that ot
input. Hence it is called inverting amplifier.
 The input and output waveforms are shown in the Fig. 3.2 (b).

Vn
(Input)

Timet

Vo Phase shift
(Output) of 180

Timet

Fig. 3.2 (b) Wavefoms of inverting amplifier

Observations

1. The output is inverted with respect which is indicated

to input, by minus sign.
2 The voltage gain is independent of open loop gain of the op-amp, which is
assumed to be large.
3 The voltage gain depends on the ratio of the two resistances. Hence selecting R
and R, the required value of gain can be easily obtained.

4. If R >
R1, the gain is greater than 1
If R < R, the gain is less than 1.

R = R 1, the gain is unity.

hus the
output voltage be greater than, less than
can or
equal to the input
voltage, in magnitude.

5. If the ratio of R, and R is K whuch is other than one, the cireuit is called scale
changer while for R R 1 it is called phase inverter.

6. The closed loop gain is denoted ds

Ayi r
Ayci t.e. gain with teedback.
3.3.1 Sign Changer
In the ideal inverting amplifier if R¢ = R1 then the gain is ACL = -1. Thus the

magnitude of output is same as that of the input but its sign is opposite to that of the
input.
Vo =Vin for R =R

This circuit is called sign changer or phase inverter.

3.3.2 Scale Changer

In the ideal if R¢ # R1 then the gain is AcL - K where
inverting amplifier
K Rf/R1. Thus the circuit is used to multiply input by a constant K called scaling
factor.
Vo=-KVin
The resistances must be precision resistors to adjust the scaling factor K precisely.
This circuit is called scale changer.
3.4 ldeal Non-inveting Amplifier
An amplifier whichamplifies the R
input without producing any phase w
shift between input and output is
called non-inverting amplifier. The
basic circuit diagram of a

non-inverting amplifier using op-amP

is shown in the
Fig. 3.5 (a). The input
is applied to the
non-inverting input
terminal of the op-amp.

Derivation Fig. 3.5 (a) Noninverting amplifer

of closed loop gain
The node B is at potential Vin, hence the of
potential point A is same as B which is
Vin, from the concept of virtual share.

VA VB =Vin (1)
From the output side we can write,
I= VA
RE
I =-Vn
RE 2

At the inverting terminal,

I = VA-0
R
I =in
R ()

Entire current passes

through R^ as input current of op-amp is zero.
Equating equations (2) and (3),

V-in=
R
Vin
R
V in.
Rr R R

R in RR
R R
 pnduoS Or Op-amp

(R+Rr)Rr R+Rr
Vin R Rr R

AVF Vin=1 R
(4)

nsiive sign indicates that there is no phase

The shift between input and output.
The input and output waveforms are shown in the Fig. 3.5 (b).

Vin
(Input)

Timet

Vo No
(Output). Phase
shift

Timet
0

Fig. 3.5 (b) Waveforms of non-inverting amplifier

3.4.1 Comparison
the ideal inverting and non-inverting
ne lable 3.1 provides the comparison of
amplifier op-amp circuits.
Ideal non-inverting amplifier
Sr. No. ldeal inverting amplifier
Voltage gain
= 1 +(R;/Ri)
Voltage gain = - Rs/R

shift between input and

to No phase
he output is inverted with respect
output.
nput.
is always greater than
as The voltage gain
ne
voltage gain can be adjusted
One.
ne.
8Teater than, equal to or less than
impedance is
extremely large.
The input
The input impedance is R
Table 3.1
3.9 Voltage Follower (Buffer) Dec.-05

A circuit in which the output voltage follows

the input voltage is called voltage follower circuit.
The voltage follower circuit using op-amp is
is
A o Vo
shown in the Fig. 3.20.
The node B is at potential Vin Now node A is
B
also at the same potential as B i.e. Vin Vin
VA = VB = Vin (1)

Now node A is directly connected to the

Fig. 3.20 Voltage follower
output. Hence we c a r write,

No VA
Vo (2)

Equating the equations (1) and (2),

. 3)
Vo =Vin
For this circuit, the voltage gain is unity.

Thus the output voltage V, is equal Vin

to the input voltage Vin If Vin
Vm
in
increases, Vo also increases. If Vin
0
decreases, then V also decreases.
Thus output follows the input hence
the circuit is called voltage follower
Vm
circuit. It is also called source
follower, unity gain amplifier, buffer 0

amplifier or isolation amplifier. The

input and output waveforms are

shown in the Fig. 3.21.

Fig. 3.21
3.9.1 Advantages of Voltage Follower

The advantages of such voltage follower circuit are,

) Very large input resistance, of the order of M2.
2) Low output impedance, almost zero Hence it can be used to connect high
impedance source to a low impedance load, as a buffer.
3) It has large bandwidth.

4) The output follows the input exactly without a phase shift.

3.10 Summer or Adder Circuit
As the input impedance of an op-amp is extremely large, more than one input signal
can be applied to the inverting amplifier. Such circuit gives the addition of the applied
signals at the output. Hence it is called summer or adder circuit. Depending upon the
sign of the outpuy the summer circuits are classified as inverting summer and
non-inverting summer.

3.10.1 Inverting Summer

In this circuit, all the input R
R www
signals to be added applied are to
w
the inverting input terminal of the I
op-amp.The circuit with two input
A
signals is shown in the Fig. 3.24. R2 V
ww B
As point B is grounded, due to
2_ l2
virtual ground concept the node A
is also at virtual ground potential.
VA = 0 ..((1) Fig. 3.24 Inverting summer

Now from the input side,

V-VA (2)
R1 R1

2 V2-Va2
R2 R2
(3)

Applying KCL at node A and as input op-amp current is zero,

I = I1 + I2 (4)

From the output side,

I = Vo_Vo
R (5)

Substituting (5), (2) and (3) in (4),

Vo V2
R R R2
 Vo .. (6)

If the three resistances are

equal, R1 =R2 Rr
Vo - V1 + V2 ) (7)

By properly selecting Rf, R1 and R2, we can have weighted addition of the input
signals like aV1 + bV2, as indicated by the equation (6).

Infact in such a way, n input voltages can be added.

Thus the ana

Key Point
magnitude of the ouput voltage is the sum of the input voltages
hence circuit is called summer or adder circuit.

3.10.2 Non-inverting Summing Amplifier

The circuit discussed above is R
which can
ww
inverting summing amplifier,
be noticed from the negative sign in the R
wI A
equation (6). But a summer that gives
non-inverted sum of the
input signals isv, R
ww3
called non-inverting summinng
amplifier. The circuit is shown in thev,°
R2
Fig. 3.25. Fig. 3.25 Non-inverting summing amplifier
Let the voltage of node B is VB. Now
the node A is at the same potential as that of B, due to virtual ground.

VA = VB . (8)

From the input side,

V Band I2 =
V2 VB ..(9)
I1 =

R2
R
the current of op-amp is zero,
But as input
I +l2 =F .(10)

-VBV2
+
-V» 0
R R2
V
R R2 -V R2
=
(R V +R, V2) .(11)
(R +R2)
 Now at node A,

as Vg VA (12)
R

and
VVA_ V-VB .(13)
R R

Equating the two equations (12) and (13),

VB
R R

R VsRR
V R+R]
B R .(14)

Substituting equations (11) in (14) we get,

(R V +R, V»)[R +R]

R (R + R2)

R (R+Rilv+R
R (R+R2)
(R+R)
R (R+R2)
V2 (15)

The equation (15) shows that the output is weighted sum of the inputs.
R = R =R = Rf, we get

Vo V1 +V2 (16)

Key Point As there is no phase difference between input and output, it is called
1o-inverting summer amplifier.

3.10.3 Average Circuit

1f in the inverting summer circuit, the values of resistance are selected as,

R = R2 = R

R
and

Then from the equation (6) we get,

R
 Difference Amplifier Dec.-11
3.11 Subtractor or

Similar to the summer circuit, the subtraction of two input voltages is pøssible with
the help of op-amp circuit, called subtractor or differerneé ampliier circuit.
 The circuit diagram is shown in the R
Fig 3.28. wW

To find the relation between the R

inputs
and output let us use V A
Superposition principle.
R2 B
be the output, with
Let Vol input v +0
I2
Vactin8 assuming V2 to be zero.

2R
And Vo2 be the output, with input V

acting, assuming V to be zero.

Case 1 With V2 zero, the circuit

acts asS an
inverting amplifier, as Fig. 3.28 Subtractor circuit

shown in the Fig. 3.29. Hence we can

write,
R

R
V, w
Vo
R2

Fig. 3.29

Vol=
R RV1 ...(1)

the circuit reduces to as shown in the Fig. 3.30.

Case 2 While with V1 as zero,

R
w
|

R
A Vo2

R2
R
 Let potential of node B is Vg. The potential of node A is same as B ie. Va =
Vg
Applying voltage divider rule to the input V2 loop,

Rr
VB R2 tRf-V2 (2)

Now I =A VB (3)
R Ri
And I = Vo2-VA Vo2-VB (4)
R R
Equating the equations (3) and (4) e
Ve Vo2-VB
Ri Rf

Vo2 +RR Ve
R
RfV
Va2 1+R V (5)

Substituting Vg from (2) in (5) we get,

Va1 R R2+Rfj .(6)

Hence using superposition principle,

Vo Vol + Vo2

V +1R RE V2 ... (7)

R R R2 +Rr
Now if the resistances are selected as Ri =
R2,

RV+|1+RRRr V2 RRV* R
RE V2
No +(V2Vi) ..(8)

Key Point Thus the output voltage is proportional to the difference between the two npu
voltages. Thus it acts as a subtractor or difference amplifier.
3.18 Integrator May-04, Dec.-04
In an integrator circuit, the output voltage is theintegration of the input voltage. The
integrator circuit can be obtained without using active devices like op-amp, transistors
etc. In such a case a n integrator is called passive integrator. While an integrator us
will diser:s
active integrator. In this section, we
an active devices like op-amp is called
integrator circuit.
the operation of active op-amp
3.18.1 Ideal Active Op-amp Integrator
Consider the op-amp integrator circuit
as shown in the Fig. 3.63.

The node B is grounded. The node A R1 C

ww
is also at the ground potential from the
concept of virtual ground.
B
VA= 0 = VB

As input current of op-amp is zero,

the entire current I flowing through R1, Fig. 3.63 Op-amp integrator
also flows through Cf, as shown in the
Fig. 3.63.

From input side we can write,

I = Vin-VA in (1)
R RI
From output side we can write,

d (VA V,)
I = Cr
dt

dVo
I =
= -c.
dt (2)

Equating the two equations (1) and (2)

Vin Ci dt (3)
R
Integrating both sides,

0
Rdtdt=-C
R dt dt
i.e. - dt =- C¢ Vo (4)
R
Vin dt +V,(0)
Vo R,Cr (5)

There ,(0) is the constant of integration, indicating the initial output voltage.
3.18.2 Input and Output Waveforms
For simplicityy
Let us see the output waveforms, for various input signals. o-

that the time constant R Cf = 1 and the initial voltage is

understanding, assume

Vo (0) 0 V.
=

i) Step input signal

Let the input waveform is of step type,
shown in
with a magnitude of A units as Vint)
the Fig. 3.65. Input
be
Mathematically the step input can

expressed as,

.(6)
Vin (t) = A for t 20 -time(t)-
0
And =0 fort <0
with RjCf = 1 and
From equation (5),
V(0) = 0, Fig. 3.65 Step input signal
 We can write,

V) =-| Vin() dt = -

Adt =
- A | dt = -

A [U
0

V 0)=-At (7)

Thus output waveform is a straight line time(t)

with a slope of -A where A is
magnitude
of the step input. The output waveform is
shown in the Fig. 3.66.
-2 A
i) Square wave input signal

Let the input waveform is a

-3 A slope(-A)
square
wave as shown in the Fig. 3.67.
It can be observed that the square wave
Fig. 3.66 Output waveform for step input
is made up of steps i.e. a step of A
between time period of 0 to T/2 while a
Vin)
step of A units between a time period of
T/2 to T and so on.

time-
Mathematically it can be expressed as, 0 T/2

Vin(t)= A, 0 < t < T/2 (8) A

= - A, T/2 < t < T

This is the expression for the input Fig. 3.67 Square wave input signal
signal for one period.
As discussed earlier, the output for step
input is a straight line with a slope of -A.
So for the period 0 to T/2 output will be
V)
straight line with slope A. From t = T/2
O T/2 3T/2 2T
tillt =T, the slope of the straight line will time

become (-A) i.e. + A.

So the output can be expressed T
mathematically for one period as, Slope +A volts/sec.
V(t)=- At 0<t< T/2 Slope A volts/sec.

+ At T/2 < t <T (9) wave

Fig. 3.68 Output waveform for square
The output waveform is shown in the input
Fig. 3.68.
iii) Sine wave input signal
Let the input waveform is Vin)
purely sinusoidal with a frequency Saturation levels
of o rad/sec. Mathematically it can N
be expressed as, T/2 time (t)-
Vin (t) = V,m sin o t (10)

Where Vm is the amplitude of Nt

the sine wave and T be the period
of the waveform. V)
To find the output waveform,
use the equation (5) with R,Cf = 1
-V
and V,(0) = 0 V. T/2 - time (t)-
V ()=-J Vin dt
V
=-J Vm Sin ot dt
= -

Vm-cosot) Fig. 3.69 Sine wave input and cosine output

V (t) =
m(-cos t) . (11)

Thus it can be seen that the output of an integrator is a cosine waveform for a input
Due to inverting integrator, the output waveform is as shown in the Fig. 3.69.

C Vi, () Vo(t)

R Step Ramp
Vin o www-

Vo Squarewave Triangular wave

Sine wave Cosine wave

Integrator
3.20 Differentiator
Dec.-05
The circuit which produces the differentiation of the input voltage at its output is
called differentiator. The differentiator circuit which does not use any active device is
called passive differentiator. While the differentiator using an active device like op-amp
is called an açtive differentiator. Let us discuss first the operation of ideal active
op-amp differentiator circuit.

3.20.1 ldeal Active Op-amp Differentiator

The active differentiator circuit can
be obtained by
R
exchanging the
positions of R and C in the basic active
circuit. The
C
integrator op-amp Vin o-
differentiator circuit is shown in the A
Fig. 3.76. Vao
B
The node B is grounded. The node
A is also at the ground potential hence
VA = 0.

Fig. 3.76 Op-amp differentiator

As input current of op-amp is zero,
entire current I1 flows through the resistance Rs.

From the input side we can write,

=c, dViny (1)

I I1 =
C dinVA)
dt dt

From the output side we can write,

I: VAV= No
R
(2)
Rr
 Equating the two equations,
d Vin
C = Vo (3)
dt R
V - C R, dVin
in . (4)
dt

The equation shows that the output is C1Rf times the differentiation of the input and
product CRf is called time constant of the differentiator.

The negative sign indicates that there is a phase shift of 180° between input and
main advantage of such
output. The an

active differentiator is the small time R

for differentiation. ww
constant required
 Nonlinear Applicatiorns of Op-amp
Linear IC Applications 4-2 and Waveform Generators

4.1 Introduction
It is seen that op-amp in open loop configuration produces the output voltage which
is either at its positive
saturation or at its negative saturation level. This is because open

loop gain of op-amp is very large. The output saturation voltages are denoted as sat
and Vsat are usually given by,
-

+Vsat+Vcc-1V . (1)

- Vsat- VEE+ 1 V (2)

The 1 V difference may change from op-amp to op-amp. For very small change in
input voltage, the op-amp output switches from + Vsat to - Vsat and vice versa. So

though this property of op-amp is not suitable for linear applications, it is suitable for
various nonlinear switching circuits such as comparators, crossing detectors, Schmitt
triggers etc. Such nonlinear circuits using op-amp are discussed in this chapter. In these
circuits many timespositive feedback is used and op-amp generally does not require
any frequency compensation.
4.2 Basic Comparator
The op-amp in open loop configuration can be used as a basic comparator. When two
inputs are applied to the open loop op-amp then it compares the two inputs. Depending
upon the comparison, it produces output voltage which is either positive saturation
voltage (+ Vsat) or negative saturation voltage(- Vsat
A comparator is a circuit which
+Vcc
compares a signal VN
voltage applied at one input of an op-amp with a - Vo
known reference voltage at the other input, and
Op-amp
Vp
produce either a
high or a low output voltage,
depending on which input is higher. As comparator
-VEE
output has two voltage levels, either high or low, it is Fig. 4.1
Op-amp as a comparator
not linearly proportional to input voltage.
The op-amp as a comparator is shown in the Fig. 4.1.
Let VN = Voltage of inverting terminal

Vp = Voltage of noninverting terminal1

The two voltages are

compared with each other and
is very high.
Vo is either + Vsat or -

Vsat as AoL
Depending upon to which terminals, the input is applied, the comparators are
classified as,
i) Noninverting comparator ii) Inverting comparator
4.3 Basic Noninverting Comparator
Dec-11
In this comparator, the input voltage is applied to the nonin verting terminal and no
reference voltage is applied to other terminal. So inverting terminal is grounded. The
input voltage is denoted as Vin while the voltage applied to other terminal with which
V. is compared is denoted as Vref In the basic comparator, Vref = 0 V. The basic
noninverting comparator is showr. in the Fig. 4.2.

Vret 0 Ncc
+V9at for Vin> Vref
Op-amp -o Vout
-Vsat for VinVre
Vin NEE

Fig. 4.2 Basic noninverting comparator

Vsat i.e.
noninverting comparator, if Vin is greater than Vref then output
is +
In the
is Vsat i.e. almost
almost equal to + Vcc: While if Vin is less than Vref then output
-

equal to - VEE

Thus for Fig. 4.2, as Vref =

0 V when Vin is positive then V, = +
Vsat = +
Vcc while
then V, - Vsat -
VEE This is because, as open loop gain
when Vin is negative =

saturates.
IS very very high even tor very small Vin the op-amp output
op-amp (Ao
are + Vsat and Vsat
-

Thus the two possible output levels of the comparator

than or less than the reference voltage.
indicating whether the input voltage is greater
is at saturation level is known as
Such type of the comparator, in which the operation

saturating type of comparator. Assuming Vin

symmetrical conditions, the two possible
output levels of the saturating type
comparator are + Vsat and V sat
Vet0 V
Note that no feedback is applied to the o
op-amp and it is operated in open loop
conditions, because of which the op-amp V VnVre
is operating in saturating conditions.
+Vsat+Vcc
The input and output waveforms for a
basic noninverting comparator, for
sinusoidal input are shown in the Fig. 4.3.

The op-amp differential voltage gain -Vsat-VEE

AoL is very large. So when inverting
input is grounded, very small input basic noninverting
microvolt is Fig. 4.3 Waveforms of a
i n in the range of comparator
 The point at which the transfer characteristics is
straight line is called a trip point.
The trip point is the
input voltage at which the output changes its states from low to
high or high to low. In the basic comparator this trip point is zero as at
Vin 0, the
=

output changes its states. So we can say that when

Vin is greater than trip point, the
output is high while if Vin is less than the trip point the
Over ocCurs at
output is low. As this change
Vin 0, the basic comparator can be used to detect occurrence of zero in
Vo Vo
+V _al
+Nsat

Vin Vin

For 0-a
N sat V=+Vsat
For 0- b
V-Vsat
(a) ldeal
(b) Practical
Fia, 4.4 Transfer characteristics of basic
noninverting comparator
 4.4 Inverting Comparator

The 4.8 shows comparator in which the reference voltage Vref is

Fig. inverting
the noninverting (+) input and signal voltage (Vin) is applied to the
applied to
inverting ( nput or the op-amp. The Vref can

be set using a battery and potential divider as

+Vcc
discussed earlier for noninverting comparator. Vret
Operation
When Vin is less than Vref»the output voltage Vin
V is at +Vsat +Vcc) because the voltage at the
inverting input () is less than that at the
NEE
Fig. 4.8 Basic inverting comparator
noninverting (+) input. On the other hand, when with Vref 0V
than Vrefthe noninverting (+)
Vin is greater
input becomes negative with respect to the inverting () input, and V, goes to -Vsat
(-VEE). The Vref can be set positive and negative finite value using potential divider
circuit. The Fig. 4.9 shows the input and output waveforms for inverting comparator.

Vin
p Vp

0VL 10V
Vret
-VpL -Vp
Vinreft . VinVre
*Vsat
+ sat

0V
LOV
-Vsat
sat Vin Vref V,nVre
and output waveforms for inverting comparator
Fig. 4.9 Input
is shown in the Fig. 4.10.
Transfer characteristics for inverting comparator
with + Vref

VinVref<

-Vjin
Vref

V> Vref
4.10 Transfer characteristics for inverting comparator
Fig.