Logical Effort

→ Logical Effort allows us to determine the optimized delay of each stage in a multi-stage network.
→ It tells us how much worse a gate is at producing output current compared to an inverter.
𝑪𝑰𝒏 𝑮𝒂𝒕𝒆 𝑪𝑰𝑵
𝑳𝒐𝒈𝒊𝒄𝒂𝒍 𝑬𝒇𝒇𝒐𝒓𝒕, 𝑮 = =
𝑪𝑰𝒏 𝑹𝒆𝒇𝒆𝒓𝒆𝒏𝒄𝒆 𝑰𝒏𝒗𝒆𝒓𝒕𝒆𝒓 𝑪𝑹𝑬𝑭

Driver Loads
COUT CIN
CIN

𝑪𝑶𝒖𝒕 𝑮𝒂𝒕𝒆 𝑪𝑶𝑼𝑻

𝑬𝒍𝒆𝒄𝒕𝒓𝒊𝒄𝒂𝒍 𝑬𝒇𝒇𝒐𝒓𝒕, 𝑯 = =
CIN 𝑪𝑰𝒏 𝑮𝒂𝒕𝒆 𝑪𝑰𝑵
= 𝑭𝒂𝒏 𝒐𝒖𝒕

CIN
𝑪𝑶𝑼𝑻 𝑪𝑰𝑵 𝑪𝑰𝑵 𝑪𝑰𝑵 𝑪𝑰𝑵
𝑯= = =𝟒
𝑪𝑰𝑵 𝑪𝑰𝑵
CIN

Reference Inverter:
Driver Loads

Parasitic
Capacitance

𝑪𝑰𝑵 𝟑𝑪
𝑮= = =𝟏
𝑪𝑹𝑬𝑭 𝟑𝑪

𝑪𝑶𝑼𝑻 𝟑𝑪 𝟑𝑪 𝟑𝑪 𝟑𝑪
𝑯= = =𝟒
𝑪𝑰𝑵 𝟑𝑪
Parasitic Capacitance:

→ Parasitic Capacitance is the output capacitance of a logic gate with Zero load.
→ It is essentially the diffusion capacitances of the output node.
→ Normalized Parasitic Capacitance is a logic gate’s parasitic capacitance as compared to the reference
inverter’s parasitic capacitance.
Output diffusion
𝒑𝑮𝑨𝑻𝑬 capacitance of the gate
𝑷𝑮𝑨𝑻𝑬 =
𝑷𝑹𝑬𝑭 𝑰𝑵𝑽
Output diffusion capacitance
2-input NAND Gate: of the Reference Inverter

→ Logical Effort of a 2-input NAND gate is

given by,
𝟐𝑪 𝟐𝑪 𝟒
𝑮𝑵𝑨𝑵𝑫𝟐 = =
𝟑𝑪 𝟑
→ Hence we can see from the above
equation that a 2-input symmetric NAND gate
can produce more current than an inverter since
𝑮𝑰𝑵𝑽 = 𝟏 and 𝑮𝑵𝑨𝑵𝑫𝟐 = 𝟏. 𝟑𝟑.

→ The normalized parasitic capacitance of a

2-input NAND gate is given by,

𝟐𝑪 𝟐𝑪 𝟐𝑪 𝟔𝑪
𝑷𝑵𝑨𝑵𝑫𝟐 = = =𝟐
𝟑𝑪 𝟑𝑪

2-input NOR

→ Logical Effort of a 2-input NOR gate is

given by,
𝟒𝑪 𝑪 𝟓
𝑮𝑵𝑶𝑹𝟐 = =
𝟑𝑪 𝟑

→ The normalized parasitic capacitance of a

2-input NOR gate is given by,

𝟒𝑪 𝑪 𝑪 𝟔𝑪
𝑷𝑵𝑶𝑹𝟐 = = =𝟐
𝟑𝑪 𝟑𝑪
 Summary of Logical Effort (𝑮) and Normalized Parasitic Capacitance (𝑷)

𝟒
𝑮𝑵𝑨𝑵𝑫𝟐 = 𝑷𝑵𝑨𝑵𝑫𝟐 = 𝟐
𝟑

𝟐𝑪 𝟑𝑪 𝟓 𝟐𝑪 𝟐𝑪 𝟐𝑪 𝟑𝑪 𝟗𝑪
𝑮𝑵𝑨𝑵𝑫𝟑 = = 𝑷𝑵𝑨𝑵𝑫𝟑 = = =𝟑
𝟑𝑪 𝟑 𝟑𝑪 𝟑𝑪

𝟓
𝑮𝑵𝑶𝑹𝟐 = 𝑷𝑵𝑶𝑹𝟐 = 𝟐
𝟑

𝟔𝑪 𝑪 𝟕 𝟔𝑪 𝑪 𝑪 𝑪 𝟗𝑪
𝑮𝑵𝑶𝑹𝟑 = = 𝑷𝑵𝑶𝑹𝟑 = = =𝟑
𝟑𝑪 𝟑 𝟑𝑪 𝟑𝑪
Logical Effort:
For a multi-stage network, the delay is given by:

𝑫𝒆𝒍𝒂𝒚, 𝑫 = 𝑵 𝒇 𝑷
Where, 𝑵 = 𝑵𝒖𝒎𝒃𝒆𝒓 𝒐𝒇 𝑺𝒕𝒂𝒈𝒆𝒔;

𝒇 = 𝑺𝒕𝒂𝒈𝒆 𝑬𝒇𝒇𝒐𝒓𝒕;
𝑷 = 𝑵𝒐𝒓𝒎𝒂𝒍𝒊𝒛𝒆𝒅 𝑷𝒂𝒓𝒂𝒔𝒊𝒕𝒊𝒄 𝑪𝒂𝒑𝒂𝒄𝒊𝒕𝒂𝒏𝒄𝒆 = 𝒑𝟏 𝒑𝟐 𝒑𝟑 … … … … … 𝒑𝒏
→ For a multi-stage network, if the delay of each stage is equal, that will produce optimized delay for
the entire network.
𝟏
→ Stage Effort, 𝒇 is defined as 𝒇 = 𝑭𝑵 = 𝒈 𝒉
where, 𝑭 = 𝑷𝒂𝒕𝒉 𝑬𝒇𝒇𝒐𝒓𝒕 & 𝑵 = 𝑵𝒖𝒎𝒃𝒆𝒓 𝒐𝒇 𝑺𝒕𝒂𝒈𝒆𝒔
𝒈 = 𝑺𝒕𝒂𝒈𝒆 𝒍𝒐𝒈𝒊𝒄𝒂𝒍 𝒆𝒇𝒇𝒐𝒓𝒕 & 𝒉 = 𝑺𝒕𝒂𝒈𝒆 𝒆𝒍𝒆𝒄𝒕𝒓𝒊𝒄𝒂𝒍 𝒆𝒇𝒇𝒐𝒓𝒕
→ Path Effort, 𝑭 is defined as 𝑭 = 𝑮 𝑩 𝑯 = ∑ 𝒈 ∑ 𝒃 𝑯

Where, 𝑮 = 𝑳𝒐𝒈𝒊𝒄𝒂𝒍 𝑬𝒇𝒇𝒐𝒓𝒕 = 𝒈𝟏 𝒈𝟐 𝒈𝟑 ………… 𝒈𝒏

𝑩 = 𝑩𝒓𝒂𝒏𝒄𝒉𝒊𝒏𝒈 𝑬𝒇𝒇𝒐𝒓𝒕 = 𝒃𝟏 𝒃𝟐 𝒃𝟑 ………… 𝒃𝒏
𝑯 = 𝑬𝒍𝒆𝒄𝒕𝒓𝒊𝒄𝒂𝒍 𝑬𝒇𝒇𝒐𝒓𝒕
𝑪𝑰𝑵 𝑶𝑵 𝑪𝑰𝑵 𝑶𝑭𝑭 𝑪 𝑪
→ Branching Effort, 𝑩 is defined as 𝒃 = = 𝑶𝑵 𝑶𝑭𝑭
𝑪𝑰𝑵 𝑶𝑵 𝑪𝑶𝑵
→ The Logical Effort calculation is always done on a path across the network. 𝑪𝑰𝑵 𝑶𝑵 are the input
capacitances of the gates that are on that path. 𝑪𝑰𝑵 𝑶𝑭𝑭 are the input capacitances of the gates that
are not on that path.

𝑪𝑶𝑭𝑭
𝑪𝑶𝑭𝑭

𝑪𝑶𝑵 𝑪𝑶𝑵
𝑪𝑶𝑵
Question: Evaluate the logical effort (𝑮), electrical effort (𝑯), branching effort
(𝑩), path effort (𝑭), parasitic delay (𝑷) and minimum path delay (𝑫) for the
multi-stage network given below. (Gate input capacitances are shown inside the
gates and the output capacitances are shown outside the gates.) Then find the
values of 𝒙 and 𝒚 to achieve this delay and size the transistor accordingly.

Solution:
Step 1:
𝟒
𝒈𝟏 = 𝑮𝑵𝑨𝑵𝑫𝟐 =
𝟑
𝟒 𝟓 𝟓 𝟏𝟎𝟎
𝒑𝟏 = 𝑷𝑵𝑨𝑵𝑫𝟐 = 𝟐 𝑮 = 𝒈𝟏 𝒈𝟐 𝒈𝟑 = =
𝟑 𝟑 𝟑 𝟐𝟕
𝟓
𝒈𝟐 = 𝑮𝑵𝑨𝑵𝑫𝟑 =
𝟑 𝑷 = 𝒑𝟏 𝒑𝟏 𝒑𝟏 = 𝟐 𝟑 𝟐=𝟕
𝒑𝟐 = 𝑷𝑵𝑨𝑵𝑫𝟑 = 𝟑
𝟓 𝑪𝑶𝑼𝑻 𝟒𝟓
𝒈𝟑 = 𝑮𝑵𝑶𝑹𝟐 = 𝑯= =
𝟑 𝑪𝑰𝑵 𝟖
𝒑𝟑 = 𝑷𝑵𝑶𝑹𝟐 = 𝟐
Branching Effort
𝑪𝑶𝑵 𝑪𝑶𝑭𝑭

𝒙 (𝒙 𝒙) 𝒚 𝒚
𝑩 = 𝒃𝟏 𝒃𝟐 = =𝟑 𝟐=𝟔
𝒙 𝒚
𝑪𝑶𝑵
𝟏𝟎𝟎 𝟒𝟓
𝑷𝒂𝒕𝒉 𝑬𝒇𝒇𝒐𝒓𝒕, 𝑭 = 𝑮 𝑩 𝑯= 𝟔 = 𝟏𝟐𝟓
𝟐𝟕 𝟖
𝟏 𝟏
𝑺𝒕𝒂𝒈𝒆 𝑬𝒇𝒇𝒐𝒓𝒕, 𝒇 = 𝑭 = (𝟏𝟐𝟓) = 𝟓 → Delay of each stage
𝑵 𝟑

𝑷𝒂𝒕𝒉 𝑫𝒆𝒍𝒂𝒚, 𝑫 = 𝑵 𝒇 𝑷=𝟑 𝟓 𝟕 = 𝟐𝟐

Step 2: Transistor Sizing

𝑺𝒕𝒂𝒈𝒆 𝟏 𝑺𝒕𝒂𝒈𝒆 𝟐 𝑺𝒕𝒂𝒈𝒆 𝟑

𝑩𝒓𝒂𝒏𝒄𝒉 𝟏 𝑩𝒓𝒂𝒏𝒄𝒉 𝟐
𝑺𝒕𝒂𝒈𝒆 𝑬𝒇𝒇𝒐𝒓𝒕, 𝒇 = 𝒈 𝒉 = 𝒈𝟏 𝒉𝟏 = 𝒈𝟐 𝒉𝟐 = 𝒈𝟑 𝒉𝟑
Since the values of 𝒙 and 𝒚 (input capacitances of Branch-1 NAND gates and Branch-2 NOR
gates) are unknown, we can find out their values from the calculations shown below.
Stage – 3: Stage – 2: Stage – 1:
𝒇 = 𝒈𝟑 𝒉𝟑 𝒇 = 𝒈𝟐 𝒉 𝒇 = 𝒈𝟏 𝒉𝟏 = 𝟓
𝟓 𝟒𝟓 𝟓 𝒚 𝒚
⟹𝟓= ⟹𝟓=
𝟑 𝒚 𝟑 𝒙
⟹ 𝒚 = 𝟏𝟓 𝟐𝒚 𝟐 𝟏𝟓
⟹𝒙= =
𝒙 𝒙
⟹ 𝒙 = 𝟏𝟎
2-input NAND Gate Sizing (Stage – 1):
𝟐𝑾 𝟐𝑾 = 𝟖 (Input capacitance is given in the figure)
⟹ 𝟒𝑾 = 𝟖
⟹𝑾=𝟐
Hence,
𝑵𝑴𝑶𝑺 𝑾𝒊𝒅𝒕𝒉 = 𝟐𝑾 = 𝟐 𝟐 = 𝟒
𝑷𝑴𝑶𝑺 𝑾𝒊𝒅𝒕𝒉 = 𝟐𝑾 = 𝟐 𝟐 = 𝟒
3-input NAND Gate Sizing (Stage – 2):
𝟑𝑾 𝟐𝑾 = 𝟏𝟎 = 𝒙
⟹ 𝟓𝑾 = 𝟏𝟎
⟹𝑾=𝟐
Hence,
𝑵𝑴𝑶𝑺 𝑾𝒊𝒅𝒕𝒉 = 𝟑𝑾 = 𝟑 𝟐 = 𝟔
𝑷𝑴𝑶𝑺 𝑾𝒊𝒅𝒕𝒉 = 𝟐𝑾 = 𝟐 𝟐 = 𝟒
2-input NOR Gate Sizing (Stage – 3):
𝟒𝑾 𝑾 = 𝟏𝟓 = 𝒚
⟹ 𝟓𝑾 = 𝟏𝟓
⟹𝑾=𝟑
Hence,
𝑵𝑴𝑶𝑺 𝑾𝒊𝒅𝒕𝒉 = 𝑾 = 𝟑
𝑷𝑴𝑶𝑺 𝑾𝒊𝒅𝒕𝒉 = 𝟒𝑾 = 𝟒 𝟑 = 𝟏𝟐