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No we simplify all the values and forms an equation for 𝑄 with the help of K-Map,

𝑄 0 1
𝐷
0 0 0

1 1 1

So the equation becomes, 𝑸𝒏 𝟏 = 𝑫𝒏

Excitation Table for SR Flip Flop

The excitation table is the table which determines the input for which the required given
output came. We fill out it with the help of characteristics table.
Inputs Outputs

𝑄 (Present State) 𝑄 (Next State) 𝐷

0 0 0
0 1 1
1 0 0

1 1 1

JK FLIP FLOP
The SR Flip Flop or Set-Reset flip flop has lots of advantages. But, it has the following
switching problems:
o When Set 'S' and Reset 'R' inputs are set to 1, this condition is always avoided.
o When the Set or Reset input changes their state while the enable input is 0, the
incorrect latching action occurs.
The JK Flip Flop removes these two drawbacks of SR Flip Flop. The JK flip flop is an
improved clocked SR flip flop.
The JK flip flop is one of the most used flip flops in digital circuits and is considered as a
universal flip flop having two inputs 'J' and 'K'. In SR flip flop, the 'S' and 'R' are the
shortened abbreviated letters for Set and Reset, but J and K are not. The JK flip flop has 'J'
and 'K' flip flop instead of 'S' and 'R' which are themselves autonomous letters and are chosen
to distinguish the flip flop design from other types. The JK flip flop work in the same way as
the SR flip flop work.. The only difference between JK flip flop and SR flip flop is that when
both inputs of SR flip flop is set to 1, the circuit produces the invalid states as outputs, but in
case of JK flip flop, there are no invalid states even if both 'J' and 'K' flip flops are set to 1.
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The JK flip flop has

 Two data inputs J and K.
 One clock signal input (CLK).
 Two outputs Q and Q’.
The JK flip flop is an improved clocked SR flip flop as mentioned above butut it still suffers
from the "race" problem. This problem occurs when the state of the output Q is changed
before the clock input's timing pulse has time to go "Off". We have to keep short timing plus
period (T) for avoiding this period.
The symbol of a JK flip – flop is shown below.

The circuit of a JK flip – flop using gates is shown below. It is similar to a modified NAND
SR flip – flop.

G3 G1

G4 G2

Working
Case -1 : When CLK = 0
Then whatever the value of value of J and K is, there is no effect. The circuit continues with
its previous memory.
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Let’s assume Q=1 And Q’=0 as previous memory, at present our CLK is off i.e. 0 and (J and
K) =0
Then our both G3 and G4 got two input as 0 and produces the result as 1,irrespective of the
third input which further will be one input of G1 and G2, Now the G1 will get the second
input from the previous result of Q’(0) and similarly the G2 will get their second input from
the previous result of Q(1) and hence Q=1 and Q’=0 i.e. previous state.
Similarly it happens in each case for every value of J,K and its previous states.
Case-2 : When CLK is high,J is low and K is low,
then also Q and Q’ returns its previous state value i.e. it holds the current state.
Now both G3 and G4 will get two inputs as 0 and 1 which results out in 1,irrespective of the
third input. When both G1 and G2 got one input as 1 then we cann’t predict anything, and
take out the help of second input which is the previous state of Q and Q’ and hence the result
came out will again be its previous state.
Case-3 : When J is low and K is high,
then flip – flop will be in reset state i.e. Q = 0, Q’ =1.
The G3 gets two input 0 and 1 which results out 1 as the result and G4 got two input ,both as
1 and depends on third input.In this situation we cann’t proceed further, so we assume here
two cases of previous state of Q and Q’ for procedding further:
i. When Q=0 and Q’=1
Now as third input of G4 is previous
state of Q, so we got the third input as 0 which results out in 1.
Now we got one input as 1 for both G1 and G2, now second input
we again take the previous value of Q and Q’. Hence new value of
Q=0(from the combination of 1 and 1) and Q’=1(from the
combination of 1 and 0) i.e. RESET state.
ii. When Q=1 and Q’=0
Now as third input of G4 is previous
state of Q, so we got the third input as 1 which results out in 0.
Now we got one input as 1 for G1 and as 0 for G2, so having 0 as
one input for G2 will results out in 1. Now this result would also
be the second input of G1 and that results out in 0 Hence new value
of Q=1(from the combination of 1 and 1) and Q’=0(having one
input as 1) i.e. RESET state.
Now we saw in both above cases The result came out to be is RESET state. Hence the
circuit will be in reset state when J is low and K is high.

Case-4 : When J is high and K is low

then flip – flop will be in set state i.e. Q = 1, Q’ =0.
The gate G4 gets two input 0 and 1 which results out 1 as the result and G3 gate got two
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input ,both as 1 and depends on third input. In this situation we again cann’t proceed further,
so we assume here two cases of previous state of Q and Q’ for procedding further :

i. When Q=1 and Q’=0

Now as third input of G3 is previous state of Q’, so we got the third
input as 0 which results out in 1. Now we got one input as 1 for both
G1 and G2 and now second input we again take the previous value of
Q and Q’. Hence new value of Q=1(from the combination of 1 and 0)
and Q’=0(from the combination of 1 and 1) i.e. SET state.
ii. When Q=0 and Q’=1
Now as third input of G3 is previous state of Q’, so we got the third
input as 1 which results out in 0. Now we got one input as 0 for G1 and
as 1 for G2, so having 0 as one input G1 will results out in 1. Now this
result would also be the second input of G2 and that results out in 0
Hence new value of Q=1(from the combination of 1 and 0) and ––
Q’=0(from the combination of 1 and 1) i.e. SET state.
Now we saw in both above cases The result came out to be is SET state Hence the
circuit will be in reset state when J is high and K is low. .
Case-5 :When J is high and K is high
then flip – flop will be in Toggle state or flip state. This means that the output will
complement to the previous state value
Now both the G3 and G4 got two input ,both as 1 and depends on third input.In this situation
we cann’t proceed further, so we assume here two cases of previous state of Q and Q’ for
procedding further :
i. When Q=1 and Q’=0 [SET state]
Now as third input of G3 is previous state of Q’, so we got the
third input as 0 which results out in 1.Similarly third input of
G4 is previous state of Q, so we got the third input as 1 which
results out in 0. Now we got one input as 0 for G2 and as 1 for
G1, so having 0 as one input G2 will results out in 1. Now this
result would also be the second input of G1 and that results out
in 0.Hence new value of Q=0 (from the combination of 1 and
1) and Q’=1 i.e. RESET state and if we proceeed this again
then again the value gets reversed as shown below
ii. When Q=0 and Q’=1 [RESET state]
Now as third input of G3 is previous state of Q’, so we got the
third input as 1 which results out in 0.Similarly third input of
G4 is previous state of Q, so we got the third input as 0 which
results out in 1. Now we got one input as 0 for G1 and as 1 for
G2, so having 0 as one input, G1 will results out in 1. Now this
result would also be the second input of G2 and that results out
in 0.Hence new value of Q=1 and Q’=0 i.e. SET state.
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This process of transformation of values of Q and Q’ i.e. called TOOGLING will continues
upto infinite times. Until the CLK will be turned off.

Truth Table
CLK 𝐽 𝐾 𝑄 𝑄 ’ STATE

0 X X Q Q’ PREVIOUS

1 0 0
1 0 1 0 1 RESET
1 1 0 1 0 SET

1 1 1 Q’ Q TOGGGLING
OR
COMPLEMENTARY

The J-K flip-flop has the distinction that it can be used to construct any other flip-flop, much
like NAND gates can be used to construct any other type of gate (and by extension, any
digital circuit). Because of this, the J-K is sometimes called a universal flip-flop

Characteristics Table for SR Flip Flop

𝑄 𝐽 𝐾 𝑄

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 1
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1 0 1 0

1 1 0 1

1 1 1 0

Characteristics Equation for SR Flip Flop

So for Characteristics equation , firstly we have to draw the characteristics table with the
help of our truth table observed above :
No we simplify all the values and forms an equation for 𝑄 with the help of K-Map,
II
𝑄 𝐽 00 01 11 10
𝐾
0 0 1 1 1

1 0 1 0 0

So the equation becomes, 𝑸𝒏 𝟏 = 𝑱𝒏 (𝑸𝒏 )′ + 𝑸𝒏 (𝑲𝒏 )′

Excitation Table for SR Flip Flop

The excitation table is the table which determines the input for which the required given
output came. We fill out it with the help of characteristics table.
Inputs Outputs

𝑄 (Present State) 𝑄 (Next State) 𝐽 𝐾

0 0 0 X
0 1 1 X
1 0 x 1

1 1 x 0

Master-Slave JK Flip Flop

Race Around Condition In JK Flip-flop – For J-K flip-flop, if J=K=1, and if clk=1
for a long period of time, then Q output will toggle as long as CLK is high, which makes the
output of the flip-flop unstable or uncertain i.e. in a period of one cycle, the result Q oscillates
multiple time from 0 to 1 . This problem can be
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This problem is called race around condition in J-K flip-flop.

This problem (Race Around Condition) can be avoided by :
 Decreasing the clock pulse time in respect to propagation delay of flip flop (but this
propagation delay is in nano second , and is inpractical to implement.)
 ensuring that the clock input is at logic “1” only for a very short time.
 Use edge triggering instead of level trigerring
 Use of Master Slave Flip Flop.
This introduced the concept of Master Slave JK flip flop.
The master-slave flip flop is constructed by combining two JK flip flops. These flip flops are
connected in a series configuration. In these two flip flops, the 1st flip flop work as "master",
called the master flip flop, and the 2nd work as a "slave", called slave flip flop. The master-
slave flip flop is designed in such a way that the output of the "master" flip flop is passed to
both the inputs of the "slave" flip flop. The output of the "slave" flip flop is passed to inputs
of the master flip flop.
In "master-slave flip flop", apart from these two flip flops, an inverter or NOT gate is also
used. For passing the inverted clock pulse to the "slave" flip flop, the inverter is connected to
the clock's pulse. In simple words, when CP set to false for "master", then CP is set to true for
"slave", and when CP set to true for "master", then CP is set to false for "slave".

Diagaram