Discrete and Integrated Electronics Volume Two Analysis and Design For Engineers and Engineering Technologists. 2 (2020)

Discrete and Integrated
Electronics
Volume Two
Analysis and Design

For
Engineers and Engineering Technologists
Stephen R. Fleeman
Associate Professor and Electrical Engineer Emeritus
Cover Design: Douglas M. Decker
Cover Photograph: Umberto on Unsplash
Copyright © 2020 by Stephen R. Fleeman

CONTENTS
Preface X
Volume Two
7 BJT and FET Biasing 1
7-0 Study Objectives 2
7-1 Midpoint Bias 2
7-2 Device Variations Due to Tolerance and Temperature 5
7-3 BJT Fixed Base Bias 12
7-4 FET Bias Lines: Escaping the Math Attack! 14
7-5 BJT Collector-Voltage Feedback Bias 20
7-6 MOSFET Drain-Voltage Feedback Bias 27
7-7 BJT Voltage-Divider Bias 31
7-8 JFET and DE-MOSFET Self Bias 39
7-9 FET Voltage-Divider Bias 43
7-10 BJT Emitter Bias 50
7-11 FET Constant-Current Source Biasing: Escaping the
Graph Attack 55
7-12 BJT Temperature Compensation 61
7-13 Biasing PNP BJTs 64
7-14 Using EDA to Analyze Bias Circuits 65
7-15 FET Analysis Using the Quadratic Formula (optional)
70
Problems for Chapter 7 79
8 Voltage Amplifier Models 98

8-1 The Basic Voltage Amplifier 99
8-2 Unloaded Voltage Gain 101
8-3 Output Loading Effects 102
8-4 Input Loading Effects 103
8-5 Voltage Amplifier Current Gain 105
8-6 Power Gain 108
8-7 Decibels 112
Contents iii
8-8 Relative Decibel Scales 117
8-9 Applying Decibels 120
8-10 Amplifier Models and Multisim 125
9 Inverting Voltage Amplifiers 133

9-1 The Role of Superposition in Amplifier Analysis 134
9-2 BJT and FET Small-Signal Models 135
9-3 BJT Gains: hfe and gm 141
9-4 FET Transconductance 147
9-5 BJT and FET Input Resistance 151
9-6 BJT and FET Output Resistance 153
9-7 The Common-Emitter Amplifier 162
9-8 The Common-Source Amplifier 173
9-9 Removing the Emitter Bypass Capacitor 178
9-10 Partial Source Resistor Bypassing 189
9-11 The Ideal Op Amp 194
9-12 Meet the Real Op Amp 196
9-13 The Op Amp Inverting Amplifier 201
9-14 Applying EDA to Analyze Amplifier Circuits 208
9-15 Derivations (Optional) 211
10 Non-Inverting Voltage Amplifiers 233

10-1 BJT Emitter Followers 234
10-2 FET Source Followers 246
10-3 The Op Amp Voltage Follower 250
10-4 BJT Common-Base Amplifiers 251
10-5 FET Common-Gate Amplifiers 263
10-6 The Op Amp Non-Inverting Amplifier 265
10-7 Applying EDA to Analyze Non-Inverting Amplifiers 271
11 Differential and Cascaded Amplifiers 283

11-1 Simplified BJT/FET Amplifier Analysis 284
11-2 Differential Amplifiers Using Discrete Devices 293
11-3 Common-Mode Voltage Gain and CMRR 303
11-4 The Op Amp Differential Amplifier 320
11-5 Cascaded Amplifier Systems 325
iv CONTENTS
11-6 BJT and FET Cascaded Amplifier Systems 327
11-7 Op Amp Cascaded Amplifier Systems 336
11-8 Instrumentation Amplifiers 339
11-9 Inside the Op Amp 355
12 Frequency Response 376

12-1 The Frequency Domain 377
12-2 RC Filters and the RC Low-pass Filter 380
12-3 Poles and Zeros 388
12-4 Bode Approximations 401
12-5 RC High-Pass Filters 405
12-6 Low-Frequency Roll-Off in RC-Coupled Amplifiers 410
12-7 The Effects of the Emitter- and Source-Bypass
Capacitors 419
12-8 Single-Supply Op Amps and Low-Frequency
Roll-Off 429
12-9 BJT Device Capacitances and the BJT High-Frequency
Model 443
12-10 FET Device Capacitances and the FET High-Frequency
Model 446
12-11 The Miller Effect 449
12-12 High-Frequency Roll-Off in BJT and
FET Amplifiers 453
12-13 High-Frequency Roll-off in Frequency-Compensated
Op Amps 457
12-14 A MESFET is a GASFET or a GaAs MESFET 459
Answers to Selected Odd-Numbered Problems 475

Index for Volume Two 492
Contents v
Volume One
1 Solid-State Physics and the P-N Junction 1

1-1 Why Study Solid-State Physics? 2
1-2 The Atom and Electrical Conductors 4
1-3 Semiconductors 11
1-4 Semiconductor Crystals and Covalent Bonding 13
1-5 Conduction in Pure (Intrinsic) Semiconductor Crystals 15
1-6 Doped Semiconductors 19
1-7 Organic Semiconductors 22
1-8 The P-N Junction 27
1-9 The Forward-Biased P-N Junction 35
1-10 The Reverse-Biased P-N Junction 39
1-11 The Diode 44
2 Diodes and Circuit Analysis 51

2-1 The Diode V-I Characteristic Curve 52
2-2 The Shockley Diode Equation and the DC Load Line 66
2-3 The Ideal Diode Model 70
2-4 The Knee-Voltage Diode Model 72
2-5 The Reverse Current Source Diode Model 77
2-6 Zener and Avalanche Diodes 77
2-7 The Ideal Zener Diode Model 81
2-8 Static and Dynamic Resistance 83
2-9 The Zener Dynamic-Resistance Diode Model 86
2-10 Using Thevenin’s Theorem 92
vi CONTENTS
3 Diode Applications and Additional Devices 104

3-1 Diode Clippers and Limiters 105
3-2 Diode Clamper Circuits 109
3-3 Temperature Effects on P-N Junction Operation 113
3-4 NTC and PTC Thermistors 119
3-5 Varistors 125
3-6 Light-Emitting and Laser Diodes 127
3-7 Photoconductive Cells, Photodiodes, and Solar Cells
137
3-8 Frequency Effects on P-N Junction Operation 150
3-9 The Schottky Diode 154
3-10 The Varactor Diode 156
4 DC Power Supplies: Rectification and Filtering 170

4-1 Linear Versus Switching DC Power Supplies 171
4-2 The Load 173
4-3 The Single-Phase AC Power Distribution System 175
4-4 Average and RMS Values 177
4-5 The Transformer 186
4-6 The Half-Wave Rectifier 192
4-7 Full-Wave Rectifiers Using a Center-Tapped
Transformer 202
4-8 Full-Wave Bridge Rectifiers 207
4-9 Dual-Complementary Full-Wave Rectifiers 213
4-10 Filter Capacitor Considerations 215
4-11 Simple Capacitor Filters 218
4-12 Ripple Factor 221
4-13 Light-Loading Constraint 223
4-14 Ripple Voltage Equation 224
4-15 Rectifier Average and Peak Repetitive Currents 229
4-16 Nonrepetitive Diode Surge Current 235
4-17 Capacitor Ripple Current 238
4-18 Transformer Secondary Current 241
4-19 Diode Rectifier Specifications 243
4-20 Three-Terminal IC Voltage Regulators 248
Contents vii
5 Bipolar Junction Transistors 269
5-1 The Basic BJT Structure 270
5-2 Unbiased Transistors 271
5-3 BJT Operation 273
5-4 BJT Connections and Current Gain 279
5-5 Leakage Currents 283
5-6 The Transistor Convention 286
5-7 V-I Curves 287
5-8 Finding the Q-point 298
5-9 The BJT Amplifier 306
5-10 The Transistor Switch 311
5-11 The Clapper 313
6 Field-Effect Transistors 332

6-1 The JFET Structure 333
6-2 Operation of the JFET 336
6-3 FET Configurations and V-I Curves 346
6-4 The FET Transfer Equation 354
6-5 The Depletion-Enhancement MOSFET 356
6-6 Enhancement MOSFETs 361
6-7 Finding the Q-point 365
6-8 The FET Signal Process and Applying Superposition
371
6-9 CMOS – The Logical Choice for Linear 376
6-10 MOSFET Latching Circuit 380
6-11 Insulated Gate Bipolar Transistor (IGBT) 384

Index for Volume One 400
viii CONTENTS
Volume Three
13 Op Amp Negative Feedback
14 Additional Op Amp Amplifier Circuits
15 Introduction to Power Amplifiers
16 Oscillators
17 AC Power Control
18 DC Power Supplies: Regulation and Protection
Answers to Selected Odd-Numbered Problems
Index for Volume Three
Master Index for Volumes One - Three
Contents ix
Preface
Who Should Read this  Illustrations to help you grasp every

concept.
Book?  Narrated examples to help you
Discrete and Integrated Electronics Volume understand the whys and not just the
Two is designed to assist serious students in hows.
learning the basic concepts in electronics  Step-by-step screen captures that
which lead to the analysis and design of illustrate the use of National
electronic circuits. This includes: Instruments (NI) Multisim to verify
 Electrical and Electronic concepts and approximations
Engineering Technology students incorporated in the textbook.
pursuing a degree or certificate.
 Electrical Engineering students who
Why is Discrete and
desire to understand the applications Integrated Electronics a
underpinning the topics and Kindle eBook?
mathematics found in their studies.
 The advantages offered by eBooks
 Mechanical Engineering students
include lower cost when compared to
struggling to understand the
traditional printed textbooks.
relevance of their required course in
engineering circuit analysis.  eBooks provide greater portability
when contrasted with the effort
In general, it can be used in an instructor-led
required to lug traditional textbooks
course, an on-line course, or for self-study.
around.
The reader should have completed a basic
course in DC circuit analysis. Completion or  Nearly zero chance you will lose
enrollment in an AC circuit analysis class is your textbook. This covers its
required. Calculations requiring complex misplacement or theft.
numbers appear in the last chapter. The  Amazon provides a free Kindle
reader should also understand the basic application for personal computers.
principles underlying the application of
diodes, bipolar junction transistors, and field  Kindle eBooks are also compatible
effect transistors. These topics are provided with iPads, Android tablets, and
in Discrete and Integrated Electronics smart phones.
Volume One, but other sources are available.  eBooks provide compatibility with
instructor-led, on-line, and distance
What Features are education course formats.
Included?  Natural resources are preserved since
 Objectives at the beginning of each printing, storage, and distribution of
chapter to help you guide your traditional textbooks are eliminated
studies. by digital eBooks.
x PREFACE
What is “NI Multisim”? Kirt is a man purely comfortable in his own
skin. Brennan is an accomplished electrical
Multisim is a computer program that allows engineer in his own right. Blake is a gifted
you to enter an electrical schematic physician and healer. They each make me
graphically. It is a widely-used circuit very proud.
simulation program. It is popular in both
Most importantly, I thank my beautiful wife
industry and academia. Studica
Claudia who supports me in every endeavor.
(www.studica.com) provides a student-
Beyond being my wife and helpmate, she is
version of Multisim for under $50 USD.
an artist, author, and engineer. She is a lady
Who or What is a who can handle a chain saw, pour concrete,
design and construct furniture, and grow and
“Stephen R. Fleeman”? nurture mystical gardens and yards. Beyond
Now retired, Professor Fleeman was an those incredible talents, she also provides our
educator and electrical engineer. He has 39 family with artisan dinners.
years of teaching at the university and college
level while working concurrently as an
Stephen R. Fleeman
electrical engineer at an aerospace company
for 31 years. He wrote this textbook to
combine that teaching experience and
practical engineering savvy.
Dedication
I am thankful for the engineering experiences
provided by Hamilton Sundstrand and
Precision Governors. I delighted in my
teaching experiences at Rock Valley College
and Purdue University.
I am grateful for my faculty colleagues at
Rock Valley College: Professor Linden
Griesbach (always willing to examine my
mathematical derivations and make
suggestions), Professor Joe Etminan (always
eager to help in anyway needed) and Dr. Tom
Lombardo (always available to offer
suggestions to help me make my teaching
more effective).
Family support is an immeasurable help to
achieving one’s goals. I owe a debt of thanks
to my three sons Kirt, Brennan, and Blake.
Preface xi
7
BJT and FET Biasing
F or a BJT to serve as an amplifier, it must be biased to be in its active region. This means its
collector-base p-n junction must be reverse biased, while its base-emitter p-n junction is
forward biased. Similarly, an FET to be used as an amplifier must be in pinch-off. This
requires that its drain-to-gate voltage be equal to, or greater than, its pinch-off voltage VP. The goal
of a good BJT (or FET) bias circuit is to establish a “solid” DC collector (or drain) current. Chapter
9 reveals the importance of this. A BJT’s AC parameters depend on the value of its DC collector
current. Similarly, an FET’s AC parameters depend on its DC drain current. Consequently, if
the DC collector or drain current varies, the AC responses will also vary. Such a lack of control
over the active devices is unacceptable in the world of mass production. To establish a constant
DC collector or drain current, a bias circuit must counter the wide variation in device parameters.
It must also combat the effects of temperature. (The necessity of keeping the BJT and FET AC
signals small is also important. This too is explained in Chapter 9.)
Discrete BJT and FET voltage amplifier circuits are not popular choices for new designs.
Economics, packaging, design time, and overall system reliability mandate the use of integrated
circuits whenever, and wherever possible. However, discrete BJTs and FETs are sometimes used
to embellish integrated-circuit-based designs. It is also important that we understand the role of
the BJTs, and FETs found in integrated circuits. When BJT, CMOS or BiFET (BJT/FET
combination) integrated circuits are employed, their inputs and outputs are connected internally to
amplifying (active) devices. We connect these integrated circuit inputs and outputs to external
circuitry. It is therefore important that we understand the characteristics of these active devices
even though they are located inside the integrated circuit. In this chapter, you will discover:
◼ Midpoint Bias
◼ Device Variations Due to Tolerance and Temperature
◼ BJT Fixed Base Bias
◼ FET Bias Lines: Escaping the Math Attack!
◼ BJT Collector-Voltage Feedback Bias
◼ MOSFET Drain-Voltage Feedback Bias
◼ BJT Voltage-Divider Bias
◼ JFET and DE-MOSFET Self Bias
◼ FET Voltage Divider Bias
◼ BJT Emitter Bias
◼ FET Constant-Current Source Biasing: Escaping the Graph Attack!
◼ BJT Temperature Compensation
◼ Biasing PNP BJTs and P-Channel FETs
◼ Using EDA (Electronic Design Automation) to Analyze Bias Circuits
1
7-0 Study Objectives
After completing this chapter, you should be able to:
• Explain the purpose of midpoint bias.
• Describe the expected variation in DC and use a BJT data sheet to extract information
about DC.
• Explain the effects of temperature variations on a BJT’s collector current.
• Describe the FET’s parametric variations due to tolerance and temperature.
• Analyze a fixed base bias circuit and describe its deficiencies.
• Explain the advantages provided by FET bias lines and the procedure for generating
them.
• Use a bias line to analyze a JFET fixed-gate bias circuit.
• Analyze a collector-voltage-feedback bias circuit.
• Analyze a MOSFET drain-voltage-feedback bias circuit.
• Analyze a BJT voltage-divider bias circuit.
• Describe the basic operation of JFET and DE-MOSFET self-bias circuits.
• Use a bias line to analyze JFET and DE-MOSFET self-bias circuits.
• Employ bias lines to analyze FETs circuits that use voltage-divider bias.
• Analyze a BJT emitter-bias circuit.
• Analyze constant-current source biasing for FETs.
• Describe temperature compensation as it relates to BJT biasing.
• Analyze pnp BJT bias circuits.
• Use EDA to analyze BJT and FET bias circuits, including the effects of temperature.
7-1 Midpoint Bias

We have two general performance goals for a bias circuit design. First, we want the DC collector
or drain current to be reasonably constant and independent of parameter tolerance and the effects
of temperature. Second, we want the DC operating point (Q) to be a value that will permit the
maximum, undistorted, symmetrical output voltage swing [see Fig. 7-1]. We have two boundaries
that limit the output voltage swing: circuit saturation and cutoff. Recall that when a BJT reaches
cutoff, its VCE will equal VCC. Further, when a BJT saturates, its VCE will be zero.
2 BJT AND FET BIASING

IC
BJT Midpoint Bias
I C(SAT) DC Load Line
VCC
I C(SAT) Q Cutoff Boundary VCC
15 V
2
VCE
0 VCE IC = 1 mA
VCE(OFF)
VCE(OFF) + 0V
Saturation Boundary
2
RC 7.5 V
VCC 7.5 k _
I C(SAT) = 15 V
= = 2 mA
RC 7.5 k
+
I
IC = C(SAT) = 2 mA = 1 mA VCE = 7.5 V
2 2 _
VCE(O FF) VCC 15 V
VCE = = = = 7.5 V
2 2 2
Figure 7-1.
As can also be seen in Fig. 7-1, the collector current is set to one-half of the value of IC(SAT). This
centers the collector current. Also, by establishing VCE at one-half of VCC, the collector-to-emitter
voltage is also centered. The net result is the Q point is in the middle of the DC load line. It is at
the midpoint between saturation and cutoff. (The characteristic curves have been omitted for
clarity.)
If the signal gets too large and the operating point enters saturation and/or cutoff, the output signal
will be distorted severely. This gives rise to a condition called clipping [see Fig. 7-2]. If VCE is
closer to the cutoff boundary, clipping can occur on the positive half-cycles as illustrated in Fig.
7-2(a). If VCE is closer to the saturation boundary, clipping can occur on the negative half-cycles
as illustrated in Fig. 7-2(b). Even if the Q point is centered, it is still possible to overdrive the
amplifier such that both the positive and negative half-cycles are clipped [see Fig. 7-2(c)].
Midpoint Bias 3
Clipping
Cutoff Boundary Cutoff Boundary
VCC VCC
VCE
VCE
0V 0V
Saturation Boundary Saturation Boundary
(a) The collector-emitter voltage (b) The collector-emitter voltage
is too close to cutoff. is too close to saturation.
Cutoff Boundary VCC
VCE
0V
Saturation Boundary
(c) The collector-emitter voltage
is centered, but the signal is too large.
Figure 7-2.
The same relationships apply to the FET as indicated in Fig. 7-3. Study it carefully and compare
it to Fig. 7-1. Figure 7-2 can also be made to apply to the FET by simply changing the
nomenclature. VCC becomes VDD and VCE is changed to VDS. (There are other factors that also
direct the location of the Q point to achieve the maximum, symmetrical, undistorted signal swing,
but we defer that discussion for now.)
ID
FET Midpoint Bias
I D(SAT)
DC Load Line
I D(SAT) Q Cutoff Boundary VDD

2
VDD
VDS
15 V VDS
0
VDS(OFF)
VDS(OFF) ID = 1 mA 0V
Saturation Boundary
2 RD
VDD 7.5 k
I D(SAT) =
RD
+
I
ID = D(SAT) VDS = 7.5 V
2
_
VDS(O FF) VDD
VDS = =
2 2
Figure 7-3.

7-2 Device Variations Due to Tolerance and Temperature
Over the years, manufacturers have refined their processes to provide us with an array of very
reliable solid-state devices. Even so, we find that most solid-state components exhibit a
respectable variation in their various parameters. For example, the 2N3904 is a very-widely-used
npn BJT. At a collector current (IC) of 10 mA, this BJT offers a DC that can range from 100 to
300. While a 3:1 variation in DC seems substantial, even larger variations because of temperature
are possible. To illustrate, a partial data sheet for the 2N3904 npn BJT has been reproduced in
Fig. 7-4.1
Figure 7-4.
1 Data sheets are available on the Internet. Simply type “2N3904” in a search engine and it will return data sheets from many
different manufacturers.
Device Variations Due to Tolerance and Temperature 5

In Fig. 7-4, we see the 2N3904 is an npn transistor that is available in an injection-molded TO-92
case style, and surface mount technology (SMT) packages as well2. In the case of the SMT
packages, the acronym SOT stands for small-outline transistor, while SOIC represents small-
outline integrated circuit. The 2N3904 is designed for general-purpose switching and amplifier
applications. The maximum ratings include the maximum collector-emitter voltage of 40 V, the
maximum collector-base voltage of 60 V, and the maximum base-emitter reverse bias of 6 V. Note
the “O” means the unlisted third terminal is open. For example, VCEO is the voltage from the
collector to the emitter with the base terminal open. The maximum collector current of 200 mA
is also provided on the data sheet.
In Fig. 7-5, we see another portion of the data sheet for the 2N3904. The electrical characteristics
are measured at room temperature, which is standardized to be 25oC as indicated at point A. The
DC current gain hFE (which we shall use as DC) is specified at a collector current of 10 mA and a
VCE of 1 V as noted at point B. The current gain can assume a minimum value of 100 (point C)
and a maximum value of 300 (point D).
B C D
Figure 7-5.
2 Packages such as the TO-92 are designed to be used with printed-circuit boards with mounting holes for its leads. To improve
packaging density, surface-mount technology has been developed. Surface-mount technology permits the mounting of
components on both sides of the printed-circuit board.

BJT Parametric Variations Due to Temperature
A BJT’s current gain is also affected by the size of its collector current, and the BJT’s junction
temperature (Tj). The variation in the minimum DC current gain is reflected in the values provided
in Fig. 7-6. We see the current gain decreases gradually with IC to a point, and then falls off rapidly
at higher values of IC. The collector-base junction temperature is a critical parameter. (From our
basic BJT theory of operation, we recall that the carriers moving from the base to the collector
region lose a large amount of energy as heat.) The variation in the current gain with temperature
is also shown in Fig. 7-6. There are three key points to remember. First, the current gain varies
with collector current. Second, at high values of collector current, the current gain diminishes
rapidly, and third, the current gain increases with increasing temperature.
Figure 7-6.
In addition to the DC current gain, the BJT’s base-emitter voltage, and its leakage currents are also
susceptible to the effects of temperature. Let us consider the base-emitter voltage VBE. A forward-
biased diode p-n junction exhibits a temperature coefficient of –2 mV/oC. This is also the case for
a BJT’s forward-biased base-emitter p-n junction. The BJT’s leakage currents (like ICEO and ICBO)
tend to increase with temperature3.
FET Parametric Variations Due to Tolerance

Like the BJT, FETs have a respectable tolerance in their parameters. The two most important
JFET and DE-MOSFET biasing parameters are VGS(OFF) and IDSS. On a data sheet, the device
manufacturers will typically list the minimum and maximum values for these parameters. Because
the parameters are a function of device geometry and doping level, FETs that have the maximum
(magnitude) of VGS(OFF) will also have the maximum (magnitude) of IDSS. The converse is also
true. FETs that have the minimum (magnitude) of VGS(OFF) will also have the minimum
(magnitude) of IDSS. Consequently, an FET of a given type can exhibit a range of possible transfer
characteristic curves. The minimum and maximum transfer curves are defined by Eqs. 7-1 and 7-
2.
3 Temperature effects on a p-n junction are introduced in Volume 1, Section 3-3. BJT leakage currents ICBO and ICEO are
explained in Volume 1, Section 5-5.

For Minimum Transfer Curves:
2
 VGS 
I D = I DSS (m in) 1 −  (7-1)
 VGS (OFF − m in) 
For Maximum Transfer Curves:
2
 VGS 
I D = I DSS (max) 1 −  (7-2)
 VGS (OFF − max) 
A partial data sheet for the 2N5457 n-channel JFET has been given in Fig. 7-7. The drain
saturation current (IDSS) for the 2N5457 ranges from 1.0 to 5.0 mA. Its corresponding gate-to-
source cutoff voltage (VGS(OFF)) ranges from –0.5 to –6.0 V. Equations 7-1 and 7-2 are used to
produce the minimum and maximum transfer curves as illustrated in Fig. 7-84. The minimum and
maximum transfer curves define the boundaries of the operation. Most of the actual transfer curves
will fall between these two extremes.
2N5457 JFET
GENERAL PURPOSE
2N5458 N-CHANNEL - DEPLETION
2N5459
CASE 29-02, STYLE 5
TO-92 (TO-226AA)
ELECTRICAL CHARACTERISTICS (TA = 25 oC unless otherw ise noted.)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Gate Source Cutoff Voltage V GS(off) Vdc
(V DS = 15 V, I D = 10 nA) 2N5457 -0.5 - -6.0
2N5458 -1.0 - -7.0
2N5459 -2.0 - -8.0
ON CHARACTERISTICS
Zero-Gate Voltage Drain Current I DSS mAdc
(V DS = 15 V, V GS = 0 V) 2N5457 1.0 3.0 5.0
2N5458 2.0 6.0 9.0
2N5459 4.0 9.0 16
Figure 7-7.
4 The FET transfer equation is introduced in Volume 1, Section 6-4.

The Minimum and Maximum Transfer Curves for the 2N5457
ID
2
 VGS 
I D = I DSS(max) 1 −  5 mA IDSS(max)
 VGS(OFF − max) 
4 mA
3 mA
2
 VGS 
I D = I DSS(min) 1 −  2 mA
 VGS(OFF − min) 
1 mA IDSS(min)
6 5 4 3 2 1 0
VGS(OFF-max) VGS(OFF-min)
Figure 7-8.
FET Parametric Variations Due to Temperature

In addition to the variation produced by tolerance, temperature also affects a JFET’s performance.
At low levels of drain current, the JFET behaves much like a BJT. Specifically, its drain current
(like a BJT’s collector current) tends to increase as the temperature is raised. However, at higher
levels of drain current, the JFET demonstrates the opposite effect. In this case, the drain current
will decrease as the device temperature is raised. The two underlying mechanisms are illustrated
in Fig. 7-9.
In Fig. 7-9(a) we see why the drain current exhibits a positive temperature coefficient.
Temperature increases cause the width of depletion regions to decrease. This produces an increase
in the channel thickness. This raises the drain current. As a direct consequence of the increase in
the channel thickness, the required magnitude of VGS(OFF) increases. Figure 7-9(b) shows us why
the JFET demonstrates a negative temperature coefficient. Carrier mobility decreases as
temperature is raised. Atoms in a solid tend to vibrate around a point of equilibrium, and their
amplitude of vibration is directly proportional to temperature. Therefore, the probability of
collisions between the charge carriers and the atoms in the crystalline structure increases. This
means the resistivity of the silicon increases with temperature increases. Consequently, the drain
saturation current IDSS will decrease as the device temperature is elevated. The effects of these two
distinct mechanisms are reflected in the transfer characteristic as shown in Fig.7-10.

Temperature Effects
Increases with temperature.
He at 2
 VGS 
ID = I DSS 1 − 
 VGS(O FF) 
+
+
VDD Magnitude increases with temperature
VGS _
Fixed because channel thickness increases.
V GG
Fixed
+
(a) At low values of drain current, the drain current has a positive
temperature coefficient.
Decreases with temperature.
He at 2
 VGS 
ID = IDSS 1 − 
 VGS(OFF) 
+
+
VDD Magnitude decreases with temperature
VGS
_ Fixed because carrier mobility decreases.
V GG
Fixed
+
(b) At high values of drain current, the drain current has a negative
temperature coefficient.
Figure 7-9.
The drain current exhibits both a positive and a negative temperature coefficient. In Fig. 7-10 we
see a point where the two transfer curves cross. There is no temperature sensitivity in this value
of drain current. This is the zero-temperature coefficient (tempco) point.

Temperature Effects on the Transfer Curve
ID
IDSS @ 25 o C
o IDSS @ 125 o C
TA = 25 C
At higher levels of drain current,

the drain current decreases as
the ambient temperature is raised.
o
At low er levels of drain current, TA = 125 C
the drain current increases as
the ambient temperature is raised.
VGS
0
VGS(OFF) @ 25 o C Zero tempco point
VGS(OFF) @ 125o C
Figure 7-10.
In addition to the effects of temperature on IDSS and VGS(OFF), the gate leakage current IGSS also
affects bias stability. IGSS stands for the gate-to-source leakage current as measured with the
drain shorted to the source. A test circuit that defines the measurement of IGSS is provided in Fig.
7-11. This current is produced by minority carrier generation within the gate-channel depletion
region. The reverse saturation current that flows through a reverse-biased p-n junction
approximately doubles for each 10oC rise in temperature5. Figure 7-11 also includes part of the
data sheet for the 2N5457. The transistor convention is used. The negative value of IGSS means
that it flows out of the n-channel JFET. The test circuit indicated in Fig. 7-11, establishes the
test conditions defined for the measurement of IGSS. The current measurement scheme is not
defined because nanoampere current measurement require special attention.
The extremely small leakage currents for MOSFETs, is less susceptible to the effects of
temperature since no p-n junctions are involved. The DE-MOSFET parametric variations in IDSS
and VGS(OFF) are like those of the JFET. The E-MOSFET demonstrates the same temperature
characteristics in its drain current as the JFET. This will become more important to us when we
investigate power amplifiers. We will examine the E-MOSFET temperature characteristics more
closely at that point.
5 Reference Volume 1, Section 3-3.

Test Circuit to Measure I GSS
o
TA = 25 C
VDS = 0V
I GSS
+ 2N5457
VGS _
VGG
15 V
+
ELECTRICAL CHARACTERISTICS (TA = 25 oC unless otherw ise noted.)

Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Gate Reverse Current IGSS -1.0 nAdc
(V GS= -15 Vdc, VDS = 0 V)
o -200
(V GS= -15 Vdc, VDS = 0 V, T A= 100 C)
Figure 7-11.
7-3 BJT Fixed Base Bias
The fixed base bias circuit was introduced in Volume 1, Section 5-8, with the three steps to its
analysis captured in Fig. 5-28. A fixed base bias circuit has been shown in Fig. 7-12.
Fixed Base Bias Analysis
VCC • Basic equations: • Provides no compensation for BJT
V − 0.7V parameter variation.
15 V IB = CC
RB
• The collector current is directly
IC =  DC IB proportional to beta.
RC VCE = VCC – IC RC
RB
Q1 3.6 k
1.8 M • Simple, but extremely poor Constant
IB
2N4124 IC
+
bias stability.
I C =  DC I B
+ VCE
0.7 V_
_
Figure 7-12.

Figure 7-12 reminds us the base current IB is determined primarily by VCC and RB. Therefore, IB
is reasonably fixed, or constant. This is the fundamental weakness of the circuit. The collector
current IC is given by the product of IB and DC. This means IC will vary directly with DC. This
is best demonstrated by example.
Example 7-1. The npn BJT in Fig. 7-12 is a 2N4124 silicon unit. It has a DC that ranges
from 120 to 360. Determine IB, IC, and VCE if a 2N4124 with a DC of 120 is used.
Solution: First, we analyze the input and find the base current IB.
VCC − 0.7 V 15 V - 0.7 V
IB = = = 7.94 A
RB 1.8 M
Second, we transfer across the device and find the collector current IC.
I C =  DC I B = (120)(7.944 A) = 0.953 mA
We conclude our analysis by analyzing the output to determine the collector-emitter voltage VCE.
VCE = VCC − I C RC = 15 V - (0.9533 mA)(3.6 k) = 11.6 V
Solution: First, we analyze the input. The base current IB is unaffected by the size of DC.
VCC − 0.7 V 15 V - 0.7 V
IB = = = 7.94 A
RB 1.8 M
Now we transfer from the input to the output by finding the collector current IC.
I C =  DC I B = (360)(7.944 A) = 2.86 mA
We conclude our analysis by analyzing the output to determine the collector-emitter voltage VCE.
VCE = VCC − I C RC = 15 V - (2.86 mA)(3.6 k) = 4.70 V
Obviously, this circuit is not very stable6. The collector-to-emitter voltage can range from 4.70 to
11.6 V. In fact, if IB is too large for a given DC, the BJT can become saturated. Similarly, if the
base current is too small for a given DC, the BJT can begin to enter cutoff. Vast improvements
can be made by arranging a bias circuit such that it will automatically decrease IB if the DC is large
and automatically increase IB if the DC is small. This is called DC negative feedback. This is the
secret underlying any successful bias circuit.
6 There are two things a designer of a poor (beta-dependent) bias circuit can count on. The first is being invited to be the featured
speaker in a staff meeting called by the Production Manager. The second is to be the target of hostile thought projections
launched by disgruntled field service repair technicians.
BJT Fixed Base Bias 13

For the purposes of comparison, the BJT bias circuits that follow are designed for a nominal IC
of 2 mA.
7-4 FET Bias Lines: Escaping the Math Attack!

The first step in the investigation of any amplifier circuit is to perform a DC analysis. A three-
step process can be used that includes analyzing the input circuit, transferring from the input circuit
to the output circuit, and then analyzing the output circuit.
What Makes BJT Analysis So Easy?

Two facts about the BJT simplify its DC analysis. First, its base-emitter voltage VBE is reasonably
constant, and can be treated as a known quantity (e.g., for silicon VBE is 0.7 V). Second, its transfer
functions DC and DC can be approximated as constants. This means the collector current is
directly proportional to the controlling input current. We have a linear relationship between the
input and output currents.
What Makes FET Analysis Different?

Analysis of FET bias circuits requires a bit more effort. There are two reasons. First, we cannot
approximate VGS. Second, there is a non-linear relationship between the controlling input VGS, and
the output drain current ID. Many FET bias circuits will produce an equation for the controlling
input voltage VGS that will be in terms of the controlled drain current ID. This gets messy since we
have one equation and two unknowns. Basic algebraic concepts tell us that we need two
independent equations to solve for two unknowns. The required second equation in these cases is
the FET’s transfer equation. Its square-law nature complicates the analysis when we solve it
algebraically. Specifically, we enter the world of the quadratic formula and the need to eliminate
extraneous roots. (Yes, that entire math tool set is required.) If we elect to solve the problems
graphically, we eliminate this algebra. However, now we must draw graphs, and be neat. This is
not a thrilling option but is does offer us increased insight into circuit operation.
The Bias Line is Obtained by Plotting the Equation for VGS.

To understand this graphical escape from mathematical tedium7, we shall examine the fixed-gate
bias circuit (Fig. 7-13). The complete common-source amplifier is shown in Fig. 7-13(a).
Capacitors C1 and C2 are the input and output coupling capacitors, respectively. They act like
short circuits to the AC signal and open circuits to the DC bias. In Fig. 7-13(b) the capacitors have
been replaced by open circuits.
7 Unfortunately, some students might feel compelled to suggest “terror” is a more appropriate description than “tedium”.

Finding the Q-Point of a Common-Source Amplifier
V DD ID
15 V
+
RD RD
820  C2 820  + VDD

C1 I GSS 15 V
+ +
+
+ VDS
+ + vOUT 
+ VGS 
vIN RG
RG -
- 220 k 
220 k Output circuit
VGG
-VGG 3V Input circuit
-3 V +
(a) The common-source amplifier. (b) The DC equivalent circuit.
Figure 7-13.
Step 1: Analyze the Input.

Write a Kirchhoff's voltage law equation around the input circuit and solve for VGS. This is the
bias line equation. Examine the DC equivalent circuit shown in Fig. 7-13(b). We write a
Kirchhoff's voltage law equation around the input circuit.
VGG – IGSSRG + VGS = 0
We solve the equation for VGS.
VGS = -VGG + IGSSRG
Recall that the leakage current IGSS is so small the voltage drop across RG is negligible. This gives
rise to an approximation. Equation 7-3 forms our bias line equation.
VGS  -VGG (7-3)
Step 2: Transfer Across the Device.

We take the transfer equation (Eq. 7-4) and graph it.
2
𝑉𝐺𝑆
𝐼𝐷 = 𝐼𝐷𝑆𝑆 [1 − ] (7 − 4)
𝑉𝐺𝑆(𝑂𝐹𝐹)
According to the manufacturer’s data for this JFET, IDSS is 30 mA and VGS(OFF) is –7V. It has been
graphed as indicated in Fig. 7-14(a). The bias line is then placed on the transfer characteristic.
This is indicated in Fig. 7-14(b). The intersection between the bias line and the transfer
characteristic yields the Q-point. This means we obtain the unique values for VGS and ID that
satisfy the bias line (for the circuit) and the transfer equation (for the FET) simultaneously.
FET Bias Lines: Escaping the Math Attack! 15

Since VGS is a constant, its value is not a surprise here. However, knowing the drain current permits
us to analyze the output.
Step 3: Analyze the Output.

Once ID is determined, we are freed from graphs. We return to analytical methods. Specifically,
we apply Kirchhoff's voltage law to the output circuit, and solve it for VDS. Refer to Fig. 7-13(b).
-VDD + IDRD + VDS = 0
VDS = VDD – IDRD (7-5)
Finding the Drain Current Using a Bias Line

2
ID
 VGS 
I D = I DSS 1 −  I
 VGS(OFF)  30 mA = DSS
VGS (V) ID (mA)

0 30.0
-1 22.0 20 mA
-2 15.3
-3 9.8
-4 5.5
-5 2.5
-6 0.6 10 mA
-7 0
-7 -6 -5 -4 -3 -2 -1 0 VGS
(a) Graphing the transfer curve.

ID
I DSS
Bias Line
VGS = -3.0 V 30 mA
Q
9.8 mA
0 mA
-7 V 0.0V VGS
-3.0 V
VGS(OFF)
(b) Plotting the bias line.
Figure 7-14.

Example 7-3. Perform a DC analysis of the common-source amplifier shown in Fig. 7-13,
which has been repeated in Fig. 7-15. Specifically, determine VGS, ID, and VDS.
Solution: With reference to the DC equivalent circuit shown in Fig. 7-15(b), we apply Eq. 7-
3 to obtain the controlling input voltage VGS. This is the equation for the bias line.
VGS = -VGG = -3 V
We transfer from the input circuit to the output circuit using the bias line. From the
manufacturer’s data sheet, we learn that IDSS = 30 mA and VGS(OFF) = -7 V. Equation 7-4 has
been graphed as illustrated in Fig. 7-14(a). We plot the bias line as shown in Fig. 7-14(b). The
intersection between the bias line and the transfer characteristic gives us ID.
ID  9.8 mA
We use Eq. 7-5 to find VDS.
VDS = VDD – IDRD = 15 V – (9.8 mA)(820 ) = 6.964 V  6.96 V
Figure 7-15.
The Analytical Method for Fixed-Gate Bias is Easier

Example 7-3 illustrates the bias line approach. This graphical method is not the best choice to
analyze a fixed-gate bias circuit. The pure analytical approach is preferred as demonstrated below.
FET Bias Lines: Escaping the Math Attack! 17

We use KVL around the input circuit and solve for VGS.
VGS = -VGG = -3 V
We transfer from the input to the output using the square-law equation.
𝑉𝐺𝑆
2
−3 V 2
𝐼𝐷 = 𝐼𝐷𝑆𝑆 [1 − ] = (30 mA) [1 − ] = 9.80 mA
𝑉𝐺𝑆(𝑂𝐹𝐹) −7 V
We write a KVL equation around the output circuit and solve for VDS.
VDS = VDD – IDRD = 15 V – (9.8 mA)(820 ) = 6.964 V  6.96 V
Our intention here is to illustrate the methods and obtain confidence in the results they provide.
Again, we use the graphical approach to simplify our work.
The Bias Line is Used to Examine the Effects of Parametric Variation

Now we shall see how to examine an FET fixed-bias circuit to determine the effects of parametric
variation due to tolerance. Study Example 7-4.
Example 7-4. Perform a DC analysis of the common-source amplifier shown in Fig. 7-

16(a). Specifically, determine VGS, ID, and VDS if the 2N5457 has the maximum transfer curve.
Repeat the analysis if the 2N5457 has the minimum transfer curve. (The transfer curves were
originally presented in Fig. 7-8.)
Solution: We apply Eq. 7-3 to obtain the controlling input voltage VGS. This is the equation
for the bias line.
VGS = -VGG = -0.25 V
We plot the bias line as shown in Fig. 7-16(b). The intersection between the bias line and the
maximum transfer characteristic gives us the maximum value for ID.
ID  4.6 mA
We use Eq. 7-5 to find VDS.
VDS = VDD – IDRD = 12 V – (4.6 mA)(2.2 k) = 1.88 V
We repeat the analysis using the minimum transfer curve. From Fig. 7-16(b) we see the
intersection between the bias line and the minimum transfer curve gives us the minimum value
of ID

ID  0.25 mA
Again, we use Eq. 7-5 to find VDS.
VDS = VDD – IDRD = 12 V – (0.25 mA)(2.2 k) = 11.5 V
Finding the Q-Point Variation ID

V DD
12 V 5 mA
I D(max)
RD
= 4.6 mA
2.2 k 4 mA
Q1
C1 2N5457
+
C2 +
3 mA
+ + v OUT
vIN
RG -
2 mA
- 470 k
1 mA
-VGG
-0.25 V
ID(min)
6V 5V 4V 3V 2V 1V 0
= 0.25 mA
VGS
(a) The common-source amplifier. (b) The bias line analysis.
Figure 7-16.
Consider these results. The drain current can be as large as 4.6 mA, which makes the drain-to-
source voltage only 1.88 V! The circuit is nearly saturated. At the opposite extreme, we see the
drain current can be as small as 0.25 mA. This produces a drain-to-source voltage of 11.5 V. In
this case, the circuit is almost in cutoff. This fixed-gate bias circuit is extremely poor indeed.8
Fixed Base Bias and Fixed Gate Bias Both Perform Poorly
In our quest to obtain stable bias circuits, fixing the BJT’s base current IB, or the FET’s gate-source
voltage VGS is not the correct approach. If the BJT’s collector current increases, we need to
automatically reduce its base current. This can be accomplished by using DC negative feedback.
Similarly, if an FET’s drain current increases, we want to increase the size its VGS. How? Again,
we use DC negative feedback. The same basic approach is used to achieve bias stability for both
BJTs and FETs.
8 If this bias circuit were a beast, the kindest thing we could do is put it out of its misery.
FET Bias Lines: Escaping the Math Attack 19

7-5 BJT Collector-Voltage Feedback Bias
At first glance, the collector-voltage feedback bias circuit [Fig. 7-17(a)] looks like an accident!
The base resistor RB is tied to the BJT’s collector instead of being connected to VCC. To analyze
the circuit, we shall draw on our three-step procedure. Specifically, we analyze the input, transfer
from the input side to the output side, and then analyze the output. The circuit has been redrawn
in Fig. 7-17(b). Observe that both IC and IB flow through RC. To analyze the input, we write a
Kirchhoff's voltage law equation, and solve for the base current IB. With reference to Fig. 7-17(b),
we start our Kirchhoff's voltage law at ground moving in the direction of the collector current. The
signs are based on the polarity of the terminal voltages as we encounter them.
-VCC + (IC + IB)RC + IBRB + 0.7 V = 0
We eliminate IC by substituting IC = DCIB into the Kirchhoff's voltage law equation.
-VCC + (DCIB + IB)RC + IBRB + 0.7 V = 0

-VCC + (DC + 1)RCIB+ IBRB + 0.7 V = 0
Since DC is much larger than one (1), we can simplify the equation slightly.
-VCC + DCRCIB+ IBRB + 0.7 V = 0
We transpose the voltages to the right-hand side, and factor out the base current IB.
DCRCIB+ IBRB = VCC - 0.7 V

(DCRC + RB)IB = VCC – 0.7 V
We divide both sides by the quantity in parentheses to arrive at Eq. 7-6 for the base current.
VCC − 0.7 V
IB = (7-6)
R B + β DC RC
Collector-Voltage Feedback Bias Circuit Analysis

Given Circuit Step 1: Analyze the Input
RC IC+ IB
VCC 3.6 k
15 V
_ +
VCC − 0.7 V RB
IB =
RC R B +  DCR C IB IC
RB 820 k VCC +
820 k 3.6 k
_ 15 V
+ +
Q1 0.7 V
_
2N4124
Input Output
(a) (b)
Figure 7-17.
Collector-Voltage Feedback Bias Circuit Analysis (continued)
Step 2: Transfer from the Input Step 3: Analyze the Output
to the Output
VCE ~= VCC – IC RC
IC =  DC IB RC RC
IC + IB ~
= IC
3.6 k 3.6 k
_ +
RB RB
IC
820 k VCC + 820 k + VCC +
15 V VCE 15 V
(c) (d)
Figure 7-17 (continued).
Observe that DC appears in the denominator of Eq. 7-6. As we shall see, this is very significant.
Figure 7-17(c) reminds us that we use DC to transfer from the input side to the output side. Our
output analysis consists of finding VCE. Again, we use Kirchhoff's voltage law. To simplify the
analysis, we assume the base current that flows through the collector resistor RC is negligibly small
when compared to the collector current IC.
-VCC + (IC + IB)RC + VCE = 0
-VCC + ICRC + VCE  0
VCE  VCC - ICRC (7-7)
The operation of the circuit is demonstrated in Examples 7-5 and 7-6.
Example 7-5. The npn BJT in Fig. 7-17(a) is a 2N4124 silicon unit. It has a DC that ranges
Solution: The base current IB is given by Eq. 7-6.
VCC − 0.7 V 15 V - 0.7 V 14.3 V

IB = = = = 11.4 A
R B + β DC RC 820 k + (120)(3.6 k) 1.252 M
Now we can find the collector current IC.

I C = β DC I B = (120)(11.42 A) = 1.37 mA
We conclude our analysis by determining the collector-emitter voltage VCE.

VCE  VCC − I C RC = 15 V - (1.371 mA)(3.6 k) = 10.1 V
BJT Collector-Voltage Feedback Bias 21

Example 7-6. The npn BJT in Fig. 7-17(a) is a 2N4124 silicon unit. It has a DC that ranges
Solution: The base current IB is given by Eq. 7-6.
VCC − 0.7 V 15 V - 0.7 V 14.3 V

IB = = = = 6.76 A
R B + β DC RC 820 k + (360)(3.6 k) 2.116 M
Now we can find the collector current IC.

I C = β DC I B = (360)(6.758 A) = 2.43 mA
We conclude our analysis by determining the collector-emitter voltage VCE.

VCE  VCC − I C RC = 15 V - (2.433 mA)(3.6 k) = 6.24 V
Let us reflect on these results. With the fixed-base bias circuit, VCE can range from 4.70 to 11.6
V. In contrast, the collector-voltage feedback bias circuit offers a VCE that ranges from 6.24 to
10.1 V. While not perfect, the collector-voltage feedback bias circuit appears to be a step in the
right direction. When DC increases, the base current IB is reduced automatically. Consequently,
the collector current does not increase as much. Refer to Fig. 7-18. The converse is also true. If
DC decreases, the base current IB is increased automatically.
Collector-Voltage Feedback Bias Circuit Operation
VCC
• The
An increase in  increases I .
DC C
• voltage drop across R increases because I

C C increases.
• AV corresponding
CE 
=V -I R
CC C C
reduction in V w ill occur.
CE
~
RB RC
= IC
• The reduced V w ill low er the base current.
CE
V − 0.7V VCE
I B = CE 
+ RB RB
VCE • The net increase in the collector current will be reduced.

IB Q1
_
I C = DC I B
Figure 7-18.

The collector-voltage feedback bias circuit is summarized in Fig. 7-19. Also note the BJT’s
terminal-to-ground voltages have been defined in Fig. 7-19. When ground is the point of reference,
a single subscript is employed (e.g., VC is the collector-to-ground voltage). These voltages are
useful for testing and troubleshooting purposes in the laboratory. We ground our DMM (digital
multimeter) and probe the three BJT terminals. A voltage measurement that disagrees with our
calculations usually means we have a problem with the circuit. For instance, VB should be 0.7 V
approximately. However, if the base terminal connection is open, the left end of the base resistor
RB will be pulled toward VCC.
Collector-Voltage Feedback Bias Circuit Summary

VCC VCC − 0.7 V
IB =
R B +  DC R C
~
= IC I C =  DC IB
RB RC
VCE  VCC − IC R C
+
The terminal-to-ground voltages:
VCE VC = VCE
Q1
_ VB = VBE  0.7 V
VE = 0
Figure 7-19.
Examples 7-5 and 7-6 have examined the collector voltage feedback bias circuit using a 2N4124
BJT. Multisim can also be used to analyze the circuit.
Run Multisim and you should obtain a blank page. Click on Place and select component. Select
Basic under Group. Select Resistor [see Fig. 7-20(a)]. Place two resistors on the schematic sheet.
Next, select Sources under Group. Choose Power Sources and then VCC and place it on the
schematic page [see Fig. 7-20(b)]. Also select Ground and place it on the schematic page. Select
Transistors under Group and then BJT_NPN. You can scroll down through list or simply type
2N4124 in the Component box [see Fig. 7-20(c)]. Wire the components. Voltages and currents
can be measured by using multimeters located on the right side of the sheet [see Fig. 7-20(d)].

(a.) (b.)
Multimeter
(c.) (d.)
Figure 7-20.
Clicking on the green arrow (located on the top tool bar) will run the simulation. The results are
provided in Fig. 7-21. The values lie between the two extreme limits analyzed in Examples 7-5
and 7-6.

(a.)
(b.)
Figure 7-21.
Since we have measurements for IC and IB, we can determine the current gain for the 2N4124
library part.
𝐼𝐶 1.887 mA
𝛽𝐷𝐶 = = = 207
𝐼𝐵 9.137 μA
Recall the ßDC for the 2N4124 ranges from 120 to 360. The library part is using the geometric
mean. The calculation follows:
𝛽𝐷𝐶(𝐴𝑉𝐺) = √𝛽𝐷𝐶(𝑀𝐼𝑁) 𝛽𝐷𝐶(𝑀𝐴𝑋) = √(120)(360) = 208

7-6 MOSFET Drain-Voltage Feedback Bias
Drain-voltage feedback bias is very similar to BJT collector-voltage feedback bias. Drain-voltage
feedback bias is used for enhancement-mode biasing only. Consequently, it cannot be used to
bias JFETs.14 A typical bias circuit for an n-channel E-MOSFET is given in Fig. 7-22(a).
The E-MOSFET Drain Voltage Feedback Bias Circuit
A DE-MOSFET can also be used, but NOT a JFET.
V DD ID
Bias Line:
RD
+ V DD V GS = VDD - I D R D
RD
RG -
ID
C2
Q1
+ +
C1 +
VDS
+ v OUT
+ +
VGS -
vIN -
= VDS -
-
VGS
0
V DD
Figure 7-22.
Recall the E-MOSFET transfer equation is given by Eqs. 7-8 and 7-9. The E-MOSFET also has
a minimum and a maximum transfer characteristic.
2
𝐼𝐷 = 𝐾𝑚𝑖𝑛 [𝑉𝐺𝑆 − 𝑉𝐺𝑆(𝑡ℎ−𝑚𝑖𝑛) ] (7-8)
2
𝐼𝐷 = 𝐾𝑚𝑎𝑥 [𝑉𝐺𝑆 − 𝑉𝐺𝑆(𝑡ℎ−𝑚𝑎𝑥) ] (7-9)
Recall that K is a constant we need to determine and VGS(th) is the E-MOSFET threshold voltage,
which the value of VGS that just forms the channel and allows drain current to begin to flow.
Example 7-7 shows how Eqs. 7-8 and 7-9 can be used to develop the minimum and maximum
transfer curves.
14 A JFET can be biased this way, but it will not work very well. In a worst-case scenario, we may permit the “magic” smoke
within it to escape. From that point on, the JFET will cease to function. This can be catastrophic if the JFET happens to
belong to a short-tempered lab partner!

Example 7-7. Determine the minimum and maximum transfer curves for the E-MOSFET to
be used in the common-source amplifier shown in Fig. 7-22(a).
Solution: Using the manufacturer’s data, we obtain E-MOSFET’s parameters. For this
particular E-MOSFET VGS(th) ranges from 1 V to 5 V. It has an ID(ON) that ranges from 2 mA to 20
mA for a VGS of 10 V. We use this information to determine the E-MOSFET’s minimum and
maximum K values. The manufacturers do not provide the K values, but they do provide drain
current (ID(ON)) values for specified VGS values. We solve Eqs. 7-8 and 7-9 for Kmin and Kmax,
respectively. Let’s find Kmin first.
I D (ON − min) 2 mA A
K min = = = 24.7 2
(VGS − VGS (th − min) )
2
(10 V - 1 V) 2
V
The maximum value of K is determined in the same fashion.

I D (ON −max) 20 mA A
K max = 2
= 2
= 800 2
(VGS − VGS(th−max ) ) (10 V - 5V) V
We apply these results to Eqs. 7-8 and 7-9. To graph the characteristics, we select convenient
values of VGS and compute the corresponding values for ID. This process yields the two transfer
characteristic curves [see Fig. 7-22(b)].
ID = Kmin[VGS – VGS(th-min)]2 = (24.7 A/V2)(VGS – 1 V)2
ID = Kmax[VGS – VGS(th-max)]2 = (800 A/V2)(VGS – 5 V)2
The Bias Line Equation for Drain-Voltage Feedback

The gate leakage current (IGSS) of a MOSFET is even smaller than the leakage current associated
with JFETs. Typical values might range from picoamperes (pA) to nanoamperes (nA).
Consequently, the voltage drop across the gate resistor RG is negligibly small [see Fig. 7-23.].
Figure 7-23.
MOSFET Drain-Voltage Feedback Bias 27
This means the gate-to-source voltage VGS will be equal to the drain-to-source voltage VDS. If
we include this observation and apply Kirchhoff's voltage law to the drain circuit in Fig. 7-23, we
obtain Eq. 7-10.
VGS = VDS = VDD - IDRD (7-10)
This is our bias line equation as indicated in Fig. 7-24. The easiest way to plot the bias line is to
set ID to zero in the bias line equation. VGS is then equal to VDD. In Fig. 7-24 we see that point
indicated on the horizontal VGS axis.
VGS = VDD
If we set VGS to zero in the bias line equation and solve for the resulting drain current, we get
𝑉𝐷𝐷
𝐼𝐷 =
𝑅𝐷
This endpoint lies on the vertical ID axis as shown in Fig. 7-24.
Figure 7-24.
Example 7-8. Perform a DC analysis of the common-source amplifier shown in Fig. 7-25(a).
Specifically, use a bias line to determine the minimum drain current ID(min) for an E-MOSFET that
has a minimum transfer characteristic. Use that result to find the corresponding values of the gate-
to-ground voltage VG, the source-to-ground voltage VS, the drain-to-ground voltage VD, and VDS.
Repeat the analysis if the E-MOSFET has the maximum transfer curve.
Solution: The E-MOSFET’s minimum and maximum transfer curves were determined in
Example 7-7. Now we can plot the bias line as illustrated in Fig. 7-26.

VGS = VDS = VDD - IDRD = 15 V – 750ID
The bias line endpoints are determined and then connected with a straight line. For ID equal to
zero and then VGS set to zero, we obtain the results that follow.
VGS = VDD = 15 V
𝑉𝐷𝐷 15 𝑉
𝐼𝐷 = = = 20 𝑚𝐴
𝑅𝐷 750 Ω
7-8
Figure 7-25.
The bias line intersections with the transfer curves are shown in Fig. 7-26.
We analyze the circuit using the minimum drain current. VS must be zero since the source
terminal is tied to ground. The DC equivalent circuit is given in Fig. 7-25(b).
ID(min) = 3.29 mA
VG = VGS = VDD – IDRD = 15 V – (3.29 mA)(750 ) = 12.5 V
VS = 0 V
VD = VDS = VGS = 12.5 V
We conclude our analysis by considering the maximum drain current case.
ID(max) = 8.89 mA
VG = VGS = VDD – IDRD = 15 V – (8.89 mA)(750 ) = 8.33 V
VS = 0 V
VD = VDS = VGS = 8.33 V
MOSFET Drain-Voltage Feedback Bias 29

7-8
Figure 7-26.
7-7 BJT Voltage-Divider Bias

The most popular BJT bias circuit using a single-polarity DC power supply employs a voltage
divider on the base of the transistor and includes an emitter resistor. As we shall see, the emitter
resistor provides the required DC negative feedback. The circuit is illustrated in Fig. 7-27(a).
Observe we have a new capacitor C3. While C1 and C2 are input and output coupling capacitors,
C3 is called the emitter bypass capacitor. It prevents AC negative feedback. Its purpose is
explained in detail in Chapter 9. It does not concern us here because all charged capacitors act
like open circuits to the DC bias. Hence, the corresponding DC equivalent circuit is shown in Fig.
7-27(b).
DC
Figure 7-27.
Study Objectives 30
To perform an exact analysis on the voltage divider bias circuit, it is necessary to apply Thevenin’s
theorem. Specifically, we find the Thevenin equivalent circuit driving the base terminal of the
BJT. This is illustrated in Fig. 7-28. (Note the use of four significant figures represents the attempt
to minimize round-off errors rather than indicate a high degree of precision.)
Figure 7-28.
In Fig. 7-28(b), we see the BJT’s base-terminal-to-ground treated as the load. The load is
disconnected from the circuit that we are Thevenizing. The Thevenin equivalent (open-circuit)
voltage VTH is given by simple voltage division between resistors R1 and R2. We find the Thevenin
equivalent resistance RTH by setting the voltage source to zero. This requires that we replace it
with a short circuit as illustrated in Fig. 7-28(c). This places resistors R1 and R2 in parallel. The
Thevenin equivalent circuit is used to replace the original circuit as indicated in Fig. 7-28(d).
We begin the analysis using the equivalent circuit shown in Fig. 7-28(d). First, we analyze the
input. We use Kirchhoff's voltage law to develop an equation for the base current IB. We start at
the negative terminal of VTH and proceed in a clockwise direction around the input circuit.
-VTH + IBRTH + 0.7 V +(IC + IB)RE = 0 (7-11)
BJT Voltage-Divider Bias 31

To simplify the analysis, we recall that IC >> IB and (IC + IB)  IC. We eliminate the collector
current by recognizing that IC = DCIB and substituting this relationship into Eq. 7-11.
-VTH + IBRTH + 0.7 V + IC RE  0
-VTH + IBRTH + 0.7 V + DC IBRE = 0 (7-12)
We conclude our efforts by performing the algebra necessary to solve Eq. 7-12 for IB.
IBRTH + DC IBRE = VTH - 0.7 V
IB (RTH + DCRE) = VTH - 0.7 V
Dividing both sides by the quantity in parenthesis leads us to Eq. 7-13.
VTH − 0.7 V
IB  (7-13)
RTH + β DC R E
where we have VTH = R2VCC/(R1 + R2) and RTH = R1R2/(R1 + R2).

This result is very similar to our equation for the base current of the collector-voltage feedback
bias circuit (Eq. 7-6).15
Transfer from Voltage Divider Bias Analysis IC
the Input to
the Output: +
RC
IC =  DC IB RC
+ _ +
IB VCC
RTH RTH + VCC
_ VCE
+ + + + _
0.7 V_
VTH + VTH +
RE RE IE ~
= IC
_ I E = IC + I B _
~
= IC
Input Output
(a) (b)
Figure 7-29.
Okay, now we transfer across the transistor with IC = DCIB as indicated in Fig. 7-29(a). Next, we
apply Kirchhoff's voltage law around the output side shown in Fig. 7-29(b) and solve it for VCE.
Again, we shall start at ground. We move in the direction of the collector current.
-VCC + ICRC + VCE + IERE = 0
The emitter current IE flows through the emitter resistor RE. We recall that IE = IC + IB  IC.
-VCC + ICRC + VCE + ICRE  0
We solve for VCE to obtain Eq. 7-14.
VCE  VCC – (RC + RE) IC (7-14)
15 Yes, go peek! The goal is to understand what the equations mean rather than just “crank out” values.

As was mentioned previously, the terminal voltages with respect to ground are very useful. The
emitter-to-ground voltage (VE) is relatively easy to obtain. It is equal to the voltage drop across
the emitter resistor RE.
VE = IERE  ICRE (7-15)
Since the base-emitter p-n junction is forward biased, the base-to-ground voltage (VB) of an npn
BJT is one base-emitter voltage drop (VBE) more positive than the emitter. If we assume the BJT
is a silicon unit, VBE  0.7 V.
VB = VE + VBE  VE + 0.7 V (7-16)
The collector-to-ground voltage (VC) is equal to the collector supply voltage (VCC) minus the
voltage drop across the collector resistor.
VC = VCC - ICRC (7-17)
Other equations can be developed. For instance, VCE = VC – VE and VC = VCE + VE. However,
these relationships are merely rearrangements of the equations developed previously. When a BJT
is saturated, it acts like a closed switch between its collector and emitter. IC(SAT) is limited only by
VCC and RC with RE being effectively in series. When the BJT is in cutoff, IC is zero which means
no current flows through RC or RE. VCC is dropped between the BJT’s collector-emitter terminals.
The fundamental equations are summarized in Fig. 7-30.
Voltage Divider Bias Summary

VCC
R1 R 2 The terminal-to-ground
15 V R TH = voltages:
R1 + R 2
R1 RC VC = VCC − IC R C
4.3 k R2
13 k VTH = VCC
R1 + R 2 VE  IC R E
Q1 VTH − 0.7 V VB = VE + 0.7 V
IB =
2N4124
R TH +  DC R E
IC =  DC IB
R2 RE
2.2 k 750 VCE  VCC − IC (R C + R E )
VCC
IC(SAT) =
IC(SAT) RC + R E IC =  IC = 
RC RC RC RC
+ + + +
Q1 VCC VCC Q1 + VCC + VCC
Q1 VCE(OFF) Q1 VCE(OFF) = VCC
Saturation - Cutoff
Equivale nt Equivale nt -
RE Circuit RE RE Circuit RE
Figure 7-30.

from 120 to 360. Determine IB, IC, and VCE if a 2N4124 with a DC of 120 is used. Also find VE,
VB, VC, IC(SAT),, and VCE(OFF).
Solution: Our first task is to find the Thevenin equivalent base circuit. Specifically, we must
find RTH and VTH. (This is detailed in Fig. 7-30.)
R1R2 (13 k)(2.2 k)

RTH = = = 1.882 k
R1 + R2 13 k + 2.2 k
R2 2.2 k
VTH = VCC = (15 V) = 2.171 V
R1 + R2 13 k + 2.2 k
Now we can find the base current IB using Eq. 7-13, which is repeated in Fig. 7-30.
VTH − 0.7 V 2.171 V - 0.7 V
IB  = = 16.01 A
RTH + β DC R E 1.882 k + (120)(750 )
Next, we find the collector current IC and the collector-emitter voltage VCE. The relationships are
repeated in Fig. 7-30.
IC = DCIB = (120)(16.01 A) = 1.921 mA

VCE  VCC − I C (RC + RE ) = 15 V - (1.921 mA)(4.3 k + 750 ) = 5.30 V
We conclude our analysis by finding VE, VB,VC (using Eqs. 7-15 through 7-17, respectively),
IC(SAT) and VCE(OFF). (All of the pertinent equations are also included in Fig. 7-30.)
VE  ICRE = (1.921 mA)(750 ) = 1.44 V
VB  VE + 0.7 V = 1.441 V + 0.7 V = 2.14 V
VC = VCC - ICRC = 15 V – (1.912 mA)(4.3 k) = 6.73 V
VCC 15 V
I C ( SAT ) = = = 2.97 mA
RC + R E 4.3 k + 750 
VCE(OFF) = VCC = 15 V
from 120 to 360. Determine IB, IC, and VCE if a 2N4124 with a DC of 360 is used. Also find VE,
VB, VC, IC(SAT), and VCE(OFF).
Solution: The Thevenin equivalent base circuit is not affected by the BJT’s DC.
Consequently, the values for RTH and VTH are unaffected. (This means we use the values
determined in Example 7-9.)

RTH = 1.882 k
VTH = 2.171 V
Now we can find the base current IB using Eq. 7-13, which is repeated in Fig. 7-30.
VTH − 0.7 V 2.171 V - 0.7 V

IB  = = 5.41 A
RTH + β DC R E 1.882 k + (360)(750 )
Next, we find the collector current IC and the collector-emitter voltage VCE. The relationships are
repeated in Fig. 7-30.
IC = DCIB = (360)(5.410 A) = 1.95 mA

VCE  VCC − I C (RC + RE ) = 15 V - (1.948 mA)(4.3 k + 750 ) = 5.16 V
We conclude our analysis by finding VE, VB, and VC using Eqs. 7-15 through 7-17, respectively.
(These are also included in Fig. 7-30.)
VE  ICRE = (1.948 mA)(750 ) = 1.46 V
VB  VE + 0.7 V = 1.461 V + 0.7 V = 2.16 V
VC = VCC - ICRC = 15 V – (1.948 mA)(4.3 k) = 6.62 V
ICSAT) and VCE(OFF) are unaffected by DC and remain 2.97 mA and 15 V, respectively.
Without a doubt, the voltage-divider bias circuit offers the greatest bias stability. The collector
current ranges from 1.91 to 1.95 mA with our 3:1 variation in DC. It should be obvious why this
circuit is so popular.
An Approximate Analysis Simplifies Our Work

Because a well-designed voltage-divider bias circuit offers such excellent bias stability, it is often
described as being a “DC-independent” bias circuit. Consequently, an approximate analysis
works extremely well if the circuit is designed properly. This approximate analysis approach is
summarized in Fig. 7-31.
If the bleeder current (I) that flows down through the R1-R2 voltage divider “swamps out” the
BJT’s base current, we can assume that the two resistors are in series (approximately). This means
the base-to-ground voltage VB is given by simple voltage division between resistors R1 and R2.
R2
VB = VCC (7-18)
R1 + R2
Since the base must be 0.7 V more positive than the emitter, it is easy to find VE.
VE = VB – 0.7 V (7-19)

If we assume the emitter and collector currents are approximately equal, we may use Eq. 7-20 to
approximate the collector current.
VE
IC  I E = (7-20)
RE
We determine the collector-to-ground voltage VC by using Eq. 7-17, which has been repeated
below as Eq. 7-21.
The collector-emitter voltage VCE is given by Eq. 7-22.
VCE = VC - VE (7-22)
Voltage Divider Bias Approximate Analysis

VCC
15 V Properly designed, the Equations:
bias circuit is "beta independent". R2
RC
R1 IC VB = VCC
4.3 k The bleeder current I is R1 + R 2
13 k
I Q1 VC assumed to be much,
VB + much greater than VE = VB – 0.7 V
VCE the base current.
VE
_ IC  I E =
Resistors R 1 andR 2 RE
R2 VE are effectively in series.
RE
2.2 k 750  VC = VCC - ICRC
VCE = VC - VE
Figure 7-31.
Example 7-11. The npn BJT in Fig. 7-31 is a 2N4124 silicon unit. Determine VB, VE, IC, VC
and VCE using the approximate analysis detailed in Fig. 7-31.
Solution: The equations summarized in Fig. 7-31 can be solved sequentially.

R2 2.2 k
VB = VCC = (15 V) = 2.17 V
R1 + R2 13 k + 2.2 k
VE = VB – 0.7 V = 1.47 V
VE 1.471 V
IC  I E = = = 1.96 mA
RE 750 
VC = VCC - ICRC = 15 V – (1.961 mA)(4.3 k) = 6.57 V

VCE = VC – VE = 6.566 V – 1.471 V = 5.09 V
These results compare favorably with the more exact approach used in Examples 7-9 and 7-10.
A summary is provided in Table 7-1. The approximate approach assumes that the base current is
negligibly small, which means DC is effectively very large.
Table 7-1. Voltage Divider Bias Analysis Summary

Quantity DC = 120 DC = 360 Approximate Analysis
IC 1.92 mA 1.95 mA 1.96 mA
VCE 5.30 V 5.16 V 5.09 V
VC 6.73 V 6.62 V 6.57 V
VB 2.14 V 2.16 V 2.17 V
VE 1.44 V 1.46 V 1.47 V
So, What’s All This Stuff About DC Negative Feedback?

As we can see in Fig. 7-32 at point 1, the bleeder current “swamps out” the base current, which
“locks in” the base-to-ground voltage VB. If DC increases, the DC collector current IC will increase
[see point 2 in Fig.7-32]. At point 3 in Fig. 7-32, we note that the increase in IC means the emitter-
to-ground voltage VE will increase since VE  ICRE. Therefore, at point 4 we deduce this reduces
VBE since VBE = VB – VE. The reduction in the forward base-to-emitter bias VBE will reduce IC. The
increase in IC produces a reaction that counters its increase, and this is called DC negative feedback.
DC Negative Feedack at the Emitter

VCC
RC
R1 IC 2 1 The base-to-ground voltage is constant.
I Q1 2 An increase in beta raises the collector current.

1 VB
+
VBE - 3 The emitter-to-ground voltage will increase.
R2 4
RE VE 3
4 This reduces the base-emitter voltage which
reduces the collector current.
Figure 7-32.
Get Your Credit Card?
With this attention to bias stability, it is easy to forget that it is a means to the desired end goal.
The purpose of an amplifier is to operate on a signal. Typically, it should make its input signal
larger without producing distortion. Bias stability represents an important first step to insuring an
imprecise BJT behaves in a more predictable fashion. Bias stability is not a marketable feature.

7-8 JFET and DE-MOSFET Self Bias
The secret to creating a successful bias circuit is to incorporate negative feedback. This is true for
the BJT, and it is also the case for FETs. As we just saw, one source of DC negative feedback in
a BJT bias circuit is via an emitter resistor. The same strategy can be used for FETs by using a
source resistor. This is shown in Fig. 7-33(a). Observe that three resistors are used. The gate is
pulled to ground by the gate resistor RG. This makes VG approximately equal to zero volts.
VG = IGSSRG  0 V (7-23)
The drain current (ID) flows down through the drain resistor RD and the source resistor RS.
(Remember: IS = ID.) The current flow through RS makes the source terminal positive with
respect to ground.
VS = IDRS (7-24)
This results in the gate terminal being negative with respect to the source terminal. Hence, VGS
is a negative voltage. Since a negative VGS is obtained without the use of a separate (negative)
DC supply (e.g., VGG), the circuit is described as self-bias. In Fig. 7-33(b), we see an example in
which VGS is made equal to –3 V.
JFET Self Bias
+
RD ID RD
 Output circuit
VGS = - 3 V
I GSS +
+ VDS + VDD  + VDD
 ID
VGS 3V +
RG = 3 mA
+ + + +
RS 0V RS
 3V
  1 k 
RG
Input circuit
(a) The DC equivalent circuit. (b) An example of self bias.

Figure 7-33.
Now let us develop an equation for VGS. This will be our bias line equation. We apply Kirchhoff's
voltage law around the input circuit indicated in Fig. 7-33(a). We shall start at ground and move
in a clockwise direction.
-IGSSRG + VGS + IDRS = 0
VGS = -IDRS + IGSSRG
We shall assume the gate leakage current IGSS does not produce a significant voltage drop across
the gate resistor RG. This leads us to Eq. 7-25.

VGS  - IDRS (7-25)
We employ our three-step procedure. We analyze the input to obtain the bias line equation (Eq.
7-25). We transfer from the input to the output circuit by superimposing the bias line on the
transfer characteristics. This intersection between the bias line and the transfer curves provides an
indication of the drain current (ID). Once we have ID, we analyze the output circuit. We apply
Kirchhoff's voltage law around the output circuit designated in Fig. 7-33(a). We shall start at
ground and work our way around the circuit in a counter-clockwise direction.
-VDD + IDRD + VDS + IDRS = 0
We solve for VDS and factor out the drain current to arrive at Eq. 7-26.
VDS = VDD – ID(RD + RS) (7-26)
The drain-to-ground voltage VD can be determined by Eq. 7-27.
VD = VDD - IDRD (7-27)
Circuit saturation occurs when VDS is zero volts. Resistor RD and RS serve to limit the maximum
drain current. The drain (circuit) saturation current is defined by Eq. 7-28.
VDD
I D(SAT) = (7-28)
RD + RS
The FET can be thought of as acting like a closed switch when the circuit is saturated. When the
FET is in cutoff, the drain current is zero. The FET acts like an open switch in this case. Since
the drain current is zero, no voltage drops will be developed across RD and RS. Therefore, the
entire drain supply voltage VDD will be dropped across the FET. This is stated by Eq. 7-29.
VDS(OFF) = VDD (7-29)
These circuit relationships should seem rather familiar. They are duplicates of the kinds of
equations we developed for the BJT. The subscripts constitute the only differences.
JFET and DE-MOSFET Self Bias 39

To illustrate the bias analysis, we shall examine the self-bias circuit depicted in Fig. 7-34(a). A
2N5457 n-channel JFET is being used. Capacitors C1 and C2 serve as the input and output coupling
capacitors, respectively. Capacitor C3 is called the source bypass capacitor. It serves the same
function as the emitter bypass capacitor. It prevents AC negative feedback. The DC equivalent
circuit is the same as that given in Fig. 7-34(a).
Example 7-12. Perform a DC analysis of the common-source amplifier shown in Fig. 7-

32(a). Specifically, use a bias line to determine the maximum drain current ID(max) for 2N5457
JFETs that possess a maximum transfer characteristic. Use that result to find the corresponding
values of VG, VS, VD, and VDS. Repeat the analysis if the 2N5457 has the minimum transfer curve.
Solution: We apply Eq. 7-25 to obtain the bias line.
VGS  -IDRS = -3300ID
We plot the bias line as shown in Fig. 7-32(b). We shall pick two arbitrary values of ID in order
to plot the bias line. If ID is selected to be zero, then VGS must also be zero. This places one of
our two bias line points at the origin. If we let ID be equal to 2 mA, the corresponding value of
VGS is determined easily.
VGS  -3300ID = -(3300)(2 mA) = - 6.6 V
The intersection between the bias line and the maximum transfer characteristic gives us the
maximum value for ID [see Fig. 7-34(b)].
ID(max)  1.0 mA
Employing this value of drain current, we complete the analysis by drawing on Eqs. 7-23, 7-24,
and7-26 through 7-27.
VG = 0 V
VS = IDRS = (1 mA)(3.3 k) = 3.3 V
VD = VDD – IDRD = 12 V – (1 mA)(6.8 k) = 5.2 V
VDS = VDD – ID(RD + RS) = 12 V – (1 mA)(6.8 k + 3.3 k) = 1.9 V
The intersection between the bias line and the minimum transfer characteristic in Fig. 7-34(b)
reveals the minimum value for ID.

12
Figure 7-34.
ID(min)  0.10 mA
We duplicate our previous analysis using this minimum value of drain current.
VG = 0 V
VS = IDRS = (0.1 mA)(3.3 k) = 0.33 V
VD = VDD – IDRD = 12 V – (0.1 mA)(6.8 k) = 11.3 V
VDS = VDD – ID(RD + RS) = 12 V – (0.1 mA)(6.8 k + 3.3 k)
= 10.99 V  11.0 V
Although not requested specifically, we shall compute ID(SAT) and VDS(OFF) as a check of our
proximity to these (distortion-producing) boundary points.
VDD 12 V
I D(SAT) = = = 1.188 mA  1.19 mA
RD + RS 6.8 k + 3.3 k
VDS(OFF) = VDD = 12 V
This bias circuit has improved bias stability when compared to the fixed-bias approach. In this
case, a VDS of 11 V is about a volt away from (circuit) cutoff, and a VDS of 1.9 V is almost two
volts away from saturation.
The self-bias circuit can also be used to bias DE-MOSFETs when they are to be used in their
depletion mode of operation. A typical circuit is shown in Fig. 7-35. The analysis of a DE-
MOSFET self-bias circuit is identical to that for the JFET.
JFET and DE-MOSFET Self Bias 41

The DE-MOSFET Self-Bias Circuit
ID
The analysis is Identical to that for the JFET self-bias circuit.
V DD
Bias Line:
RD
C2 V GS = -R I
S D
Q1
+
rs C1 +
+ + v OUT
vs
+
vIN RG +
RS C3 I D(max)
-
- ID(min)
- 0
VGS
Figure 7-35.
7-9 FET Voltage-Divider Bias
The voltage-divider bias circuit can be applied to JFETs, DE-MOSFETs, and even E-MOSFETs.
In the case of the MOSFETs, it can be used to establish either the depletion- or enhancement-mode
of operation. (Remember that JFETs are not typically biased in the enhancement mode of
operation. This restriction is made to avoid causing conduction in the p-n junction between the
gate and channel. Gate current flow is a bad thing.) A JFET voltage-divider bias circuit is
illustrated in Fig. 7-36(a). A common-source amplifier is indicated. To simplify the gate circuit,
we apply Thevenin’s theorem to the DC equivalent circuit as noted in Fig. 7-36(b). The
relationships given by Eqs. 7-30 and 7-31 are identical to those developed for BJT voltage-divider
bias. The basis for these equations is indicated in Fig. 7-36(c).
R2
VTH = V DD (7-30)
R1 + R2
R1 R2 (7-31)
RTH =
R1 + R2

DC
(c) (d)
Figure 7-36.
The simplified gate circuit is depicted in Fig. 7-36(d). We apply Kirchhoff's voltage law around
the gate circuit to obtain our (bias line) equation for VGS. We start at ground and proceed in a
clockwise direction.
-VTH – IGSSRTH + VGS + IDRS =0
VGS = VTH + IGSSRTH – IDRS
Since the gate leakage current is so small, we shall assume the voltage drop across RTH is negligibly
small. This takes us to Eq. 7-32.
VGS  VTH – IDRS (7-32)
FET Voltage-Divider Bias 43

To plot the bias line defined by Eq. 7-32, we pick two convenient points. If we let ID be equal to
zero in Eq. 7-32, we obtain a positive value of VGS that is equal to VTH. This is given by Eq. 7-33.
(The vertical bar is read “with the condition that”. It is mathematical short-hand notation.)
VGS  VTH I D =0 (7-33)
In the case of the n-channel JFET, the value resulting positive value of VGS will place the bias line
in the first quadrant as shown in Fig. 7-37(a). If this is not convenient, any two arbitrary points
may be used. Equation 7-34 indicates the case where VGS is set to zero. (It is important to
understand the distinction; we are plotting the bias line and not defining the operation of the FET.)
VTH – IDRS  VGS
VTH – IDRS  0
– IDRS  -VTH
VTH
ID  (7-34)
RS VGS = 0
The Bias Line for Voltage-Divider Bias

V DD
ID
12 V
5 mA
Bias Line :
4 mA
VGS = VTH - ID R S R1 RD
= 2.975 V - 6200 ID 910 k 3.3 k
3 mA
The ve nize
2 mA ID(max) Q1
= 1.0 mA 2N5457
ID(min) R2
RS
= 0.50 mA 300 k
6.2 k
VGS
6V 5V 4V 3V 2V 1V 0 1V 2V 3V
-3.3 V VTH
2.975 V
V DD (b)
(a)
12 V
RD
Q1 3.3 k
2N5457
RTH
225.6 k ID
+
+ V GS
-
V TH + RS
2.975 V 6.2 k
-
(c)
Figure 7-37.
In general, we may select any value of ID, substitute it into our bias line equation (Eq. 7-32), and
then calculate the corresponding value of VGS. The bias line is plotted on the transfer characteristic
curves as shown in Fig. 7-37(a). The intersections between the bias line and the transfer
characteristics give us the expected minimum and maximum values of drain current. Once we
have determined the drain current, we proceed with the analysis of the circuit. Refer to the DC
equivalent circuit provided in Fig. 7-36(b) or the simplified version given in Fig. 7-36(d).
The gate-to-ground voltage VG is equal to VTH as stated by Eq. 7-35.
R2
VG = VTH = VDD (7-35)
R1 + R2
The drain-to-ground voltage VD, and the source-to-ground voltage VS are defined by Eqs. 7-36 and
7-37, respectively.
VS = IDRS (7-37)
The drain-to-source voltage can be found by subtracting VS from VD. Alternatively, we can apply
Kirchhoff's voltage law around the output circuit and solve for VDS directly. Either approach will
provide us with the correct relationship. Both are stated in Eq. 7-38.
VDS = VD – VS = VDD – ID(RD + RS) (7-38)
Circuit saturation and cutoff are given by Eqs. 7-39 and 7-40, respectively. They are identical to
the relationships defined for the self-bias circuit.
VDD
I D ( SAT ) = (7-39)
RD + RS
VDS(OFF) = VDD (7-40)

Figure 7-38.
Example 7-13. Perform a DC analysis of the common-source amplifier shown in Fig. 7-38.
Specifically, use a bias line to determine the maximum drain current ID(max) for 2N5457 JFETs
that possess a maximum transfer characteristic. Use that result to find the corresponding values
of VG, VS, VD, and VDS. Repeat the analysis if the 2N5457 has the minimum transfer curve. Also
determine ID(SAT) and VDS(OFF).
Solution: We apply Thevenin’s theorem as indicated in Fig. 7-37(b). We determine VTH and
RTH by employing Eqs. 7-30, and 7-31. (Recall from Eq. 7-35 that VG is equal to VTH.)
R2 300 k
VG = VTH = VDD = (12 V) = 2.975 V
R1 + R2 910 k + 300 k
R1R2 (910 k)(300 k)

RTH = = = 225.6 k
R1 + R2 910 k + 300 k
The Thevenin equivalent circuit is depicted in Fig. 7-37(c). Next, we plot the bias line on the
transfer characteristics. Equations 7-33 and 7-34 provide us with convenient points to plot the
bias line.
VGS  VTH I D =0
= 2.975 V
This point lies on the horizontal axis (where ID = 0) as shown in Fig. 7-34.
VTH 2.975 V
ID  = = 0.480 mA
RS VGS = 0
6.2 k

This is the point where the bias line crosses the vertical axis (where VGS = 0) as shown in Fig. 7-
37(a). If either of these two points is inconvenient, we can arbitrarily select a value of ID and use
the bias line equation (Eq. 7-30) to determine the corresponding value for VGS. For instance, let
ID = 1 mA.
VGS  VTH –RS ID = 2.975 V – (1 mA)(6.2 k) = -3.23 V
This point lines on the bias line given in Fig. 7-37(a). Reading the graph carefully, we determine
the maximum and minimum values of drain current. We analyze the circuit first using the
maximum drain current ID(max) = 1 mA.
VD = VDD - IDRD = 12 V – (1 mA)(3.3 k) = 8.7 V

VS = IDRS = (1 mA)(6.2 k) = 6.2 V
VDS = VD – VS = 8.7 V – 6.2 V = 2.5 V
The analysis of the circuit using the minimum drain current ID = ID(min) = 0.5 mA is similar.
VD = VDD - IDRD = 12 V – (0.5 mA)(3.3 k) = 10.4 V

VS = IDRS = (0.5 mA)(6.2 k) = 3.1 V
VDS = VD – VS = 10.4 V – 3.1 V = 7.3 V
We conclude our analysis by finding ID(SAT) and VDS(OFF).
VDD 12 V
I D ( SAT ) = = = 1.3 mA
RD + RS 3.3 k + 6.2 k
VDS(OFF) = VDD = 12 V
The voltage-divider bias circuit has resulted in a much more stable (0.5 to 1.0 mA) drain current.
In contrast, the self-bias circuit yielded a drain current that can range from 0.1 to 1.0 mA.
A DE-MOSFET can be biased into either its depletion- or enhancement-mode of operation. A

voltage-divider bias circuit and the corresponding bias line are provided in Fig. 7-39. Observe that
the bias line intersects the transfer characteristics in the first quadrant when the DE-MOSFET is
being used in its enhancement mode of operation.

The DE-MOSFET Voltage-Divider Bias Circuit
Depletion- and enhancement-modes of operation are possible. ID
V DD
Enhance me nt Bias Line
Bias Line :
R1 RD
V GS = VTH - I D R S
C2
Q1
+ +
rs C1
Depletion Bias Line
+ v OUT
+
vs
+
v IN R2 +
C3
- RS
-
-
0 VGS
Figure 7-39.
7-10 BJT Emitter Bias

When a dual-polarity DC power supply is available, it becomes possible to use the emitter bias
circuit. The emitter bias circuit is shown in Fig. 7-40. The resistor values are like those used in
the voltage-divider bias circuit given in Fig. 7-38. Specifically, resistor R1 has been removed,
resistor R2 is now called the base resistor RB, and the collector resistor RC is unchanged. The
emitter resistor RE has been increased by an order of magnitude from 750  to 7.5 k and is now
tied to the negative terminal of the 15-V emitter supply (VEE).
The Emitter Bias Circuit
VCC
15 V
RC
4.3 k 
Q1
2N4124
RB RE
2.2 k  7.5 k
-VEE
-15 V
Figure 7-40.
The analysis of the emitter bias circuit is almost identical to the approach we used to analyze the
BJT voltage-divider bias circuit. It is detailed in Fig. 7-41(a). We write a Kirchhoff's voltage law
equation around the input side, approximate IE using IC, and eliminate IC using IC = DCIB.

IBRB + 0.7 V + IERE – VEE = 0
I B RB + 0.7 V + I C RE − VEE  0
IBRB + 0.7 V + DCIBRE – VEE  0

IB (RB + DCRE)  VEE - 0.7 V
V EE − 0.7 V
IB  (7-41)
R B + β DC R E
Compare this result with Eqs. 7-6 and 7-13. The forms are identical.
Emitter Bias Analysis
+ IC
RC RC
_
IB
+
VCE
_ + _
0.7 V_ VCC + VCC
+ + +
RB
RE IE ~
= IC RB
RE IE ~
= IC
_ _
+
VEE VEE
+ +
Input Output
(a) (b)
Figure 7-41.
Next, we write a Kirchhoff's voltage law equation around the output circuit as indicated in Fig. 7-
41(b) and solve for VCE. We start at the negative terminal of the collector supply VCC and work
our way around the output circuit in the direction of IC.
-VCC + ICRC + VCE + ICRE – VEE  0
Note that we have assumed IE  IC through RE in the Kirchhoff's voltage law equation. Solving
for VCE leads us to Eq. 7-42.
VCE  VCC + VEE – (RC + RE)IC (7-42)
The fact that we have assumed that IE  IC suggests the base current IB is negligibly small. In
keeping with that assumption, we shall assume the voltage drop across resistor RB is approximately
zero. (In reality, the BJT’s base terminal will be slightly negative with respect to ground.)
BJT Emitter Bias 49

VB  0 V (7-43)
Since the base terminal is zero volts with respect to ground, the emitter must be –0.7 V with
respect to ground. This is true because the base is 0.7 V more positive than the emitter terminal.
This is depicted in Fig. 7-42.
VE  -0.7 V (7-44)
Base and Emitter Voltages

VB ~
= 0V
RC VB = 0 V RC
IB ~
= 0A
RB
_
~
+
0.7 V_ + VCC ~
=
+
0.7 V_
VE = _ 0.7 V
+ VCC
= 0V RE RE
+
VEE VEE
+ +
Figure 7-42.
The collector-to-ground voltage is the collector supply voltage VCC minus the voltage drop across
the collector resistor.
To examine the behavior of the emitter bias circuit, you should study Examples 7-14 and 7-15.
from 120 to 360. Determine IC and VCE if a 2N4124 with a DC of 120 is used. Also, find VE, VB,
and VC.
Solution: We find the base current by using Eq. 7-41.
V EE − 0.7 V 15 V - 0.7 V
IB  = = 15.85 A
R B + β DC R E 2.2 k + (120)(7.5 k)

Figure 7-43.
Next, we find the collector current and the collector-emitter voltage VCE (which is given by Eq.
7-42).
IC = DCIB = (120)(15.85 A) = 1.902 mA

VCE  VCC + VEE − I C(RC + RE ) = 15 V + 15 V - (1.902 mA)(4.3 k + 7.5 k) = 7.56 V
We conclude our analysis by finding VB, VE, and VC using Eqs. 7-41 through 7-43, respectively.
VB  0V
VE  -0.7 V
VC = VCC - ICRC = 15 V – (1.902 mA)(4.3 k) = 6.82 V
from 120 to 360. Determine IC and VCE if a 2N4124 with a DC of 360 is used. Also, find VE, VB,
and VC.
Solution: We find the base current by using Eq. 7-39.
V EE − 0.7 V 15 V - 0.7 V
IB  = = 5.292 A
R B + β DC R E 2.2 k + (360)(7.5 k)
Next, we find IC and then the collector-emitter voltage VCE. The collector-emitter voltage is
given by Eq. 7-40.
IC = DCIB = (360)(5.292 A) = 1.905 mA

VCE  VCC + VEE − I C(RC + RE ) = 15 V + 15 V - (1.905 mA)(4.3 k + 7.5 k) = 7.52 V
BJT Emitter Bias 51

We conclude our analysis by finding VB, VE, and VC using Eqs. 7-43 through 7-45, respectively.
VB  0V
VE  -0.7 V
VC = VCC - ICRC = 15 V – (1.905 mA)(4.3 k) = 6.81 V
This circuit laughs at DC variations. The collector current only changes from 1.902 to 1.905 mA!
Applying approximations here certainly presents no problems.
Emitter Bias Approximations

We have already approximated IB as zero, VB as zero, and VE as –0.7 V. The tightly-controlled
collector current may also be approximated. Refer to Fig. 7-44. We apply Kirchhoff's voltage law
to the simplified base-emitter circuit. We start at the BJT’s base terminal and work around the
base-emitter circuit in a clockwise direction.
0.7 V + IERE – VEE = 0
If we approximate the emitter current IE with the collector current, we can then solve the
resulting Kirchhoff's voltage law equation for IC.
0.7 V + ICRE – VEE  0
VEE − 0.7 V
IC  (7-46)
RE
Collector Current Approximation

VB ~
= 0V
RC VB = 0 V RC
IB ~
= 0A
RB
_
~
+
0.7 V_ + VCC ~
=
+
0.7 V_
+ + VCC
= 0V RE RE
_ IE ~
= IC
+
VEE VEE VEE − 0.7 V

IC 
+ + RE
Figure 7-44.

Example 7-16. The npn BJT in Fig. 7-43 is a 2N4124 silicon unit. Use Eq. 7-46 to
approximate the BJT’s collector current.
Solution: We find the collector current by using Eq. 7-46.
VEE − 0.7 V 15 V - 0.7 V

IC  = = 1.907 mA
RE 7.5 k
This result compares favorably with our more accurate (1.902 to 1.905 mA) prediction of the
collector current. Obviously, the approximation simplifies our calculations significantly.
7-11 FET Constant-Current Source Biasing: Escaping the

Graph Attack!
We have been using bias lines to avoid cumbersome (scary) analytical methods. Graphical
techniques offer insight and understanding into circuit operation. However, they require careful
plotting, and a concerted effort to be neat. Accuracy is directly affected by the amount of care
used in obtaining the solution. These facts trouble engineers, technicians, and even the most
dedicated students. The bias circuit approach depicted in Fig. 7-45 offers freedom from graphs,
and superior bias stability.
To gain even more control over the drain current, we invoke fundamental principles. If we want
the current through the FET to be fixed, place a constant-current source in series with it. This is
illustrated in Fig. 7-45(a). The circuit is described (appropriately) as constant-current source
bias. The BJT makes an excellent constant-current source. The use of a BJT with a dual-polarity
power supply is indicated in Fig. 7-45(b). Emitter bias is being used to establish the BJT’s
collector current. Although two active devices are used in this approach, its simplicity and
outstanding performance warrant serious consideration. (To satisfy the curious, we should point
out the bias line will be horizontal as shown in Fig. 7-46.)
BJT Emitter Bias 53

Constant-Current Source FET Bias
Making the FET behave
V DD V DD
12 V
RD
RD I D = I S = I SOURCE 6.2 k
C2
Q1
C1 +
Q1 +
+ + 2N5457
RG rL v
IS v IN LOAD
RG +
- 470 k C3
-
I SOURCE Q2
2N3904
RE
The constant-current source 12 k
in series with the JFET -VEE
establishes the drain current. -12 V
(a) The basic approach. (b) A common-source amplifier circuit.
Figure 7-45.
In Fig. 7-47(a), we have the DC equivalent circuit. The BJT’s emitter current is determined first.
VEE − 0.7 V
IE = (7-45)
RE
Constant-Current Source FET Bias Line

ID
5 mA
4 mA
3 mA
Bias Line
2 mA I D(max) = ID(min) = 0.942 mA
VGS
6V 5V 4V 3V 2V 1V 0
Figure 7-46.

Since the BJT is in series with the JFET, we arrive at the relationships provided by Eq. 7-46.
ID = IS = IC  IE (7-46)
We determine the FET and BJT terminal-to-ground voltages next. Refer to Fig. 7-47(a).
VG = IGSSRG  0 V (7-47)

VB = 0 V (7-49)
VE = -0.7 V (7-50)
Constant-Current Source FET Bias DC Analysis

V DD
+
RD ID
VG = IGSS R G  0 V _
Q1 VD = VDD - IDR D
I GSS
+ IS = IC  IE
RG
_
Q2
+
0.7 V _
VB = 0 V
VE = - 0.7 V
+
RE IE
_
-VEE
(a)
Figure 7-47.
FET Constant-Current Source Biasing: Escaping the Graph Attack! 55

Constant-Current Source FET Bias DC Analysis
V DD
RD
Q1
This v oltage must satisfy
_ the JFET AND the BJT!
+ 1V
+
RG 0V VC = 1 V
_
Q2
+
1.7 V
+
0.7 V _ _
VE = - 0.7 V
RE
-VEE
(b)

The FET’s source-to-ground voltage VS, and the BJT’s collector-to-ground voltage VC are the
same. Understanding how this voltage is established is central to understanding the operation
of the constant-current-source bias circuit. For the JFET to have a given drain current, it must
have the necessary gate-to-source voltage. The operation of the JFET is governed by its square-
law equation. Since the gate is pulled to ground via the gate resistor RG, a negative VGS requires a
positive source-to-ground voltage. For a BJT to act like a constant-current source, it must remain
in its active region. A (silicon) BJT will begin to enter saturation when its VCE goes below about
0.7 V.
Typical values are indicated in Fig. 7-47(b). The gate-to-ground voltage is zero. However, since
the source-to-ground voltage is one volt, this makes the gate negative one volt with respect to its
source terminal. The BJT’s emitter-to-ground voltage is –0.7 V. Since its collector is one volt
with respect to ground, its collector-to-emitter voltage is 1.7 V.
We can verify proper operation of the JFET and the BJT by determining the FET’s required VGS.
This requires using a little algebra on its transfer equation. The square-law equation is written to
place VGS on the left side.
2
 VGS 
I DSS 1 −  = ID
 VGS(OFF) 
We divide both sides by IDSS.

2
 VGS  I
1 −  = D
 VGS(OFF)  I DSS
Next, we take the square root of both sides, and subtract 1 from both sides.

VGS ID
1− =
VGS(OFF) I DSS
VGS ID
− = −1
VGS(OFF) I DSS
We multiply both sides by –VGS(OFF) to obtain Eq. 7-51.

 ID 
VGS = −VGS(OFF) − 1
 I DSS 
 ID 
VGS = VGS(OFF)1 −  (7-51)
 I DSS 
Once we know VGS, the source-to-ground voltage VS, and the collector-to-ground voltage VC are
determined easily.
VC = VS = -VGS (7-52)
Example 7-17. Perform a DC analysis of the common-source amplifier shown in Fig. 7-48.
Find IE, IC, IS, ID, VG, VB, VD, VE, VGS, VC, and VS. Assume the 2N5457 has the minimum values
IDSS(min) = 1 mA, and VGS(OFF-min) = -0.5 V. Repeat the analysis for a 2N5457 with the maximum
values IDSS(max) = 5 mA and VGS(OFF-max) = -6 V.
Solution: We apply Eqs. 7-45 and 7-46 initially. (We get one heck of a lot of information from
this relatively simple calculation.)
VEE − 0.7 V 12 V - 0.7 V
I D = I S = IC  I E = = = 0.9417 mA  0.942 mA
RE 12 k
The gate-to-ground voltage VG and the base-to-ground voltage VB are both equal to zero.
VG = VB = 0 V
We use Eq. 7-48 to find VD.
VD = VDD – IDRD = 12 V – (0.9417 mA)(6.2 k) = 6.162 V  6.16 V
The only quantities that are affected by the JFET’s parameters are VGS, VC, and VS. We use the
minimum set of parameters first. VGS is obtained from Eq. 7-51.
 ID   0.9417 mA 
VGS = VGS(OFF-m in ) 1 −  = (−0.5 V) 1 -  = −14.80 mV  -0.0148V
 I DSS( m in )   1 mA 
FET Constant-Current Source Biasing: Escaping the Graph Attack! 57

Since we are operating so close to IDSS, it is reasonable to expect a VGS that is nearly zero. We
continue our analysis to find VC and VS.
VC = VS = -VGS = -(-0.01480 V)  0.0148 V
The BJT is close to saturation since its VCE is approaching 0.7 V. However, the circuit should
operate properly.
VCE = VC – VE = 0.01480 V – (-0.7 V)  0.715 V
Now we consider 2N5457 JFETs that possess the maximum parameters.
 ID   0.9417 mA 
VGS = VGS(OFF-m ax ) 1 −  = (−6 V) 1 -  = −3.396 V  -3.40V
 I DSS( m ax )   5 mA 
VC = VS = -VGS = -(-3.396 V)  3.40 V

The BJT is further away from saturation in this instance.
VCE = VC – VE = 3.396 V – (-0.7 V)  4.10 V
We are finished, and with not a single graph in sight! This circuit is nice to have in our “bag of
tricks”.
Figure 7-48.

7-12 BJT Temperature Compensation
As the temperature of a BJT is raised, its DC and leakage current (ICEO) tend to increase. Equation
7-53 shows us the collector current must also increase with temperature.
IC = DCIB + ICEO (7-53)
A BJT’s transfer characteristic curve is also affected by temperature as depicted in Fig. 7-49.
Specifically, as a BJT’s temperature is raised, the base-emitter (forward-bias) voltage required to
produce a given collector current decreases. This is very similar to the effects of temperature on
a forward-biased diode.
The Effect of Temperature on a BJT's Transfer Characteristic Curve
(The base-emitter voltage decreases 2 mV
for each one degree Celsius rise in temperature.)
IC
(mA)
45 o C
o
Less VBE is required to produce 35 C
a given collector current as the 25 oC
temperature increases.
VBE(volts)
0
0.66 0.68 0.70
Figure 7-49.
Bias stabilization circuits employ DC negative feedback exclusively to control the collector
current. Another approach to controlling the collector current is described as temperature
compensation. Temperature compensation circuits employ temperature-sensitive devices to
measure the BJT’s temperature and adjust the bias accordingly. Temperature compensation can
be used to enhance the bias stability of circuits that also include DC negative feedback. This is
the case in Fig. 7-50(a), we see a forward-biased diode that is being used to provide temperature
compensation. In the same fashion as shown in Fig. 7-49, the forward voltage drop across a diode
has a negative temperature coefficient. Consequently, the base-to-ground voltage will be reduced
automatically as the diode’s temperature is raised. Ideally, the diode’s temperature should track
the BJT’s temperature. Let’s see how temperature compensation works.
BJT Temperature Compensation 59

3.3
Figure 7-50.
In Fig. 7-50(b) the collector supply VCC connection to the bias circuit is shown. The forward-
biased diode is replaced with its knee-voltage model in Fig. 7-50(c). We find the base-to-ground
voltage VB by using the principle of superposition. The diode’s knee-voltage source is set to zero
(replaced by a short circuit) in Fig. 7-50(d). The component of the base-to-ground voltage
produced by VCC acting alone is called VB. It is equal to the voltage across resistor R2 and is given
by simple voltage division. The collector supply VCC is set to zero in Fig. 7-50(e). The component
of VB produced by the diode’s knee-voltage source acting alone is called VB. It is equal to the
voltage drop across resistor R1. The algebraic sum of the two components yields VB as indicated
in Fig. 7-50.
R2 R1
VB = VCC + VD (7-54)
R1 + R2 R1 + R2

Example 7-18. The 1N4148 diode in Fig. 7-50(a) is a silicon unit. Use Eq. 7-54 to
determine the BJT’s base-to-ground voltage VB. Also find VE, IC, VC and VCE. Assume the
circuit is operating at 25oC.
Solution: We find VB by using Eq. 7-54 and assuming the voltage across the silicon diode
(VD) is equal to 0.7 V.
R2 R1 2.2 k 13 k
VB = VCC + VD = (15 V) + (0.7 V)
R1 + R2 R1 + R2 13 k + 2.2 k 13 k + 2.2 k
= 2.171 V + 0.599 V = 2.77 V
We know from our previous work the emitter-to-ground voltage (VE) is one diode drop (e.g., 0.7
V) less than VB.
𝑉𝐸 = 𝑉𝐵 − 0.7 𝑉 = 2.77 V − 0.7 V = 2.07 V
The emitter-to-ground voltage is the voltage a across the emitter resistor. We use Ohm’s law to
find the emitter current (IE) and use it to approximate the collector current (IC).
𝑉𝐸 2.07 𝑉
𝐼𝐶 ≅ 𝐼𝐸 = = = 2.76 mA
𝑅𝐸 750 Ω
Now the collector-to-ground voltage (VC) can be determined.
𝑉𝐶 = 𝑉𝐶𝐶 − 𝐼𝐶 𝑅𝐶 = 15 V − (2.76 mA)(3.3 kΩ) = 5.89 V
The collector-to-emitter voltage (VCE) should be computed to make sure the BJT is in its active
region. Recall that if VCE is less than one diode voltage drop, the transistor is in saturation and
the circuit will not function properly.
𝑉𝐶𝐸 = 𝑉𝐶 − 𝑉𝐸 = 5.89 V − 2.07 V = 3.82 V
These results look reasonable.
If the ambient temperature experienced by the BJT and the diode is increased, the required base-
emitter forward bias will decrease. Simultaneously, the forward bias supplied by the biasing
network (which includes the diode) will decrease. The emitter resistor also provides DC negative
feedback. The overall bias circuit performance will be improved significantly.
BJT Temperature Compensation 61

7-13 Biasing PNP BJTs
The pnp BJT is the complement of the npn BJT. From a circuit standpoint, this means its voltage
polarities, and current directions are reversed from those of an npn BJT. This be accomplished by
using a negative collector supply as shown in Fig. 7-51(a). Alternatively, a positive supply may
be used, and the pnp BJT is installed upside down as illustrated in Fig. 7-51(b).
-VCC PNP Biasing VCC

-15 V 15 V
R1 RC R1 RE
IC 7.5 k  2 k 1.3 k
13 k
VC VE
Q1 Q1
VB VB
2N3906 2N3906
VE VC
R2 RE R2
IC RC
2 k 1.3 k 13 k 7.5 k 
(a) (b)
Figure 7-51.
Example 7-19. Using approximations, determine VB, VE, IC, and VC for the 2N3906 silicon
pnp BJT circuit given in Fig. 7-51(a).
Solution: We find VB by voltage division.

R2 2 k
VB = VCC = (−15 V) = -2V
R1 + R2 13 k + 2 k
Since the BJT is a silicon device, we assume the emitter is 0.7 V more positive than the base.
VE = VB + 0.7 V = -2 V + 0.7 V = -1.3 V
Now we can find the emitter current as an approximation of the collector current. Note in Fig. 7-
51(a) that the emitter current flows up through resistor RE. This means the voltage drop across
RE is –VE.
− VE − (−1.3 V)
IC  I E = = = 1 mA
RE 1.3 k
We finish the problem by finding VC.
VC = -VCC + ICRC = -15 V + (1mA)(7.5 k) = -7.5 V

The analysis is virtually identical to the analysis of an npn BJT circuit. The only difference is
the signs are reversed. However, the collector current remains positive because its direction is
defined to be opposite to that of an npn BJT.
Example 7-20. Using approximations, determine VB, VE, IC, and VC for the 2N3906 silicon
pnp BJT circuit given in Fig. 7-51(b).
Solution: We find VB by voltage division. Note that the base-to-ground voltage is across
resistor R1 not R2. The DC supply is still called “VCC” although it should be called “VEE”. This
was done on purpose because in many systems both pnp and npn BJTs will be used. Convention
favors the (more popular) npn BJTs.
R2 13 k
VB = VCC = (15 V) = 13V
R1 + R2 2 k + 13 k
Since the BJT is a silicon device, we assume the emitter is 0.7 V more positive than the base.
VE = VB + 0.7 V = 13 V + 0.7 V = 13.7 V
Now we can find the emitter current as an approximation of the collector current. Note in Fig. 7-
51(b) that the emitter current flows down through resistor RE. It is also important to realize the
voltage drop across RE is the difference between VCC and VE.
VCC -VE 15 V - 13.7 V)

IC  I E = = = 1 mA
RE 1.3 k
We finish the problem by finding VC. In this case VC is simply the voltage drop across the
collector resistor RC.
VC = ICRC = (1mA)(7.5 k) = 7.5 V
7-14 Using EDA to Analyze Bias Circuits

Electronic Design Automation (EDA) can be used to examine the affects of temperature. We are
going to use Multisim to analyze the temperature-compensated provided in Fig. 7-50(a). It has
been drawn in Multisim as shown in Figure 7-52. Our goal here is to sweep the temperature and
observe the affects. Multisim incorporates non-linear models for the diode and the BJT and this
would be challenging non-linear circuit problem if we were to attempt solve it by hand.11
11 The default room temperature for Multisim is 27oC rather than the customary 25oC. This because the Kelvin absolute
temperature is used for calculations. If we convert 27oC to (degrees) kelvin we use T(K) = T(oC) + 273 = 27 + 273 = 300 K.
This made a great deal of sense in the ancient days of slide rules my children. Also notice there is no degree indication on
kelvin degrees. Specifically, 300 K is proper while 300 oK is not correct. This goes back to the ancient days of typewriters.
Using EDA to Analyze Bias Circuits 63

Figure 7-52.
To place the transistor, we click on Place and then select Component. Make the Group
Transistors and select the BJT_NPN Family as shown in Fig. 7-53(a). To place the diode, make
the Group Diodes and select the SWITCHING DIODE Family as shown in Fig. 7-53(b).
Connect the multimeters as shown in Fig. 7-52. Click on the green arrow to run the simulation
and voltage measurements provided in Fig. 7-52 should appear. They have been labeled VB, VD,
VC, and VE as indicated. This accomplished clicking on Place and selecting Text.
The circuit was analyzed in Example 7-18. Let’s compare the results. First, the diode voltage is
closer to 0.6 V instead of 0.7 V. The diode voltage we used is about 17% higher. The base-to-
ground voltage is 2.649 V. It was calculated to be 2.77 V which is only about 5% higher. Multisim
indicates the emitter-ground voltage is 1.959 V. It was calculated to be 2.07 V in Example 7-18.
The calculation was about 6% higher. This means the collector current approximation will also
be a little higher than the Multisim result. Multisim yielded a collector-to-ground voltage of 6.437
V value. It was calculated to be 5.89 V which is about 9% lower. The Example 7-18 results
agree favorably with the simulation.

(a)
(b)
Figure 7-53.
To run a temperature sweep, go to the top toolbar and click on the Simulate tab and then select
the Analyses and Simulate choice. Next pick Temperature Sweep. The sweep will be setup to
run from -20oC (-4oF) to 85oC (185oF) in one step of 105oC. This is the industrial temperature
rang.12 . Refer to Fig. 7-54.
Under Analysis to sweep chose DC Operating Point. Check the radio dial Display Results in a
Table.
12 The commercial, industrial, and military temperature ranges are 0 oC to 45oC, -20oC to 85oC, and -55oC to 125oC, respectively.

Figure 7-54.
Click on the Output tab of the Temperature Sweep. You will see list of variables as indicated in
Fig. 7-55. Select the collector current I(Q1[IC]) and then Add. It will then appear on the right
side.
Figure 7-55.
Click on the green (Run) arrow to run the simulation. The results are shown in Fig. 7-56.

Figure 7-56.
At -20oC the collector current is about 2.58 mA and at 85oC it is approximately 2.61 mA. This a
variation of only 0.03 mA. Just to see if the temperature compensation is working, we replace the
diode with a DC voltage source set to the diode’s room temperature voltage. Everything will be
the same except the “diode” voltage will remain constant. The circuit and simulation results are
provided in Fig. 7-57.
Figure 7-57.
The collector current change with temperature runs from about 2.48 mA to roughly 2.73 mA. This
is a change of 0.25 mA. Compared to the actual circuit this is an increase of 83%! The temperature
compensation performs well.

Problems for Chapter 7
Drill Problems
Section 7-1
7-1. What are the two general performance goals for a bias circuit design?
7-2. The BJT in Fig. 7-1 has its VCC increased to 20 V and has an IC(SAT) of 4 mA. Determine
the requisite values for VCE and IC to achieve a maximum symmetrical output voltage
swing. Calculate the ideal value should be used for RC.
7-3. The BJT in Fig. 7-1 has its VCC decreased to 12 V and has an IC(SAT) of 1 mA. Determine
the requisite values for VCE and IC to achieve a maximum symmetrical output voltage
swing. Calculate the ideal value should be used for RC.
7-4. A BJT common-emitter amplifier exhibits clipping on the positive half-cycles of its
output voltage. This means the BJT’s operating point is entering the _____________
(active, saturation, or cutoff) region of operation.
7-5. A BJT common-emitter amplifier exhibits clipping on the negative half-cycles of its
output voltage. This means the BJT’s operating point is entering the _____________
(active, saturation, or cutoff) region of operation.
7-6. The FET in Fig. 7-3 has its VDD increased to 25 V and has an ID(SAT) of 10 mA.
Determine the requisite values for VDS and ID to achieve a maximum symmetrical output
voltage swing. Calculate the ideal value should be used for RD.
7-7. The FET in Fig. 7-3 has its VDD decreased to 6 V and has an ID(SAT) of 15 mA. Determine
the requisite values for VDS and ID to achieve a maximum symmetrical output voltage
swing. Calculate the ideal value should be used for RD.
7-8. An FET common-source amplifier exhibits clipping on the positive half-cycles of its
output voltage. This means the FET’s operating point is entering the _____________
(pinch-off, circuit saturation, or circuit cutoff) region of operation.
7-9. An FET common-source amplifier exhibits clipping on the negative half-cycles of its
output voltage. This means the FET’s operating point is entering the _____________
(pinch-off, circuit saturation, or circuit cutoff) region of operation.
Section 7-2
7-10. The voltage rating VCEO is the maximum collector-to-emitter voltage as measured with
the base terminal open. Using the data sheet provided in Fig. 7-4, what happens if VCE
exceeds 40 V.
7-11. The voltage rating VEBO is the maximum emitter-to-base voltage as measured with the
collector terminal open. The data sheet provided in Fig. 7-4, indicates the VEBO rating is
6.0 V. Is this a forward or reverse bias? Explain your answer briefly.
7-12. The current gain (DC) _________________ (increases, decreases, remains the same) at
high values of collector current.

7-13. The current gain (DC) _________________ (increases, decreases, remains the same) as a
BJT’s temperature is raised.
7-14. A BJT’s base-emitter voltage _________________ (increases, decreases, remains the
same) as the BJT’s temperature is raised.
7-15. A BJT’s leakage current _________________ (increases, decreases, remains the same) as
the BJT’s temperature is raised.
To minimize your aggravation, it is recommended that you generate and graph carefully the minimum
and maximum transfer characteristics for the 2N5458 JFET. Photocopy your graph so that you can use
copies to solve multiple problems, without taking the chance of ruining your original. The vertical (I D)
scale should run from 0 to 10 mA. The horizontal (VGS) scale should extend from –8 to 0 V. An example
that was generated using Excel is provided in Fig. 7-58.
Figure 7-58.
7-16. Using the data sheet provided in Fig. 7-7, determine the minimum and maximum values
of IDSS and VGS(OFF) for the 2N5458 n-channel JFET. Use Eqs. 7-1 and 7-2 to graph the
minimum and maximum transfer curves. Show some sample calculations. Your graph
should comply with the suggestions given above. You may use any graphing program to
achieve this, but Excel is recommended.
7-17. In general, at low values of drain current, the drain current exhibits a
_________________ (positive, negative) temperature coefficient.

7-18. In general, at high values of drain current, the drain current exhibits a
_________________ (positive, negative) temperature coefficient.
7-19. The gate reverse leakage current for a JFET is designated IGSS and exhibits a
________________ (positive, negative) temperature coefficient.
Section 7-3
7-20. The npn BJT in Fig. 7-59(a) has a DC that ranges from 100 to 300. Determine IB, IC, and
VCE if the BJT has the minimum DC. Repeat the analysis if the BJT has the maximum
DC.
7-21. The npn BJT in Fig. 7-59(b) has a DC that ranges from 50 to 200. Determine IB, IC, and
DC.
Figure 7-59.
7-22. The npn BJT in Fig. 7-59(b) has a DC that ranges from 50 to 200. The collector resistor
RC has been increased to 1.5 k. Determine IB, IC, and VCE if the BJT has the minimum
DC. Repeat the analysis if the BJT has the maximum DC. Is there a problem? Explain.
7-23. What is meant by the term DC negative feedback?
Section 7-4
7-24. The fixed gate bias circuit in Fig. 7-60(a) employs a 2N5458 n-channel JFET. Turn to
Fig. 7-7 to obtain its minimum and maximum values for VGS(OFF) and IDSS. Graph its
minimum and maximum transfer characteristics on graph paper. You may use a copy the
curves developed for Prob. 7-16. Write the bias line equation and place it on your graph
of the transfer characteristics. Determine ID(min) and ID(max) and the corresponding values
of VDS.

7-25. The fixed gate bias circuit in Fig. 7-60(b) employs a 2N5458 n-channel JFET. Turn to
curves developed for Prob. 7-16. Write the bias line equation and place it on your graph
of the transfer characteristics. Determine ID(min) and ID(max) and the corresponding values
of VDS.
Figure 7-60.
Section 7-5
7-26. The npn BJT in Fig. 7-61(a) has a DC that ranges from 100 to 300. Determine IB, IC, and
DC.
7-27. The npn BJT in Fig. 7-61(b) has a DC that ranges from 50 to 200. Determine IB, IC, and
DC.

Figure 7-61.
Section 7-6
7-28. An n-channel E-MOSFET is being used in the drain-voltage feedback bias circuit shown
in Fig. 7-62(a). The E-MOSFET has square-law equation below:
I D = K(VGS − VGS(th) )2 = (900 A/V2 )(VGS − 2) 2
Use a bias line to find ID. Compute the corresponding values of VGS and VDS.
7-29. An n-channel E-MOSFET is being used in the drain-voltage feedback bias circuit shown
in Fig. 7-62(b). The E-MOSFET has square-law equation below:
I D = K(VGS − VGS(th) )2 = (900 A/V2 )(VGS − 2) 2
Use a bias line to find ID. Compute the corresponding values of VGS and VDS.
Figure 7-62.

Section 7-7
7-30. The npn BJT in Fig. 7-63(a) has a DC that ranges from 100 to 300. Apply Thevenin’s
theorem to the base circuit and determine VTH and RTH. Using those results find IB, IC and
VCE if the BJT has the minimum DC. Also determine VC, VE, and VB. Repeat the
analysis if the BJT has the maximum DC.
7-31. The npn BJT in Fig. 7-63(b) has a DC that ranges from 50 to 200. Apply Thevenin’s
theorem to the base circuit and determine VTH and RTH. Using those results find IB, IC and
VCE if the BJT has the minimum DC. Also determine VC, VE, and VB. Repeat the
analysis if the BJT has the maximum DC.
7-32. Analyze the BJT circuit in Fig. 7-63(a) using approximations. Specifically, find VB, VE,
IC, and VC.
7-33. Analyze the BJT circuit in Fig. 7-63(b) using approximations. Specifically, find VB, VE,
IC, and VC.
Figure 7-63.
Section 7-8
7-34. When an n-channel JFET is being used in a self-bias circuit its source terminal is made
_______________ (positive, negative) with respect to its gate terminal.
7-35. When a p-channel JFET is being used in a self-bias circuit its source terminal is made
_______________ (positive, negative) with respect to its gate terminal.
7-36. The self-bias circuit in Fig. 7-64(a) employs a 2N5458 n-channel JFET. Turn to Fig. 7-7
to obtain its minimum and maximum values for VGS(OFF) and IDSS. Graph its minimum and
maximum transfer characteristics on graph paper. You may use a copy the curves
developed for Prob. 7-16. Write the bias line equation and place it on your graph of the
transfer characteristic. Determine ID(min) and ID(max) and the corresponding values of VD,
VS, VG, VGS, VDS, ID(SAT), and VDS(OFF).

7-37. The self-bias circuit in Fig. 7-64(b) employs a 2N5458 n-channel JFET. Turn to Fig. 7-7
to obtain its minimum and maximum values for VGS(OFF) and IDSS. Graph its minimum and
maximum transfer characteristics on graph paper. You may use a copy the curves
developed for Prob. 7-16. Write the bias line equation and place it on your graph of the
transfer characteristic. Determine ID(min) and ID(max) and the corresponding values of VD,
VS, VG, VGS, VDS, ID(SAT), and VDS(OFF).
Figure 7-64.
7-38. Can the self-bias circuit be used to establish a Q-point for an E-MOSFET? Explain your
answer briefly.
7-39. Can the self-bias circuit be used to operate a DE-MOSFET in its enhancement mode of
operation? Explain your answer briefly.
7-40. The DE-MOSFET in Fig. 7-65 has an IDSS of 5 mA and a VGS(OFF) of –3 V. Determine ID,
VD, VS, VG, VGS, and VDS.
7-41. The DE-MOSFET in Fig. 7-65 has an IDSS of 15 mA and a VGS(OFF) of –8 V. Determine ID,
VD, VS, VG, VGS, and VDS.
Figure 7-65.

Section 7-9
7-42. The voltage-divider bias circuit in Fig. 7-66 employs a 2N5458 n-channel JFET. Turn to
curves developed for Prob. 7-16. Apply Thevenin’s theorem to the gate circuit and find
VTH and RTH. Write the bias line equation and place it on your graph of the transfer
characteristic. Determine ID(min) and ID(max) and the corresponding values of VD, VS, VG,
VGS, VDS, ID(SAT), and VDS(OFF).
7-43. The voltage-divider bias circuit in Fig. 7-66 employs a 2N5458 n-channel JFET. The drain
supply voltage VDD has been reduced to 12 V. Turn to Fig. 7-7 to obtain its minimum and
maximum values for VGS(OFF) and IDSS. Graph its minimum and maximum transfer
characteristics on graph paper. You may use a copy the curves developed for Prob. 7-16.
Apply Thevenin’s theorem to the gate circuit and find VTH and RTH. Write the bias line
equation and place it on your graph of the transfer characteristic. Determine ID(min) and
ID(max) and the corresponding values of VD, VS, VG, VGS, VDS, ID(SAT), and VDS(OFF).
7-44. A JFET is normally biased in its ________________ (enhancement, depletion) mode when
voltage-divider bias is used.
7-45. A DE-MOSFET can be biased in its ______________ (depletion, enhancement, either
depletion or enhancement) mode using voltage-divider bias.
7-46. An E-MOSFET ____________ (can, cannot) be biased successfully using voltage-divider
bias.
Figure 7-66.
7-47. An n-channel DE-MOSFET is being biased using the voltage-divider bias circuit indicated
in Fig. 7-67(a). Assume its IDSS is 12 mA and its VGS(OFF) is –6 V. Graph its transfer
characteristic curve. The vertical (ID) axis should run from 0 to 15 mA. The horizontal
(VGS) axis should run from –6 V to +10 V. Apply Thevenin’s theorem to the gate
circuit and find VTH and RTH. Write the bias line equation and place it on your graph of the

transfer characteristic. Determine ID, VD, VS, VG, VGS, VDS, ID(SAT), and VDS(OFF). Is the DE-
MOSFET in its enhancement or depletion mode of operation? Explain your answer briefly.
Figure 7-67.
7-48. An n-channel DE-MOSFET is being biased using the voltage-divider bias circuit indicated
in Fig. 7-67(b). Assume its IDSS is 12 mA and its VGS(OFF) is –6 V. Graph its transfer
characteristic curve. The vertical (ID) axis should run from 0 to 15 mA. The horizontal
(VGS) axis should run from –6 V to +10 V. Apply Thevenin’s theorem to the gate circuit
and find VTH and RTH. Write the bias line equation and place it on your graph of the transfer
characteristic. Determine ID, VD, VS, VG, VGS, VDS, ID(SAT), and VDS(OFF). Is the DE-MOSFET
in its enhancement or depletion mode of operation? Explain your answer briefly.
Section 7-10
7-49. The npn BJT in Fig. 7-68(a) has a DC that ranges from 100 to 300. Find IC and VCE if the
BJT has the minimum DC. Also determine VC, VE, and VB. Repeat the analysis if the BJT
has the maximum DC.
7-50. The npn BJT in Fig. 7-68(b) has a DC that ranges from 50 to 200. Find IC and VCE if the
BJT has the minimum DC. Also determine VC, VE, and VB. Repeat the analysis if the BJT
has the maximum DC.
7-51. Analyze the BJT circuit in Fig. 7-68(a) using approximations. Specifically, find VB, VE,
IC, and VC.
7-52. Analyze the BJT circuit in Fig. 7-68(b) using approximations. Specifically, find VB, VE,
IC, and VC.

(a) (b)
Figure 7-68.
Section 7-11
7-53. The constant-current source bias circuit in Fig. 7-62 employs a 2N5458 n-channel JFET.
Turn to Fig. 7-7 to obtain its minimum and maximum values for VGS(OFF) and IDSS. Use
these values to determine IE. IC, IS, ID, VG, VB, VD, VE, VGS, VC, VS, and VDS.
Figure 7-69.

Section 7-12
7-54. Explain the fundamental difference between a bias stabilization circuit and a temperature
compensation circuit.
7-55. Calculate the base-to-ground voltage VB for the circuit given in Fig. 7-70. Perform the
analysis at 25oC, 50oC, and at 75oC. Assume the diode is silicon and has a voltage drop of
0.7 V at 25oC. (Hint: Use Eq. 3-2 to find the diode voltage at the elevated temperatures.)
2 mV
𝑉𝐷 (𝑇) = 𝑉𝐷 (25℃) − (𝑇 − 25℃) (3-2)
℃
7-56. The VD of a diode and the VBE of a BJT in Fig. 7-70 obey Eq. 3-2. Find VB, VBE, and the
approximate collector current IC at 80oC. The electronic devices are silicon, which makes
VD and VBE equal to 0.7 V at 25oC. (Hint: The circuit is unaffected by DC.)
Figure 7-70.
Section 7-13
7-57. The collector supply VCC in Fig. 7-51(a) has been changed to -12 V. Find VB, VE, IC, and
VC using approximations. Also find VCE.
7-58. The collector supply VCC in Fig. 7-51(b) has been changed to 12 V Find VB, VE, IC, and VC
using approximations. Also find VCE.
.

Design Problems
Section 7-4
7-59. The design procedure for a voltage-divider bias circuit is presented in Fig. 7-71. Design a
bias circuit such as that shown in Fig. 7-71. The collector supply voltage is 20 V, and the
collector current is to be established at approximately 1 mA. The nearest standard 5-%
tolerance resistor values shall be used. (Use a search engine or smart phone application.)
Figure 7-71.
As we shall see in our later work, the emitter-to-ground voltage VE restricts the AC
output signal swing. Therefore, it should be made relatively small.
VCC
VE =
10
Find VE.
(a) The emitter current (IE) and collector current (IC) are approximately equal. This
permits us to determine RE.
VE
RE 
IC
Find RE.
(b) As we shall see in our later work, the boundaries on the maximum output signal
swing are VCC and VE. Therefore, the collector-to-ground voltage VC should be
centered between these two limits.
VCC V E
VC = +
2 2

Determine the optimal value for VC.
(c) Once we have found VC, we can find the voltage drop across the collector resistor RC,
which we shall designate VRC.
VRC = VCC - VC
Find VRC.
(d) Now we can find the required RC. (Remember to specify the nearest upper standard
resistor value.)
V RC
RC =
IC
(e) The base-to-ground voltage VB will be one base-emitter voltage drop more positive
than the emitter-to-ground voltage VE. Assume the transistor is silicon and find VB.
VB = VE + 0.7 V
(f) The bleeder current (I) should be much larger than the BJT’s maximum base current.
To ensure this is the case, the bleeder current established at 50% to 100% of the
collector current. Find I by using the relationship below.
I = 0.5IC
(g) Now that we have established values for VB and I, we can determine the value of R2.
VB
R2 =
I
Find R2.
(h) The last step is to determine the value of R1. The voltage across it is the difference
between the collector supply and the base-to-ground voltage. We assume the current
through it is equal to the bleeder current I.
VCC − VB
R1 =
I
7-60. The constant-current source approach to FET bias yields the most stable bias circuit. This
bias circuit can be used for common-source, common-drain, and common-gate amplifiers.
In this problem, we specify the required values for RE, RC, and RG. The circuit is provided
in Fig. 7-72.
(a). First, we obtain the data sheet parameters for the 2N5459 n-channel JFET. Turn to
Fig. 7-7. Record the values for IDSS(min), IDSS(max), VGS(OFF-min), and VGS(OFF-max).
(b). The design target for the drain current is given to be ID = 3 mA. This value must not
exceed IDSS(min) or IDSS(max). Is a drain current of 3 mA reasonable for a 2N5459?
(c). Since the emitter current of the BJT establishes the drain current, we must size RE
accordingly. Calculate the required value for RE.
VEE − 0.7 V
RE =
IE
Select the nearest standard 5% tolerance value.

(d). To ensure a wide output voltage swing, we size the drain resistor to drop
approximately one-half of the drain supply voltage VDD. Recall that ID = IE.
0.5VDD
RD =
ID
Select the nearest standard 5% tolerance value.
(e). The gate-to-ground resistor RG establishes the input resistance of the common-source
amplifier. Generally, we want a large value. (This will be explained in Chapter 9.)
For example, assume that we desire an Rin of greater than 450 k. In this case, we
might select a 470 k standard 5% tolerance value.
RG = Rin
The only concern is that if RG is too large, the bias stability can be affected by the
gate leakage current IGSS. To check that IGSS will not produce a significant voltage
drop, we calculate the minimum VGS a 2N5459 will have to make ID be equal to 3
mA. We call upon Eq. 7-51, which is repeated below.
 ID 
VGS = VGS (OFF − m in) 1 − 
 I DSS (m in) 
Next, we go to the data sheet and find the maximum value of IGSS at 25oC. Turn to
Fig. 7-11. Verify that an RG of 470 k meets the requirement below:
0.01VGS
RG 
I GSS
Figure 7-72.

Troubleshooting Problems
Effective troubleshooting can only be accomplished by being methodical. We must ask ourselves
questions as we progress through the problem. For instance, are we repairing equipment that
was in the field and failed? Is the equipment a production-line failure, or are we trying to fix a
prototype being used to develop a new product? Equipment that has been in the field is typically
a proven design but may exhibit common failure modes. A component may have failed, and we
shouldn’t expect to find solder bridges between circuit board traces. (A solder bridge is a
production problem normally.) In contrast, a production-line failure can be produced by
components installed backwards, by missing components, or by wrong component values. A
solder bridge is a possibility here. Troubleshooting a prototype unit offers the greatest challenge.
The fundamental design could be incapable of working or designed to fail! (This condition is
guaranteed to produce an embarrassed, defensive engineer.)
Section 7-3
7-61. A short circuit exists on a printed circuit board due to a solder bridge between two traces.
Consequently, the base-emitter terminals of the transistor in Fig. 7-12 are shorted together.
Determine VCE and IC.
7-62. During production, a 360-k resistor was installed instead of the specified 3.6 k for RC
in Fig. 7-12. Determine VCE and IC.
Section 7-5
7-63. The base-emitter terminals of transistor Q1 in Fig. 7-27(a) have been shorted together.
Determine VCE and IC. What is the current through the collector resistor RC?
7-64. Resistor RB in Fig. 7-17(a) has been shorted out. Determine VCE.
7-65. Transistor Q1 in Fig. 7-27(a) has a short circuit between its collector and emitter terminals.
What is VCE? What is VBE? What is the current through the collector resistor RC?
Section 7-7
7-66. A short circuit exists across the emitter resistor RE in Fig. 7-27(a). The transistor has a DC
of 120. Find VB, IB, IC, and VC. (Hint: Draw the equivalent circuit and analyze it carefully.)
7-67. A short circuit exists across the collector resistor RC in Fig. 7-27(a). The transistor has a
DC of 120. Find VB, IB, IC, and VC. (Hint: Draw the equivalent circuit and analyze it
carefully.)
7-68. Resistor R1 in Fig. 7-27(a) is an open circuit. Find VB, IB, IC, and VC.
EDA Problems
7-69. Duplicate the temperature sweep analysis presented in Section 7-14 using the circuit shown
in Fig. 7-70. What is the variation in the collector current over the commercial temperature
range (-20oC to 85oC)?

7-70. Start Multisim. Go to Place, Component, Group: Transistors, and then MOS Depletion.
Place two (2) BSP149 transistors on the schematic sheet. The schematic symbol is
explained in Fig. 7-73. The parasitic diode is inside the device and is characterized fully
on the device data sheet. It can be useful in certain transient suppression situations13. The
model for the device includes provisions for specifying the junction and case temperatures.
These are important when a thermal analysis is conducted. Again, this is not important
now.
Tj – junction
temperature
Parasitic Diode
Tc – case temperature
Figure 7-73.
7-71. This device is manufactured by a company called Infineon Technologies. Use an internet
search engine to find a data sheet for the BSP149. The information of immediate concern
is indicated in Fig. 7-74(a). Circle 1 is around the gate-to-source cutoff voltage VGS(OFF).
This manufacturer calls it the gate-source threshold voltage VGS(th) which is normally
associated with enhancement-only MOSFET (E-MOSFET). We see it ranges from -1 to -
-2.1 V. The test conditions for measurement of VGS(th) include a VDS of 3 V, and a drain
current of 300 µA. The bottom circuit in Fig. 7-74(b) allows you to determine the VGS(th)
associated with the BSP149 model used in Multisim. You must adjust the values of the
V3 voltage source until XMM2 displays a current very close to 300 µA. Construct the
circuits shown in Fig. 7-74(b). Determine VGS(th) for the BSP149 model by adjusting the
V3 voltage source value.
7-72. Circle 2 in Fig. 7-74(a) indicates the IDSS(min) value is 140 mA with VGS equal to zero and
VDS equal the 10 V. The top circuit in Fig. 7-74(b) will indicate the value of IDSS for the
BSP149 model used in Multisim. The XMM1 displays the value. Run the simulation and
you will have both VGS(th) and IDSS for the device model.
13 The use of a “free-wheeling” diode to suppress the counter emf produced by inductive loads is introduced in Volume 1, Section
5-11 – The Clapper.

1
2
3
(a)
(b)
Figure 7-74.
7-73. Circle 3 in Fig. 7-74(a) indicates the maximum drain current value is 660 mA. Since the
MOSFET is only to be used in the depletion mode, we shall use it as IDSS(max). Plot three
transfer curves the minimum, maximum, and for the Multisim model. Excel works well.
Your result should look like Fig. 7-75.
Figure 7-75.
7-74. The black line in Fig. 7-75 is the bias line. Constant-current source biasing yield a
horizontal bias line. Careful examination shows the current source produces 60 mA. The
Multisim circuit is provided in Fig. 7-76. Note that precision 1%-tolerance resistors have
been used. Draw the circuit and simulate it. Examine the results carefully to ensure they
are reasonable. Specifically, the drain current should be close to 60 mA, the drain-to-
ground voltage should be established for midpoint bias, and transistor Q2 should not be
saturated.

Figure 7-76.

8
Voltage Amplifier Models
T he primary purpose of a linear voltage amplifier is to take a small electrical voltage signal
and make it larger. A linear amplifier should accomplish this without altering the shape of
its input signal. Further, the voltage amplifier should serve this function regardless of the
actual shape, initial size, or frequency of the original input signal. A voltage amplifier’s
desirable characteristics seem straightforward and uncomplicated. However, once we conduct a
serious study, the task reveals itself formidable. We know that BJTs and FETs can be used as
amplifiers. To provide linear amplification, the BJT must be operated in its active region. The
FET must be in pinch-off. Because the BJTs and FETs can be used as amplifiers, they are often
called active devices. Active devices can deliver energy to a circuit continuously, while passive
devices (like resistors and rectifier diodes) tend to dissipate (or absorb) energy. There are many
other types of active devices. A linear integrated circuit called an operational amplifier (or op
amp) can be thought of as an active device. The op amp contains several BJTs, JFETs, and/or
MOSFETs. We shall begin our investigation of op amps in Chapter 9. Before we get to the
details of the various BJT, FET, MOSFET, and op amp amplifier circuits, it is useful to establish
the characteristics and parameters associated with all amplifiers. That is our goal in this chapter,
and we therefore cover:
◼ The Basic Voltage Amplifier

◼ Unloaded Voltage Gain
◼ Output Loading Effects
◼ Input Loading Effects
◼ Voltage Amplifier Current Gain
◼ Power Gain
◼ Decibels
◼ Relative Decibel Scales
◼ Applying Decibels
◼ Amplifier Models and Multisim

After completing this chapter, the you should be able to:
• List the features of the ideal amplifier.

• Describe the nature of unloaded voltage gain.
• Explain amplifier output loading effects and amplifier output resistance.
98 VOLTAGE AMPLIFIER MODELS
• Explain amplifier input loading effects including amplifier input resistance.
• Describe the current gain of a voltage amplifier.
• Define power gain.
• Define voltage gain in decibels, current gain in decibels, and power gain in decibels.
• Define some of the relative dB scales such as dBV and dBm.
• Describe some of the applications of decibels in electronics.
• Use Multisim to analyze the voltage amplifier model.
8-1 The Basic Voltage Amplifier

The voltage amplifier can be thought of as a voltage-controlled voltage source as illustrated in
Fig. 8-1. A controlled source is often described as being a dependent source. To remind us of its
dependency, it is often represented with a diamond shape. The controlling input voltage vIN
establishes the output voltage vOUT.17 The constant of proportionality between them is called the
open-circuit voltage gain Av(oc).18 This is the ideal voltage-amplifier equivalent circuit, or model.
A Voltage Amplifier Can Be Thought of as
A Voltage-Controlled Voltage Source
Small input voltage

Large output voltage
1V
0.1 V Output
0 Voltage
Input
Amplifier
-0.1 V t
0
-1 V
(a)
Ideal Voltage Amplifier Model

+ +
+
v IN v OUT
A
- v(oc)v IN
- -
(b)
Figure 8-1
17 Lower case letters with capital subscripts are used to designate total instantaneous AC + DC quantities.
18 The “A” is selected to remind us it is an amplification (signal increase) or an attenuation (signal decrease).
The Basic Voltage Amplifier 99

The relationship between the input voltage vIN and the output voltage vOUT is defined by Eq. 8-1.
v OUT = Av(oc)v IN (8-1)
Example 8-1. The voltage amplifier in Fig. 8-1(a) has a peak input voltage of 0.1 V, and a
peak output voltage of 1 V. What is its open-circuit voltage gain? What is output voltage if its
input is doubled?
Solution: We solve Eq. 8-1 for Av(oc).

vOUT 1V
Av(oc) =
= = 10
v IN 0.1 V
Note the voltage gain has no units19. It is sometimes described as being unitless. The output
voltage is directly proportional to the input voltage. Hence, by Eq. 8-1, we obtain the result
below.
vOUT = Av(oc)v IN = (10)(0.2 V) = 2 V
The key idea here is that Av(oc) is a constant. It remains ten regardless of the size of vIN.
The unconnected terminals in Fig. 8-1(b) often bother students. Do not let it trouble you.
Remember that voltage is a pressure. It can exist between any two terminals unless they are
shorted together. Also note the lack of a resistance in series with the dependent source. It is an
ideal voltage source. This means that once vIN establishes its vOUT, it maintains that voltage in
the same manner as a “regular” ideal voltage source. The current through it will not affect its
voltage.
The ideal voltage amplifier possesses two important attributes.

1. Its input resistance is infinite, which means it acts like an open circuit.
2. Its output resistance is zero, which means it behaves like an ideal voltage source.
A more realistic voltage amplifier equivalent circuit is depicted in Fig. 8-2. It has a finite input
resistance Rin and a nonzero output resistance Rout. Fundamentally, it is still a voltage-controlled
voltage source. The choice of an uppercase R with lowercase subscripts is somewhat arbitrary.
However, it is consistent with rms (AC) notation. The intention is to emphasize that Rin, Rout,
and Av(oc) are amplifier parameters, while the AC resistance external to the amplifier are
designated with lowercase r, and capital subscripts. Specifically, rS is used to denote the signal
source internal resistance, and rL is used to represent the external load resistance connected
across the amplifier’s output terminals. The significance of rL and rS is explained in Sections 8-3
and 8-4, respectively.
19 To emphasize the fact, we are dealing with a voltage gain, the units may be retained. For example, a voltage gain of 2000
could be expressed as 2000 V/V or even as 2 V/mV.

A Realistic Voltage Amplifier Model
R out
Output
Voltage + +
Input
Amplifier
~
= v IN R in
+
v OUT
A
- v(oc)v IN
- -
Figure 8-2
Given the ideal amplifier attributes, it should be clear that a good voltage amplifier should have a
large Rin, and a small Rout. The importance of a small Rout and a large Rin is explained in the next
three sections.
8-2 Unloaded Voltage Gain

Normally, a voltage amplifier delivers an output voltage to a load. The load (designated rL)
could be the input resistance of the next amplifier stage, or the equivalent resistance of a
transducer. To emphasize that it is an AC equivalent resistance, a lowercase letter is used to
represent it. It is useful to determine the voltage gain of a real voltage amplifier when its output
load (rL) is disconnected. This is the case in Fig. 8-3.
Unloaded Voltage Gain

R out
+ +
+
vIN R in vOUT rL
A
- v(oc)v IN
- -
Load is disconne cted
Figure 8-3.
With the load disconnected, no current flows through the output resistance Rout. Consequently,
there will be no voltage drop across it. This means the voltage across the open-circuit output will
be equal to the voltage produced by the dependent voltage source.
vOUT = Av(oc)vIN
Unloaded Voltage Gain 101

Solving for the ratio of the output voltage to the input voltage produces the voltage gain. This is
given by Eq. 8-2.
vOUT
Av(oc) = (8-2)
v IN
Equation 8-2 defines the unloaded, or open-circuit, voltage gain. This is the maximum
possible voltage gain a given voltage amplifier can deliver.
8-3 Output Loading Effects
When a load is connected across the output of an amplifier, voltage division will occur between
the amplifier’s output resistance and the load. This means some of the amplifier’s output signal
will be lost across its (internal) output resistance. This is described in Fig. 8-4.
Output Loaded Voltage Gain

R out
+ +
+
v IN R in rL v L
A
- v(oc)v IN
- -
Load is conne cte d
Figure 8-4.
By inspection of Fig. 8-4, and applying voltage division, we obtain Eq. 8-3 for the voltage across
the load (vL).
rL
vL = Av(oc)v IN (8-3)
rL + Rout
Dividing the left and right sides of Eq. 8-3 by vIN, permits us to obtain the (output loaded)
voltage gain that occurs when the load is connected.
vL rL
Av = = Av(oc) (8-4)
v IN rL + Rout

With a little thought, it should be clear that Av must be less than Av(oc).
Example 8-2. The voltage amplifier in Fig. 8-4 has an Rout of 1 k, and an Av(oc) of 100.
Find Av if rL is (a) disconnected, (b) equal to 10 k, and (c) equal to 1 k.
Solution: We apply Eq. 8-4 in each case. If rL is disconnected, it can be regarded as being an
infinite () resistance.
vL rL  
Av = = Av(oc) = (100 ) = (100 ) = (1)(100 ) = 100
v IN rL + Rout   + 1 k 
Hence, with an rL of infinite ohms, Av is equal to Av(oc). 20 Next, we let rL equal 10 k.
v rL 10 k
Av = L = Av(oc) = (100 ) = (0.9091)(100 ) = 90.9
v IN rL + Rout 10 k + 1 k
To complete the problem, we set rL equal to 1 k.
v rL 1 k
Av = L = Av(oc) = (100 ) = (0.500 )(100 ) = 50.0
Because of the voltage division that occurs between Rout and rL, the voltage gain Av becomes
smaller as the size of the load resistance is reduced. Stated another way, if a voltage amplifier’s
output resistance is kept small relative to rL, the output loading effects are reduced.
8-4 Input Loading Effects

A complete amplifier system is shown in Fig. 8-5. In addition to the amplifier and its load, the
Thevenin equivalent circuit of a signal source is shown. The signal source could be the output
of a previous amplifier stage, a computer’s audio output, an MP3 player, or a laboratory signal
generator. The open-circuit voltage produced by the signal source is labeled vS. Its AC
equivalent internal source resistance is called rS. (Remember that all real voltage sources will
have an internal resistance. Alternatively, we can say we have the Thevenin equivalent circuit of
the signal source.) The voltage across the amplifier’s input remains vIN. As we shall see, voltage
division will occur between the internal resistance of the signal source (rS) and the input
resistance of the voltage amplifier (Rin). Hence, we arrive at Eq. 8-5.
Rin
vS v IN = (8-5)
rS + Rin
When input loading effects are included, an overall gain equation from vS to the amplifier’s
loaded output can be developed. This is accomplished by substituting Eq. 8-5 into Eq. 8-3. The
resulting voltage gain is denoted as Avs.
20 Mathematicians get really upset with engineers and technicians when we do things like take infinity divided by infinity as
being equal to unity (1). They argue that infinity divided by infinity is undefined – and rightly so. To get “off the hook” we
should say “taken as a limit, as rL approaches infinity the quantity rL/(rL + Rout) approaches unity.” At the very least, this will
lower their ire, and raise a smile.
Input Loading Effects 103

A Complete Voltage Amplifier System
R out
rs
+
+ 1 k + 3 k
R in +
v rL vL
v IN 20 k A
S - v(oc)v IN 10 k
- 150 v IN
-
-
Signal Source Voltage Amplifie r Load
Figure 8-5.
Equation 8-3 is repeated below.
rL
vL = Av(oc)v IN (8-3)
rL + Rout
Substituting in Eq. 8-5 leads us to Eq. 8-6.
rL Rin
vL = Av(oc) vS
rL + Rout rS + Rin
vL rL Rin
Avs = = Av(oc) (8-6)
v S rL + Rout rS + Rin
Since the first part of Eq. 8-6 is simply Av, Eq. 8-6 can be rewritten as Eq. 8-7.
vL Rin
Avs = = Av (8-7)
vS rS + Rin
Equation 8-7 makes it clear that we are dealing with the attenuation (signal reduction) between
the amplifier’s input resistance, and the source internal resistance. With a little reflection, it
should also be obvious that Avs must be less than Av. In fact, we have the overall relationships
provided by Eq. 8-8.
Avs < Av < Av(oc) (8-8)

Example 8-3. Given the voltage amplifier shown in Fig. 8-5, determine Av and Avs.
Solution: We apply Eq. 8-4 to determine Av.
vL rL 10 k
Av = = Av(oc) = (150 ) = 115 .4  115
Hey, we have a life to live. We use Eq. 8-7 to find Avs.
vL Rin 20 k
Avs = = Av = (115.4) = (115.4)(0.9524 ) = 110
vS rS + Rin 1 k + 20 k
The guiding principle is that a signal is considered precious. Signal loses across the internal
resistance of the signal source should be minimized. This is achieved by making Rin large
compared to rS.
8-5 Voltage Amplifier Current Gain

A voltage amplifier should be optimized to provide voltage gain. This means it should possess a
large Rin compared to rS, and a small Rout compared to rL. In that light, it seems absurd to
consider its current gain. In fact, since the ideal voltage amplifier has an infinite input
resistance, its input current is zero. This means the current gain for an ideal voltage amplifier
is indeterminate. However, current gain is often used to establish comparisons between one real
(non-ideal) voltage amplifier and another. Consider Fig. 8-6.
Voltage Amplifier Current Gain

i IN R out
rS
i OUT
+ 10 k + 3 k
R in +
vS rL
v IN 20 k A
- v(oc)v IN 10 k
- 150 v IN
-
Figure 8-6.
Voltage Amplifier Current Gain 105

The voltage amplifier’s output circuit forms a series connection between the output resistance
(Rout), the external load resistance (rL), and the dependent voltage source (Av(oc)vIN).
Consequently, developing an equation for the output current is straightforward.
Av(oc)v IN
iOUT = (8-9)
rL + Rout
By inspection of Fig. 8-6 and Ohm’s law, we produce Eq. 8-10.
VIN = RiniIN (8-10)
We substitute Eq. 8-10 into Eq. 8-9 to eliminate vIN. We then solve for the current gain Ai.
Av(oc)v IN Av(oc)Rin i IN Av(oc)Rin
iOUT = = = i IN
rL + Rout rL + Rout rL + Rout
iOUT Av(oc)Rin
Ai = = (8-11)
i IN rL + Rout
Example 8-4. Determine the current gain (Ai) of the voltage amplifier given in Fig. 8-6.
Solution: We apply Eq. 8-11 to determine Ai.

i Av(oc)Rin (150)(20 k)
Ai = OUT = = = 231
i IN rL + Rout 10 k + 3 k
Huge Current Gain from a Voltage Amplifier?

At first glance, it appears the voltage amplifier does a better job at providing current gain than
voltage gain. (From Example 8-3, we recall that Av is 115.) However, the voltage amplifier
reveals its shortcoming when we consider its performance with a current source as its input.
A real current source has an equivalent (internal) resistance (rS) across it as shown in Fig. 8-7.
When a load (e.g., a voltage amplifier’s input resistance Rin) is connected across it, the current
will divide between the two resistances. We have a current-division problem. The input voltage
vIN is developed across the parallel equivalent resistance as is flows through it. This is shown in
Fig. 8-7.
rS Rin
v IN = iS (8-12)
rS + Rin
The input current iIN flows through the input resistance Rin. Ohm’s law and substitution of Eq. 8-
12 yields Eq. 8-13.
v IN 1 1 rS Rin rS
i IN = = v IN = iS = iS (8-13)
Rin Rin Rin rS + Rin rS + Rin

From our previous work, it should be clear that we can rearrange Eq. 8-11 to arrive at Eq. 8-14.
iOUT = AiiIN (8-14)
If we substitute Eq. 8-13 into Eq. 8-14, we can arrive at the current gain from the signal source to
the loaded output of the voltage amplifier. We designate this current gain Ais.
rS
iOUT = Ai i IN = Ai iS
rS + Rin
iOUT rS
Ais = = Ai (8-15)
iS rS + Rin
Voltage Amplifier Current Gain When

Driven by a Real Current Source
i IN R out
i OUT
+
R in +
i rS rL
v IN A
S - v(oc)v IN
Figure 8-7.
Example 8-5. Determine the current gain from the signal source to the load (Ais) of the
voltage amplifier given in Fig. 8-8.
Solution: In Example 8-4, we determined that Ai is 231. Now we apply Eq. 8-15 to
determine Ais.
iOUT rS 10 k
Ais = = Ai = (231) = 77
iS rS + Rin 10 k + 20 k
Input loading has reduced the current gain substantially.
Voltage Amplifier Current Gain 107

As the Rin of a voltage amplifier increases, so does its current gain Ai. However, to minimize
input loading effects, it is necessary for the voltage amplifier’s input resistance to be as low as
possible. In fact, the ideal input resistance of a current amplifier is zero.
Figure 8-8.
8-6 Power Gain

In addition to describing a voltage amplifier in terms of its current gain, a power gain description
is also used. The ratio of the (resistive) signal power delivered to the load to the (resistive)
signal power delivered to the amplifier’s input is defined to be the power gain Ap. With
reference to Fig. 8-9, we state the power gain Ap by Eq. 8-16. Observe that rms notation
(uppercase V’s and I’s with lowercase subscripts) has been used. Power calculations must be
performed using rms values, or their equivalents21.
Voltage Amplifier Power Gain

I in R out I out
rs
5.1 k +
+ 2 k +
R in +
Vs rL Vload
Vin 10 k - A
v(oc)v in 20 k
- 180 v in
-
-

Pin Pout
- the power used to driv e - the power de liv e red to
the amplifier's input. the amplifier's load.
Figure 8-9.
21 By “equivalents” we mean the peak voltage divided by 2 , the peak-to-peak voltages divided by 2 2 , and so forth.

Pout
Ap = (8-16)
Pin
By inspection of Fig. 8-9, we arrive at Eq. 8-17.
Pout Vload I out Vload I out

Ap = = = = Av Ai
Pin Vin I in Vin I in
Pout
Ap = = Av Ai (8-17)
Pin
Example 8-6. Determine the voltage gain (Av), the current gain (Ai), and the power gain of
the voltage amplifier given in Fig. 8-9.
Solution: We apply Eq. 8-4 to find Av.
vload rL 20 k
Av = = Av(oc) = (180) = 143.4  143
vin rL + Rout 20 k + 5.1 k
Equation 8-11 leads us to the current gain.
iout Av(oc)Rin (180)(10 k)

Ai = = = = 71.71  71.7
i in rL + Rout 20 k + 5.1 k
The power gain is determined from Eq. 8-17.
Pout
Ap = = Av Ai = (143 .4)(71.71) = 10283
Pin
The power gain can be misleading. It is important to understand that while the power gain can
be large, the actual power levels can be extremely small. The input power can be on the order of
nanowatts, while the output power levels are milliwatts.
Power Gain 109

Why Don’t We Just Use a Transformer? 22
Recall that when we have a current flow through a wire, a magnetic field is developed around
that wire. The strength of the magnetic field is directly proportional to the magnitude of the
current. The direction of the magnetic field depends on the direction of the current. Reversing
the current direction will therefore reverse the direction of the magnetic field. Consequently, a
sinusoidal AC voltage (V1) applied to the primary winding (a coil) creates a sinusoidal magnetic
field [see Fig. 8-10(a)]. The changing magnetic field produced in the primary is used to induce a
voltage in the secondary winding. No direct electrical connection exists between the primary
side and the secondary side. This means the secondary is electrically isolated from the primary
side. The relationship between a transformer’s primary and secondary voltages depends on its
turn ratio. A transformer may be used to step down the primary voltage (N2 < N1) as shown in
Fig. 8-10(b), simply provide isolation (N2 = N1) as indicated in Fig. 8-10(c), or step up the
primary voltage (N2 > N1) as illustrated in Fig. 8-10(d).
While a transformer can be used to step up a voltage level, the power it delivers to the load
across its secondary is equal to the power delivered to its primary. The power is extracted from
the signal source [see Fig. 8-10(e)]. A voltage amplifier avoids this constraint.
22 This question was originally posed by one of my most tenacious students John Lyle. John had insight. John would read
assignments prior to lectures. Every class should have at least one John!

Figure 8-10.
Power gain answers the question: “Why don’t we just use a transformer?” A feeble signal source
typically cannot deliver the required load power. When an amplifier is used, the input signal
controls the power levels delivered to the load. The signal source is merely used to drive the
amplifier’s input. So, where does the load power come from? The answer to this is simple. The
load power is extracted from the amplifier’s DC power supply [see Fig. 8-10(f)].
Power Gain 111

The voltage amplifier converts the DC input power
into AC load power. The power drawn from the AC
signal source is small.
8-7 Decibels
The decibel is a (base 10) logarithmic measure. Most students are not thrilled at the prospect of
remembering (much less using) logarithmic functions. However, with a little review, we can
become quite comfortable with decibels and their use23. The original motivation for the use of
the decibel found its roots in audio work. Our ears respond to power levels logarithmically. In
fact, a change in the power level by one decibel is barely perceptible to the human ear. This
power change is right at the threshold of human hearing detection. The decibel (dB) is used
extensively throughout the electronics industry. A summary of powers of ten, and the definition
of the logarithm are provided in Fig. 8-11. Although a scientific calculator can find a logarithm
easily, it is important to have a fundamental sense of what a logarithm is. Study Fig. 8-11
carefully.
23 Dare we say: “it’s as easy as falling off a log?” No, we probably shouldn’t. Never mind.

Powers of 10 and Logarithms
Powers of 10
10-6 = 0.000001
10-5 = 0.00001
10-4 = 0.0001 Negativ e powers of te n re prese nt numbe rs
10-3 = 0.001 that are le ss than one .
10-2 = 0.01
10-1 = 0.1
100 = 1 Any base number raised to the zero power
is unity.
101 = 10
102 = 100
103 = 1000
104 = 10000 Positive powe rs of ten repre se nt numbe rs
105 = 100000 that are gre ater than one.
106 = 1000000
Log10100 = “10 to what power gives 100” 2 is the answer

Log100.01 = “10 to what power gives 0.01” -2 is the answer
Figure 8-11.
The fundamental definition of the bel (named after Alexander Graham Bell) is provided by Eq.
8-18.
Pout
A p (B) = log bels (8-18)
Pin
Decibels 113
Note that Ap(B) is the magnitude of the power gain in bels (B). For example, a power gain of
1000 is equivalent to
P
A p (B) = log out = log A p = log 1000 = 3 B
Pin
The bel proved to be too large for most practical work. Consequently, one-tenth of a bel – the
decibel (dB) – was adopted. We can arrive at the relationship for the power gain in decibels by
applying a unit conversion. (Ten decibels equal one bel.) Consider the previous example.
10 dB 10 dB
A p (dB)= A p (B) = (3 B) = 30 dB
1B 1B
The general relationship is provided by Eq. 8-19. It is very important.
Pout
A p (dB) = 10 log A p = 10 log (8-19)
Pin
In practice, it is much easier to measure voltages than to measure power levels. Therefore, a
relationship between the voltage gain in decibels and the power gain in decibels is very useful.
However, before we attempt the derivation, it is beneficial to review three fundamental logarithm
properties. These are described in Fig. 8-12. Using simple powers of ten tests helps us
understand the relationships.
Logarithm Properties Sanity Test
log AB = log A + log B log [(10)(100)] = log10 + log100= 1 + 2 = 3
Absolute ly! log[(10)(100)] = log1000 = 3
A 1000
log = logA - log B log = log1000 - log10 = 3 - 1 = 2
B 10
1000
Sure! log = log100 = 2
10
log AB = B log A log 10 2 = 2 log 10 = (2)(1) = 2

2
Yes! log 10 = log 100 = 2
Figure 8-12.
Armed with the basic logarithm properties, let us derive the relationship between voltage gain,
and power gain. First, we start with Eq. 8-19 and substitute the basic power relationships below:

2
Vload
Pout =
rL
Vin2
Pin =
Rin
2
Vload 2
P r V2 R V 2 Rin V  R
A p (dB)= 10 log out = 10 log 2 L = 10 log load in2 = 10 log load
2
= 10 log load  in
Pin Vin rL Vin Vin rL  Vin  rL
Rin
At this point, we recognize that the log of a quantity raised to a power is equal to that power
times the log of the quantity. We also recall the log of a product is equal to the sum of the logs
of the individual terms of that product24.
2 2
V  Rin V  R V  R
A p (dB) = 10 log  load  = 10 log  load  + 10 log in = 20 log  load  + 10 log in (8-20)
 Vin  rL  Vin  rL  Vin  rL
Generally, when we are concerned about power gain, we are also interested in achieving
maximum power transfer. If this is the case, impedances are matched. Specifically, the source
resistance rS, the amplifier’s input resistance Rin, the amplifier’s output resistance Rout, and the
load resistance rL will all be equal in value. (In telephone systems 600  is used, and in radio
frequency work 50  is the standard.) In this case, Rin = rL, and Eq. 8-20 reduces to Eq. 8-21.
V  R V  V 
Ap (dB)= 20 log load  + 10 log in = 20 log load  + 10 log1 = 20 log load  (8-21)
 Vin  rL  Vin   Vin 
From Eq. 8-4, we remember that Av = Vload/Vin. This takes us to Eq. 8-22.
For matched impedances (Rin = rL):

A p (dB) = 20 log Av (8-22)
The magnitude of the voltage gain in decibels will be equal to the magnitude of the power gain
if the impedances are matched. In practice, we often express the magnitude of the voltage gain
in decibels with a total disregard for the impedance levels. The only consequence of this is that
the magnitude of the voltage gain in decibels is no longer equal to the magnitude of the power
gain in decibels. (The two gains can still be related by using Eq. 8-20.) However, if a simple
statement of the magnitude of the voltage gain in decibels is required, we may use Eq. 8-23.
Av (dB) = 20 log Av (8-23)
24 Sure, take another peek at Fig. 8-12.
Decibels 115
In a similar fashion, the current gain in decibels can also be related to the power gain in decibels.
2
P I 2 rL  I out  rL
A p (dB) = 10 log out = 10 log out = 10 log  
Pin I in2 Rin  I in  Rin
Applying the logarithm properties takes us to Eq. 8-24.
2
I  rL I r
A p (dB) = 10 log  out  = 20 log out + 10 log L (8-24)
 I in  Rin I in Rin
Drawing from Eq. 8-11, we recall that Ai = Iout/Iin. If we also assume the impedances are
matched, we obtain Eq. 8-25.
For matched impedances (Rin = rL):

A p (dB) = 20 log Ai (8-25)
To merely state the current gain in decibels, we ignore the impedance levels and use Eq. 8-26.
Ai (dB) = 20 log Ai (8-26)
Example 8-7. Determine the voltage gain, the current gain, and the power gain in decibels of
the voltage amplifier given in Fig. 8-9. (Refer back to Example 8-6.)
Solution: In Example 8-6, we determined that Av is 143. To find the magnitude of the
voltage gain in decibels, we use Eq. 8-23.
Av (dB) = 20 log Av = 20 log 143 = 43.1 dB
In Example 8-6, we determined that Ai is 71.7. Equation 8-26 provides us with the current gain
in decibels.
Ai (dB) = 20 log Ai = 20 log 71.7 = 37.1 dB
In Example 8-6, we determined that Ap is 10283. We use Eq. 8-19 to calculate the power gain in
decibels.
A p (dB) = 10 log A p = 10 log 10283 = 40.1 dB

8-8 Relative Decibel Scales
The voltage gain Av relates the input voltage to the load voltage of a voltage amplifier. For
instance, by knowing that Av is 10, we know that the load voltage will always be 10 times larger
than the input voltage. (The Av relationship holds until the capabilities of the amplifier are
exceeded.) As we have seen, the decibel scale is used to describe the ratio between an output
quantity and a similar input quantity. Basically, we must always compare one quantity with
reference to another quantity. However, they need not be input and outputs. We can reference
any measurement to a standard reference quantity. This gives rise to the relative decibel scales.
Convenience? The dBmV Scale!

The dBmV scale uses 1 mV (1000 V) as its reference. In radio frequency (RF) and audio
frequency (AF) applications, low-level voltage signals are encountered on a regular basis. In
these cases, the dBmV scale proves useful. The dBmV scale is defined by Eq. 8-27.
Vx
V x (dBmV)= 20 log (8-27)
1 mV
where Vx(dBmV) is the magnitude of a measured voltage expressed in dBmV’s, Vx is the rms
value of the measured voltage, and the 1 mV (rms) level is the reference.
If a measured signal (Vx) is above the 1-mV reference level, a positive dBmV value will result. If
a measured signal is at the reference level, a 0-dBmV value results. Signal levels below the 1-
mV reference will generate negative dBmV values. Consider Example 8-8.
Example 8-8. Determine the dBmV values for (rms) signal levels of 100 mV, 1 mV, and
0.01 mV.
Solution: To find the magnitude of the voltages in dBmV, we use Eq. 8-27.
Vx 100 mV
V x (dBmV)= 20 log = 20 log = 40 dBmV
1 mV 1 mV
The calculations for the 1-mV, and 0.01-mV levels are identical.
Vx 1 mV
V x (dBmV)= 20 log = 20 log = 0 dBmV
1 mV 1 mV
Vx 0.01 mV
V x (dBmV)= 20 log = 20 log = −40 dBmV
1 mV 1 mV
Relative Decibel Scales 117

The dBV Scale uses a 1-V rms Reference Level
While the dBmV scale is convenient for low-level signal work, general-purpose laboratory
instrumentation often uses a 1-V rms reference level. This relative dB scale is called the dBV
scale. It is incorporated in some digital multimeters, and in some audio-frequency-range
spectrum (spectral or frequency content) analyzers. The dBV scale is defined by Eq. 8-28.
Vx
Vx (dBV)= 20 log (8-28)
1V
This scale is extremely easy to use. A 10-V rms level corresponds to 20 dBV. A 1-V rms level
is equivalent to 0 dBV. A 0.1-V rms level is the same as –20 dBV. Consider Example 8-9.
Example 8-9. Determine the dBV values for (rms) levels of 150 mV, 1.5 V, and 15 V.
Solution: To find the magnitude of the voltages in dBV, we use Eq. 8-28.
Vx 150 mV
V x (dBV)= 20 log = 20 log = −16.5 dBV
1V 1V
The calculations for the 1.5-V, and 15-V levels are identical.
Vx 1.5 V
V x (dBV)= 20 log = 20 log = 3.52 dBV
1V 1V
Vx 15 V
V x (dBV)= 20 log = 20 log = 23.5 dBV
1V 1V
The dBm Scale uses a 1-mW Reference Level

An often-used reference level in audio25 communications electronics is 1 mW. A resistive
impedance level of 600  is also specified. Notice that we are referring to power levels here.
Px
Px (dBm)= 10 log (8-29)
1 mW
The 600  impedance level becomes very significant when voltage levels are related to the dBm
scale. Very often voltmeters will include a dBm scale. Let us see what the equivalent voltage
levels are on the dBm scale.
25 The audio frequency range is held to be from 20 Hz to 20 kHz. The dBm scale is also used in radio frequency applications. In
this case the impedance level is specified to be 50 Ω. For example, a cell phone may experience power signal levels that range
from -30 dBm to -110 dBm at its antenna.

V x2
Px =
R
We solve for the voltage Vx as demonstrated below.
V x2
= Px
R
V x2 = Px R
Vx = Px R = (1 mW)(600  ) = 0.7746 V
Consequently, from our previous work, it should be clear that Eq. 8-30 will produce the
magnitude of a measured voltage (Vx) in dBm units.
Vx
V x (dBm)= 20 log (8-30)
0.7746 V R = 600 
Example 8-10. Determine the dBm value for an (rms) level of 1.5 V. It is across a 600-
resistance.
Solution: To find the magnitude of the voltages in dBm, we use Eq. 8-30.
Vx 1.5 V
V x (dBm) = 20 log = 20 log = 5.74 dBm
0.7746 V 0.7746 V
The dBm scale is also called the Volume Units (VU) scale found on the level meters of audio
equipment. The VU measure is used extensively in the audio recording industry. The VU units
are designated dBu.
Other Relative dB Scales

In addition to the dBmV, dBV, and dBm (VU or dBu) scales, several other relative dB scales have
been defined. For instance, the dBW scale references power measurements to one watt. The
dBc scale is used extensively in radio frequency (RF) work. This scale uses a “moving”
reference. Specifically, signal voltage measurements are made relative to the nominal value of
the RF carrier. (The RF carrier is a sine wave that is modulated in some fashion by another
signal e.g., voice, music or data.) Although the value of the RF carrier may not be specified, a
signal measured at –40 dBc is 40 dB below the carrier level. (This also means the measured
signal is 1/100 of the carrier amplitude.) We shall not pursue these other relative dB scales
further. However, a solid understanding of the scales we have discussed provides us with the
skills necessary to handle other relative dB scales when (or if) we encounter them.
Relative Decibel Scales 119

8-9 Applying Decibels
Decibels are used to ease the analysis of electronic systems, to characterize electronic circuits,
and often appear as the units of some of the parameters on electronic device manufacturers’ data
sheets. Let us see how decibels are used.
Decibel Voltage Gains Add in Cascaded Systems

A cascaded amplifier system is depicted in Fig. 8-13. A multiple-stage amplifier system is
cascaded when the output of a given amplifier is used to drive the input of the next successive
stage. This arrangement makes it possible to achieve very large voltage gains.
A Cascaded Voltage Amplifier System
rS
Voltage Voltage Voltage
Amplifier Amplifier Amplifier
+ + + +
+ 1 k Stage 1 Stage 2 Stage 3
Vs Vin V1 V2 rL Vload
10 k
-
- - - -
Signal Source Load

Figure 8-13.
The input to stage 1 is the input voltage to the system Vin. The output voltage of the first stage V1
is also the input voltage to the second stage. Similarly, the output voltage of the second stage V2
is also the input voltage to the third stage. The ultimate output of the system is Vload. We define
the (output loaded) system voltage gain as Eq. 8-31.
Vload
Av = (8-31)
Vin
The overall voltage gain Av can be described in terms of the product of the individual loaded
voltage gains. This relationship is given by Eq. 8-32.
Vload  V1  V2  Vload 
Av = =    
Vin  in  V1
V  V2 
Vload
Av = = Av1 Av 2 Av 3 (8-32)
Vin
Av is the overall voltage gain of the cascaded system, Av1 is the voltage gain of the first stage, Av2
is the voltage gain of the second stage, and Av3 is the voltage gain of the third stage. In each
instance, we are dealing with the (output) loaded voltage gains. Internally, the input resistance
of a successive voltage amplifier stage loads down the output of the stage driving it. While the
product of the individual gains produces the overall voltage gain, the use of decibel gains is
simpler. Decibel voltage gains are additive. This is indicated in Eq. 8-33. (The required
logarithm property is provided in Fig. 8-12. The logarithm of a product is equal to the sum of
logarithms of the individual terms.)
Vload
Av (dB) = 20 log = 20 log Av1 Av 2 Av 3 = 20 log Av1 + 20 log Av 2 + 20 log Av 3
Vin
Av (dB) = Av1(dB) + Av 2(dB) + Av3(dB) (8-33)
Let us see if this really works. Consider Examples 8-11 and 8-12.
Example 8-11. Given the amplifier in Fig. 8-13, determine the overall voltage gain Av if Av1
is 10, Av2 is 100, and Av3 is 1. Also, determine the overall voltage gain in decibels.
Solution: To find Av, we use Eq. 8-32.

Vload
Av = = Av1 Av 2 Av 3 = (10)(100)(1) = 1000
Vin
Next, we determine Av(dB).
Av (dB) = 20 log Av = 20log(1000 ) = 20(3) = 60 dB
Example 8-12. Given the amplifier in Fig. 8-13, determine the individual stage voltage
gains in decibels if Av1 is 10, Av2 is 100, and Av3 is 1. Also, determine the overall voltage gain in
decibels.
Solution: First, we find the individual decibel gains.
Av1(dB) = 20 log Av1 = 20log(10) = 20(1) = 20 dB

Av 2(dB) = 20 log Av 2 = 20log(100) = 20(2) = 40 dB
Av3(dB) = 20 log Av3 = 20log(1) = 20(0) = 0 dB
Now we can employ Eq. 8-33 to find Av(dB).
Av (dB) = Av1(dB) + Av 2(dB) + Av3(dB) = 20 dB + 40 dB + 0 dB = 60 dB
Applying Decibels 121

As can be seen, the approaches demonstrated in Examples 8-11 and 8-12 yield the same result.
If the individual stage gains are given in decibels, a system analysis is a matter of simple addition
to determine the overall, or net, result.26
Voltage Attenuators Offer Negative dB Gains

A voltage attenuator has a voltage transfer function that is less than one. Voltage transfer
functions relate the input and output signals of a circuit. A voltage transfer function can be
thought of as a voltage gain. Voltage attenuators are used to reduce large signal levels. A
voltage attenuator can be a simple voltage divider as illustrated in Fig. 8-14.
A Voltage Attenuator
R1
+
+ 1 k
Vs R2
V2
2 k
- -
Figure 8-14.
By voltage division, we solve for voltage V2 that exists across resistor R2.
R2
V2 = Vs
R1 + R 2
The voltage transfer function (or voltage gain) can be determined by dividing both sides by Vs.
This leads us to Eq. 8-34.
V2 R2
Av = = (8-34)
Vs R1 + R2
Example 8-13. Find the voltage gain of the attenuator circuit given in Fig. 8-14. Also,
determine the attenuator’s voltage gain in decibels.
Solution: First, we find the straight-ratio voltage gain by using Eq. 8-34.
V2 R2 2 k
Av = = = = 0.66 6  0.667
Vs R1 + R2 1 k + 2 k
26 The great thing about this is we can be paid to do addition. We just call it a system analysis.

Now we find Av(dB).
Av(dB) = 20logAv = 20log(0.6667) = 20(-0.17609) = -3.52 dB
Finding the Straight-Ratio Voltage Gain from the Decibel Gain

Quite often, we are given a voltage gain in decibels and we need to find the straight-ratio voltage
gain. This requires a little algebra but is straightforward. We start with Eq. 8-23.
20 log Av = Av (dB)
We divide both sides by 20.
Av (dB)
log Av =
20
To solve for Av, we take the anti-logarithm of both sides. This produces Eq. 8-35.
Av (dB)
Av = 10 20
(8-35)
Example 8-14. An amplifier has a voltage gain of 48 dB. Find its straight-ratio voltage
gain.
Solution: We find the straight-ratio voltage gain by using Eq. 8-35.

Av (dB) 48
Av = 10 20
= 10 20 = 10 2.4 = 251
The hardest part about using Eq. 8-35 is finding the 10x button on your scientific calculator.
Using the Relative dB Scales to Find Av – It’s a Matter of Subtraction

An amplifier is indicated in Fig. 8-15. A digital multimeter is used to measure the input and
output levels in volts, dBVs, and dBms. When relative dB scales are used, a simple subtraction
produces the voltage gain in decibels. This works for any relative dB scale (e.g., dBV or dBm).
Let us see why. First, we recall the definition of the voltage gain in decibels.
Vload
Av (dB) = 20 log
Vin
Applying Decibels 123

We divide the numerator and the denominator by an arbitrary reference voltage Vref. We also
apply our logarithm property, which states that the logarithm of a ratio is equal to the logarithm
of the numerator minus the logarithm of the denominator.
Vload Vref Vload V

Av (dB)= 20 log = 20 log − 20 log in
Vin Vref Vref Vref
This takes us to Eq. 8-36.
Av (dB) = Vload (dB ref) − Vin (dB ref) (8-36)
Equation 8-36 is generic. Any relative dB scale that permits us to measure voltages can be
used. Figure 8-15 demonstrates this fact. The reader should verify that 0.1 V rms is equivalent
to – 20 dBV and –17.8 dBm. The reader should also verify that 2 V rms is equivalent to 6.02
dBV and 8.24 dBm.
Measuring the dB Gain of a Voltage Amplifier
Decibel Gain Calculation
0.1 V rms 2 V rms
2 V rms
Av = = 20
0.1 V rms
Av(dB) = 20 log Av
rs
A = 20 = 20 log 20
v
+
Input Output = 26.0 dB
Vs rL
(a) Using voltage measurements.

-20 dBV 6.02 dBV
Av(dB) = Vout(dBV) – Vin(dBV)
= 6.02 dBV - (-20 dBV)

rs
A = 20 = 6.02 dBV + 20 dBV
v
+
Vs rL
(b) Using dBV measurements.

-17.8 dBm 8.24 dBm
Av(dB) = Vout(dBm) – Vin(dBm)
= 8.24 dBm - (-17.8 dBm)

rs
A = 20 = 8.24 dBm + 17.8 dBm
v
+
Vs rL
(c) Using dBm measurements.
Figure 8-15.
8-10 Amplifier Models and Multisim
Linear integrated circuits called operational (op amps) amplifiers are introduced in Chapter 9.
When their internal electrical schematic diagrams are examined, they are seen to have 30 or more
transistors. If those circuits were used in simulation, the simulation time will increase
significantly, errors due to inaccuracies will increase, and our circuit size will become more
restricted. An alternative approach is to only model the key op amp features. The op amp
equivalent circuit is then described as being a macromodel. A macromodel employs transistors,
diodes, resistors, capacitors, voltage sources, and current sources to mimic the (often non-linear)
terminal characteristics of an operational amplifier. Generally, we may not need to simulate an
entire circuit, but only a critical portion of interest. We can model other portions using ideal
components.
We shall use Multisim to analyze Fig. 8-16. We want to find Av, Avs and Ai using Multisim.
Figure 8-16.
First, we shall find Av and Avs in Example 8-15
Example 8-15. Find Av and Avs for the amplifier model shown in Fig. 8-16.
Solution: We use Eq. 8-6 to find Av.
Equation 8-7 provides Avs.
Amplifier Models and Multisim 125

To place the voltage-controlled voltage source in Multisim, we click on Place, Component,
Group: Sources, Family: Controlled Voltage Sources, Component: Voltage Controlled
Voltage Source. The symbol is shown in Fig. 8-17. The rectangular box on the left acts like an
open and is used to define the controlling voltage. The default gain is one (1). It can be edited
by double clicking on it.
Figure 8-17.
The complete amplifier model has been simulated as shown in Fig. 8-18. It is convenient to edit
the signal source to have a value of 1 Vrms. The voltage across the load will be equal to Avs.
Figure 8-18.
We determine Av = Vload/Vin = 76.92V/666.7 mV = 115.4, which agrees with the results in

Example 8-15. We modify the Multisim circuit so we can find the current gain Ai as shown in
Fig. 8-19.

Figure 8-19.
The current gain was calculated in Example 8-4 and Ai = 231. The Multisim simulation provides
the same result. Ai = Iload/Iin = 7.692 mArms/33.333 µArms = 231.
Drill Problems
Section 8-1
8-1 The (linear) voltage amplifier in Fig. 8-1 has a peak input voltage of 20 mV, and a peak
output voltage of 800 mV. What is its open-circuit voltage gain (Av(oc))? Suppose the
input voltage is doubled. What is Av(oc) under this condition?
8-2 The (linear) voltage amplifier in Fig. 8-1 has a peak input voltage of 5 mV, and a peak
output voltage of 1500 mV. What is its open-circuit voltage gain (Av(oc))? Suppose the
input voltage is halved. What is Av(oc) under this condition?
8-3 An ideal voltage amplifier has a(an) ___________ (infinite, zero) input resistance, and
a(an) ___________ (infinite, zero) output resistance.

Section 8-2
8-4 When a load is connected across the output of a (real) voltage amplifier, its output
voltage will ______________ (increase, decrease, remain the same).
8-5 As the load resistance connected across the output of a (real) voltage amplifier decreases,
the voltage drop across the amplifier’s output resistance will ______________ (increase,
decrease, remain the same).
8-6 The open-circuit voltage is the ______________ (minimum, maximum) voltage gain
offered by a voltage amplifier.
Section 8-3
8-7 Given the voltage amplifier provided in Fig. 8-4, Av(oc) is 220, Rout is 5.1 k, and rL is 20
k. Determine Av.
8-8 Given the voltage amplifier provided in Fig. 8-4, Av(oc) is 120, Rout is 2 k, and rL is 12
k. Determine Av.
8-9 To minimize output loading effects, the output resistance of a voltage amplifier should be
__________ (large, small) relative to the load resistance.
8-10 As the load resistance rL is increased, a voltage amplifier’s output voltage will tend to
_____________ (increase, decrease).
Section 8-4
8-11 Given the voltage amplifier provided in Fig. 8-5, rs is 2 k, Rin is 10 k, Av(oc) is 200,
Rout is 5.1 k, and rL is 20 k. Determine Av and Avs.
8-12 Given the voltage amplifier provided in Fig. 8-5, rs is 1.5 k, Rin is 20 k, Av(oc) is 175,
8-13 Given the voltage amplifier provided in Fig. 8-5, rs is 5 k, Rin is 1 k, Av(oc) is 200, Rout
is 5.1 k, and rL is 2 k. Determine Av and Avs.
8-14 Given the voltage amplifier provided in Fig. 8-5, rs is 12 k, Rin is 10 k, Av(oc) is 150,
8-15 To minimize input loading effects, the input resistance of a voltage amplifier should be
__________ (large, small) relative to the source resistance.
8-16 In general, signal losses across the internal resistance of the signal source should be
(maximized, minimized).
Section 8-5
8-17 Determine the current gain (Ai) of the voltage amplifier indicated in Fig. 8-6. The source
resistance rs is 5 k, Rin is 1 k, Av(oc) is 200, Rout is 5.1 k, and rL is 2 k.
8-18 Determine the current gain (Ai) of the voltage amplifier indicated in Fig. 8-6. The source
resistance rs is 12 k, Rin is 10 k, Av(oc) is 150, Rout is 6.8 k, and rL is 3 k.

8-19 Determine the current gain from the signal source to the load (Ais) of the voltage
amplifier given in Fig. 8-7. The source resistance rs is 5 k, Rin is 1 k, Av(oc) is 200, Rout
is 5.1 k, and rL is 2 k. (Note that these are the values used to determine Ai in Prob. 8-
17.)
8-20 Determine the current gain from the signal source to the load (Ais) of the voltage
amplifier given in Fig. 8-7. The source resistance rs is 12 k, Rin is 10 k, Av(oc) is 150,
Rout is 6.8 k, and rL is 3 k. (Note that these are the values used to determine Ai in
Prob. 8- 18.)
Section 8-6
8-21 Determine the voltage gain (Av), the current gain (Ai), and the power gain (Ap) of the
voltage amplifier given in Fig. 8-8. The source resistance rS is 2 k, Rin is 10 k, Av(oc)
is 180, Rout is 7.5 k, and rL is 15 k.
8-22 Determine the voltage gain (Av), the current gain (Ai), and the power gain (Ap) of the
voltage amplifier given in Fig. 8-8. The source resistance rS is 0.5 k, Rin is 5 k, Av(oc)
is 130, Rout is 5.6 k, and rL is 12 k.
8-23 When large power gains are available, the associated power levels must also be large.
True or False?
Section 8-7
8-24 An amplifier has an Av of 200, and an Ai of 30. Find the power gain Ap. Also, compute
the values of Av, Ai, and Ap in decibels.
8-25 An amplifier has an Av of 150, and an Ai of 60. Find the power gain Ap. Also, compute
the values of Av, Ai, and Ap in decibels.
Section 8-8
8-26 Determine the dBmV values for 20 mV rms, 1.5 V rms, and 6 V rms.
8-27 Determine the dBmV values for 20 V rms, 950 V rms, and 1200 V rms.
8-28 Determine the dBV values for 0.02 V rms, 0.18 V rms, and 1.5 V rms.
8-29 Determine the dBV values for 0.008 V rms, 120 mV rms, and 5 V rms.
8-30 Determine the dBm values for 20 mV rms, 1.5 V rms, and 6 V rms. (Note these are the
same voltage values used in Prob. 8-26.)
8-31 Determine the dBm values for 20 V rms, 950 V rms, and 1200 V rms. . (Note these
are the same voltage values used in Prob. 8-27.)
Section 8-9
8-32 Given the amplifier system indicated in Fig. 8-13, determine the overall voltage gain Av.
The voltage gain of the first stage (Av1) is 25, the voltage gain of the second stage (Av2) is
120, and the voltage gain of the third stage (Av3) is 0.95. Also, determine the overall
voltage gain in decibels.

8-33 Given the amplifier system indicated in Fig. 8-13, determine the overall voltage gain Av.
The voltage gain of the first stage (Av1) is 30, the voltage gain of the second stage (Av2) is
190, and the voltage gain of the third stage (Av3) is 0.90. Also, determine the overall
voltage gain in decibels.
8-34 An amplifier system indicated in Fig. 8-13. The voltage gain of the first stage (Av1) is 25,
the voltage gain of the second stage (Av2) is 120, and the voltage gain of the third stage
(Av3) is 0.95. Determine the individual stage gains in decibels. Also, determine the
overall voltage gain in decibels by addition . (Note that these are the same values given
in Prob. 8-32. You might wish to compare your calculation results there to the overall
voltage gain in decibels.)
8-35 Given the amplifier system indicated in Fig. 8-13. The voltage gain of the first stage
(Av1) is 30, the voltage gain of the second stage (Av2) is 190, and the voltage gain of the
third stage (Av3) is 0.90. Determine the individual stage gains in decibels by addition.
Also, determine the overall voltage gain in decibels. (Note that these are the same values
given in Prob. 8-33. You might wish to compare your calculation results there to the
overall voltage gain in decibels.)
8-36 Find the voltage gain of the attenuator given in Fig. 8-14. Resistor R1 is a 28-k unit,
while R2 is a 100-k unit. Also, determine the voltage gain of the attenuator in decibels.
8-37 Find the voltage gain of the attenuator given in Fig. 8-14. Resistor R1 is a 56-k unit,
while R2 is a 33-k unit. Also, determine the voltage gain of the attenuator in decibels.
8-38 A voltage amplifier has a voltage gain of 65 dB. Determine its straight-ratio voltage
gain.
8-39 A voltage amplifier has a voltage gain of 35 dB. Determine its straight-ratio voltage
gain.
8-40 A voltage attenuator has a voltage gain of -42 dB. Determine its straight-ratio voltage
gain.
8-41 A voltage attenuator has a voltage gain of -12 dB. Determine its straight-ratio voltage
gain.
8-42 The amplifier in Fig. 8-15(b) has an input of –25 dBV, and an output of 10 dBV. What is
its voltage gain in decibels? What is its input voltage?
8-43 The amplifier in Fig. 8-15(b) has an input of –5 dBV, and an output of 37 dBV. What is
its voltage gain in decibels? What is its output voltage?
8-44 The amplifier in Fig. 8-15(c) has an input of –40 dBm, and an output of -10 dBm. What
is its voltage gain in decibels? What is its input voltage?
8-45 The amplifier in Fig. 8-15(c) has an input of 8 dBm, and an output of 38 dBm. What is
its voltage gain in decibels? What is its output voltage?

Design Problems
8-46 An amplifier is to be driven by a signal source with a source resistance (rS) of 1 k.
Determine the amplifier’s required input resistance (Rin) if no more than 2% of the
(voltage) signal can be lost due to input loading effects.
8-47 An amplifier is to be driven by a signal source with a source resistance (rS) of 3 k.
Determine the amplifier’s required input resistance (Rin) if no more than 5% of the
(voltage) signal can be lost due to input loading effects.
8-48 An amplifier is to drive a load of 300 . Determine the amplifier’s required output
resistance (Rout) if at least 95% of its output (voltage) signal is to reach the load.
8-49 An amplifier is to drive a load of 1 k. Determine the amplifier’s required output
resistance (Rout) if at least 99% of its output (voltage) signal is to reach the load.
When any analog electronic system is to be repaired, an oscilloscope should be used. A direct-
coupled (DC input) oscilloscope will quickly indicate DC bias problems. It will also show the
presence or absence of the signal as well as any signal distortion. However, if we are reasonably
certain a given system is functional, a digital multimeter (DMM) with either a dBV or a dBm
mode may be used.
8-50 An amplifier is to have a gain between 100 and 125. A DMM indicates a voltage of –25
dBV at its input and a reading of 27 dBV at its output. What is the amplifier’s gain in
decibels? What is its straight ratio voltage gain? Is the amplifier acceptable?
8-51 An amplifier is to have a gain between 100 and 125. A DMM indicates a voltage of –28
dBm at its input and a reading of 29 dBm at its output. What is the amplifier’s gain in
decibels? What is its straight ratio voltage gain? Is the amplifier acceptable?
EDA Problems
8-52 Given the amplifier depicted in Fig. 8-16, use Multisim to determine its voltage gains Av
and Avs. Also report the gains in decibels. Use an rS of 150 , an Rin of 5 k, an Av(oc) of
220, an Rout of 3 k, and an rL of 12 k.
8-53 Given the amplifier depicted in Fig. 8-17, use Multisim to determine its voltage gains Av
and Avs. Also report the gains in decibels. Use an rS of 300 , an Rin of 15 k, an Av(oc)
of 250, an Rout of 6.8 k, and an rL of 20 k.
8-54 The Multisim simulation in Fig. 8-20 is using three multimeters in their (AC) dB mode.
Based on XMM3 are the dB’s dBmV, dBV, or dBm? Explain. Use XMM2 and XMM1
to determine Av in decibels. Use XMM2 and XMM3 to determine Avs in decibels.

Figure 8-20.

9
Inverting Voltage Amplifiers
A mplification is as fundamental to electronics as the lever is to basic mechanics. Quite

often, our goal is to take a very weak electrical signal and increase its size without
altering its shape. The bipolar transistor was the first solid-state device to accomplish
this task. FET amplifier circuits followed and offered new design challenges and unique
advantages. Amplifier designs based on using discrete devices have fallen into obsolescence.
The preferred design approach employs the op amp linear integrated circuit as the “active
device”. However, the discrete BJTs and FETs remain important tools in modern electronic
designs but are often relegated to the embellishment of integrated-circuit-based designs. We
focus on the inverting voltage amplifiers in this chapter. (Inverting amplifiers provide 180o of
phase shift between the input and output signals – positive inputs generate negative outputs and
vice versa.) In this vein we address:
◼ The Role of Superposition in Amplifier Analysis
◼ BJT and FET Small-Signal Models
◼ BJT Gains: hfe and gm
◼ FET Transconductance
◼ BJT and FET Input Resistance
◼ BJT and FET Output Resistance
◼ The Common-Emitter Amplifier
◼ The Common-Source Amplifier
◼ Removing the Emitter Bypass Capacitor
◼ Partial Source Bypassing
◼ Meet the Op Amp
◼ The Op Amp Inverting Amplifier
◼ Applying EDA to Analyze Amplifier Circuits
◼ Derivations (Optional)

• Explain and apply the principle of superposition to amplifier circuits.
• Describe the hybrid-pi model used for BJTs and FETs.
• Define the BJT small-signal AC gains (the current gain) hfe and (transconductance)
gm.
Study Objectives 133

• Define transconductance (gm) as it relates to JFETS, DE-MOSFETs, and E-
MOSFETs.
• Describe the input resistance of a BJT and contrast it with that possessed by FETs.
• Relate the Early voltage to the output resistance of BJTs and FETs.
• Explain the relation between a BJT’s output resistance and the h-parameter called hoe.
• Explain the relation between an FET’s output resistance and the y-parameter called
yos.
• Analyze a common-emitter BJT amplifier circuit.
• Analyze a common-source FET amplifier circuit
• Explain the role of the emitter bypass capacitor, and the resulting effects when it is
removed.
• Explain the role of the source bypass capacitor, and the resulting effects when it is
removed.
• Analyze FET circuits with partial source bypassing.
• Interpret BJT and FET data sheets.
• Use EDA to analyze BJT, FET, and op amp amplifier circuits.
9-1 The Role of Superposition in Amplifier Analysis

An AC signal can cause a variation around the DC operating point of a BJT or an FET amplifier.
Superposition can be applied to analyze any BJT, FET, or op amp (integrated circuit) amplifier
circuit. It allows us to make a separate DC and AC analysis. To review, we re-state the
superposition theorem:
The superposition theorem is used to analyze electric circuits
in which there are two or more sources acting simultaneously
to produce a net voltage or current. To find this unknown
voltage or current by superposition, we find the component
produced by each source, in turn with all other sources set to
zero, and algebraically add the individual components to
arrive at the net effect. The primary constraint upon the
superposition theorem is the circuit must be linear.
The superposition theorem permits us to perform separate DC and AC analyses. However,

linearity is a requirement. This is accomplished by constraining the AC signals to be small. A
summary of the superposition approach is presented in Fig. 9-1. A general amplifier circuit is
shown in Fig. 9-1(a).
The DC analysis is conducted first and is indicated in Fig. 9-1(b). After the DC analysis is
performed, the AC analysis can be conducted. The AC equivalent circuit is developed in Fig. 9-
1(c). The coupling capacitors act like short circuits. In practice, a DC power supply also
behaves like a short circuit to the AC signal. To perform an AC analysis, we need to find an
appropriate AC equivalent circuit (or model) for the BJT, FET, or op amp. That is our next
endeavor. We shall see the small-signal parameters for both the BJT, and the FET are controlled
by their DC operating points. It is for this reason the DC analysis must precede the AC analysis.
The composite (DC and AC) response can be produced by simple addition as indicated in Fig. 9-
1(d).
134 INVERTING VOLTAGE AMPLIFIERS

(c) An AC analysis is performed.
Figure 9-1.
9-2 BJT and FET Small-Signal Models

The BJT can be viewed as a current-controlled, current source or as a voltage-controlled, current
source. The hybrid parameter or h-parameter model shown in Fig. 9-2 has been the standard BJT
model for many years. This model is often viewed by many beginning students as difficult to
understand. The h parameters change with bias point, temperature, and signal frequency. In
general, they are not very “friendly”. However, h parameters are included on many BJT
manufacturers’ data sheets. We will not use this model, but we will explain its parameters since
we are likely to encounter them on those data sheets.
BJT and FET Small-Signal Models 135

The h-parameter model is often characterized using a Kirchhoff's voltage law equation (Eq. 9-1)
for its input, and a Kirchhoff's current law equation (Eq. 9-2) for its output.27
Vbe = hieIb + hreVce (9-1)
Ic = hfeIb + hoeVce (9-2)
The hybrid parameter model derives its name from the fact it uses four (4) different parameters –
an impedance, a voltage-controlled voltage source, a current-controlled current source, and an
admittance. Equation 9-1 is detailed in Fig. 9-2(a) and Eq. 9-2 is described in Fig. 9-2(b).
+ -
(a)
KVL
Input = Voltage drop + Voltage source
Voltage
Output Current source

= + Shunt current
Current
KCL
(b)
Figure 9-2.
The parameter hie is the BJT’s common-emitter, short-circuit input impedance. It is measured with an
AC short28 placed between the collector and emitter terminals (which makes Vce = 0). By applying this
constraint, we can solve Eq. 9-1 for hie. This is given by Eq. 9-3. (The vertical line is read “with the
condition that”.)
27 Remember capital letters with lowercase subscripts represent rms quantities. This means Vbe, Ic, Vce, and Ib are rms quantities.
When all lowercase is used, we are dealing with dynamic (pure AC) quantities. Specifically, hie, hre, hfe, and hoe are all AC
quantities.
28 AC short circuits are produced by using capacitors, while AC open circuits are created by using inductors in series. These
reactive components will not affect the DC operating point.

Vbe = hieIb + hreVce = hieIb + hre(0) = hieIb
hieIb = Vbe
Vbe
hie = (9-3)
Ib Vce =0
The parameter hre is the BJT’s common-emitter, open-circuit reverse voltage gain. It is a
measure of the effect the output voltage Vce has upon the BJT’s input voltage Vbe with an open
(to AC) input circuit. This effect is exceedingly small.
Consequently, the voltage source is often approximated as a short circuit [see Fig. 9-3]. Its
definition is obtained by setting Ib to zero in Eq. 9-1 and solving for hre. The result is given by
Eq. 9-4.
Vbe = hieIb + hreVce = hie(0) + hreVce
hreVce = Vbe
Vbe
hre = (9-4)
Vce I b =0
The h-parameter model treats the BJT as a current-controlled, current source. The common-
emitter, short-circuit (forward) current gain is called hfe. It is defined by solving Eq. 9-2 for hfe
with Vce set to zero and is given by Eq. 9-5.
Ic = hfeIb + hoeVce = hfeIb + hoe(0) = hfeIb
hfeIb = Ic
Ic
h fe = (9-5)
Ib Vce = 0
The BJT’s common-emitter, open-circuit output admittance is called hoe. Because hoe is so low,
it is also often approximated as zero. (Remember: A low value of admittance means a large
value of impedance. If the admittance is nearly zero, the impedance is nearly infinite. A large
impedance may be approximated as an open circuit.) It is obtained by solving Eq. 9-2 for hoe
with Ib set to zero.
Ic = hfeIb + hoeVce = hfe(0) + hoeVce
hoeVce = Ic
Ic
hoe = (9-6)
Vce I b =0
The h-parameter model approximations are captured in Fig. 9-3.

The Hybrid-Parameter or H-parameter Model
Treats the BJT as a current-controlle d curre nt source .
Ib Ic
B C The h-parameters are often available

C + + on BJT data sheets.
B h ie The common-emitter h-parameters are:
+
= Vbe
h re Vce
- h f e Ib
h oe Vce
hie = the input impedance
hfe = the forw ard current gain
E hre = the reverse voltage gain
- - hoe = the output admittance
E E
Ib Ic
B C
+ + The reverse voltage generator
~
= Vbe h ie h oe Vce
h reVce is approximated as 0V.
h f e Ib
- -
E E
Ib Ic
B C The output admittance h oe
+ + is approximated as 0 siemens.
~
= Vbe h ie Vce
h f e Ib
- -
E E
Low-frequency approximation
Figure 9-3.
The much friendlier hybrid-pi model is shown in Fig. 9-4. This model treats the BJT as a
voltage-controlled, current source. The hybrid-pi model is an attractive choice for a several
reasons:
When the simplified low-frequency version is employed, it is as easy to use and the
values for the equivalent circuit components are given by simple relationships.
It is easily modified to permit its use in high-frequency amplifier analysis.
The same model can be used for field-effect transistors.
This model is often favored by linear integrated circuit manufacturers.

The Hybrid-Pi BJT Model
Treats the BJT as a voltage-controlled current source.
Ic
B
C
C +
B Vbe r g Vbe rO
m
= -
E
E
Ic
B
C
+
~
= Vbe r g Vbe
m
Low-frequency E
approximation
Figure 9-4.
The BJT’s equivalent base-emitter AC resistance is designated r. The BJT’s output resistance is
rO. It is often large enough to be treated as an open-circuit. Fundamentally, the BJT’s base-
emitter voltage Vbe is viewed as controlling the collector current Ic. The gain constant is the
transconductance gm. Each of these AC parameters is developed and discussed thoroughly in the
sections that follow.
FET Small-Signal Models

Just as the h-parameters are provided by many manufacturers on their BJT data sheets,
manufacturers tend to publish the short-circuit admittance (y) parameters on their datasheets for
FETs. The y-parameter model is shown in Fig. 9-5(a). Note the same FET small-signal models
are used for the n- (and p-) channel JFETs, DE-MOSFETs, and E-MOSFETs as indicated in Fig.
9-5. Although we shall not use the y-parameter model, we need to be familiar with it when we
work with manufacturers’ FET data sheets. The y-parameter model is often characterized by
input and output Kirchhoff’s current law equations. These are given by Eqs. 9-7 and 9-8,
respectively.
Ig = yisVgs + yrsVds (9-7)
Id = yfsVgs + yosVds (9-8)

In Eq. 9-7, the AC gate (input) current is Ig29. The common-source, short-circuit input
admittance is yis. This is the admittance (which is the reciprocal of impedance) between the gate
and source terminals as measured with an AC short placed between the drain and source
terminals to make Vds equal to zero. Solving Eq. 9-7 produces the definition of yis.
Ig
y is = (9-9)
V gs
Vds = 0
The common-source, short-circuit reverse transfer admittance is yrs. It is a measure of the

effect the AC (output) drain-to-source voltage Vds has on the input current Ig as measured with an
AC short across the input to make Vgs equal to zero. Its definition is given by Eq. 9-10.
Ig
y rs = (9-10)
V ds V gs = 0
In a similar fashion, Eq. 9-8 can be used to arrive at the common-source, short-circuit forward
transfer admittance yfs.
Id
y fs = (9-11)
V gs
Vds = 0
Solving Eq. 9-8 for yos yields the common-source, short-circuit output admittance.
Id
y os = (9-12)
Vds V gs = 0
Most beginning students shun admittance. It is just not as “intuitive” as impedance. To

compound the problem, these FET admittances have a real (conductance) and an imaginary
(capacitive susceptance) component. In rectangular form, this is written y = g + jb. However, at
low frequencies (e.g., 1 kHz) the capacitive susceptance is negligible, while the forward transfer
admittance is a (real) conductance. The FET’s hybrid-pi model is given in Fig. 9-5(b). The two
y-parameters we are usually interested in are yfs and yos. Specifically, we use yfs to find an
FET’s gm and yoe to determine its rO. We will investigate these ideas more fully as our studies
progress.
29 The gate current is small. We will again call it zero, but we should keep in mind that is an approximation.

Two FET Small-Signal Models
D D D
G or or
G G
S S S
Ig Id
D Id
G
+ +
G + D
y V
Vgs rs ds Vgs r gm Vgs rO
y y Vds
is os
y fs Vgs -
_ _
S
S
(a.) The y-parame te r model. (b.) The hybrid-pi mode l.
Figure 9-5.
9-3 BJT Gains: hfe and gm

Fundamentally, the BJT can be viewed as a current-controlled current source or as a voltage-
controlled current source. Specifically, the base current controls the collector current. The AC
beta () relates the rms values of the base and collector currents as defined in Eq. 9-13.
Ic
β= (9-13)
Ib
We shall use the common-emitter, short-circuit AC current gain hfe available on

manufacturers’ data sheets as an approximation of . Our  approximation30 is given by Eq.
9-14.
  hfe (9-14)
The hybrid-pi model regards the BJT as a voltage-controlled current source as illustrated in Fig.
9-4. In this case, the base-emitter voltage is assumed to control the collector current. This
becomes clear when we examine the common-emitter V-I transfer characteristic shown in Fig.
9-6. It has the same basic shape as a diode’s V-I characteristic curve.
30 Note the AC beta  is approximately equal to hfe while the DC beta DC is approximately equal to hFE. Yes, it is a matter of
subscripts, BUT the AC current gain hfe is not necessarily equal to the DC current gain hFE.
BJT Gains: hfe and gm 141

Common Emitter Transfer Curves
RC IC 10.0 mA
IC
RB +
8.0 mA
+ VCE VCC
+ (held + VCE = 10 V
VBB VBE _ constant) 6.0 mA
_
4.0 mA
input output
2.0 mA
0 200 400 600 800
VBE (mV)
(a) (b)
Figure 9-6.
Figure 9-6(b) reminds us the BJT is non-linear. A linear change in VBE will produce a non-linear
change in IC. When dealing with AC signals that cause the base-emitter voltage to increase and
decrease, we constrain the BJT operation to small signals31.
A Small Signal Produces an Approximate Linear Response

The BJT’s transfer characteristic has been reproduced in Fig. 9-7. Since we are dealing with the
total instantaneous changes in the base-emitter voltage and in the collector current, we use the
notation vBE and iC, respectively. We are looking at the variations about the DC operating point,
or Q point, as indicated in Fig. 9-7. The figure reveals that a small sinusoidal variation in vBE
produces a sinusoidal variation in iC. The collector current developed in response to the
variations in vBE has the same shape as vBE. This means we have a linear response.
31 The AC variation in the base-emitter voltage will be on the order of a few millivolts. It is not a constant 0.7 V for silicon
BJTs. That is a DC approximation.

time
time
Figure 9-7.
In contrast, Fig. 9-8 shows that a large signal variation in vBE produces a distorted (non-
sinusoidal) variation in iC. A non-sinusoidal signal means that harmonics are being generated.
Harmonics are sinusoidal signals with frequencies that are integer multiples of the fundamental’s
frequency. A non-sinusoidal periodic signal can be represented by an infinite series of sinusoidal
signals that are harmonically related to the original fundamental signal. For instance, if the
fundamental frequency is 1 kHz, the second harmonic is 2 kHz, the third harmonic is 3 kHz, and
so on. Generally, the amplitude of the harmonics tends to diminish as their order increases. This
means the second and third harmonics tend to be much more significant than the sixth and
seventh. The production of harmonics due to transfer characteristic non-linearity is called
harmonic distortion. Harmonic distortion is undesirable. Signals frequencies are being
produced in the output that are not present in the input signal.

time
time
Figure 9-8.
If we constrain our discussion to small-signal operation, a BJT behaves in a linear fashion. A
change in the base-emitter voltage produces a correspondingly proportional change in the
collector current. The gain a BJT offers can be defined as the ratio of its output (collector)
current to its input (base-emitter) voltage. This gain is described as a transfer conductance,
which is contracted to transconductance. Because this conductance effect is shared between the
BJT’s input and output, it also said to be a mutual conductance. Consequently, the symbol for
transconductance is gm. It is defined by Eq. 9-15.
ΔiC
gm = (9-15)
Δv BE
Equation 9-15 states that the transconductance is given by the ratio of the change in the collector
current (iC) to the (corresponding) change in the base-emitter voltage (vBE). Transconductance
has units of siemens (S). There is also a graphical interpretation of gm. The slope of a straight
line that is drawn tangent to the Q point on the transfer characteristic yields the
transconductance. This has been indicated in Fig. 9-9. While a graphical definition yields
insight, we generally prefer a formula.

Figure 9-9.
An equation for gm can be developed, but it requires the use of calculus (Derivations are
included at the end of this chapter for interested readers.). Do not let this trouble you. Calculus
is not required to use the formula. In Fig. 9-9, we see the transfer curve resembles the V-I
characteristic of a diode. The ideal diode V-I can be described by the Shockley diode equation.
Consequently, the fact that a similar exponential relationship describes the transfer characteristic
should not be too surprising. It is given by Eq. 9-16. The quantity ICES is the collector leakage
current as measured with a short placed between the base and emitter. It is like the reverse
saturation current (IS) associated with a reverse-biased p-n junction.
(9-16)
To find the transconductance, we take the derivative of Eq. 9-16 with respect to vBE and perform
a little algebra. The result is a simple equation for gm.
IC
gm = (9-17)
26 mV
Equation 9-17 states the transconductance (in siemens) is given by the ratio of the DC collector
current to 26 mV. The constant 26 mV is the voltage equivalent of room temperature. It is
significant to note the transconductance is controlled by the DC collector current. Increasing the
DC collector current raises gm. This idea is supported in Fig. 9-10.

Transconductance = Tangent Line Slope
10.0 mA
iC
8.0 mA
6.0 mA
Tangent line 2 at a higherCI
larger slope = larger m
g
4.0 mA Q2
2.0 mA
Q1 Tangent line 1 at a lowerCI

smaller slope = smallerm g
0 200 400 600 800
v (mV)
BE
Figure 9-10.
Example 9-1. A BJT is biased to have a DC collector current (IC) of 1 mA. Find its
transconductance (gm). What is its gm if IC is raised to 2 mA?
Solution: We apply Eq. 9-17 in each case. If IC = 1 mA, we obtain the result below.
IC 1 mA
gm = = = 38.46 mS
26 mV 26 mV
If IC is doubled to 2 mA, the transconductance will also double.
IC 2 mA
gm = = = 76.92 mS
26 mV 26 mV
Example 9-2. A BJT has a gm of 40 mS. Its base-emitter is being driven by a 50-mV peak-
to-peak AC signal. What is its peak-to-peak AC collector current?
Solution: We apply Eq. 9-15. Note the ratio of the AC (peak-to-peak) collector current (ic)
to the AC (peak-to-peak) base-emitter voltage is also equal to gm.
ΔiC i
gm = = c
Δv BE vbe
We solve for ic.
ic = gmvbe = (40 mS)(50 mV p-p) = 2 mA p-p
This result is illustrated in Fig. 9-11.

Using the Transconductance
ic 2 mA p-p
gm = 40 mS
output
50 mV p-p +
v be
ic = gmvbe = (40 mS)(50 mV p-p) = 2 mA p-p
_
input
Figure 9-11.
9-4 FET Transconductance

Although the BJT may be modeled as either a current-controlled current source or a voltage-
controlled current source, there is little doubt that the FET is most appropriately modeled as the
latter. Like the BJT, the FET transconductance (gm) specifies the control its input voltage has
on its output current. In Section 9-3, we developed the transconductance relationships for the
BJT. Let us expand the BJT relationships and contrast them with those for the FET.
For BJTs:
di C iC i I
gm =  = c = c (9-18)
dv BE v BE vbe Vbe
The notation “diC/dvBE” is read “the derivative of iC with respect to vBE”. It is the rate of change
in the collector current with respect to the base-emitter voltage. The change in theses quantities
is small (approaching zero). We need to be familiar with the notation and the notion of taking a
derivative. Do not let the mathematical details produce concern.
Equation 9-18 also tells us that gm for a BJT is given by the ratio of the change in the total
instantaneous collector current to the change in the total instantaneous base-emitter voltage.
(Except when either or both are at the DC level or zero.) A finite large change is denoted by
Greek letter  (delta). This transconductance is also given by the ratio of the instantaneous
collector current ic to the instantaneous base-emitter vbe. (Except when either or both are at
zero.) Further, this is the same as the ratio of the rms value of the AC collector current Ic to the
rms value of the AC base-emitter voltage Vbe. Compare these relationships with those for the
FET as given by Eq. 9-19.
FET Transconductance 147

For FETs:
di D i D i I
gm =  = d = d (9-19)
dv GS vGS v gs V gs
The notation “diD/dvGS” is read “the derivative of iD with respect to vGS”. To find an equation for
a BJT’s gm, we take the derivative of the equation that describes its transfer characteristic. The
basic approach for the FET is identical. We take the derivative of its (square law) transfer
equation which applies to JFETs and DE-MOSFETs. The required calculus is detailed at the end
of this chapter.)32 The result is given by Eq. 9-20.
ID
g m = g fso (9-20)
I DSS
Manufacturers typically specify the gm for JFETs and DE-MOSFETs at a VGS of zero volts. This
is denoted yfso at low frequencies (e.g., 1 kHz) this transfer admittance is a transfer conductance
gfso. Equation 9-20 shows us the gm for JFETs and DE-MOSFETs is controlled by the DC drain
current ID. The FET transfer characteristic and the meaning of gm is depicted in Fig. 9-12.
The transconductance of the BJT is given graphically by finding the slope of a line that is
drawn tangent to the Q-point on the BJT’s transfer characteristic curve. The same definitions
apply to the FETs.
Again, we see the transconductance is the slope of a line drawn tangent at the Q-point. If VGS is
equal to zero volts, the drain current will be equal to IDSS, and the transconductance is equal to
gfso. As the drain current is reduced, the transconductance decreases. (This also occurs for BJT.
Reducing its collector current lowers its gm.)
32 Only the bold visit Derivations. If you have taken a calculus course, it is an excellent review and illustrates how calculus can
be applied.

The Graphical Definition of g m
iD
2
 v GS 
i D = IDSS 1 -  I DSS Slope at iD withDI =DSS
I
 VGS(O FF)
is gfso.
The slope of a line drawn

tange nt at the Q-point is mg .
di D  iD
Q gm = = = the slope
dv GS  vGS
 iD
The e quation for g

m is obtaine d
by using calculus.
0 mA ID
0.0V vGS g m = g fso
VGS(OFF) IDSS
 vGS
Figure 9-12.
Example 9-3. A 2N5549 is an n-channel JFET that has a |yfso| at 1 kHz of 15 mS, and an IDSS
of 60 mA. What is its gm when its ID is 30 mA?
Solution: First, we note that at 1 kHz gfso  |yfso|. We then employ Eq. 9-20 directly.
ID 30 mA
g m = g fso = (15 mS) = 10.6 mS
I DSS 60 mA
E-MOSFET Transconductance
Equation 9-20 permits us to determine the gm of a JFET or DE-MOSFET at any given Q-point
(ID). While the equation that describes the transfer characteristic of an E-MOSFET is different,
the approach to finding an equation for gm is the same. Similarly, because some students can
injure themselves by merely looking at a calculus-based derivation, it too has been locked away
at the end of this chapter.
Generally, E-MOSFET manufacturers will specify the gm (gfs) at a given ID. Typically, we will
need to know gm at a different ID. Equation 9-21 addresses this need.
FET Transconductance 149

ID
g m = g m1 (9-21)
I D1
In Eq. 9-21 gm is the transconductance at ID and gm1 is the transconductance at ID1. The similarity
to Eq. 9-20 is striking. Particularly after we remind ourselves that gfso is the transconductance as
measured at ID = IDSS. The graphical definition of gm for the E-MOSFET is shown in Fig. 9-13.
Example 9-4. An n-channel E-MOSFET has a gfs of 25 mS at an ID of 25 mA. The E-
MOSFET has an ID(MAX) of 60 mA. What is its gm when its ID is 50 mA?
Solution: We employ then Eq. 9-21 directly.
ID 50 mA
g m = g m1 = (25 mS) = 35.4 mS
I D1 25 mA
This result makes sense. Raising the drain current produces as increase in gm.
The Graphical Definition of g m for the E-MOSFET
iD
I D(MAX) The slope of a line drawn

2
tange nt at the Q-point ismg .
ID = K[VGS – VGS(th) ] di D  iD
gm = = = the slope
dv GS  vGS
The equation for gm is obtaine d

by using calculus.
By knowing gm1 at D1
I ,
we can find gm at DI .
ID
g m = g m1
ID1
 iD
Q
vGS
0
V GS(th)
 v GS
Figure 9-13.

9-5 BJT and FET Input Resistance
In Fig. 9-14 we see the hybrid-pi model of the BJT has an equivalent AC resistance between its
base and emitter terminals called r. Our next problem is to obtain an equation that permits us to
find the r of a given BJT. The required relationships are summarized in Fig. 9-14. By Ohm’s
law, it is be clear that Eq. 9-22 yields r.
Vbe
rπ = (9-22)
Ib
We substitute Ib = Ic/ into Eq. 9-22 to arrive at Eq. 9-23.
Vbe V βV
rπ = = be = be (9-23)
Ib Ic β Ic
Next, we use our transconductance relationship. It may also be expressed in terms of rms values
as indicated in Eq. 9-24.
Ic
gm = (9-24)
Vbe
We solve Eq. 9-24 for Ic (Ic = gmVbe) and substitute the result into Eq. 9-23. This takes us to Eq.
9-25.
Vbe βVbe βVbe

rπ = = =
Ib Ic g mVbe
β
rπ = (9-25)
gm
Recall that gm is controlled by the DC collector current IC. Consequently, r is also controlled by
IC. (It should also be remembered that  is also affected by IC as explained in Section 7-2.)
BJT and FET Input Resistance 151

Finding r 
Ib Ic
Ib B
C
+ +
Vbe ~
= Vbe r g Vbe
m
_
-
r E
Vbe Vbe Vbe 

r = = = =
Ib Ic g m Vbe gm
Figure 9-14.
Example 9-5. A BJT has a gm of 40 mS. It also has an hfe of 200. Determine its r.
Solution: From Eq. 9-14, we set  equal to hfe.
 = hfe = 200
Next, we use Eq. 9-25 to find r.
β 200
rπ = = = 5 k
g m 40 mS
Example 9-6. A BJT has a  equal to 150. Find its gm and its r if IC is 4 mA. What are its
gm and r if IC is lowered (halved) to 2 mA?
Solution: We use Eq. 9-17 to find gm and we then apply Eq. 9-25 to find r.
IC 4 mA
gm = = = 153.8 mS
26 mV 26 mV
β 150
rπ = = = 975 
g m 153 .8 mS
Next, we find the parameters if IC = 2 mA.

IC 2 mA
gm = = = 76.92 mS
26 mV 26 mV
β 150
rπ = = = 1950 
g m 76.92 mS
Halving the DC collector current IC, also halved the transconductance gm, but doubled r.
The input impedance of JFETs as measured between the gate and source terminals is essentially
the resistance of a reverse-biased diode – perhaps hundreds of megohms. The input impedance
of MOSFETs is much higher – perhaps gigaohms33! Consequently, we shall approximate the
input impedance (r) of both JFETs and MOSFETs as infinite ohms. This is stated by Eq. 9-
26.
For FETs:
r    (9-26)
As we shall see, when we ignore the effects of rO, the FET model becomes an ideal voltage-
controlled current source.
9-6 BJT and FET Output Resistance

In Fig. 9-15 we have the output curves for a common-emitter BJT. At higher values of IC, an
increase in VCE produces a significant increase in IC. At lower values of IC, the same effect
occurs, but does not appear to be as pronounced. However, the same percentage change in IC
occurs in both cases. In 1952, James Early of Bell Laboratories developed an explanation. As
VCE is increased, the reverse bias on the collector-base p-n junction is also increased. When the
reverse bias across the collector-base p-n junction is increased, its depletion region widens. This
narrows the base region even more. This means that even more of the charge carriers from the
emitter region will form collector current. Thus, we observe an increase in IC. Early also
discovered that if the output characteristic curves are projected into the second quadrant, they
intersect at a common point. This point is called the Early voltage and is designated VA34. This
is indicated in Fig. 9-15. Negative values are indicated because they lie in the second quadrant.
33 Just as the “a” in mega is dropped in megohms, some prefer to drop the “a” in giga to form gigohms. Regardless, we are
dealing with resistances on the order of 109 ohms.
34 Sorry, James, but VE is taken to be the emitter-to-ground voltage.
BJT and FET Output Resistance 153

The Early Voltage:
The output curves project back to a common point.
IC I B3
The Early voltage

I B2
-VA
Typical values range
from -150 to -250 V
I B1
VCE
0
Figure 9-15.
The upward slope in the output characteristics can be included our BJT model by placing a
resistance in parallel with our dependent constant current source. This is the BJT’s output
resistance (rO). The significance of the Early effect is that it will permit us to obtain an equation
to predict the value of rO. Let us first see how a resistor in parallel with a current source
produces an upward slope in a V-I characteristic. In Fig. 9-16(a), we see the V-I curve for a
constant current source. A horizontal V-I curve means the current is not influenced by the
voltage across the current source. Figure 9-16(b) illustrates the effect of placing a 10-k resistor
in parallel with the 1-mA constant current source. The current through the combination is given
by Kirchhoff's current law. This leads us to Eq. 9-27.
VS
I = IS + (9-27)
RS
As the voltage across the source (VS) increases, the total current (I) also increases. Consequently,
we gain an upward slope. Substituting in the appropriate values for Fig. 9-16(b) into Eq. 9-27
produces the result given by Eq. 9-28.
VS VS
I = IS + = 1 mA + (9-28)
RS 10 k
With a little thought, we can see the V-I curve will have an upward slope of 0.1 mA/V.

The Effects of Source Resistance
V VS
I = IS + S = 1 mA +
RS 10 k
I
I (mA) I (mA)
+
2 2
1.8 1.8
IS
V
1.6 S 1.6
1 mA
1.4 1.4
1.2 _ I
1.2
1 1 +
0.8 0.8
I = IS = 1 mA I
S RS VS
0.6 0.6
1 mA 10 k 
0.4 0.4
_
0.2 0.2
0 0
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
VS (V) VS (V)
(a) (b)
Figure 9-16.
Now that we understand that placing a resistance in parallel with a constant current source
produces an upward slope, let us tie in the Early effect. The resistance in parallel with the
constant current source is a dynamic resistance35. Dynamic resistance is the change in voltage
(V) divided by the corresponding change in current (I). Consider Fig. 9-17(a). The dynamic
resistance of the current source is 10 k. In Fig. 9-17(b), we find the dynamic resistance
associated with the BJT’s V-I characteristic curve.
35 Dynamic resistance is introduced in Volume One Section 2-8.

Finding the Dynamic Resistance
I (mA)
2
1.8
1.6
I
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0 1 2 3 4 5 6 7 8 9 10
VS (V)
VS
I VS 10 V - 0 V
S R
S RS = = = 10 k
1 mA 10 k 
I 2 mA - 1 mA
(a)
I B2
Q
IC
 IC = IC - 0 = IC
-VA
0 VCE
VCE = VCE – (-VA) = VCE + VA  VA
VCE VA
rO = 
I C IC
(b)
Figure 9-17.

As demonstrated in Fig. 9-17(b), the BJT’s dynamic output resistance (rO) is given by Eq. 9-29.
ΔVCE VCE − ( − V A ) VCE + V A V A
rO = = =  (9-29)
ΔI C IC − 0 IC IC
A typical value for VA is 200 V. We use it routinely to estimate the value of rO. This
approximation is shown in Eq. 9-30. Again, the DC collector current establishes the value of this
AC parameter.
VA 200 V
rO   (9-30)
IC IC
Example 9-7. A BJT has an IC of 2 mA. Determine its rO.
Solution: From Eq. 9-30, we compute rO directly.
200 V 200 V
rO  = = 100 k
IC 2 mA
Recall the parameter hoe is called the open-circuit output admittance. It is the dynamic output
admittance as measured with the base circuit opened to the flow of AC base current. The
parameter rO is equal to the reciprocal of hoe if the DC operating points are similar.
1
rO = (9-31)
hoe
Example 9-8. A BJT has an IC of 2 mA and an hoe of 5 S. Determine its rO.
Solution: From Eq. 9-31, we compute rO directly.
1 1
rO = = = 200 k
hoe 5 S
Example 9-9. Repeat Example 9-8 if the BJT’s hoe of 5 S at an IC of 2 mA, but the BJT is
to be biased to have an IC of 1 mA.

Solution: Since rO is 200 k at an IC of 2 mA, we can use that information to determine the
Early voltage VA. We solve Eq. 9-30 for VA.
VA = ICrO = (2 mA)(200 k) = 400 V
Now we use Eq. 9-30 to find rO.
V A 400 V
rO   = 400 k
IC 1 mA
If we do not know the value of hoe then we cannot find the Early voltage. In these situations, we
use our “standard guess” of 200 V.
Putting it all Together – The Complete Hybrid-Pi Model

Now we have the relationships to determine all three of the parameters used in the hybrid-pi
model. They have been summarized Fig. 9-18. Also note the same model is used for both npn
and pnp BJTs. It is also important to recognize that all three of the small-signal AC parameters
are controlled by the DC collector current.
The Hybrid-Pi BJT Model
C Ic
B B
NPN C
+
E g Vbe rO 200 V
Vbe r m rO 
OR
= -
IC
C
B
PNP   hfe IC
E gm =
E  26 mV
r =
gm
Ic
B
C
+
~
= Vbe r g Vbe
m
- Low-frequency
approximation
E
Figure 9-18.

Like the BJT, FETs also exhibit output resistance (rO). When a JFET or a DE-MOSFET just
reaches pinch-off, their depletion regions extend across the channel and barely touch36.
However, as VDS is increased, the depletion regions begin to move back along the channel as
shown in Fig. 9-19(a). As can be seen, the channel length decreases slightly as VDS increases.
Consequently, the channel resistance decreases, and ID will increase slightly more as VDS is
raised. This gives an upward slope to the drain characteristic curves [see Fig. 9-19(b)]. This is
similar to the Early effect for the BJT. In fact, JFETs, DE-MOSFETs, and E-MOSFETs also
have an Early voltage as indicated in Fig. 9-19(b).
FET Output Resistance
The deple tion re gion me ets here at a
lower value of VDS .
_ +
p gate
-
n channel
n+
drain
-
_
p gate
The deple tion re gion move s back asDSV

is increased - shorte ning the le ngth of
the channel.
(a.) An increase in V DS shortens the channel length,
which decreases the channel resistance - JFET example.
iD VGS3
v DS VDS − (−VA ) VDS + VA VA
rO = = = 
i D ID − 0 ID ID
The Early voltage VGS2

-VA Q
ID
i D VGS1
v DS
0 VDS
v DS
(b.) The graphical determination of r Ofor JFETs, DE-MOSFETs,

and E-MOSFETs.
Figure 9-19.
36 The operation of the JFET is described in Volume One, Section 6-2. If Fig. 9-19(a) is baffling, a quick review will help – a
great deal!

Equation 9-32 defines rO. Its derivation is identical to that for the BJT’s rO described in Fig. 9-16(b).
Since rO is a dynamic (AC) resistance, it is given by the ratio of the change in the voltage across it to the
corresponding change in the current through it.
Δv DS V DS − ( − V A ) V DS + V A V A
rO = = = 
Δi D ID − 0 ID ID
VA
rO = (9-32)
ID
Generally, rO will be large enough to ignore. (Yes, just like the BJT.) However, we do
encounter instances when we need to know its value. We may use the short-circuit admittance
parameter yos to provide an estimate of rO. This requires that yos be specified at a low frequency
(e.g., 1 kHz). Once we have an estimate of rO, we can find the FET’s Early voltage VA. This
permits us to find rO for other values of ID. Consider Example 9-10.
Example 9-10. An n-channel 2N5457 JFET has a common-source output conductance gos
of 50 S (maximum) as measured with VGS = 0 V. The JFET also has a maximum IDSS of 5.0
mA. Determine the minimum rO if the JFET is operated with a drain current (ID) of 1.0 mA. By
the way, it is foggy in London simultaneously.
Solution: Let us sort this out. The last comment about London fog is probably extraneous.
The reciprocal of gos will produce a value for rO.
1 1
rO = = = 20 k
g os 50 S
The test conditions for this measurement indicate that VGS = 0 V. When VGS = 0 V, ID = IDSS =
5.0 mA. This revelation permits us to find the Early voltage VA. We apply Eq. 9-32 by solving it
for VA.
VA = ID rO = IDSS rO = (5 mA)(20 k) = 100 V
Now that we know VA, we can find the value of rO if ID = 1 mA. This time we apply Eq. 9-32
directly.
V A 100 V
rO = = = 100 k
I D 1 mA
This result should make sense. A lower value of ID should produce a larger value of rO. Take a
serious (informed) look at Fig. 9-19(b). With luck, that London fog and yours have dissipated.
If not, start again at the top of Example 9-10.

A summary of the hybrid-pi model for FETs is provided in Fig. 9-19. Contrast it with the
hybrid-pi model for BJTs depicted in Fig. 9-18. The formulas for determining the model
component values are different, but the use of identical models for the BJTs and FETs reduces
our work by half. This will become evident as we examine the common-emitter and common-
source amplifiers. Their AC equivalent circuits will be identical.
The FET Hybrid-Pi Model

N- or P-Channel Devices
D
Id
G
S G + D
VA I DSS yos
Vgs r gm Vgs rO rO = =
OR
ID ID
D -
G = ~
S
r =
S
OR
E-MOSFETs JFETs and DE-MOSFETs
D ID ID
gm = g m1 gm = g fso
I D1 I DSS
G
S Id
~
=
G +
gm Vgs
D
Vgs
-
Figure 9-20.
Figure 9-20 employs IDSS and yos to determine the Early voltage VA. The relationship is based on
our previous discussion.
 1  I DSS
V A = I D rO = I DSS   =
 y os  y os

9-7 The Common-Emitter Amplifier
Recall the three BJT configurations common-emitter, common-base, and common-collector are
defined by the terminals selected to serve as the input and output connections. The definitions
are repeated in Table 9-1.
Table 9-1. BJT Configurations
Configuration Input Terminal Output Terminal
Common Base Emitter Collector
Common Collector Base Emitter
Common Emitter Base Collector
A common-emitter amplifier circuit is shown in Fig. 9-21(a). Voltage-divider bias is used. An

emitter bypass capacitor (C3) is connected across the emitter resistor RE. This capacitor permits
the AC signal current to flow around (or bypass) RE. Consequently, the emitter bypass capacitor
effectively shorts out RE to the signal. This places the BJT’s emitter at AC ground. (The emitter
bypass capacitor is explained further in Section 9-9.) The AC equivalent circuit is drawn in Fig.
9-20(b). The BJT is replaced with its hybrid-pi model as indicated in Fig. 9-20(c).

DC
Figure 9-21.
As explained in Chapter 8, to characterize a voltage amplifier we must know its input resistance
Rin, its open-circuit voltage gain Av(oc), and its output resistance Rout. We find the input resistance
in Fig. 9-22.
Common-Emitter Input Resistance
Rin = R1 || R 2 || r 
rs Hybrid-pi Model Ic
B C
+ + g Vbe +
Vs m
R1 R2 Vbe r Vload
RC rL
- - -
E
Figure 9-22.
The Common-Emitter Amplifier 163

The common-emitter amplifier input resistance is presented to the signal source. It is given by
the parallel combination of bias resistors R1 and R2, and the BJT’s input resistance r. This stated
by Eq. 9-33.
Rin = R1 || R2 || r (9-33)
The open-circuit voltage gain Av(oc) is the voltage gain from the amplifier’s input to its unloaded
output. This means the load rL is disconnected temporarily. The open-circuit voltage gain is
determined as illustrated in Fig. 9-23.
Common-Emitter Open-Circuit Voltage Gain
Ic Disconnected
rs Hybrid-pi Model
B C Load
+ + +
Vs
g Vbe
m -
R1 R2 Vbe = Vin r = g Vin Vout rL
m RC
- - +
E -
Vbe = Vin
V
Ic = gmVbe = gmVin A v(oc) = out = - gmR C
Vin
Vout = -gmVinRC
Figure 9-23.
We observe that the input voltage Vin appears between the BJT’s base and emitter terminals.
Vbe = Vin (9-34)
This means the AC collector current will be directly proportional to Vin.
Ic = gmVbe = gmVin (9-35)
Note that because the collector current flows up through collector resistor RC, the upper
terminal is negative.
Vout = -gmVinRC (9-36)
Dividing both sides of Eq. 9-36 by Vin produces the equation for the open-circuit voltage gain.
The negative sign means there is a 180o phase shift across the common-emitter amplifier37.
This classifies it to be an inverting amplifier.
37 This agrees with the development of the common-emitter amplifier signal process presented in Volume One, Section 5-9.

Vout
Av ( oc ) = = − g m RC (9-37)
Vin
The last amplifier parameter we need to find is the output resistance Rout. The output resistance
is defined by Eq. 9-38.
Vout
Rout = (9-38)
I out Vs =0
With a little reflection, Eq. 9-38 appears to be in error. If the signal source is set to zero, how
can we have an output voltage and current? This is clarified in Fig. 9-24. While the input is
indeed set to zero, the output of the amplifier is excited artificially by an AC voltage source
Vout.38
Amplifier Output Resistance

rS
I out
Voltage
Amplifier
+
Vs = 0 Disconnected
Vout rL
Load
-
Vout
R out =
Iout V = 0
s
Figure 9-24.
38 This is fine for paper and pencil analyses. This is even fine for Multisim simulations. However, in the laboratory we will only
succeed in producing a great deal of smoke. Real voltage amplifier outputs will be damaged if driven by voltage sources.

In Fig. 9-25(a) we apply this definition to our common-emitter amplifier. Setting Vs to zero
forces Vin to be zero. Since Vin is zero, this means Vbe is also zero. With a Vbe of zero, the
voltage-controlled current source (gmVbe) must also be zero. A current source that produces no
current acts like an open circuit. As we can see in Fig. 9-25(b), the equivalent resistance
“looking into” the output must be equal to the collector resistor RC. This produces an extremely
simple relationship for Rout. It is equal to RC as defined by Eq. 9-39.
Rout = RC (9-39)
Common-Emitter Output Resistance

Hybrid-pi Model I out Disconnected
rS
B C Load
+ + +
g Vbe
m
Vs = 0 Vbe = Vin r Vout
R1 R2 = g Vin RC rL
=0 m
- - =0 -
E
Vout
R out =
(a) Iout V = 0
s
Figure 9-25.

Once we have determined Rin, Av(oc), and Rout, the common-emitter amplifier can be represented
by the universal amplifier model developed in Chapter 8. This is emphasized in Fig. 9-26. Once
this is achieved, we can find any (or all) of the amplifier quantities of interest. Specifically, we
can find the voltage gains Av, and Avs, the current gains Ai, and Ais, and the power gain Ap.
Replacing the Common-Emitter Amplifier with the Amplifier Model
VCC
Rin = R1 || R2 || r
R1 RC Vout
C1 C2 A v(oc) = = - gmR C
rS Vin
+ + R out = R C
Q1 +
+ rL V load
+
Vs
Vin R2 RE +
C3 -
-
-
(a) A common-emitter amplifier.

R out
rS
+
+ + +
Vs R in A rL Vload
Vin - v(oc) Vin
- -
-
Signal Source Voltage Amplifier Load
(b) Replacing the common-emitter amplifier with its model.
Figure 9-26.
Figure 9-27 gives the complete story. It is important to understand the strategy. The goal is not
a formula memorization exercise. When we encounter an amplifier, we must: 1.) perform a DC
analysis, 2.) determine the BJT small-signal parameters, 3.) ascertain the values of Rin, Av(oc), and
Rout, and 4.) conduct an amplifier analysis to find the voltage gains Av, and Avs, the current gains
Ai, and Ais, and the power gain Ap

DC
Figure 9-27.
Example 9-11. A common-emitter amplifier circuit is provided in Fig. 9-28. Ultimately,

we are interested in the voltage, current, and power gains it has to offer. Perform a DC analysis.
Solution: We use the approximate analysis detailed in Fig. 9-27(b). First, we find the base-
to-ground voltage.

R2 2.7 k
VB = VCC = (18 V) = 2.746 V  2.75 V
R1 + R2 15 k + 2.7 k
The emitter-to-ground voltage is one base-emitter voltage drop less positive than VB.
VE = VB – 0.7 V = 2.746 V – 0.7 V = 2.046 V  2.05 V
Now we can find the approximate collector current.
VE 2.046 V
IC  I E = = = 1.137 mA  1.14 mA
RE 1.8 k
Next, we determine the collector-to-ground voltage.
VC = VCC - ICRC = 18 V – (1.137 mA)(8.2 k) = 8.680 V  8.68 V
We complete the DC analysis by finding the collector-to-emitter voltage.
VCE = VC – VE = 8.680 V – 2.046 V = 6.634 V  6.63 V
Figure 9-28.
Example 9-12. Using the DC operating point determined in Example 9-11, find the values
for the BJT’s small-signal parameters. Specifically, find , gm, and r for IC = 1.137 mA.
Solution: We use the equations provided in Fig. 9-27(c). We go to the data sheet for the BJT
and find that hfe = 150 at IC = 1 mA.
  hfe = 150

Next, we determine the BJT’s transconductance.
IC 1.137 mA
gm = = = 43.71 mS  43.7 mS
26 mV 26 mV
We complete this stage of the analysis by computing the equivalent resistance “looking into” the
BJT’s base-emitter.
 150
r = = = 3.431 k  3.43 k
gm 43.71 mS
Example 9-13. Using the small-signal parameters calculated in Example 9-12, find Rin,
Av(oc), and Rout for the common-emitter amplifier given in Fig. 9-28.
Solution: We use the equations provided in Fig. 9-27(d). First, we find Rin.
Rin = R1 || R2 || r = 15 k || 2.7 k || 3.431 k = 1.373 k  1.37 k
The open-circuit voltage gain Av(oc) is defined with the load disconnected.
Av(oc) = - gmRc = -(43.71 mS)(8.2 k) = -358.4  -358
We conclude this stage of the analysis by determining Rout.
Rout = RC = 8.2 k
Now that we have the three basic amplifier parameters, we can find the various gains. This is
demonstrated in Example 9-14.
Example 9-14. Using the amplifier parameters calculated in Example 9-13, find Av, Avs, Ai,
Ais, and Ap for the common-emitter amplifier given in Fig. 9-28.
Solution: We use the equations summarized in Fig. 9-26(e). First, we find Av.
Vload rL 3 k
Av = = Av(oc) = (−358 .4) = −96.01  −96.0
Vin rL + Rout 3 k + 8.2 k
The voltage gain Avs includes amplifier input (and output) loading effects.
Vload Rin 1.373 k

Avs = = Av = (−96.01) = −39.08  −39.1
Vs rS + Rin 2 k + 1.373 k
Next, we find the current gain from the amplifier’s input to the load.

I out Av(oc)Rin (−358 .4)(1.373 k)
Ai = = = = −43.93  −43.9
I in rL + Rout 3 k + 8.2 k
The current gain from the input to the output includes input loading effects.
I out rS (2 k)
Ais = = Ai = (−43.93) = −26.05  −26.1
Is rS + Rin 2 k + 1.373 k
The power gain calculation is straightforward.
Ap = Av Ai = (-96.01)(-43.93) = 4218
Multisim will be used to verify the results of Examples 9-11 through 9-14. A 2N4124 npn BJT
is used and capacitor values have been defined. The capacitors establish the low-end frequency
response. (Frequency response is covered in Chapter 12.) The signal source is set to 7.071
mVrms at a frequency of 1 kHz. The Multisim DC values are given in Fig. 9-29.
Figure 9-29.
The Multisim instrument suite includes a two-channel oscilloscope that is connected as shown in
Fig. 9-30. Channel A is connected to the signal source and channel B is connected to the load.

Figure 9-30.
Double clicking on the oscilloscope icon causes the front panel to appear [see Fig. 9-31].
Cursor 2 Load Signal Source
Figure 9-31.

As can be seen in Fig. 9-31, the time base is adjusted to 500 µs/Division, the channel A (Signal
Source) sensitivity is set to 10 mV/Division, and the channel B (load voltage) sensitivity is set to
200 mV/Division. The default screen is black, which is changed to (printer-friendly) white by
clicking on Reverse. The trigger (synchronization) default is Auto. The waveforms will flicker
as the screen updates. To stop the flicker, select Single. (This means a single trace will be
displayed.) Stop the simulation. On the left side of the screen are two cursors. Click and hold
the left mouse button to drag the cursor into position. The values of channel A and B are
displayed. The peak values have been used to calculate Avs as – 39.3, which agrees favorably
with the value calculated in Example 9-14. Obviously, this inverting amplifier provides 180o of
phase shift between its input and output.
9-8 The Common-Source Amplifier

When the input signal is applied to an FET’s gate terminal, and the output signal is extracted
from its drain terminal, we are dealing with a common-source amplifier. The common-source
amplifier offers characteristics like the BJT common-emitter amplifier. To emphasize the
similarities, we offer Fig. 9-32.
The Common-Emitter and Common-Source Amplifiers

VCC V DD
R1 RD
R1 RC
C2 rS C2
rS
+ + + + +
+ Q1
C1 Q1 C1
+ rL Vload + rL
Vs + Vs
+ Vload
Vin R2 RE + Vin R2 +
C3 RS C3
- -
- - - -
(a) The common-emitter amplifier. (b) The common-source amplifier.
Figure 9-32.
In Fig. 9-33(a) we have a common-emitter BJT amplifier, and in Fig. 9-33(b) we see a common-
source amplifier. Both employ voltage divider bias. In “BJT Land” life is simple. The DC
analysis is straightforward, as made evident in Fig. 9-33(a). The “FET World” is not as kind. A
graphical analysis is necessary. This is depicted in Fig. 9-33(b). Once the Q-point is established,
the small-signal parameters can be determined. The BJT parameters are computed using the
relationships given in Fig. 9-33(c). The JFET parameters are determined using the equations
shown in Fig. 9-33(d). Recall that r for an FET is approximated as infinity (). This is an
important advantaged offered by the FET.
The Common-Source Amplifier 173

DC DC
Figure 9-33.
After the values of the small-signal parameters are determined, we draw the AC equivalent
circuit. Contrast Fig. 9-34(a) for the common-emitter amplifier with Fig. 9-34(b) for the
common-source amplifier. Except for the terminal designations and their effects on some of the
subscripts, the two circuits are virtually identical. Therefore, the corresponding equations for Rin,
Av(oc), and Rout are also essentially the same. Once the three amplifier parameters are determined,
the universal amplifier-equivalent circuit and relationships can be applied. This is indicated in
Fig. 9-34(c).

The AC Analysis
BJT Land FET World
rS Hybrid-pi Model Ic rS Hybrid-pi Model Id

B C G D
+ + g Vbe + + + +
m g Vgs
Vs Vs m
R1 R2 Vbe r Vload Vgs r Vload
rL R1 R2
RC RD rL
- - - - -
-
E S
Rin = R1 || R 2 || r Rin = R1 || R 2 || r = R1 || R 2
V Vout
A v(oc) = out = - g m R C A v(oc) = = - gmR D
Vin Vin
R out = R C R out = R D
(a) The common-emitter amplifier parameters (b) The common-source amplifier parameters
are calculated. are calculated.
Rout V rL
rS A v = load = A v(oc)
+ Vin rL + R out
+ + + V R in
Vs Rin rL V A vs = load = A v
Av(oc)V load Vs rS+ R in
Vin - in
- - i A v(oc) R in
A i = out =
- i in rL + Rout
Signal Source Voltage Amplifier Load
i rS
A is = out = A i
is rS+ R in
P
A p = out = A v A i
Pin
(c) Both amplifiers are analyzed using the same (universal) model.
Figure 9-34.
Example 9-15. Perform an AC analysis of the common-source amplifier shown in Fig. 9-
35. Specifically, find Rin, Av(oc), Rout, Av, Avs, Ai, Ais, and Ap. (The DC bias analysis for this
circuit was analyzed in Example 7-13.) Assume the 2N5457 has the minimum values IDSS(min) =
1 mA, and VGS(OFF-min) = -0.5 V, which means the drain current is 0.5 mA. The bias line results
are provided in Fig. 9-36.

Figure 9-35.
Figure 9-36.

Solution: We need JFET’s transconductance gfso to determine its gm at the amplifier’s Q-
point. (The required equation is provided in Fig. 9-33(d), which is repeated below.) Recall that
if the 2N5457 has the minimum IDSS, it must also have the minimum VGS(OFF) and the
minimum gfso. According to the manufacturer the 2N5457 has a minimum gfso of 1000 S [Fig.
9-35.] . We can now find gfs at our ID of 0.5 mA.
ID 0.5 mA
g m = g fso = (1000 S) = 707.1 S
I DSS 1 mA
The r of an FET is assumed to be infinite ohms, which means it acts like an open circuit
between its gate and source terminals.
r =  
Next, we determine the amplifier’s parameters Rin, Av(oc), and Rout as indicated in Fig. 9-34(b).
Rin = R1 || R2 = 910 k || 300 k = 225.6 k
Av(oc) = -gmRD = -(701.1 S)(3.3 k) = -2.333  -2.33
Rout = RD = 3.3 k
Notice the low value of open-circuit voltage gain Av(oc). This is typical of FETs. Their low gm
values (as compared with those of the BJT) result in characteristically low values of voltage gain.
(We complete our analysis by finding the requested voltage, current, and power gains. We draw
on the relationships summarized in Fig. 9-34(c). First, we find Av.
Vload rL 10 k
Av = = Av ( oc ) = (−2.333) = −1.754  −1.75
Vin rL + Rout 10 k + 3.3 k
Avs = = Av = (−1.754 ) = −1.747  −1.75
Vs rS + Rin 1 k + 225.6 k
Cool! Virtually no input loading effects. The large input resistance of the common-source
amplifier is responsible. The large input resistance is the primary advantage offered by using a
common-source amplifier. Next, we find the current gain Ai.
I out Av(oc)Rin (−2.333)(225.6 k)

Ai = = = = −39.58  −39.6
I in rL + Rout 10 k + 3.3 k
I out rS (1 k)
Ais = = Ai = (−39.58) = −0.1747  −0.175
Is rS + Rin 1 k + 225.6 k

Ap = Av Ai = (-1.754)(-39.58) = 69.42  69.4
With a little reflection, we can see the common-source amplifier does not offer voltage,
current, and power gains as large as those available from a common-emitter amplifier. Its
sole advantage is its large input resistance39. Accordingly, the common-source amplifier is an
excellent choice as an input stage of a cascaded amplifier system.
9-9 Removing the Emitter Bypass Capacitor

The removal of the emitter bypass capacitor permits an AC signal to be developed across the
emitter resistor. As we shall see, this results in AC negative feedback.
Figure 9-37.
To analyze this amplifier circuit, we must again determine Rin, Av(oc), and Rout. The AC
equivalent circuit is developed in Fig. 9-38.
39 FETs offer other advantages too. They offer lower (intermodulation) distortion levels, less noise, and better frequency
response than BJTs. We investigate distortion and frequency response in our later work.

DC
Figure 9-38.
The Resistance “Looking Into” the Base Terminal40

The resistance “looking into” the base terminal (rIN(BASE)) is important when the base terminal is
being used as an amplifier’s input. This is the case for the common-emitter (and common-
collector) amplifier(s). When finding the equivalent resistance looking into any terminal, the
attached external resistance is removed temporarily and replaced with an AC source (e.g., Vb)
to excite the circuit. The BJT is replaced with its simplified hybrid-pi model. This is illustrated
in Fig. 9-39.
40 A “terminal” resistance analysis is not a fatal condition - even though some algebra is required.
Removing the Emitter Bypass Capacitor 179

Finding r
IN(BASE)
Vb
r IN(BASE) =
Ib
Ib Ic
Ib B Hybrid-pi Model C
+ +
Q1
Vb r g Vbe
+ Vbe
=
m
E
Vb - - RC rL
RE RC rL
- +
RE I b + g mVbe

= g mVbe
-
Figure 9-39.
The collector current is given by Eq. 9-40, which is a rearrangement of Eq. 9-18.
Ic = gmVbe (9-40)
The emitter current is equal to the sum of the base and collector currents. Because the base
current is so small, the emitter current is approximately equal to the collector current. This
approximation is given in Eq. 9-41.
Ie = Ib + Ic = Ib + gmVbe  gmVbe (9-41)
Applying Kirchhoff’s Voltage Law around the input and using our approximation for Ic leads us
to Eq. 9-42.
Vb = Vbe + gmVbeRE = (1 + gmRE)Vbe (9-42)
By inspection of Fig. 9-39 and Ohm’s Law, we obtain Eq. 9-43.
Vbe = Ibr (9-43)
Substitution of Eq. 9-43 into Eq. 9-42 produces Eq. 9-44.
Vb = (1 + gmRE)Vbe = (1 + gmRE)Ibr (9-44)
Solving for Vb/Ib results in rIN(BASE).

Vb
rIN ( BASE ) = = (1 + g m R E )r = r + g m r R E (9-45)
Ib

Recalling that r = and substituting this into Eq. 9-45 yields Eq. 9-46.
gm


rIN ( BASE ) = r + g m r R E = r + g m RE
gm
rIN(BASE) = rπ + βR E (9-46)
This result is extremely powerful. Consider Fig. 9-40(a). If a BJT has an un-bypassed emitter
resistance, the equivalent resistance looking into the base terminal is extremely large and
approximately equal to the beta of the BJT times the un-bypassed emitter resistance. If the
emitter resistor RE is bypassed, we have the situation is shown in Fig. 9-40(b). The equivalent
resistance looking into the base terminal is equal to r.
the AC signal is concerned.
Figure 9-40.
When the emitter-bypass capacitor is removed, rIN(BASE) increases significantly, and this raises the
Rin of the amplifier. Examination of Fig. 9-41 permits us to arrive at Eq. 9-47.
Rin = R1 || R2 || rIN(BASE)  R1 || R2 (9-47)

The Effect on the Input Resistance
r IN(BASE) = r + R 
 E = R E (typically, and very large)
rs
1 k C
B
+ g Vbe
m
Vbe r
+ + +
Vs R1 R2
- RC rL
Vin Vload
E
- - 8.2 k 1.8 k 10 k 20 k -
RE
2 k
Rin = R 1 || R 2 || r in(BASE)  R1 || R 2
Figure 9-41.
Example 9-16. Perform a DC analysis on the common-emitter amplifier given in Fig. 9-42
(which is the same circuit given in Fig. 9-37). Specifically, determine VB, VE, IC, and VC using
approximations.
Solution: The DC analysis is not affected by the presence or absence of an emitter bypass
capacitor.
R2 1.8 k
VB = VCC = (10 V) = 1.800 V  1.80 V
R1 + R2 8.2 k + 1.8 k
VE = VB – 0.7 V = 1.800 V – 0.7 V = 1.100 V  1.10 V
VE 1.100 V
IC  I E = = = 0.5500 mA  0.550 mA
RE 2 k
VC = VCC - ICRC = 10 V – (0.5500 mA)(10 k) = 4.500 V  4.5 V

Figure 9-42.
Example 9-17. Find the small-signal parameters for the BJT used in the amplifier given in
Fig. 9-42. (The parameters are determined at the IC of 0.550 mA found in Example 9-16.)
Specifically, determine the values for gm, r, and rO.
Solution: We use the equations provided in Fig. 9-33(c). We go to the data sheet for the BJT
and find that hfe = 120 at IC = 0.5 mA.
  hfe = 120
Next, we determine the BJT’s transconductance gm and the BJT’s input resistance r.
IC 0.550 mA
gm = = = 21.15 mS  21.2 mS
26 mV 26 mV
β 120
rπ = = = 5.674 k  5.67 k
g m 21.15 mS
Normally, we assume rO is large enough to be ignored. We use Eq. 9-30 to compute its value.
200 V 200 V
rO  = = 363.6 k  364 k
IC 0.5500 mA
Example 9-18. Determine the input resistance Rin for the common-emitter amplifier given
in Fig. 9-42. Use Eq. 9-46 to find rIN(BASE) and Eq. 9-47 to find the amplifier’s input resistance.
(Figure 9-41 provides a summary.)
Solution: From Eq. 9-46 and the value of RE given in Fig. 9-42, and the small-signal
parameters determined in Example 9-17, we obtain the result below:

rIN(BASE) = r + RE = 5.674 k + (120)(2 k) = 5.674 k + 240 k =245.674 k  246 k
Obviously, r.is small in comparison to RE. Next, we employ Eq. 9-47 without the
approximation to determine Rin.
Rin = R1  R2  rIN(BASE) = 8.2 k  1.8 k  246 k = 1.467 k  1.47 k
Because rIN(BASE) is so large, it is reasonable to approximate RIN as being equal to the parallel
combination of R1 and R2 as indicated by Eq. 9-47. The approximation is close to the more
exact calculation above.
Rin = R1  R2  rIN(BASE)  R1  R2 = 8.2 k  1.8 k = 1.476 k  1.48 k
The Resistance “Looking Into” the Collector Terminal

The same basic approach used to find rIN(BASE) is taken to find rIN(COL). However, the BJT’s
output resistance rO must be included in its hybrid-pi model as illustrated in Fig. 9-45. This
analysis tends to be more involved41. Therefore, the details of the analysis are given at the end of
this chapter. The result of the analysis is given as Eq. 9-48.
 β RE 
rIN(COL)  1 +  rO (9-48)
 rπ + rB + RE 
The term rB is the equivalent AC resistance to ground “seen” by the base terminal. It is found by
setting Vs to zero temporarily. This is also defined in Fig. 9-45. The resistance “looking into”
the collector (rIN(COL)) is extremely large. When the emitter goes directly to AC ground, rIN(COL)
is equal to rO. However, when the emitter bypass capacitor is removed, rIN(COL) increases beyond
rO. Consequently, using RC to approximate the amplifier’s output resistance becomes an
even better approximation. This is defined by Eq. 9-49.
Rout = RC || rIN(COL)  RC (9-49)
41 The derivation is suitable for terrorizing undergraduates beyond the capacity for rational thought, irritating graduate students,
and amusing professors.

The Effect on the Output Resistance
rB = rS || R1 || R2 The signal source is replaced with a short circuit to find
rs rB .
1 k Ic
B C
+ g Vbe
m
Rout = R C || r IN(COL)  RC
Vbe r rO
+ + +
Vs R2
- RC rL
Vin R1 Vload
- - 8.2 k 1.8 k E 10 k 20 k -
RE
2 k
  rE 
Typically, the collector input resistance is very large. rIN(COL)  1 +  rO
The equivalent resistance "seen" by the base is used  r + rB + rE 
in its calculation.
rB = rS || R1 || R2
The amplifier's output resistance is equal to the value
of the collector resistor.
Figure 9-45.
Example 9-19. Determine the output resistance Rout for the common-emitter amplifier given
in Fig. 9-45. Use Eq. 9-48 to find rIN(COL) and Eq. 9-49 to find the amplifier’s output resistance.
Figure 9-45 provides the strategy.
Solution: We draw on the small-signal parameters determined in Example 9-17. (This

means  is 120, r is 5.674 k, and rO is 363.6 k.) We obtain the values of RC = 10 k and RE
= 2 k as given in Fig. 9-45. First, we must find the equivalent resistance “seen” by the base
terminal.
rB = rS  R1  R2 = 1 k  8.2 k  1.8 k = 596.1   596 
 β RE 
rIN(COL)  1 +  rO
 rπ + r B + R E 
 (120 )( 2 k) 
= 1 + 363 .6 k = 10.92 M
 5.674 k + 596.1  + 2 k 
The impedance “looking into” the collector has increased from 363.6 k to 10.92 M by
removing the emitter-bypass capacitor. We determine the exact value of Rout using Eq. 9-49, and
then employ the approximation.
Rout = RC || rIN(COL) = 10 k || 10.92 M = 9.991 k

The approximation that is offered in Eq. 9-49 is very reasonable.
Rout  RC = 10 k
The only quantity yet to be defined is Av(oc). As we have seen, the equivalent resistance “looking
into” the collector terminal is immense. Consequently, we can remove rO to simplify the circuit
as depicted in Fig 9-46. To arrive at the equation for Av(oc), we apply Kirchhoff's voltage law
around the input circuit and solve for Vbe.
-Vin + Vbe + IcRE = 0
We eliminate Ic by drawing on the fact that Ic = gmVbe, as indicated in Fig. 9-46.
-Vin + Vbe + gmVbeRE = 0
Next, we transpose –Vin to the right-hand side of the equation and factor out Vbe from the terms
on the left-hand side.
Vbe[1 + gmRE] = Vin
We divide both sides by the bracketed quantity to obtain Eq. 9-50.
Finding the Open-Circuit Voltage Gain

Define d polarity
B C
+ g Vbe
m
+
Ic
Vbe r
+
- -
Vin RC Vout rL Disconnecte d
E 20 k Load
- 10 k
RE + +

=I
2 k c
-
-
A voltage source is used to Actual polarity

re prese nt the input voltage.
Figure 9-46.
Vin
Vbe = (9-50)
1 + g m RE
Now we can obtain an equation for Vout. Note in Fig. 9-46 that Ic flows up through the collector
resistor RC. Consequently, the output voltage will be a negative quantity. Hence, by Ohm’s law,
we write Eq. 9-51.
Vout = - IcRC (9-51)

Figure 9-46 indicates that Ic = gmVbe. Substituting this relationship into Eq. 9-50 results in Eq. 9-
52.
Vout = - gmVbeRC (9-52)
Substituting Eq. 9-50 for Vbe into Eq. 9-52 takes us to Eq. 9-53.
− g m RC
Vout = − g mVbe RC = Vin (9-53)
1 + g m RE
Dividing both sides by Vin produces the equation for the open-circuit voltage gain Av(oc).
Vout − g m RC
Av(oc) = = (9-54)
Vin 1 + g m R E
In some circuits it is quite possible that gmRE >> 1. If this occurs, we obtain the approximation
provided by Eq. 9-55.
Vout − g m RC − g m RC R
Av(oc) = =  =− C
Vin 1 + g m R E g m RE RE
Vout R
Av(oc) = − C (9-55)
Vin RE
It is extremely important to note the approximate voltage gain is given by the ratio of the
collector resistor to the emitter resistor. This is made possible by the AC negative feedback.
Recall (from Chapter 7) that DC negative feedback creates bias circuits that are immune to BJT
parameter variation (e.g., DC). In this case, the voltage gain has been made independent of the
BJT’s gm. This is a good thing. The gm of a BJT varies with DC collector current and
temperature. Hence, it is now possible to design gm out of the gain equation. This results in a
stable and predictable voltage gain. Therefore, it should come as no surprise that AC negative
feedback is also used extensively in electronic circuits.
Example 9-20. The small-signal parameters calculated in Example 9-17 placed gm at 21.15
mS. Determine Av(oc) for the common-emitter amplifier given in Fig. 9-45. (The equivalent
circuit is given in Fig. 9-46.) Use the exact relationship given by Eq. 9-54, and approximate
relationship defined by Eq. 9-55.
Solution: First, we employ Eq. 9-54.
Vout − g m RC − (21.15 mS)(10 k)

Av(oc) = = = = −4.88
Vin 1 + g m RE 1 + (21.15 mS)(2 k)
We repeat the calculation using our approximation.

Vout R 10 k
Av(oc) = − C =− = −5
Vin RE 2 k
Obviously, the approximation is in close agreement (within about 2.5%) with the more accurate
relationship. The approximation works well for voltage gains with magnitudes of 10 or less.
A summary of the common-emitter amplifier relationships is given in Fig. 9-47. Removal of the
emitter-bypass capacitor reduces the available voltage gain but stabilizes it against BJT
parameter (gm) variation. The negative feedback at the emitter raises the input resistance, and
makes it less dependent on the BJT parameters  and gm. The negative feedback also raises the
resistance “looking into” the collector terminal. This also makes the output resistance less
susceptible to the BJT parameter rO. Av(oc), Rin, and Rout are under the control of the resistances
external to the BJT.
AC
Figure 9-47.
Beyond Formulas: What is AC Negative Feedback?

The meaning of AC negative feedback is depicted in Fig. 9-48. The input voltage vIN is
represented as a voltage source. The voltage across the emitter resistor vE is in phase with vIN.
The small base-emitter signal vBE controls the BJT’s collector and emitter currents. Kirchhoff's
voltage law is obeyed and is given by Eq. 9-55.
vIN = vBE + vE (9-55)
We solve Eq. 9-55 for vBE to obtain Eq. 9-56.

vBE = vIN - vE (9-56)
If a disturbance occurs and vE becomes too large, vBE is automatically reduced. The reduction in
vBE lowers iC and iE. Since vE = iERE then vE is lowered. Conversely, if a disturbance occurs and
vE becomes too small, vBE is automatically increased. The increase in vBE raises iC and iE. Since
vE = iERE then vE is increased. This is negative feedback.
The Meaning of Negative Feedback

By Kirchhoff's voltage law we haveINv = vBE + vE
Solving for vBE yields vBE = vIN - vE
vIN Q1 We also note that Ev = iE RE
+
+ If a system disturbance causesE vto increase then BE
v will be decreased.
-
vBE + vE
The decrease in vB E lowers iC and iE.
This lowers vE.
- R -
E The system counters (opposes) changes inE –v this is NEGATIVE
FEEDBACK.
Figure 9-48.
9-10 Partial Source Resistor Bypassing

As we saw in Section 9-9, if we remove the emitter bypass capacitor of a common-emitter
amplifier, the magnitude of its voltage gain decreased significantly. If the source bypass
capacitor is removed, the size of its voltage gain will also be reduced. In the case of common-
source amplifier, the size of its voltage gain is small initially. (In fact, some might describe it as
“puny” or even “wimpy”.) Removing the source bypass capacitor will often reduce the
magnitude of the voltage gain to less than unity. The common-source amplifier will then reduce
or attenuate its input signal. This is not good generally. One way to avoid this situation is to
partially bypass the source resistor as illustrated in Fig. 9-49.
Why Bother?
Before we examine Fig. 9-49 closely, we should understand the advantages offered by removing
a source bypass capacitor. When the source bypass capacitor is removed, negative feedback is
developed at the FET’s source terminal. Negative feedback reduces, but also stabilizes voltage
gain.42
42 Negative feedback offers additional advantages that are revealed in Volume Three, Chapter 13.
Partial Source Resistor Bypassing 189

Bypass Capacitor Removal
VCC V DD
R1 RD
R1 RC
C1 C2 rS C1 C2
rS
+ Q1 + + Q1 +
+ +
+ rL Vload + rL
Vs + Vs
+ Vload
Vin R2 RE Vin R2 RS1
- -
- - - -
+ C3
No bypass capacitor. RS2
Partial source resistor bypass.
Figure 9-49.
Contrast Fig. 9-49(a) with Fig. 9-49(b). In Fig. 9-49(a) the emitter resistor RE appears in both the
DC and AC equivalent circuits. In Fig. 9-49(b) RS1 and RS2 appear in the DC equivalent circuit,
but only RS1 appears in the AC equivalent circuit. Resistor RS2 is removed from the AC
equivalent circuit because of the action of capacitor C3. Despite partial source resistor
bypassing, the AC equivalent circuits of the two amplifiers are identical. This is illustrated in
Fig. 9-50.

The AC Equivalent Circuits are Identical
BJT Land
r IN(BASE) = r + R  r IN(COL) = VERY LARGE

 E = R E ( large)
rS C
B
+ g Vbe
m
Vbe r
+ + +
Vs - RC rL
Vin R1 R2 Vload
E
- - -
RE
Rin = R 1 || R 2 || r in(BASE )  R1 || R 2 Rout = RC || r in(COL)  R C
(a) The common-emitter amplifier.
FET World
r IN(GATE) r IN(DRAIN)
= r = INFINITE = VERY LARGE
rS D
G
+ g Vgs
m
Vgs r
+ + +
Vs - RD rL
Vin R1 R2 Vload
S
- - -
RS1
Rin = R 1 || R 2 || r in(GATE )  R1 || R 2 Rout = RD || r in(DRAIN)  R D
(b) The common-source amplifier.

Figure 9-50.

Figure 9-50(a) reminds us that the removal of the emitter bypass capacitor increases rin(BASE) and
rIN(COL). This has the effect of raising Rin and making the approximation that Rout is equal to RC
even better. Figure 9-50(b) emphasizes the similarities in the common-source amplifier.
Negative feedback will also raise rIN(GATE) and rIN(DRAIN)43.
The open-circuit voltage gain equations are provided in Fig. 9-51. While the BJT’s Av(oc) can be
approximated as the ratio of its collector resistor to its emitter resistor, this is not generally a
good approximation for FETs. This is true because the gm for FETs is usually much lower than
the gm for BJTs.
Common-Emitter/Common-Source Amplifier Comparison
BJT Land FET World
VCC V DD
R1 RD
R1 RC
C2 C2
C1 Q1 rs C1 +
rs + Q1 +
+
+ +
+ rL Vload
+ rL
Vs + Vs
+ Vload
Vin R2 RE Vin R2 RS1
- -
- - - -
+ C3
RS2
Rin = R1 || R 2 Rin = R1 || R 2
V - gmR C R V - gmR D
A v(oc) = out = − C A v(oc) = out =
Vin 1+ gmR E RE Vin 1 + g m R S1
R out = R C R out = R D
Figure 9-51.
43 Since we have approximated rIN(GATE) as infinite ohms, we must fight the urge to say, “it’s even more infinite”. This kind of
statement produces a violent response from mathematicians. In the world of the electronics technician, this is equivalent to
saying a circuit is “more open”. Technicians, being a more mellow breed compared to mathematicians, will simply offer a
funny look accompanied by the rolling of eyes.

Example 9-21. The common-source amplifier given in Fig. 9-52 was analyzed in Example
9-15. Observe the DC equivalent source resistance (RS1 + RS2 = 620  + 5.6 k = 6220 ) is
still darn near 6.2 k used in the circuit analyzed in Example 9-15. This means the DC
operating point is unchanged, and the small-signal parameters found in Example 9-15 are also
unaltered. Consequently, we can compare the performance of partial source resistor bypassing
with the bypassed case analyzed in Example 9-15. Find Rin, Av(oc), and Rout. Assume that gm is
still 707.1 S.
Solution: We draw on the relationships provided in Fig. 9-51(b).

Rin = R1 || R2 = 910 k || 330 k = 225.6 k
Vout − g m RD − (707.1 S)(3.3 k)
Av(oc) = = = = −1.622
Vin 1 + g m RS1 1 + (707.1 S)(620 )
Rout = RD = 3.3 k
Figure 9-52.
Example 9-21 reveals that partial source bypassing has not affected the Rin and Rout significantly.
However, Av(oc) has been reduced in size (as expected) from –2.33 to –1.62.

9-11 The Ideal Op Amp
Operational amplifiers (op amps) are high-gain, direct-coupled, voltage amplifiers. They were
originally designed using vacuum tubes and employed in analog computers44. By “direct-
coupled”, we mean they do not employ internal DC blocking capacitors. In Section 9-13, we
shall see that this means they can also operate on DC voltage levels. Operational amplifiers can
perform mathematical operations. Specifically, they can be used to scale, add, and subtract
voltage levels. They can also be used to perform calculus operations like integration and
differentiation. If non-linear feedback arrangements are used, the op amp can be used to
generate the logarithm and anti-logarithms of voltage levels. This capability makes it possible to
perform multiplication and division using some of the fundamental logarithm relationships
reviewed in Chapter 8.
The modern integrated circuit (IC) op amp has characteristics that approach ideal values. For
many situations, we can use three idealizations to understand how the op amp will behave in any
given circuit. The ideal op amp is depicted in Fig. 9-53.
Figure 9-53.
44As late as the 1970’s, high-speed digital computers were not available readily. Analog computers were used to generate real-
time simulations. This capability was used to help develop control system simulations. Very few analog computers are in use
today with the advent of high-speed digital computers, and digital signal processing.

In Fig. 9-53(a) we see the op amp has two input terminals. One is called the noninverting input
(+) terminal while the other is named the inverting input (-) terminal. The voltage between the
input terminals is described as the differential input voltage vDIF. The ideal model of the op amp
is a voltage-controlled voltage source. The open-circuit differential voltage gain is denoted
Avd(oc).
An example of the operation of the ideal op amp is provided in Fig. 9-53(b). Two DC voltage
sources are indicated. They represent DC input signal. If we start at ground and assign the signs
as we encounter them, we may generate a Kirchhoff’s voltage law equation. We then solve the
resulting equation for the differential input voltage.
-V2 + vDIF + V1 = 0
vDIF = V2 – V1 (9-57)
As we can see, the term “differential” means the input voltage is the difference in potential
between the noninverting and inverting input terminals. The output voltage is proportional
to the differential input voltage. We examine this concept more closely in Section 9-12.
Again, when we analyze circuits that employ op amps, we often use the ideal op amp concept.
The idealizations are presented in Fig. 9-54. The differential voltage gain is assumed nearly
infinite. Because of the op amp’s large differential voltage gain, its differential input voltage
vDIF is negligibly small. Ideally, the differential input voltage vDIF is approximately zero.
Return to Fig. 9-53(b). A differential input of only one millivolt produced an output voltage of
10 volts. Suppose the differential voltage gain is increased from 10, 000 to 100, 000. In that
case, a differential input voltage of only 0.1 mV is required to produce an output voltage of 10 V.
So, taken as a limit, we can say that as Avd(oc) approaches infinity, the differential input voltage
approaches zero.
Figure 9-54.
The Ideal Op Amp 195

The op amp has a small output resistance. An ideal op amp has an output resistance of
virtually zero. This means its output voltage is unaffected by the size of the load resistance
connected between its output terminal and ground. The op amp has a large input resistance. An
ideal op amp has an input resistance that is effectively infinite. This means the signal current
flow into its non-inverting and inverting input terminals is zero. As indicated in Fig. 9-54, two
other subtle assumptions are also made. Specifically, we assume no output offset exists and the
bandwidth in infinitely large. The means the output voltage is zero when the input voltage is
zero, and the amplifier’s response is unaffected by the frequency of the signal.
9-12 Meet the Real Op Amp

While the real op amp has performance limitations, it is still a marvelous device. A real op amp
is shown in Fig. 9-55.
Figure 9-55.
An Analog Devices AD713 is described as a quad operational amplifier. It is available in a 14-
pin DIP and a 16-pin Small-Outline Integrated Circuit (SOIC) package as illustrated in Fig. 9-55.
Many op amps are designed to work with a dual-polarity power supply. Most op amp
manufacturers specify their op amps for operation with a 15 V DC power supply. A summary
of the DC bias requirements of an op amp is provided in Fig. 9-56(a).

In addition to the positive and negative supply connections, it is extremely important that both
the inverting and non-inverting input terminals have a DC (direct coupled) bias path to
ground. This is because the inverting and non-inverting input terminals are tied to either the
base terminal of a BJT, or the gate terminal of an FET. This is shown in Fig. 9-56(b) and Fig. 9-
56(c), respectively. A BJT cannot be used as a linear amplifier without a DC base current (IB).
While an FET is a voltage-controlled device, without a DC path for its gate leakage current an
electrical charge can build up on its gate terminal. This will cause erratic behavior. It is for
these reasons that op amp inputs should never be allowed to be unconnected, or “float”.
Both inputs must have a

DC bias path to ground.
(a) Biasing requirements.
(b) BJTs require a DC base (c) FETs require a DC path for

current, which means a DC their leakage current.
bias path is required.
Figure 9-56.
Meet the Real Op Amp 197

Where the Heck is the Ground Pin?
Many beginning electronics students are bothered by the fact the op amp has no ground pin.
Basic BJT and FET amplifiers have a ground connection. Even the digital logic gates and
microprocessor integrated circuits have a ground pin45. No op amp ground pin is required
because the internal circuitry of the op amp is referenced to its negative supply input. However,
the circuitry within the op amp is balanced between its positive and negative DC supply inputs.
We can model the circuitry with equivalent (static) resistances as shown in Fig. 9-57. If we
apply Kirchhoff's voltage law, we see that vOUT is zero volts with respect to ground. For
example, we can start at the output ground reference and work our way back to ground through
the positive supply connection.
-vOUT –15 V + 15 V = 0 V
vOUT = 0 V
The Op Amp Has No Ground Pin
+
+V S
15 V
+
+ +
R 15 V
vDIF -
=0V + +
+ - R 15 V
-VS - -
vOUT
-15 V =0V
Figure 9-57.
What is the Op Amp’s Maximum Output Voltage Swing?
The op amp’s output voltage will normally lie between its power supply boundaries, or “rails”.
However, the output of a given op amp may not reach either its positive or negative supply rail.
This is because one or more transistors within the op amp will enter saturation. Op amp
manufacturers will generally provide the worst-case saturation limits on their data sheets.
However, as a rough rule-of-thumb, we can state that an op amp’s maximum output voltage is
approximately two volts less than its power supply rails. If an op amp output attempts to exceed
the saturation boundaries, clipping will result. This illustrated in Fig. 9-58. Newer op amp
designs offer outputs that are often within millivolts of the power supply rails.
45 This is just another reason why digital circuit design engineers, have an inherent distrust of analog circuit design techniques.

The Op Amp Output Voltage Swing
+V S
15 V
+ Positive Saturation Boundary = 13 V
Clipping
+
- vOUT
t
0
-
-VS
-15 V Clipping
Negative Saturation Boundary = -13 V
Figure 9-58.
What is the Op Amp’s Maximum Output Current?

The maximum output current that can be obtained from most IC op amps is approximately
10 mA46. To be sure of a given op amp’s exact limit, its manufacturer’s data sheet should be
consulted. Op amps include output short-circuit protection circuitry. It is designed to prevent op
amp destruction from momentary output shorts to ground or to either of the power supply rails.
If the load resistance to ground is too small, the op amp’s current-limiting circuitry will
produce clipping.
The Input Common-Mode Voltage Range

The voltage at either the inverting or the noninverting input terminals must be within the input
common-mode voltage range. Generally, the input common-mode voltage range is established
by the power supply rails. If an input voltage exceeds the input common-mode voltage range,
the op amp may behave in an unpredictable fashion. Specifically, the output may go to either the
positive or the negative output voltage saturation level. In some op amps a condition known as
latch up can occur. When an op amp experiences latch up, its output will effectively become
stuck at either the positive or the negative output voltage saturation level. The only way to
restore proper operation is to cycle the op amp’s DC power supplies from on to off, and then
back to on. The input (of course) must be within the input common-mode voltage range.
Modern op amps have a common-mode input range that is equal to its power supply rails.
46 The op amp specifications comply with the transistor convention. If the current flows out of the output terminal, it is given a
negative sign, and the op amp is said to be sourcing an output current. Conversely, if the current flows into the output
terminal, it is given a positive sign, and the op amp is said to be sinking an output current.
Meet the Real Op Amp 199

How Close to Zero Volts is the Differential Input Voltage?47
An op amp transfer characteristic curve is illustrated in Fig. 9-59. Typically, op amps exhibit
large open-circuit voltage gains. For example, the LF351 produced by National Semiconductor
Corporation is described as a “wide bandwidth JFET input operational amplifier”. It is available
in an 8-pin mini-DIP case style as illustrated in Fig. 9-59. The LF351 has a minimum voltage
gain of 25, 000, and a typical voltage gain of 100,000. The open-circuit voltage gain in Fig. 9-59
is assumed to be 100,000. For small differential input voltages (vDIF), the op amp’s output
voltage is proportional. The op amp behaves in a linear fashion. However, if the differential
input voltage becomes too large, the op amp’s output voltage will “bump its head” on a supply
rail. Specifically, it will enter its saturation region of operation. The output voltage swing of the
LF351 is given as a minimum of 12 V, with a typical swing of  13.5 V. The typical limit has
been used in Fig. 9-59. Close inspection of Fig. 9-59 reveals the linear region of operation
corresponds to (typical) differential input voltages of only 135 V. For linear operation, it is
reasonable to state the differential input voltage is negligibly small. We shall assume of value of
zero.
The Op Amp Transfer Characteristic
15 V
8 7 6 5
3 7
+ + 8-pin
v DIF 6
LF351 + LF351 mini-DIP
package
2 v OUT
- - 4
(top view)
-
1 2 3 4
-15 V
v OUT
13.5 V Non-linear saturation region

Linear region
of operation
v OUT
slope = = 100,000 = Avd(oc)
v DIF
-135  V
v DIF
0V
135  V
Non-linear saturation region -13.5 V
Figure 9-59.
47 The op amp transfer function shows how the controlling differential input voltage vDIF affects the controlled output voltage
vOUT.

9-13 The Op Amp Inverting Amplifier
The schematic diagram of an op-amp-based inverting amplifier is shown in Fig. 9-60(a). A
National Semiconductor Corporation LF411 op amp has been indicated. However, the op amp
used here is not critical. The LF411 is also available in an 8-pin mini-DIP package. The
corresponding pin numbers have been indicated on the schematic diagram. Observe that resistor
R2 is used to connect the op amp’s output to its inverting input terminal. This means negative
feedback is being used. This is an important observation. Do not let it trouble you. We
investigate the ramifications of negative feedback in Volume Three, Chapter 13. The op amp’s
ideal model is indicated in Fig. 9-60(b). We assume that the op amp’s input resistance is infinite.
This means the input terminals act like an open circuit. We also assume the op amp’s output
resistance is zero. Figure 9-60(b) also reminds us that because the op amp’s differential voltage
gain Avd(oc) is so large, the op amp’s differential input voltage vDIF is assumed to be zero.
The Op Amp Inverting Amplifier

8 7 6 5
R2
200 k 8-pin
LF411 mini-DIP
+V S package
(top view)
15 V
rs R1
2 7
- 1 2 3 4
600  + 10 k
6
+ LF411 +
Vs v 3 rL
IN
+ vLOAD
4 2 k
-
- -
-VS
-15 V
Source Load
(a) Basic amplifier.
The op amp's equivalent

input resistance is infinite.
The op amp's equivalent

output resistance is zero.
+
+
vDIF
A vd(oc)vDIF
+
-
-
- The op amp's voltage gain

The input voltage is is so large the differential
approximately zero. input voltage is approximately
zero.
(b) The ideal op amp model.
Figure 9-60.
The Op Amp Inverting Amplifier 201

The ideal op amp model is applied to aid in the analysis of the op-amp-based inverting amplifier
as shown in Fig. 9-60(a). Because the op amp’s noninverting input terminal is tied to ground,
and because the op amp’s differential input voltage is nearly zero, the inverting input terminal
is said to be a virtual ground. This is depicted in Fig. 9-61(a). All of vIN is impressed across the
input resistor R1. This establishes the input current iIN as given by Eq. 9-58.
v IN
iIN = (9-58)
R1
Figure 9-61(b) shows us that because the op amp’s input resistance is infinite, iIN is forced
through the feedback resistor R2. The feedback current is called iF.
vIN
iF = iIN = (9-59)
R1
Figure 9-61.

Observe in Fig. 9-62, the left end of the feedback resistor is tied to the virtual ground. Since the
output voltage is defined from the right end of the resistor with respect to ground, the output
voltage is developed across the feedback resistor R2. This leads us to Eq. 9-60.
vIN R
vOUT = −iF R2 = −iIN R2 = − R2 = − 2 vIN (9-60)
R1 R1
Figure 9-62.
If we divide both sides of Eq. 9-60 by vIN, we obtain the equation for the open-circuit voltage
gain.
vOUT R
Av(oc) = =− 2 (9-61)
vIN R1
The negative voltage gain indicates the amplifier circuit is inverting. The output signal will be
180o out of phase with the amplifier’s input signal. The amplifier circuit will have input
resistance that is equal to R1. This is made apparent by Fig. 9-61(a). We may rearrange Eq. 9-58
to obtain our equation for the input resistance Rin.
v IN
Rin = = R1 (9-62)
iIN
Since the circuit’s output is provided by the output of the op amp, the amplifier circuit’s output
resistance Rout will be approximated as zero.

Rout = 0  (9-63)
Since the amplifier circuit has an Rout of zero, a load resistance connected across its output
[e.g., Fig. 9-52(a)], will not affect its voltage gain. This means Av will be equal to Av(oc).
vLOAD rL rL r
Av = = Av(oc) = Av(oc) = L Av(oc) = Av(oc)
vIN rL + Rout rL + 0 Ω rL
Substitution of Eq. 9-61 provides us with Eq. 9-64.
vLOAD R
Av = =− 2 (9-64)
vIN R1
Figure 9-63.
Example 9-22. Analyze the op amp inverting amplifier circuit given in Fig. 9-63.
Specifically, determine its Rin, Rout, Av(oc), and Av. Find the peak load voltage if the peak vIN is 0.1
V. Find the peak load voltage if the peak vIN is increased to 1 V.
Solution: We use Eqs. 9-62 and 9-63 to find Rin and Rout, respectively.
Rin = R1 = 10 k

Rout = 0 
The open-circuit voltage gain Av(oc) and the output loaded voltage gain Av are equal. We use Eq. 9-64.
R2 200 k
Av(oc) = Av = − =− = −20
R1 10 k
If the peak vIN is 0.1 V, we use Av to determine the peak voltage across the load.
vLOAD = AvvIN = (-20)(0.1 V) = -2 V = 2 V peak -180o
If the peak vIN is 1 V, we use Av to determine the peak voltage across the load.
vLOAD = AvvIN = (-20)(1 V) = -20 V = 20 V peak -180o
Nope! This will not happen. If vIN is increased to 1 V peak, the amplifier will become non-
linear. Specifically, it will begin clipping its output signal as shown in Fig. 9-64.
Figure 9-64.

Example 9-23. Assume the vIN of the op amp inverting amplifier circuit given in Fig. 9-64
is 0.5 V DC. The circuit has been redrawn in Fig. 9-65. Find the load voltage. Repeat the
problem if vIN is –0.3 V DC.
Solution: The op amp is direct coupled. This means it will amplify a DC voltage. We have
already determined that Av is –20.
vOUT = AvvIN = (-20)(0.5 V) = -10 V
In a similar fashion, if vIN is –0.3 V, we use Av to determine vOUT.
vOUT = AvvIN = (-20)(-0.3 V) = 6 V
Figure 9-65.
Example 9-24. Determine the Avs of the op amp inverting amplifier circuit given in Fig. 9-
64.
Solution: In Example 9-22 we determined that Av is –20 and Rin is 10 k. Calculation of Avs
is straightforward. By inspection of the circuit, we note that rS = 600 Ω.
vLOAD Rin 10 k
Avs = = Av = (−20) = −18.9
vs Rin + rS 10 k + 600 

Obviously, the op-amp-based inverting amplifier is certainly easy to analyze. The DC analysis is
accomplished by inspection. (Yes, the DC power supply connections have been made, and both
inputs have a DC bias path to ground.) The op amp’s internal small-signal parameters can be
ignored. (This is true because a substantial level of negative feedback is used.) The negative
feedback offers a high degree of precision and predictability. Further, the op-amp-based
inverting amplifier also offers a response to DC. It makes good sense to avoid using the
common-emitter and common-source amplifiers48.
It was mentioned at the beginning of this chapter that discrete transistors are often used to
embellish integrated-circuit-based designs. Further, inside those marvelous integrated circuits,
there are transistors. The inputs and outputs are connected to transistors. Our work with the
discrete (CE and CS) amplifiers gives us much insight.
48 Take a hike you CE and CS amplifiers!

9-14 Applying EDA to Analyze Amplifier Circuits
Our general goal is to simulate the op amp inverting amplifier circuit given in Fig. 9-63. The
circuit uses an LF411 op amp. It is included in the Multisim library of parts. Click on Place and
then Component. The Group is Analog, and the Family is Op Amp. Rather scrolling through
the list of op amps, you can save time by typing “lf411” in the search space, Refer to Fig. 9-
66(a). As can be seen in Fig. 9-66(b), the LF411ACH has been selected. The only problem is
the function of the pins is not included. If we obtain the data sheet for the LF411, we will find
the pin functions as shown in Fig. 9-66(b). (If captured, the pin-out diagram can be pasted on the
schematic page for easy reference.)
(a.)
(b.)
Figure 9-66
Observe in Fig. 9-66(b) the symbol for the LF411 has its non-inverting terminal up. If you right
click on the symbol you can select Flip vertically. That was done in the Multisim schematic
given in Fig. 9-67. The Multisim schematic is provided in Fig. 9-67. Notice the signal source
voltage (Vs) and load voltage (Vload) are being measured.

Their ratio provides the voltage gain from the signal source to the load, which is Avs. This gain
was determined in Example 9-24 to be -18.9.
Figure 9-67
Next, we use the two-channel oscilloscope included in the Multisim suite of instruments. This
permits us to monitor the input (vIN) and output (vLOAD) signals in the time domain. This is
shown in Fig. 9-68. To minimize wiring on-page connectors can be used. Click on Place and
the Connectors. Select On-page connector. This was done twice, and both were named Load.
Multisim connects on-page connectors with the same name together.
Applying EDA to Analyze Amplifier Circuits 209

Figure 9-68
Double click on the oscilloscope icon and the front panel and traces will appear as shown in Fig.
9-69. Set the channel sensitivities to the indicated values and set the time base to its indicated
value. The black background can be changed to white by clicking on Reverse. The traces will
be running across the screen. Select Single on the trigger control and stop the simulation.
Figure 9-69

The oscilloscope is set to trigger on Channel A, which is our signal source. The output is bigger
and, 180o out of phase. If the signal source amplitude is increased to 0.7071 Vrms, the output
will be clipped as shown in Fig. 9-70. The input voltage (vIN) is one-volt peak. The gain (Av) is
-20. The peak output cannot reach 20 V. Saturation must occur. This idea was covered in
Example 9-22.
Figure 9-70
9-15 Derivations (Optional)49

Derivations of selected (key) equations are developed in this section. Differential calculus is
required in some cases. As an electrical engineer in an aerospace company for 31 years, I always
took the time to derive equations to obtain greater insight. Many engineers will take application
notes and design articles and accept the given equations. While saving time seems to be
efficient, I saw many instances in which a non-functional or under-performing design resulted.
If not allowed to derive equations on company time, lunch hours and after hours are always
available. My managers expressed appreciation for in-depth investigations.
49 “Abandon all hope ye who enter here” is the inscription at the gate to Hell first found in Dante's Divine Comedy.
Optimistically, you will gain insight in this section and not give up your hope.
Applying EDA to Analyze Amplifier Circuits 211

Transconductance of a Bipolar Junction Transistor (Eq. 9-17)
The graphical description of transconductance is provided by Fig. 9-71. It is the slope of a line
that is drawn tangent to the DC operating point (Q) on the transfer characteristic.
Figure 9-71
The general equation for the transconductance curve is given by Eq. 9-65.
The total instantaneous collector current is iC. The thermally-dependent leakage current is ICES50.
The natural number is e = 2.78128 approximately. The applied forward base-emitter bias is vBE.
The voltage equivalent of temperature is VT and is defined by Eq. 9-66.
The voltage equivalent of temperature (VT) is directly proportional to the product of Boltzmann’s
constant (k) of 1.381 X 10-23 J/K and the absolute temperature in Kelvins divided by q the charge
on a single electron of 1.602 X 10-19 C. The numerator has units of joules (J) and the
denominator is in coulombs (C). When we remember one volt is a joule per coulomb, VT is
certainly in volts.
50 ICES is the collector-emitter leakage current as measured with the base terminal shorted to the emitter terminal.

At 0 K, electrons in a semiconductor are at rest, or you can say they are in their zero-energy
state51. As we increase the temperature, an electron starts absorbing energy proportional to the
temperature and the constant of proportionality is k, which is Boltzmann’s constant. Hence, kT/q
is the voltage corresponding to this energy. Since the cause of this voltage is temperature, it is
called thermal voltage. It is an average value. For individual electrons, it can vary a little, but on
an average, it will be kT/q. At a given temperature, an electron can have energies which are
multiples of kT.
At a room temperature of 25oC, VT can be determined. First, we convert the room temperature to
Kelvins.
T(K) = T(oC) + 273 = 25 + 273 = 298 K
If we substitute 26 mV for VT in Eq. 9-65, the equation for the transconductance curve is
obtained as shown in Fig. 9-71. Equation 9-18 provided a symbolic definition of the
transconductance (gm). It is repeated below:
di C iC i I
gm =  = c = c
dv BE v BE vbe Vbe
Equation 9-65 provides the relationship that describes the transconductance curve.
We take the derivative of iC with respect to vBE to find gm.
We can eliminate the exponential by substituting in the transconductance curve relationship.
The tangent line is applied to the Q point (IC). The variation about the Q point is extremely small
(approaching zero). Consequently, the average value is equal to the DC collector current (IC).
As we have seen, VT is 26 mV at 25oC, and we arrive at Eq. 9-17.
51 According to the Laws of Thermodynamics, absolute zero cannot be attained. It is a theoretical limit.
Derivations (Optional) 213

Transconductance of JFETs and DE-MOSFETs (Eq. 9-20)
The square law equation applies to both JFETs and DE-MOSFETs.
The development of the equation for gm begins by taking the derivative of the square-law
equation with respect to VGS.
We go back to the square-law equation and perform some algebra. We divide both sides by IDSS
and then take the square root of both sides of the equation.
We can simplify our equation by substituting the last result into our equation for gm.
Next, we operate on the coefficient in front of the radical. Device manufacturers specify the gm
for an FET as measured with VGS set to zero. This means the FET’s drain current ID = IDSS. The
resulting transconductance is called gfso. The equation we developed for gm can be employed.
The last step is to substitute gfso into the equation for gm.

We have arrived at Eq. 9-20.
Transconductance of E-MOSFETs (Eq. 9-21)

Since the Enhancement-Only MOSFET or E-MOSFET does not conduct until its threshold
voltage (VGS(th)) is exceeded its square-law equation is necessarily different from the one used for
JFETs and DE-MOSFETs. The square-law equation for the E-MOSFET is below.
We obtain an equation for gm by by finding the derivative of the drain current with respect to the
gate-to-source voltage.
The device manufacturer usually provides the drain current (ID1) that occurs when the gate-to-
source voltage is at a specified value (VGS1).
The transconductance will have a different value (gm1) under this DC bias condition. We
determine its transconductance.
Next, we take the ratio of the two drain currents.
Taking the square root of both sides of the equation leads us to the result which follows.

Now we find the ratio of the transconductances and substitute in our previous result.
The result is below:
We solve for gm and arrive at Eq. 9-21.
The Resistance “Looking Into” the Collector (Eq. 9-47)

We are finding the resistance rIN(COL) for a common emitter amplifier with an unbypassed emitter
resistance. The development of the AC equivalent circuit is shown in Fig. 9-72.
Figure 9-72

Continue to work from Fig. 9-72(c). The signal source is set to zero which means it acts like a
short circuit. Resistors rS, R1 and R2 are in parallel. We find the equivalent base-to-ground
resistance rB. The collector resistor (RC) and the load resistance (rL) are in parallel. They are
disconnected while we are finding the equation for the equivalent collector input resistance
(rIN(COL)). These considerations are shown in Fig. 9-73.
r
IN(COL)
Disconnect the collector
( equivalent base-to- ( resistor and the load.

ground resistance
r
B
R r
C L
r R R R
S 1 2 E
Vs = 0
)
) to find r IN(COL)
Figure 9-73
The equivalent base-to-ground resistance rB is used. The collector resistor and the load
resistance are removed. An AC voltage source is used to excite the network and establish Vout.
r
IN(COL)
Ic
( Replace with the (
hybrid-pi model y
=
+ -
si
n
x,
Vout
-
x
∊[ The AC voltage source is used to
r R
B E 0,
excite the output and establishes
2
π] the output voltage.
Figure 9-74
Applying Ohm’s law produces rIN(COL).
In Fig. 9-75 the hybrid pi model is used to replace the BJT. The BJT’s output resistance ro
must be included.

Ic
y
ro =
+ -
si
n
x,
Vout
- x
r R ∊[
B E 0,
2
π]
Figure 9-75
The circuit is redrawn as illustrated in Fig. 9-76. The collector (C), emitter (E) and base (B)
nodes have been labeled. Kirchhoff’s current law is applied at node C to determine the current
through ro. The emitter resistor connects the the emitter node and the current through it is
approximately equal to the collector current. The controlling voltage Vbe is across r The
current I is the the base current. Observe that the polarity across r will be reversed based on the
base current I. We will handle that shortly.
gm V Ic
I be C
E
- - + y
Vbe r + ro =
I c - gmVbe + -
+ R
E
si
B - n
x,
Vout
r ~ - x
B = Ic ∊[
0,
2
π]
Figure 9-76

We write a Kirchhoff’s voltage law equation.
Next, we find the base current (I) through r by using current division.
Since the current (I) would tend to make Vbe the opposite polarity, we multiply the voltagr drop
by a -1.
We substitute our expression for I.
We substitute our expression for Vbe into the Kirchhoff voltage law equation for the output
voltage. The resistance rO is distributed and then the collector current Ic is factored out.
Both sides are divided by Ic to determine rIN(COL). The emitter resistor RE has a negligible
resistance compared to the other terms.
Equation 9-47 is the result. The result can be simplified further by remembering that r = gm
which means  = gm r

Drill Problems
Section 9-1
9-1. The DC and AC analyses may be conducted separately because of _____________
(Thevenin’s theorem, Norton’s theorem, the superposition theorem).
9-2. The analysis of a BJT amplifier begins with the ___________ (AC, DC) analysis.
9-3. Coupling capacitors behave as _____________(opens, shorts) to the DC bias, and behave
as _____________(opens, shorts) to the AC signal.
9-4. A DC power supply acts like (a/an) _____________ (short, open) circuit to an AC signal.
Section 9-2
9-5. The h-parameter model treats the BJT as a ____________ (voltage-, current-) controlled
__________ (voltage, current) source.
9-6. In words, explain the meaning of the four h-parameters hie, hre, hfe , and hoe. Also,
indicate which of the four parameters is often regarded to be negligible.
9-7. The hybrid-pi model treats the BJT as a ____________ (voltage-, current-) controlled
9-8. Name three advantages of using the hybrid-pi model.
9-9. In words, describe the three hybrid-pi model parameters r, rO, and gm associated with a
BJT.
9-10. The y-parameter model treats the FET as a ____________ (voltage-, current-) controlled
9-11. In words, explain the meaning of the four y-parameters yis, yrs, yfs, and yos. Also, indicate
which of the four parameters is often regarded to be negligible.
Section 9-3
9-12. The hfe of a BJT is 180. What is the BJT’s ?
9-13. The  of a BJT is 80. What the approximate value of its hfe?
9-14. Explain what meant by is a small signal? Why is it significant to the ac response of a
BJT?
9-15. A large-signal 3-kHz sine wave drives a BJT. Harmonic distortion results. What are the
frequencies of the second, third, and fourth harmonics?
9-16. A BJT is biased to have a DC collector current (IC) of 3 mA. Find its transconductance
(gm). What is its gm if IC is halved? Assume the BJT is at room temperature.
9-17. A BJT is biased to have a DC collector current (IC) of 0.25 mA. Find its
transconductance (gm). What is its gm if IC is doubled? Assume the BJT is at room
temperature.

9-18. A BJT has a gm of 50 mS. Its base-emitter is being driven by a 10-mV-peak AC signal.
What is its peak collector current? Determine the transistor’s DC collector current (IC).
The BJT is at room temperature (25oC).
9-19. A BJT has a gm of 20 mS. Its base-emitter is being driven by a 30-mV peak-to-peak AC
signal. What is its peak-to-peak AC collector current? Determine the transistor’s DC
collector current (IC). The BJT is at room temperature (25oC).
Section 9-4
9-20. An n-channel JFET has a gfso of 3 mS and an IDSS of 15 mA. Find its gm if its drain
current is 10 mA. Repeat the problem if ID is reduced to 5 mA.
9-21. An n-channel JFET has a gfso of 5 mS and an IDSS of 25 mA. Find its gm if its drain
current is 20 mA. Repeat the problem if ID is reduced to 5 mA.
9-22. An n-channel DE-MOSFET has a gfso of 4 mS, an IDSS of 20 mA, and an ID(MAX) of 50
mA. Find its gm if its drain current is 15 mA. Repeat the problem if ID is increased to 25
mA.
9-23. An n-channel DE-MOSFET has a gfso of 15 mS, an IDSS of 25 mA, and an ID(MAX) of 60
mA. Find its gm if its drain current is 15 mA. Repeat the problem if ID is increased to 50
mA.
9-24. An n-channel E-MOSFET has a gfs of 20 mS at an ID of 15 mA. The E-MOSFET has an
ID(MAX) of 60 mA. Determine its gm when its ID is 20 mA. Also find its gm if its ID is 40
mA.
9-25. An n-channel E-MOSFET has a gfs of 30 mS at an ID of 10 mA. The E-MOSFET has an
ID(MAX) of 75 mA. Determine its gm when its ID is 20 mA. Also find its gm if its ID is 5
mA.
Section 9-5
9-26. A BJT has a gm of 25 mS. It also has an hfe of 100. Determine its r.
9-27. A BJT has a gm of 45 mS. It also has an hfe of 150. Determine its r.
9-28. A BJT has a  of 85. Find its gm, and its r if IC is 0.5 mA. What are its gm and r if IC is
doubled?
9-29. A BJT has a  of 105. Find its gm, and its r if IC is 4 mA. What are its gm and r if IC is
halved?
9-30. What is the approximate r of an n-channel JFET?
9-31. What is the approximate r of an n-channel DE-MOSFET?
9-32. What is the approximate r of an p-channel E-MOSFET?
Section 9-6
9-33. A 100 A constant current source is in parallel with a 100-k resistor. Sketch the V-I
characteristic of the parallel combination. Let the voltage (on the horizontal axis) range
from 0 to 5 V.

9-34. A 200 A constant current source is in parallel with a 50-k resistor. Sketch the V-I
characteristic of the parallel combination. Let the voltage (on the horizontal axis) range
from 0 to 5 V.
9-35. A BJT has an IC of 5 mA. Determine its rO. What does its rO become if IC is doubled?
9-36. A BJT has an IC of 0.4 mA. Determine its rO. What does its rO become if IC is halved?
9-37. A BJT has an hoe of 20 S at an IC of 4 mA. Determine its rO.
9-38. A BJT has an hoe of 5 S at an IC of 1 mA. Determine its rO.
9-39. A BJT has hoe of 15 S at an IC of 4 mA. Find its Early voltage VA and determine its rO if
IC is 2 mA.
9-40. A BJT has hoe of 35 S at an IC of 5 mA. Find its Early voltage VA and determine its rO if
IC is 1 mA.
9-41. An npn BJT has an IC of 0.5 mA. It has a  of 150 at that IC of 0.5 mA. Find its gm, r,
and rO. Draw the schematic diagram of its hybrid-pi model. Label it completely. Also
draw and label its low-frequency approximation.
9-42. An pnp BJT has an IC of 5 mA. It has a  of 60 at an IC of 5 mA. Find its gm, r, and rO.
Draw the schematic diagram of its hybrid-pi model. Label it completely. Also draw and
label its low-frequency approximation.
9-43. An n-channel JFET has a low-frequency yos (gos) of 100 S as measured with VGS = 0 V.
The JFET also has an IDSS of 15 mA. Determine its rO if the JFET is operated with a DC
drain current (ID) of 5 mA.
9-44. An n-channel JFET has a low-frequency yos (gos) of 125 S as measured with VGS = 0 V.
The JFET also has an IDSS of 35 mA. Determine its rO if the JFET is operated with a DC
drain current (ID) of 5 mA.
9-45. A p-channel JFET has an ID of 5 mA. It has a low-frequency yos (gos) of 75 S as
measured with VGS = 0 V. The JFET also has an IDSS of 30 mA and a gsfo of 1.5 mS. Find
its gm, r, and rO. Draw the schematic diagram of its hybrid-pi model. Label it
completely. Also draw and label its low-frequency approximation.
9-46. An n-channel JFET has an ID of 2 mA. It has a low-frequency yos (gos) of 50 S as
measured with VGS = 0 V. The JFET also has an IDSS of 35 mA and a gsfo of 2.5 mS. Find
its gm, r, and rO. Draw the schematic diagram of its hybrid-pi model. Label it
completely. Also draw and label its low-frequency approximation.
Section 9-7
9-47. A common-emitter amplifier circuit is given in Fig. 9-77(b). Assume the BJT is silicon.
Perform an approximate DC analysis. Specifically, determine VB, VE, IC, VC, and VCE.
9-48. A common-emitter amplifier circuit is given in Fig. 9-77(a). Assume the BJT is silicon.
Perform an approximate DC analysis. Specifically, determine VB, VE, IC, VC, and VCE.
9-49. Using the IC found in Prob. 9-47, determine the gm, and r for the BJT given in Fig. 9-
77(b). Assume the hfe of the BJT is 100.

77(a). Assume the hfe of the BJT is 120.
9-51. Using the small-signal parameters found in Prob. 9-49, find Rin, Av(oc), and Rout for the
amplifier given in Fig. 9-77(b).
9-52. Using the small-signal parameters found in Prob. 9-50, find Rin, Av(oc), and Rout for the
amplifier given in Fig. 9-77(a).
9-53. Using the amplifier parameters found in Prob. 9-51, find Av, Avs, Ai, Ais, and Ap for the
common-emitter amplifier given in Fig. 9-77(b). [Refer to Fig. 9-27(e) for the formulas.]
common-emitter amplifier given in Fig. 9-77(a). [Refer to Fig. 9-27(e) for the formulas.]
Figure 9-77.
Section 9-8
9-55. Assume the common-source amplifier in Fig. 9-78 has an ID of 1.43 mA. Also, assume
the 2N5458 has a gfso of 1500 S and an IDSS of 2 mA. Draw the AC equivalent circuit.
Find Rin, Av(oc), Rout, Av, Avs, Ai, Ais, and Ap.
9-56. Assume the common-source amplifier in Fig. 9-78 has an ID of 1.43 mA. Also, assume
the 2N5458 has a gfso of 5500 S and an IDSS of 9 mA. Draw the AC equivalent circuit.
Find Rin, Av(oc), Rout, Av, Avs, Ai, Ais, and Ap.
9-57. In general, the common-source amplifier offers gains that are _______________ (greater
than, less than, the same as) those offered by a BJT common-emitter amplifier.

9-58. In general, the common-source amplifier offers an input resistance that is ____________
(greater than, less than, the same as) the input resistance offered by the BJT common-
emitter amplifier.
9-59. Given the amplifier circuit shown in Fig. 9-35, assume that VDD is changed to 15 V. Also
assume the 2N5457 has the maximum parameters. Perform a DC analysis to determine
ID, VG, VS, and VD. Find gm and r. Draw the AC equivalent circuit and compute Rin, Rout,
and Av(oc). Use the results to find Av, Avs, Ai, Ais, and Ap.
Figure 9-78.
Section 9-9
9-60. A common-emitter amplifier circuit is given in Fig. 9-42. Assume the BJT is silicon and
VCC is 9 V. Perform an approximate DC analysis. Specifically, determine VB, VE, IC, VC,
and VCE.
9-61. A common-emitter amplifier circuit is given in Fig. 9-42. Assume the BJT is silicon and
VCC is 15 V . Perform an approximate DC analysis. Specifically, determine VB, VE, IC,
VC, and VCE.
9-62. Using the IC found in Prob. 9-60, determine the gm, r, and rO for the BJT given in Fig. 9-
42. Assume the hfe of the BJT is 80.
9-63. Using the IC found in Prob. 9-61, determine the gm, r, and rO for the BJT given in Fig. 9-
42. Assume the hfe of the BJT is 150.

9-64. Using the small-signal parameters found in Prob. 9-62, find rIN(BASE), Rin, rIN(COL), and Rout
for the amplifier given in Fig. 9-42. Also determine the exact and approximate values of
Av(oc). Refer to Eqs. 9-54 and Eq. 9-55.
9-65. Using the small-signal parameters found in Prob. 9-63, find rIN(BASE), Rin, rIN(COL), and Rout
for the amplifier given in Fig. 9-42. Also determine the exact and approximate values of
Av(oc). Refer to Eqs. 9-54 and Eq. 9-55.
common-emitter amplifier given in Fig. 9-42. [Use the exact value of Av(oc) for your
calculations. Refer to Fig. 9-27(e) for the formulas.]
common-emitter amplifier given in Fig. 9-42. [Use the exact value of Av(oc) for your
calculations Refer to Fig. 9-27(e) for the formulas.]
9-68. When the emitter bypass capacitor in a common-emitter amplifier is removed, the input
resistance of the common-emitter amplifier will ________________ (increase, decrease).
9-69. When the emitter bypass capacitor in a common-emitter amplifier is removed, the
magnitude of the open-circuit voltage gain will ________________ (increase, decrease).
Section 9-10
9-70. Given the common-source amplifier shown in Fig. 9-52, assume the FET’s gm is 2 mS.
Draw the AC equivalent circuit. Find Rin, Rout, and Av(oc). Draw the equivalent circuit
using the universal voltage amplifier model. Compute Av, Avs, Ai, Ais, and Ap.
9-71. Given the common-source amplifier shown in Fig. 9-52, assume the FET’s gm is 1.5 mS.
Draw the AC equivalent circuit. Find Rin, Rout, and Av(oc). Draw the equivalent circuit
using the universal voltage amplifier model. Compute Av, Avs, Ai, Ais, and Ap.
9-72. Analyze the common-source amplifier provided in Fig. 9-79. Assume that the DE-
MOSFET has a gm of 3000 S. A DC analysis is unnecessary. Draw the AC equivalent
circuit. Find Rin, Av(oc), Rout, Av, Avs, Ai, Ais, and Ap.
9-73. Analyze the common-source amplifier provided in Fig. 9-79. Assume that the DE-
MOSFET has a gm of 4700 S. A DC analysis is unnecessary. Draw the AC equivalent
circuit. Find Rin, Av(oc), Rout, Av, Avs, Ai, Ais, and Ap.
9-74. Assume that ID is a constant. As RS1 in Figure 9-79 gets smaller, the open-circuit voltage
gain of the circuit ___________ (increases, decreases, remains the same).

Figure 9-79.
Section 9-11
9-75. The ideal op amp has a differential voltage gain that is __________ (zero, unity,
approaches infinity).
9-76. The ideal op amp has an output resistance that is __________ (zero, unity, infinity).
9-77. The ideal op amp has an input resistance that is __________ (zero, unity, infinite).
9-78. The ideal op amp has an output offset that is __________ (zero, unity, infinite), and a
bandwidth that is __________ (zero, unity, approaches infinity).
9-79. The op amp is very nearly an ideal _______________ (voltage-, current-) controlled
_____________ (voltage, current) source.
Section 9-12
9-80. Name the five (5) fundamental op amp terminals.
9-81. The acronym SMT stands for ___________ ___________ ___________.
9-82. The acronym SOIC stands for ___________ ___________ ___________

___________.
9-83. The op amp’s input terminals must each have ________________ (resistors in series, a
DC bias path to ground).

9-84. For an op amp circuit to function properly, both its inverting and noninverting input
terminals must _________________________ (have a resistor in series, have a DC bias
path to ground, be “floating”).
9-85. Op amps typically ____________ (do, do not) have a ground pin.
9-86. If an op amp has a ±17 V supply, what is its approximate maximum peak-to-peak
undistorted output voltage?
9-87. If an op amp has a ±5 V supply, what is its approximate maximum peak-to-peak

undistorted output voltage?
9-88. If an op amp has a ±17 V supply, what is its common-mode input voltage range?
9-89. If an op amp has a ±5 V supply, what is its common-mode input voltage range?
9-90. The op amp output in Fig. 9-80 becomes clipped. The op amp’s maximum output current
is 10 mA. What are the positive and negative clipping levels? Note that rL is 10k.
is 10 mA. What are the positive and negative clipping levels? Note that rL is changed
to 1k.
is 10 mA. What are the positive and negative clipping levels? Note that rL is changed
to 1.2 k.
9-93. An op amp has an output voltage of 12 V. It has a voltage gain of 15,000. Find its
differential input voltage vDIF to remain in its linear region of operation.
9-94. An op amp has an output voltage of 14 V. It has a voltage gain of 120,000. Find its
differential input voltage vDIF.

Figure 9-80.
Section 9-13
9-95. An op amp inverting amplifier circuit is shown in Fig. 9-81(a). Assume that rS is 100 ,
R1 is 20 k, R2 is 270 k, and rL is 7.5 k. Determine Rin, Rout, and Av(oc). Draw the
equivalent circuit using the universal amplifier model. Calculate Av, Avs, Ai, Ais, and Ap.
9-96. An op amp inverting amplifier circuit is shown in Fig. 9-81(a). Assume that rS is 2 k,
R1 is 20 k, R2 is 470 k, and rL is 3 k. Determine Rin, Rout, and Av(oc). Draw the
equivalent circuit using the universal amplifier model. Calculate Av, Avs, Ai, Ais, and Ap.
9-97. Explain briefly why pin 2 of the op amp in Fig.9-81(a) is a virtual ground.
9-98. If an oscilloscope were connected to pin 2 of the op amp in Fig. 9-81(a), we would expect
to see _______________ (a large, a small, no) AC signal.
9-99. Analyze the op amp inverting amplifier circuit given in Fig. 9-81(a). Use the indicated
component values. Specifically, find its Rin, Rout, Av(oc), Av, and Avs. Find the peak load
voltage if the peak vIN is 50 mV. Find the peak load voltage if the peak vS is 50 mV.
9-100. Analyze the op amp inverting amplifier circuit given in Fig. 9-81(a). Use the indicated
component values, but R2 is changed to 200 k. Specifically, find its Rin, Rout, Av(oc), Av,
and Avs. Find the peak load voltage if the peak vIN is 150 mV. Find the peak load voltage
if the peak vS is 150 mV.
9-101. Using the component values indicated in Fig. 9-81(b), determine vLOAD if vIN is –0.2
VDC. What is vLOAD if vIN is changed to +0.3 VDC?
9-102. Using the component values indicated in Fig. 9-81(b), assume that vIN is a 100-mV peak
sine wave riding on a 300-mV DC level. Sketch the vIN and vLOAD waveforms. Repeat
the problem if vIN is changed to a 100-mV peak sine wave riding on a –1-V DC level.

9-103. Assume that resistor R1 remains a 10 k and resistor R2 is changed to 200 k in Fig.
9-81(b). The input voltage vIN is a 200-mV peak sine wave riding on a 300-mV DC
level. Sketch the vIN and vLOAD waveforms. Repeat the problem if vIN is changed to a
150-mV peak sine wave riding on a 2-V DC level.
9-104. In general, the op amp inverting amplifier circuit can be used as a superior replacement
for the common-__________________ (collector, base, emitter) BJT amplifier.
9-105. In general, the op amp inverting amplifier circuit can be used as a superior replacement
for the common-__________________ (gate, source, drain) FET amplifier.
Figure 9-81.

Design Problems
9-106. A 2N4124 is to be used in the common-emitter amplifier circuit shown in Fig. 9-82.
Establish a collector current of about 1 mA. The bleeder current through the voltage
divider should also be about 1 mA. VE should be set to VCC/10. Rin should be greater
than or equal to 1.5 k. Rout should be 10 k, or less. The open-circuit voltage gain
Av(oc) must be equal to –5. Specify standard 5%-tolerance resistor values.
Figure 9-82.
9-107. An op amp inverting amplifier like the circuit shown in Fig. 9-81(a) is to have an input
resistance of 100 k and a voltage gain of -2. Determine the required values for R1 and
R2.
9-108. An op amp inverting amplifier like the circuit shown in Fig. 9-81(a) is to have an input
resistance of 2 k and a voltage gain of -100. Determine the required values for R1 and
R2.
9-109. The common-emitter amplifier shown in Fig. 9-83(a) was analyzed previously in
Examples 9-11 through 9-14. A direct-coupled oscilloscope is used to obtain the
waveforms indicated in Fig. 9-83(a). The amplifier is not working properly – since no
signal appears across the load. Select the most likely cause of the problem from the
following list of alternatives: (a) capacitor C2 is open, (b) rL is open, (c) capacitor C3 is
shorted, and (d) capacitor C3 is open.

9-110. The common-emitter amplifier shown in Fig. 9-83(b) was analyzed previously in
Examples 9-11 through 9-14. An AC-coupled oscilloscope is used to obtain the
waveforms indicated in Fig. 9-83(b). The amplifier is not working properly –the signal
that appears across the output is too small. Select the most likely cause of the problem
from the following list of alternatives: (a) capacitor C2 is open, (b) RC is open, (c)
capacitor C3 is shorted, and (d) capacitor C3 is open.
Figure 9-83.
9-111. The op amp circuit shown in Fig. 9-84 is malfunctioning. The novice technician only
made three DC voltage measurements before leaving for lunch. Your boss asks you what
could be wrong. Based on the measurements, you conclude one of the following: (a)
resistor R2 is too large, (b) the negative power supply connection is missing, (c) the op
amp’s noninverting input connection to ground is missing, (d) the positive power supply
connection is missing, (e) either (c) or (d), or (f) the technician should go on a diet.
DC
Figure 9-84.

9-112. The op amp circuit shown in Fig. 9-84 is malfunctioning. The novice technician only
made three DC voltage measurements before leaving for the day. Assume the voltage
readings are all positive values. Your boss asks you what could be wrong. Based on the
measurements, you conclude one of the following: (a) resistor R1 is too small, (b) the
positive power supply connection is missing, (c) the op amp’s noninverting input
connection to ground is missing, (d) the negative power supply connection is missing, (e)
either (c) or (d), or (f) the company should hire a new technician.
EDA Problems
9-113. Use Multisim to verify the effects of the possible fault options described in Prob. 9-109.
Use a C1 of 22 F, a C2 of 2.2 F, and a C3 of 330 F. The BJT is a 2N3904, and the
signal source is a 25-mV peak, 1-kHz sine wave.
9-114. Use Multisim to verify the effects of the possible fault options described in Prob. 9-110.
Use a C1 of 22 F, a C2 of 2.2 F, and a C3 of 330 F. The BJT is a 2N3904, and the
signal source is a 25-mV peak, 1-kHz sine wave.
9-115. Use Multisim to analyze the circuit shown in Fig. 9-81(a).
9-116. Use Multisim to analyze the circuit shown in Fig. 9-81(b).

10
Non-Inverting Voltage Amplifiers
N on-inverting voltage amplifiers have outputs that are in phase with the input signals.
There are two fundamental categories of non-inverting voltage amplifiers those that offer
a voltage gain of nearly unity (one) and those that offer voltage gains larger than unity.
As we shall see, the common-collector and common-drain voltage amplifiers provide a voltage
gain of about one. These are also called emitter followers, and source followers, respectively.
The op amp version is called a voltage follower. The followers are often used as buffers 52. The
common-base and common-gate voltage amplifiers offer voltage gains that are greater than one.
The op amp version is called a non-inverting amplifier. Our study of voltage amplifiers
continues in this chapter by offering:
◼ BJT Emitter Followers
◼ FET Source Followers
◼ The Op Amp Voltage Follower
◼ BJT Common-Base Amplifiers
◼ FET Common-Gate Amplifiers
◼ The Op Amp Non-Inverting Amplifier
◼ Applying EDA to Analyze Non-Inverting Amplifiers

• Explain the role of buffers and the nature of their input and output resistances.
• Analyze common-collector amplifier circuits.
• Analyze common-drain amplifier circuits.
• Analyze op amp voltage followers.
• Perform an analysis of the BJT common-base amplifier.
• Perform an analysis of the FET common-gate amplifier.
• Describe the input resistance problem associated with the common-base and
common-gate amplifiers.
• Analyze op amp non-inverting amplifier circuits.
• Employ EDA to analyze non-inverting amplifier circuits.
• Design voltage followers and non-inverting amplifiers using op amps.
52 Buffers present a large input resistance, a small output resistance, unity gain, and a wide bandwidth. In legal issues buffers are
attorneys, they handle your interests and offer resistance in every way.

10-1 BJT Emitter Followers
The emitter follower is another name for the common-collector amplifier. In Table 10-1 we
see a common-collector BJT amplifier employs the base terminal as its input, and the emitter
terminal as its output. It is called a follower because the signal at its output is in phase with its
input. Further, the emitter (output) signal is nearly equal in size to the input signal.
Table 10-1. BJT Configurations

Configuration Input Terminal Output Terminal
Common Base Emitter Collector
Common Collector Base Emitter
Common Emitter Base Collector
A typical circuit is shown in Fig. 10-1(a). Observe that a collector resistor (RC) is not required.
A decoupling, or bypass, capacitor C3 has been included. Its function is to ensure the collector
terminal is at AC (signal) ground. Once again, our goal is to determine the Rin, Rout, and the Av(oc)
for the amplifier. We shall see that it offers a large Rin, a small Rout, and an AV(oc) of nearly unity
(1). Most beginning electronics students are baffled by the fact that a BJT amplifier stage with
an Av(oc) of unity can be useful53. Admittedly, the emitter follower is not as popular as the
common-emitter amplifier but is often used as a buffer. The ideal buffer is defined in Fig. 10-
1(b). The ideal buffer has an infinite input resistance, a voltage gain of unity, and an output
resistance of zero. Consequently, the emitter follower’s large Rin, makes it a useful input buffer
stage in an amplifier system. Similarly, its small Rout makes the emitter follower an ideal output
buffer stage in an amplifier system. An amplifier system may include several amplifier stages.
Typically, the output of the first stage is connected to the input of the second stage. The output
of the second stage drives the input of the third stage, and so on. A cascaded amplifier system
block diagram is shown in Fig. 10-1(c). The input and output buffers provide a system design
with attributes that approach the ideal voltage amplifier. The overall system has a large Rin and
small Rout. Amplifier systems are explored in Chapter11.
53 In fact, many ask. “Why not just use a piece of wire?”
234 NON-INVERTING VOLTAGE AMPLIFIERS

The Emitter Follower
VCC
15 V Infinite Rin Zero Rout
R1 C3
rS 7.5 k +
2 k C1
+
+ Q1 C2
+ +
Vin Unity voltage gain
RE +
R2 rL
Vs Vload
- 7.5 k 3.6 k 20 k (b) The ideal buffe r.
- -
(a) The common-colle ctor (e mitte r follower) amplifie r.
rS
+
Vs rL +
Input Buffer Gain Stage(s) Output Buffer
Vload
-
Large Rin Small Rout
-
(c) A cascade d amplifier system.
Figure 10-1.
First, we shall find the input resistance Rin. The AC equivalent circuit of Fig. 10-1(a) is provided
in Fig. 10-2(a). We drive the base terminal with a voltage source Vb to provide the base-to-
ground equivalent voltage as shown in Fig. 10-2(b). The emitter-to-ground equivalent resistance
is denoted rE. This resistance represents the parallel equivalent resistance of rL and RE. Once the
hybrid-pi model is included, we arrive at the equivalent circuit shown in Fig. 10-2(c). The
circuit is almost identical to the common-emitter amplifier with an un-bypassed emitter resistor.
In fact, to find rIN(BASE), we invoke the same algebraic steps that were used in our analysis of the
common-emitter amplifier. As a review, we repeat that analysis, but “tweaked” to apply to the
emitter follower.
We use Fig. 10-2(c) and write a Kirchhoff’s voltage law equation.
Examination of Fig. 10-2(c) and application of Ohm’s law produces an equation for Vbe in terms
of the AC base current Ib.
Substitution of this result into the Kirchhoff’s voltage law equation produces the result below.
The base current is factored out.
A basic relationship for the BJT is the equation for .
BJT Emitter Followers 235

We apply this relationship to the Kirchhoff’s voltage law equation.
Dividing both sides by Ib takes us to Eq. 10-1.
rIN(BASE) = rπ + βrE (10-1)
where rE = RE || rL.
With reference to Fig. 10-2(c), input resistance is given by Eq. 10-2.
Rin = R1 || R2 || rIN(BASE)  R1 || R2 (10-2)
AC AC
Figure 10-2.
The Resistance “Looking Into” the Emitter Terminal
To find the output resistance of an amplifier, its signal source is set to zero, and we (artificially)
drive the output terminal54. When the base circuit is simplified, we obtain the equivalent base-
to-ground resistance rB defined in Fig. 10-3. To find rIN(EMITTER), we take the same approach we
used previously to find rIN(BASE). Observe that rE is removed and an AC source is connected to
the emitter as indicated in Fig. 10-3.
Finding r
IN(EM ITTER)
Q1
Ie
rB
+
= rS || R1 || R2 Ve
-
r IN(EMITTER) = Ve
Ie
Figure 10-3.
The equivalent circuit using the hybrid-pi model is developed in Fig. 10-4. The BJT is replaced
with its hybrid-pi model as shown in Fig. 10-4(a). The circuit has been redrawn in Fig. 10-4(b).
To simplify the analysis, both the controlling voltage Vbe and the direction of the controlled
source have been reversed. This means we will be working with Veb instead of Vbe.
By applying Kirchhoff’s current law to Fig. 10-4(c), we obtain Eq. 10-3 for Ie.
Ve
I e = g mVeb + (10-3)
rπ + rB
Since r and rB are in series [Fig. 10-4(c)], we may employ the voltage-divider rule to obtain Veb.
rπ
Veb = Ve (10-4)
rπ + rB
To eliminate Veb, we substitute Eq. 10-4 into Eq. 10-3. This takes us to Eq. 10-5.
54 If this were done in the laboratory, smoke is likely to appear, and only thing learned is to never do THAT again!

Ve rπ Ve
I e = g mVeb + = gm Ve + (10-5)
rπ + rB rπ + rB rπ + rB
Arriving at the Equivalent Circuit

to Find r IN(EMITTER)
Ie
+ -
Vbe r g Vbe
rB m
Vbe r g Vbe
m
- rC + +
Ie Ve
rB -
+ rC
Ve
(a) The BJT hybrid-pi model is included. (b) The circuit is redrawn.
Ie
+
Veb r g Veb
m
- +
Ve
rB -
rC
(c) The controlling base-emitter voltage and the current source are reversed.
Figure 10-4.
To obtain rIN(EMITTER) as defined in Fig. 10-3, we solve Eq. 10-5 for Ve/Ie. First, we rearrange it
slightly.
Ve rπ
+ gm Ve = I e
rπ + rB rπ + rB

1 g r
Ve + m π Ve = I e
rπ + rB rπ + rB
Since the two fractions have the same denominator, we can form a single fraction. We also
factor out the emitter voltage Ve simultaneously.
1 + g m rπ 
Ve   = Ie
r
 π + r B 
To isolate Ve, we multiply both sides by the reciprocal of the fractional coefficient, and then
divide both sides by Ie.
 r + rB 
Ve =  π Ie
1 + g m rπ 
Ve r + rB
rIN(EMITTER) = = π (10-6)
I e 1 + g m rπ
Again, we recall that r = /gm and substitute this into Eq. 10-6 to simplify the numerator and the
denominator.
 β   β 
   
Ve rπ + rB  g  + rB  g  + rB
rIN(EMITTER) = = =  m =  m
(10-7)
I e 1 + g m rπ  β  1+ β
1 + g m  

 gm 
Next, we recognize that  >> 1, and simplify Eq. 10-7 further.
 β   β 
   
 g  + rB  g  + rB β r
rIN(EMITTER)   m 
  m = + B
1+ β β β(g m ) β
Canceling the ’s that appear in the numerator and the denominator of the first term, takes us to
Eq. 10-8.
1 rB
rIN(EMITTER)  + (10-8)
gm β
where rB = rs || R1 || R2.

The equivalent resistance looking into the emitter tends to be rather low with typical values for
a small-signal transistor being on the order of 10 to 50 . The application of Eq. 10-8 is
depicted in Fig. 10-5. We employ it to find the output resistance of the emitter follower and use
it to find the input resistance of the common-base amplifier. In Fig. 10-5(a), we note that
rIN(EMITTER) is the common-collector amplifier’s approximate output resistance. As we can see
in Fig. 10-5(b), in the common-base configuration, rB is zero, and rIN(EMITTER) is the
amplifier’s approximate input resistance.
Using r IN(EMITTER)
r IN(EMITTER)  1
Q1 =
gm
rB
(typically low)
1 rB
r IN(EMITTER) = +
gm  rB = 0
(a) The common collector BJT amplifier. (b) The common base BJT amplifier.
Figure 10-5.
The Rout for the emitter follower is described in Fig. 10-6. The load resistance rL is disconnected
from the amplifier. It is not part of Rout. Equation 10-9 defines Rout.
1 r
Rout = RE || r IN(EMITTER)  rIN(EMITTER)  + B (10-9)
gm β
where rB = rs || R1 || R2.

The R OUT of the Emitter Follower
The resistance "looking into" the emitter is low.

Q1
(Disconnected)
rB
The emitter resistor is very large in comparison.
RE rL 1 r
R out = R E || rIN(EMITTER)  rIN(EMITTER)  + B
gm 
r IN(EMITTER)
R out
Figure 10-6.
The Open-Circuit Voltage Gain of the Emitter Follower

The last parameter we must find is the open-circuit voltage gain Av(oc). In Fig. 10-7(a), we see
the load rL is disconnected. The BJT is replaced with its hybrid-pi model in Fig. 10-7(b). The
BJT’s base-to-ground voltage is Vin. We apply Kirchhoff's voltage law around the input circuit
and solve it for Vbe.
Vin = Vbe + Vout
Vbe = Vin - Vout (10-10)
Next, we write the equation for Vout.
Vout  IcRE = gmVbeRE (10-11)
We substitute Eq. 10-10 into Eq. 10-11 and solve for Vout.
Vout = gmREVbe = gmRE(Vin –Vout) = gmREVin - gmREVout

We move the gmREVout term from the right side to the left side of the equation. (Remember to
change its sign.)
Vout + gmREVout = gmREVin
We factor out Vout.
Vout(1 + gmRE) = gmREVin

Finding A V(OC) for the Emitter Follower
rs
2 k
Q1 The load is disconnecte d.
+ +
Vs V in R1 R2 RE + rL
- 7.5 k 7.5 k 3.6 k Vout
- 20 k
-
(a) The emitter follower ac e quiv alent circuit.
Ib
Ic
B C
+ +
Vbe r g Vbe
Vin m
E
- -
+
RE
Vout I b + g mVbe

= g mVbe
-
(b) The hybrid-pi model is included.
Figure 10-7.
Next, we divide both sides by (1 + gmRE).
g m RE
Vout = Vin (10-12)
1 + g m RE
Dividing both sides of Eq. 10-12 by Vin provides us with Av(oc).
Vout g m RE
Av(oc) = = (10-13)
Vin 1 + g m RE
Example 10-1. Perform a DC analysis on the emitter follower given in Fig. 10-8.
Specifically, determine VB, VE, IC, and VC using approximations.
Solution: The DC analysis is like our previous analysis of a common-emitter amplifier.

R2 7.5 k
VB = VCC = (15 V) = 7.500 V  7.50 V
R1 + R2 7.5 k + 7.5 k
VE = VB – 0.7 V = 7.500 V – 0.7 V = 6.800 V  6.80 V
VE 6.800 V
IC  I E = = = 1.889 mA  1.89 mA
RE 3.6 k
VC = VCC = 15 V
Example 10-2. Find the small-signal parameters for the BJT used in the amplifier given in
Fig. 10-8. Specifically, determine the values for gm and r when IC = 1.889 mA.
Solution: We go to the data sheet for the BJT and find that hfe = 200 at IC = 2 mA.
  hfe = 200
Next, we determine the BJT’s transconductance gm and r.
VCC
15 V
R1 C3
rS 7.5 k +
2 k C1
+
+ Q1 C2
+ +
Vin
RE +
R2 rL
Vs Vload
- 7.5 k 3.6 k 20 k
- -
Figure 10-8.
Example 10-3. Determine the input resistance Rin for the emitter follower given in Fig. 10-
8. Use Eq. 10-1 to find rIN(BASE) and Eq. 10-2 to find the amplifier’s input resistance.
Solution: First, we find the equivalent emitter-to-ground resistance rE, and then rIN(BASE).
rE = RE || rL = 3.6 k || 20 k = 3.051 k
rIN(BASE) = r + rE = 2.753 k + (200)(3.051 k) = 2.753 k + 610 k  613 k
Obviously, r.is small in comparison to rE. Next, we employ Eq. 10-2 to determine Rin.
Rin = R1  R2  rIN(BASE) = 7.5 k  7.5 k  613 k = 3.727 k  3.73 k
Because rIN(BASE) is so large, it is reasonable to approximate RIN as being equal to the parallel
combination of R1 and R2 as indicated by Eq. 10-2.
Rin = R1  R2  rIN(BASE)  R1  R2 = 7.5 k  7.5 k = 3.750 k  3.75 k
Example 10-4. Determine the output resistance Rout for the emitter follower given in Fig.
10-8. Use Eq. 10-8 to find rIN(EMITTER) and Eq. 10-9 to find the emitter follower’s output
resistance.
Solution: First, we must find the equivalent resistance “seen” by the base terminal.
rB = rS  R1  R2 = 2 k  7.5 k  7.5 k = 1.304 k  1.30 k
1 r 1 1.304 k
rIN(EMITTER)  + B = + = 13.76  + 6.52  = 20.28   20.3 
gm β 72.65 mS 200
We determine the exact value of Rout using Eq. 10-9, and then employ the approximation.
Rout = RE || rIN(EMITTER) = 3.6 k || 20.28  = 20.17 
The approximation that is offered in Eq. 10-9 is extremely reasonable.
Rout = RE || rIN(EMITTER)  rIN(EMITTER)= 20.3 
Example 10-5. Determine the open-circuit voltage gain of the emitter follower circuit given
in Fig. 10-8.
Solution: We use Eq. 10-13.
Vout g m RE (72.65 mS)(3.6 k) 261 .54

Av(oc) = = = = = 0.9962  0.996
Vin 1 + g m RE 1 + (72.65 mS)(3.6 k) 262 .54

Obviously, the voltage gain of the emitter follower is close to unity.
Example 10-6. Find Av, Avs, Ai, Ais, and Ap for the emitter follower given in Fig. 10-8.
Solution: We use the amplifier parameters determined previously. (Specifically,

Rin = 3.750 k, Rout = 20.17 , Av(oc) = 0.9962, rL = 20 k, and rs = 2 k) First, we find Av.
Vload rL 20 k
Av = = Av(oc) = (0.9962 ) = 0.9952  0.995
Vin rL + Rout 20 k + 20.17 

Avs = = Av = (0.9952 ) = 0.6490  0.649
Vs rS + Rin 2 k + 3.750 k
Next, we find the current gain from the amplifier’s input to the load.
I out Av(oc)Rin (0.9962 )(3.750 k)

Ai = = = = 0.1866  0.187
I in rL + Rout 20 k + 20.17 
I out rS (2 k)
Ais = = Ai = (0.1866 ) = 0.06490  0.0649
Is rS + Rin 2 k + 3.750 k
Ap = Av Ai = (0.9952)(0.1866) = 0.1857  0.186
A summary of the emitter follower relationships is given in Fig. 10-9.

Emitter Follower Summary
VCC An emitter follower is a common-collector
amplifier.
C3
R1 An emitter follower is often used as a
+
rS C1 buffer stage.
Q1 r IN(BASE) = r +  rE where rE = RE || rL
+
C2 (Typically, v ery large)
+ + +
Vs + Rin = R1 || R 2 || r IN(BASE)  R1 || R 2
Vin R2 RE rL Vload 1 rB
- rIN(EMITTER)  + where rB = rS || R 1 || R 2
- gm 
-
(Typically, v ery small)
Rout = R E || r IN(EMITTER)  r IN(EMITTER)
V gmR E
A v(oc) = out =  1
Vin 1 + gmR E
(The signal at the e mitte r is almost e qual
to the input signal at the base.)
Figure 10-9.
10-2 FET Source Followers

The source follower (or common-drain amplifier) is depicted in Fig. 10-10. Guess what? It acts
just like the emitter follower (or common-collector amplifier). Because the gm of FETs is
typically lower than that for BJTs, the source follower offers a slightly lower voltage gain, and a
slightly higher output resistance. However, its input resistance is superior.
In Fig. 10-10(a) we are reminded that rIN(BASE) is large. This makes Rin approximately equal to R1
in parallel with R2. Similarly, because rIN(GATE) is extremely large, Rin for the source follower is
also approximately equal to R1 in parallel with R2. This is indicated in Fig. 10-10(b). The
equivalent resistance “looking into” the emitter (rIN(EMITTER)) is small and depends on the external
base-to-ground resistance rB. As a rough approximation, rIN(EMITTER) is nearly equal to 1/gm. The
large r of the FET eliminates the effects of the external gate-to-ground resistance on rIN(SOURCE).
Consequently, its rIN(SOURCE) is equal to 1/gm. As Fig. 10-10 indicates, Rout of the emitter follower
is essentially equal to rIN(EMITTER). However, the Rout of the source follower is equal to rIN(SOURCE)
in parallel with the source resistor RS. The open-circuit voltage gain of the emitter follower is
close to unity (1). However, the low gm of the FET makes its open-circuit voltage gain run from
approximately 0.5 to 0.85. (Specifically, approximating its Av(oc) to be nearly unity is
inappropriate.)

Figure 10-10.
FET Source Followers 247

Example 10-7. Find Rin, Av(oc), and Rout for the source follower given in Fig. 10-11. Assume
the 2N5457 has the minimum parameter set, which means VGS(OFF) = -0.5 V, IDSS = 1.0 mA, and
gfso = 1000 S as indicated on its data sheet in Fig. 10-11.
Figure 10-11.
Solution: The DC equivalent circuit of the source follower shown in Fig. 10-12(b) has the
same bias line as the common-source amplifier analyzed in Example 9-15. This means the drain
current is 0.5 mA [see Fig. 10-12(a).] The gate-to-ground voltage VG is 2.98 V, as it is given by
simple voltage division between resistors R1 and R2 and is equal to VTH. The absence of a drain
resistor means the drain-to-ground voltage VD is equal to VDD. The increased VD increases the
drain-to-source voltage VDS.
VG = VTH = 2.98 V
VD = VDD = 12 V
VS = IDRS = (0.5 mA)(6.2 k) = 3.1 V
VDS = VD – VS = 12 V – 3.1 V = 8.9 V

Figure 10-12.
Since the drain current is still 0.5 mA, the gm of 707.1 S determined in Example 9-15 also
applies. We continue the analysis by employing the relationships provided in Fig. 10-10(b).
Rin  R1 || R2 = 910 k || 300 k = 225.6 k  226 k
1 1
rIN(SOURCE) = = = 1.414 k
g m 707.1 S
Rout = RS || rIN(SOURCE) = 6.2 k || 1.414 k = 1.151 k  1.15 k
Vout g m Rs (707.1 S)(6.2 k) 4.384

Av ( oc ) = = = = = 0.8143  0.814
Vin 1 + g m Rs 1 + (707.1 S)(6.2 k) 1 + 4.384
FET Source Followers 249

As mentioned previously, the followers are often employed as buffers at the inputs and outputs
of cascaded amplifier systems. The inherently large gm of a BJT emitter follower gives it an
correspondingly low Rout. However, the Rin of a source follower is superior to that of the emitter
follower. The emitter follower is the best choice as an output buffer stage in a cascaded
amplifier system. Similarly, the source follower is the best choice as an input buffer stage in a
cascaded amplifier system.
10-3 The Op Amp Voltage Follower

The op-amp-based voltage follower is extremely simple as shown in Fig. 10-13(a) and offers
performance that far exceeds the capabilities of the emitter and source followers55. The inverting
input terminal is tied to the output. Consequently, the output voltage vOUT appears at the op
amp’s inverting input terminal, as depicted in Fig. 10-13(b). Since the op amp’s differential
input voltage is zero, the output voltage vOUT must be equal to the input voltage vIN.
[Note that since the op amp is direct coupled, DC as well as AC signal levels can appear across
the output. Therefore, we shall use the notation for total instantaneous levels (e.g., vOUT) rather
than rms notation (e.g., Vout)].
vOUT = vIN (10-14)
Dividing both sides by vIN gives us the open-circuit voltage gain.
vOUT
Av(oc) = =1 (10-15)
vIN
It should not be too surprising the voltage follower’s input resistance is infinite and its output
resistance is zero. These are stated by Eqs. 10-16 and Eq. 10-17, respectively.
Rin =   (10-16)
Rout = 0  (10-17)
It appears the (ideal) op-amp voltage follower is the perfect buffer, with its unity voltage gain, its
infinite input resistance, and its output resistance of zero. Because of its output resistance of
zero, Av is equal to Av(oc). Further, because of its infinite input resistance, Avs will also be equal
to Av. These relationships are stated by Eq. 10-18.
55 Take off you CC and CD amplifiers!!!

Avs = Av = Av(oc) = 1 (10-18)
When we recall the op amp is direct coupled internally, it becomes clear the voltage follower
offers a unity voltage gain to both DC and AC signals. The emitter and source followers are
inferior in comparison.
The Op Amp Voltage Follower

+V S
15 V
rS 3
+ 7
+
600  + 6
~
= 0V +
+ LF411 + +
Vs v 2 rL v
IN IN vOUT
- vLOAD -
4 2 k
- -
- - -
-VS
-15 V
Source Load
v = vOUT
IN
(a)
(b)
Figure 10-13.
10-4 BJT Common-Base Amplifiers

The common-base amplifier employs the BJT’s emitter terminal as its input, and the BJT’s
collector terminal as its output. (Refer to Table 10-1.) The common-base amplifier is a non-
inverting amplifier with a voltage gain is equal in magnitude to that of the common-emitter
amplifier. Further, its output resistance is also equal to that of the common-emitter amplifier.
However, it is the least popular of the three configurations. This is because the Rin of the
common-base amplifier is quite low. The BJT’s emitter terminal serves as its input, and the
resistance “looking into” the emitter is exceedingly small. The common-base amplifier is used
in applications where a low value of Rin is not a disadvantage. Typical applications include
radio-frequency (RF) amplifiers, and in a special wide-bandwidth amplifier called a cascode
amplifier56. (Bandwidth and the cascode amplifier topics are covered in Chapter 12.)
A common-base amplifier is shown in Fig. 10-14. A single-supply circuit is indicated in Fig. 10-
14(a), and a dual-supply version is shown in Fig. 10-14(b). [The DC equivalent circuit of the
common-base amplifier given in Fig. 10-14(a) is identical to that for the common-emitter
amplifier shown in Fig. 9-27(b)].
56 No, this is not misspelled. A cascade amplifier has the output of one stage tied to the input of the next stage. A cascode
amplifier is a cascade amplifier that consists of a common-emitter stage driving a common-base stage. A cascode amplifier is
a configuration that offers a wide bandwidth. It is a popular choice for video amplifiers.
BJT Common-Base Amplifiers 251

Common-Base Amplifier Biasing Options
VCC
VCC
Equations:
RC
C2 R2
R1 RC IC VB = VCC
rS C1 R1 + R 2
Q1 + VC
+ + VB + VE = VB – 0.7 V
+ rL Vload VCE
+ R1 VE
Vs _ IC  IE =
Vin RE
VCC - DC RE
- R2 RE VE
- e quivale nt VC = VCC - IC R C
R2 + circuit
C3
VC E = VC - VE
(a) A single-supply common-base amplifier.

-VEE VCC -VEE VCC
RE RC RE RC Equations:
VE = -0.7 V
rS C1 Q1 C2 Q1
VEE − 0.7 V
IC  IE =
+ + RE
+ +
+ Vload VC = V CB = V CC - ICRC
Vs rL
Vin DC VCE = VC - VE
- - e quivale nt
- circuit
(b) A dual-supply common-base amplifier.
Figure 10-14.
To arrive at the AC equivalent circuit, the coupling and bypass capacitors are replaced with short
circuits. The DC power supplies also act like short circuits. Consequently, the AC equivalent
circuit is the same for both biasing schemes. The AC equivalent circuit is given in Fig. 10-
15(a). The BJT has been replaced with its hybrid-pi model in Fig. 10-15(b). There are some
subtle points to be noted. The input voltage Vin is impressed between the emitter and base.
Specifically, we can state Vin is equal to Veb. Since the BJT’s controlling input voltage is usually
taken to be Vbe rather than Veb, we must reverse the current arrow on the controlled source.
This makes determination of the open-circuit voltage gain Av(oc) straightforward. The load is
disconnected as shown in Fig. 10-15(c).
Vin = Veb (10-19)
Vout = IcRC = gmVebRC (10-20)
Substituting Eq. 10-19 into Eq. 10-20 yields Eq. 10-21.
Vout = gmRCVeb = gmRCVin (10-21)
Next, we divide both sides by Vin to arrive at Av(oc).

Vout
Av ( oc ) = = g m RC (10-22)
Vin
The Common-Base Amplifier AC Equivalent Circuits

V means we must
Using Veb rather thanbe
reverse the direction of the arrow.
rS Q1 rS Ic
E C
+
+ + rL Vload + + + g Veb +
RC m
Vs Vin Vs Veb r Vload
RE Vin R E
- RC rL
- - B -
- - -
(a) The AC equivalent circuit. (b) The hybrid-pi model is included.
g Veb = g V Ic
m m in
E C
+ +
r
+
Vin = Veb rL (disconnecte d)
RC Vout
- B
- -
(c) Finding the open-circuit voltage gain.
Figure 10-15.
Equation 10-22 shows us the magnitude of the open-circuit voltage gain offered by the common-
base amplifier matches that provided by the common-emitter voltage amplifier. The only
difference between the two gain equations for the amplifiers is the common-emitter amplifier
provides 180o of phase shift.
The output resistance of the common-base amplifier is developed in Fig. 10-16. The signal
source Vs is set to zero. This makes Vin (and Veb) equal to zero. Since Veb is zero, the current
source is also set to zero. This means the current source acts like an open circuit. Therefore, the
output resistance is equal to the collector resistor RC.
Rout = RC (10-23)
The Common-Base Amplifier 253

The Common-Base Amplifier Output Resistance
R out
rs Q1
+ + rL (disconnected)
RC
Vs
Vin =  R E Veb =
=
- -
(a) The circuit to find the output resistance.

= 0 me ans the current source is an ope n circuit
R out
g Veb
rs m
E C
+ +
Vs r
Vin = Veb =  rL
=  RE RC (disconnected)
- B
-
(b) The hybrid-pi model is included.

R out = R C
E
open C
r
rs RE rL (disconnected)
RC
B
(c) The output resistance is determined.

Figure 10-16.
Equation 10-23 reveals the output resistance of the common-base amplifier is equal to that of the
common-emitter amplifier. Equation 10-25 provides us with the primary weakness of the
common-base amplifier – its low Rin. Let us see why this is true.
The input resistance of the common-base amplifier is low. This idea was introduced in Fig. 10-
5(b). Consider Eq. 10-24.
1
rIN(EMITTER) = (10-24)
gm

In Fig. 10-17 we see the input resistance of the common-base amplifier is given by the parallel
combination of rIN(EMITTER) and the emitter resistor RE. Typically, rIN(EMITTER) is small in
comparison to RE. Consequently, the input resistance is essentially equal to rIN(EMITTER).
Rin = RE || rIN(EMITTER)  rIN(EMITTER) (10-25)
where rIN(EMITTER) = 1/gm.
The Common-Base Amplifier Input Resistance

rIN(EMITTER)
rS Q1
+
+ rL Vload
RC
Vs
RE
-
-
1
Rin = R E || r IN(EMITTER) rIN(EMITTER)=
gm
Figure 10-17.
Example 10-8. Perform a DC analysis on the common-base given in Fig. 10-18(a).
Specifically, determine IC, VE, VB, and VC using approximations.
Solution: The DC equivalent circuit is provided in Fig. 10-18(b).

VEE - 0.7 V 12 V - 0.7 V
IC  I E = = = 2.018 mA  2.02 mA
RE 5.6 k
The emitter-to-ground voltage is a negative quantity.
VE = – 0.7 V
Since the base terminal is tied to ground, it is zero volts.
VB = 0 V
VC = VCC – IC RC = 12 V – (2.018 mA)(2.7 k) = 6.552 V  6.55 V

Example 10-9. Determine the value for gm for the 2N4124 BJT used in the amplifier given
in Fig. 10-18(a).
Solution: We find the BJT’s transconductance gm.

IC 2.018 mA
gm = = = 77.61 mS  77.6 mS
26 mV 26 mV
The Common-Base Amplifier to Be Analyzed

-V EE V CC
-12 V 12 V
RE RC
5.6 k 2.7 k
rS RE RC
C1 Q1 C2 5.6 k Q1
1 k 2.7 k
+ +
+ + + +
Vs 2N4124 rL Vload V EE V CC
Vin
12 V
- 5.6 k - 12 V +
-
(a) The dual-supply common-base amplifier. (b) The DC equivalent circuit.
Figure 10-18.
Example 10-10. Determine the input resistance Rin, the output resistance Rout, and the open-
circuit voltage gain Av(oc) for the common-base amplifier given in Fig. 10-18(a). Complete the
analysis by finding Av, Avs, Ai, Ais, and Ap.
Solution: First, we find rIN(EMITTER) using Eq. 10-24, and then we draw on Eq. 10-25 to find
Rin.
1 1
rIN(EMITTER) = = = 12.88   12.9 
g m 77.61 mS
Rin = RE  rIN(EMITTER) = 5.6 k  12.88  = 12.86   12.9 
Because rIN(EMITTER) is so small, it is reasonable to approximate RIN as being equal to rIN(EMITTER)

as indicated by Eq. 10-25. We use Eq. 10-23 to determine Rout.
Rout = RC = 2.7 k
Equation 10-22 yields the open-circuit voltage gain.
Vout
Av ( oc ) = = g m RC = (77.61 mS)(2.7 k) = 209.5  210
Vin

Now we can compute Av, which includes output loading effects.
Vload rL 5.6 k
Av = = Av(oc) = (209.5) = 141 .3  141
Vin rL + Rout 5.6 k + 2.7 k
Vload Rin 12.86 

Avs = = Av = (141 .3) = 1.794  1.79
Vs rS + Rin 1 k + 12.86 
Rin loads down the signal source significantly. Next, we find the current gain from the
amplifier’s input to the load.
I out Av(oc)Rin (209.5)(12.86 )

Ai = = = = 0.3246  0.325
I in rL + Rout 5.6 k + 2.7 k
The low Rin results in an attenuation (reduction) of the input current signal Iin. The current gain
from the input to the output includes input loading effects.
I out rS (1 k)
Ais = = Ai = (0.3246 ) = 0.3204  0.320
Is rS + Rin 1 k + 12.86 
The power gain is much smaller than that offered by the common-emitter amplifier because of
the low current gain provided by the common-base amplifier.
Ap = Av Ai = (141.3)(0.3246) = 45.87  45.9
A summary of the common-base amplifier is given in Fig. 10-19.

The Common-Base Amplifier Summary
VCC
The common-base amplifier is the least
popular of the three configurations.
RC It is used in RF amplifier applications, and
C2
in the wide-bandwidth cascode amplifier.
rS C1 1
Q1 + rIN(EMITTER) = (Typically, v e ry small)
C3 gm
+ +
+ rL Vload Rin = RE || rIN(EMITTER)  r IN(EMITTER)
Vs
+ R1
VCC
Vin RE -
-
- Rout = RC (Same as the common-emitte r)
R2 +
C3
V
A v(oc) = out = g m R C
Vin
(The input and output signals are in phase.
A single-supply common-base amplifier. The magnitude of the gain is the same as the
common-e mitte r amplifie r.)
Figure 10-19.
Tracing a Signal Through the Common-Base Amplifier
To better understand the operation of the common-base amplifier, we shall trace a signal through
it. The circuit analyzed in Examples 10-8 through 10-10 is repeated in Fig. 10-20(a). It has been
simplified in Fig. 10-20(b). A voltage source is used to represent vin57 and the load has been
disconnected so we can find the open-circuit voltage gain (Av(oc)). Observe the DC emitter
current (IE) has been indicated. Since nearly all the emitter supply DC voltage is impressed
across the emitter resistor and the AC signal is so small, the DC emitter current (IE) can be
regarded to be constant.
The rms value for the input voltage (Vin) is replaced by (vin) its time-varying equivalent. The rms
value of the output voltage (Vout) is replaced by its time-varying equivalent (vout). These changes
are necessary since out goal is to trace the time-varying signals through the amplifier.
Approximately constant
Open to DC and
a short to AC
IE
+
vin+ vout
- -
(a.) (b.)
Figure 10-20.
The input voltage vin is given as 1 mV peak as indicated in Fig. 10-21(a). The input resistance of
the common-base amplifier is 1/gm = 12.88 Ω [Fig. 10-21(a)]. The instantaneous polarities of vin
as well as the resulting peak currents drawn from the voltage source vin are shown in Figs. 10-
21(b) and (c).
57 This is permitted by the substitution theorem taught in circuit analysis. In this case the input voltage is vin and can be
represented by a single equivalent voltage source. Specifically, provided the input voltage (and input current) remain the
same, we can replace vs and rS with a single voltage source equal to vin.

0 t
0 t
77.6 uA
1 mV
Figure 10-21.
Next, we apply Kirchhoff’s current law. Pay attention to the notation. The instantaneous AC
emitter current is ie. The DC emitter current is IE. The total (AC plus DC) instantaneous emitter
current is iE.
Using Kirchhoff’s Current Law to Find the
Total Instantaneous Emitter Current
-VEE VCC
RE RC
C1 C2
+
+ + +
-
-
Figure 10-22.

By applying Kirchhoff’s current law at the connection between C1, RE and the transistor’s
emitter, and solving for the total instantaneous emitter current yields the result below:
iE = IE – ie
From Example 10-8 we have
VEE - 0.7 V 12 V - 0.7 V
IC  I E = = = 2.018 mA  2.02 mA
RE 5.6 k
Further, Fig. 10-21(b) indicates the peak AC emitter current is 77.6 µA and we can find the total
instantaneous emitter current.
iE = IE – ie = 2.018 mA – 77.6 µA = 1.940 mA
When the polarity of vin becomes negative, the direction of the AC emitter current reverses as
shown in Fig. 10-21(c).
iE = IE – (-ie) = IE + ie = 2.018 mA + 77.6 µA = 2.096 mA
The phase relationships between vin and iE are shown in Fig. 10-23.
The Emitter Current is 180 degrees

Out of Phase with the Input Voltage
vin
1 mV
0 t
-1 mV
iE
2.096 mA
2.018 mA t
1.940 mA
Figure 10-23.
Remember the collector current (iC) is essentially equal to the emitter current (iE). So now
let us see how the total instantaneous emitter current produces the total instantaneous collector-
to-ground voltage and the open-circuit output voltage.

The DC collector-to-base voltage (which is the same as the collector-to-ground voltage) was
calculated in Example 10-8.
VCB = VCC – IC RC = 12 V – (2.018 mA)(2.7 k) = 6.552 V  6.55 V

The total instantaneous value of the collector-to-base voltage (vCB) is given below:
vCB = VCC - iCRC
When iC is at its minimum instantaneous value we have the maximum value of vCB.
vCB(MAX) = VCC - iCRC = 12 V – (1.940 mA)(2.7 kΩ) = 6.762 V
The calculation is repeated for the maximum instantaneous value of iC.
vCB(MIN) = VCC - iCRC = 12 V – (2.096 mA)(2.7 kΩ) = 6.341 V
The phase relations between vin, iE, vCB and vout are given in Fig. 10-24. Since the output
coupling capacitor C2 blocks DC, the output voltage makes excursions above and below zero.
The positive and negative peak values are calculated as indicated below.
vout(positive peak) = vCB(MAX) – VCB = 6.762 V – 6.552 V = 210 mV
vout(negative peak) = vCB(MIN) – VCB = 6.762 V – 6.552 V = 210 mV
Now we can find the open-circuit voltage gain.
This is the same voltage gain we found in Example 10-10.

vin
1 mV
0 t
-1 mV
iE
2.096 mA
2.018 mA t
1.940 mA
vCB
6.762 V
VCB 6.552 V t
6.341 V
vout
210 mV
0 t
-210 mV
Figure 10-24.

10-5 FET Common-Gate Amplifiers
The common-base amplifier has a voltage gain that is equal in magnitude to the voltage gain of
the common-emitter configuration. Similarly, the common-gate amplifier has a voltage gain that
is equal in magnitude to the voltage gain of the common-source configuration. Both the
common-base and common gate amplifiers are non-inverting amplifiers. This means their input
and output signals are in phase. Just as the output resistance of the common-base amplifier
matches that offered by the common-emitter amplifier, the output resistance of the common-gate
amplifier is equal to that of the common-source amplifier. The biggest limitation of the
common-base and common-gate amplifiers is their low input resistance. This is true since we
are driving their emitter and source terminals, respectively. The various comparisons between
the common-base and common-gate amplifiers are presented in Fig. 10-25.
Common-Base/Common-Gate Amplifier Comparison

BJT Land FET World
VCC V DD
RC RD
C2 C2
C1 Q1 C1
rS + rS Q1 +
+ + + +
+ rL Vload + + rL Vload
+ R1 R1
Vs Vs
Vin - Vin -
RE VCC RS V DD
- -
- R2 +
- R2 +
C3 C3
1 1
rIN(EMITTER) = Typically, v ery small. rIN(SOURCE) = Small, but larger than
gm g m the BJT's.
Rin = RE || rIN(EMITTER)  r IN(EMITTER) Rin = RS || rIN(SOURCE)
Rout = RC Same as the common-emitte r. Rout = RD Same as the common-source .

V V
A v(oc) = out = g m R C A v(oc) = out = g m R D
Vin Vin
The input and output signals are in phase . The input and output signals are in phase .
The magnitude of the gain is the same as the The magnitude of the gain is the same as the
common-e mitte r amplifie r. common-source amplifie r. Not as large as
the BJT's.
(a) The common-base amplifier. (b) The common-gate amplifier.
Figure 10-25.
FET Common-Gate Amplifiers 263

Example 10-11. Find Rin, Av(oc), and Rout for the common-gate amplifier given in Fig. 10-
26. Assume the 2N5457 has the minimum parameter set, which means VGS(OFF) = -0.5 V, IDSS =
1.0 mA, and gfso = 1000 S.
Solution: The DC equivalent circuit of the common-gate amplifier shown in Fig. 10-26 has
the same DC equivalent circuit as the common-source amplifier analyzed in Example 9-15. This
means the drain current is 0.5 mA, and the corresponding gm at this DC operating point is 707.1
S, as determined in Example 9-15. We use the relationships summarized in Fig. 10-25(b).
1 1
rIN ( SOURCE) = = = 1.414 k
g m 707.1 S
Rin = rIN(SOURCE) || RS = 1.414 k || 6.2 k = 1.151 k  1.15 k
Rout = RD = 3.3 k
Vout
Av(oc) = = g m RD = (707.1 S)(3.3 k) = 2.333  2.33
Vin
Compare these results with those produced for the common-source amplifier analyzed in
Example 9-15. The magnitudes of the voltage gains are equal, as are the magnitudes of the
output resistances. However, the common-source amplifier offers an Rin of 226 k, while the
common-gate amplifier has an Rin of only 1.15 k. Like the common-base amplifier, the
common-gate amplifier finds its use somewhat restricted in audio amplifier applications.
However, it does lend itself to radio frequency amplifiers, and as the output stage of an FET
cascode amplifier.

Figure 10-26.
10-6 The Op Amp Non-Inverting Amplifier

The op-amp-based noninverting amplifier circuit is shown in Fig. 10-27. It has been drawn two
different ways. The circuits are identical electrically. Resistor R2 provides the negative
feedback connection. The input signal is applied to the op amp’s noninverting input terminal.
We invoke our op amp idealizations to analyze the circuit. Specifically, we assume the op amp’s
differential input voltage is zero. We also assume the op amp’s inverting and noninverting input
terminals draw no current. Our third assumption is the op amp’s output voltage is unaffected by
the load placed across it.
The Op Amp Non-Inverting Amplifier 265

Op Amp Non-Inverting Amplifier Circuits
+V S
15 V
rS 3
+ 7
600  + 6
+ LF411 +
Vs v 2 rL
IN
- vLOAD
4 2 k
-
- -
-VS
-15 V
R2
Source Load
200 k
R1
10 k
(a)
R2
200 k
+V S
15 V
R1
2 7
-
10 k
Source 6
LF411 +
rS 3 rL
+ vLOAD
4 2 k
600  +
-VS -
+
Vs v -15 V
IN
- Load
-
(b)
Figure 10-27.
The analysis of the noninverting amplifier is described in Fig. 10-28. Figure 10-28(a)
emphasizes the fact that since the op amp’s differential input voltage is zero, the input voltage vIN
appears across resistor R1. This establishes a current through resistor R1 that is given by Ohm’s
law.
vIN
i= (10-26)
R1

Because the op amp’s inverting (and noninverting) input is assumed to draw no current, resistor
R2 is effectively in series with resistor R1. This means the current i also flows through resistor
R2. This is pointed out in Fig. 10-28(b). The output voltage vOUT is equal to the sum of the
voltage drops across resistors R1 and R2. This is given by Eq. 10-27.
vOUT = iR2 + vIN (10-27)
We substitute Eq. 10-26 into Eq. 10-27 and factor out vIN to arrive at Eq. 10-28.
v  R R 
vOUT = iR2 + vIN =  IN  R2 + vIN = 2 vIN + vIN =  2 + 1vIN (10-28)
 R1  R1  R1 
If we divide both sides of Eq. 10-28 by vIN, we arrive at Eq. 10-29 for the open-circuit voltage
gain Av(oc).
vOUT  R2 
Av(oc) = =  + 1 (10-29)
vIN  R1 
Again, the use of negative feedback provides a simple, predictable equation for the voltage gain.
Since the input signal is tied directly to the op amp’s non-inverting input terminal, the input
resistance of the non-inverting amplifier circuit is held to be infinite.
Rin =   (10-30)
Who needs the common-base or common-gate amplifiers? Their small input resistances limit
their use as audio frequency range voltage amplifiers. Because the output of the amplifier circuit
is taken from the output of the op amp, we assume the output resistance of the amplifier circuit is
zero.
Rout = 0  (10-31)
The output resistance of zero means the load voltage is unaffected by the size of rL.
Consequently, the output loaded voltage gain Av is equal to the open-circuit voltage gain Av(oc).
vLOAD  R2 
Av = =  + 1 (10-32)
vIN  R1 

Analyzing the Op Amp Non-Inverting Amplifier
Zero differential
input voltage
+ +
Zero input
~ + current +
+ =0V +
v v v v
IN IN
- OUT
- OUT
- -
- -
=0A
R2 R2
The input voltage A current is - +
appears across R1 set through R1
+ + i
v
IN
v R1 R1 v i= The same current
IN IN R1 flows through R2
- -
(a) Analyzing the input circuit - all of the input voltage (b) Analyzing the feedback path - the same current
appears across the input resistor. flows through the feedback resistor.
+ v
i = IN
R1
+
v O UT = i R 2 + v IN
v
IN
- v IN
- v O UT = R 2 + v IN
R1
R2
v O UT = + 1 v IN
R2 R1
- +
v O UT
+ Av(oc) = = R2 + 1
+ v v IN R1
IN
i= v
R1 v R1 OUT
IN
- -
(c) The output voltage is equal to the sum of the voltage drops
across the input resistor and the feedback resistor.
Figure 10-28.

Example 10-12. Determine the Rin, Rout, Av(oc), Av, and Avs of the op amp non-inverting
amplifier circuit given in Fig. 10-29.
Solution: Equations 10-30 and 10-31 provide us with Rin and Rout, respectively.
Rin =  
Rout = 0 
Since Rout is zero, the voltage gains Av(oc) and Av are equal. Therefore, we can use Eq. 10-29 or
Eq. 10-32.
R  200 k
Av (oc ) = Av =  2 + 1 = + 1 = 21
R
 1  10 k
An Rin of infinite ohms means the amplifier will not load down the signal source.
v Rin 
Avs = LOAD = Av = (21) = (1)(21) = 21 58
vs Rin + rS   + 600 
This shows us that Av(oc), Av, and Avs are equal. This is truly cool. Life could not be simpler.
Figure 10-29.
58 Taken as a limit, as Rin approaches infinity the ratio approaches unity (1). The righteous mathematicians were ready to pounce.
Yikes!

The fact the op amp is direct coupled is not always an advantage. Consider Fig. 10-30. The 0.1-
V peak input signal is riding on a 1-V DC level. Therefore, the total signal makes an excursion
from 0.9 V to 1.1 V. Since the amplifier provides a gain of 21, one might assume the output
would go from 18.9 V to 23.1 V. No way! The power supply rails are 15 V. The output will
“stick” at 13 V as shown in Fig. 10-30. One solution is to include a DC blocking capacitor. This
is illustrated in Fig. 10-31. A 0.1-V peak signal will appear across the amplifier’s input, and a
2.1-V signal will appear at the amplifier’s output. Since a DC blocking capacitor is used,
resistor RB is added to provide a DC bias path to ground for the noninverting input
terminal. (Without RB, the output will tend to drift, and move close enough to a saturation
limit to produce clipping.) Resistor RB also established the input resistance Rin for the
amplifier circuit.
Rin = RB (10-33)
The Op Amp Non-Inverting Amplifier

- the input dc level produces saturation
1.1 V
1V 13 V
0.9 V
+V S
0V t
15 V t
0V
3 7
+
6
+ LF411 +
v 2 rL
IN vLOAD
- 4 2 k
-
-VS -
-15 V
R2
200 k
R1
10 k
Figure 10-30.

The Op Amp Non-Inverting Amplifier
-adding a coupling capacitor
2.1 V
1.1 V 0.1 V
1V 0V t
0.9 V -0.1 V 0V t
0V t
+V S -2.1 V
C1 15 V
3 7
+ +
6
+ LF411 +
v RB rL
IN 2
10 k - vLOAD
4 2 k
-
-VS -
-15 V
R2
200 k
R1
10 k
Figure 10-31.
10-7 Applying EDA to Analyze Non-Inverting Amplifiers
We shall see how Multisim can be used to analyze the operation of a common-base non-
inverting amplifier. We saw how a common-base amplifier processes signals in Section 10-4.
Our work there will help us understand the Multisim results. Consider Fig. 10-32. The circuit to
be investigated has been drawn using Multisim. The DC analysis is performed first.
The Multisim results are provided in Fig. 10-32. The emitter-to-ground voltage (VE) is -0.682 V.
The collector current (IC) is 2.011 mA and the collector-to-ground voltage (VC) is 6.569 V. All
three agree closely with our previous calculations -0.7 V, 2.018 mA, and 6.552 V, respectively.
Applying EDA to Analyze Non-Inverting Amplifiers 271

Figure 10-32.
Now let us see how the to use Multisim to produce the common-base amplifier signals. The
required Multisim circuit is shown in Fig. 10-33. On-page connectors simplify the wiring. The
current sensor is selected from the Virtual Instrument Suite. The AC input signal is provided by
selecting an AC voltage source from the Signal Voltage Source Family.
Virtual Instrument Suite
ON-PAGE
CONNECTOR
Current Sensor
Figure 10-33.
The resulting waveforms are shown in Fig. 10-34. When Channel 2 of the oscilloscope is direct
coupled, the small current signal is displayed on a DC level [see Fig. 10-34(a)]. To examine the
small AC (signal) part of the current we AC couple Channel 2 and increase the sensitivity [see
Fig. 10-34(b)].

AC + DC Collector Current
AC Input Voltage
AC Input Voltage
AC Only Collector Current
(a) Direct Coupled (b) AC Coupled
Figure 10-34.
Figure 10-34(b) shows the collector current signal is 180o out of phase with the input voltage.
The Multisim circuit to examine the input and output signals is provided in Fig. 10-35(a).
Figure 10-35.
The waveforms are shown in Fig. 10-35(b). Observe the input and output signals are in phase
and the output waveform is much larger than the puny input signal.59
59 Sure, we have a non-inverting amplifier. If this had not happened, I would be most likely fired and sued!
Applying EDA to Analyze Non-Inverting Amplifiers 273

(b)

The voltage gain is 174.5 which lower than the gain of 210 determined previously. There are
two reasons for this. First, the input coupling capacitor is not a perfect short circuit, and second,
the gm for the 2N4124 transistor is lower than the ideal value calculated.
Drill Problems
Section 10-1
10-1. Decoupling capacitors behave as _____________(opens, shorts) to the DC bias, and
behave as _____________(opens, shorts) to the AC signal.
10-2. A decoupling capacitor is also called a (an) _________________ (overpass, underpass,
bypass) capacitor.
10-3. The input terminal of a BJT emitter follower is the _______________ (collector, base,
emitter) while the output terminal is the ________________ (collector, base, emitter).
10-4. The ideal buffer has an Rin ___________ (0, 1, or ) ohms, an Rout ___________ (0, 1,
or ) ohms, a straight-ratio voltage gain of ___________ (0, 1, ), and a decibel voltage
gain of ___________ (0, 1, , -) decibels.

10-5. Perform a DC analysis of the emitter follower given in Fig. 10-36(a). Specifically,
determine VB, VE, IC, VC, and VCE using approximations. The BJT is a silicon device.
10-6. Perform a DC analysis of the emitter follower given in Fig. 10-36(b). Specifically,
determine VB, VE, IC, VC, and VCE using approximations. The BJT is a silicon device.
10-9. Employing the parameters determined in Prob. 10-7, continue the analysis of the emitter
follower given in Fig. 10-36(a). Find rE, rIN(BASE), Rin, rB, rIN(EMITTER), Rout, and Av(oc).
10-10. Employing the parameters determined in Prob. 10-8, continue the analysis of the emitter
follower given in Fig. 10-36(b). Find rE, rIN(BASE), Rin, rB, rIN(EMITTER), Rout, and Av(oc).
10-11. Find Av, Avs, Ai, Ais, and Ap for the emitter follower shown in Fig. 10-36(a). Use the
values of Rin, Rout, and Av(oc) determined in Prob. 10-9.
10-12. Find Av, Avs, Ai, Ais, and Ap for the emitter follower shown in Fig. 10-36(b). Use the
values of Rin, Rout, and Av(oc) determined in Prob. 10-10.
Figure 10-36.
Section 10-2
10-13. Perform a DC analysis of the source follower shown in Fig. 10-37. Find ID, VD, VG, and
VS. (Hint: You may wish to review Example 7-17.) Assume the 2N5458 has the
maximum parameter values IDSS(max) = 9 mA, VGS(OFF-max) = -7 V, and the maximum
transconductance is a gfso of 5500 S. Draw the AC equivalent circuit. (Hint: The

equivalent resistance “looking into” the collector of transistor Q2 may be regarded as
being infinite.) Perform an AC analysis. Find Rin, Av(oc), and Rout.
10-14. Repeat the analysis requested in Prob. 10-13. Assume the 2N5458 has the minimum
parameter values IDSS(min) = 2 mA, VGS(OFF-min) = -1 V, and a transconductance gfso of 1500
S.
10-15. Using the Rin, Av(oc), and Rout determined in Prob. 10-13, find Av, Avs, Ai, Ais, and Ap.
10-16. Using the Rin, Av(oc), and Rout determined in Prob. 10-14, find Av, Avs, Ai, Ais, and Ap.
10-17. The (emitter, source)____________ follower is the better choice to be the input buffer of
a cascaded amplifier system.
10-18. The (emitter, source)_____________ follower is the better choice to be the output buffer
of a cascaded amplifier system.
Figure 10-37.
Section 10-3
10-19. Analyze the op amp voltage follower circuit given in Fig. 10-13(a). Draw the AC
equivalent circuit and perform an AC analysis. Find Rin, Av(oc), Rout, Av, and Avs.
10-20. Analyze the op amp voltage follower circuit given in Fig. 10-13(a). Assume that rS is 10
k and rL is 1 k. Draw the AC equivalent circuit and perform an AC analysis. Find
Rin, Av(oc), Rout, Av, and Avs.
Section 10-4
10-21. What is the primary disadvantage of the common-base voltage amplifier? Why is it a
limitation? Explain briefly.

10-22. Perform a DC analysis of the common-base amplifier shown in Fig. 10-38(a). Solve for
VB, VE, IC, and VC using approximations. The transistor is a silicon unit.
10-23. Perform a DC analysis of the common-base amplifier shown in Fig. 10-38(b). Solve for
VB, VE, IC, and VC using approximations. The transistor is a silicon unit.
Figure 10-38.
10-26. Employing the parameters determined in Prob. 10-24, continue the analysis of the
common-base amplifier given in Fig. 10-38(a). Find rIN(EMITTER), Rin, Rout, and Av(oc).
10-27. Employing the parameters determined in Prob. 10-25, continue the analysis of the
common-base amplifier given in Fig. 10-38(b). Find rIN(EMITTER), Rin, Rout, and Av(oc).
10-28. Find Av, Avs, Ai, Ais, and Ap for the common-base amplifier shown in Fig. 10-38(a). Use
the values of Rin, Rout, and Av(oc) determined in Prob. 10-26.
10-29. Find Av, Avs, Ai, Ais, and Ap for the common-base amplifier shown in Fig. 10-38(b). Use
the values of Rin, Rout, and Av(oc) determined in Prob. 10-27.

10-30. Express Av, Avs, Ai, Ais, and Ap for the common-base amplifier shown in Fig. 10-38(a) in
decibels. Use the straight-ratio values of Av, Avs, Ai, Ais, and Ap, determined in Prob. 10-
28 for your calculations.
10-31. Express Av, Avs, Ai, Ais, and Ap for the common-base amplifier shown in Fig. 10-38(b) in
decibels. Use the straight-ratio values of Av, Avs, Ai, Ais, and Ap, determined in Prob. 10-
29 for your calculations.
Section 10-5
10-32. Analyze the common-gate amplifier given in Fig. 10-39. Determine ID. Assume the
2N5458 has a gfso of 1500 S and an IDSS of 2 mA. Draw the AC equivalent circuit. Find
Rin, Av(oc), Rout, Av, Avs, Ai, Ais, and Ap. (Hint: The equivalent resistance “looking into” the
collector of transistor Q2 may be regarded as being infinite.)
10-33. Analyze the common-gate amplifier given in Fig. 10-39. Determine ID. Assume the
2N5458 has a gfso of 5500 S and an IDSS of 9 mA. Draw the AC equivalent circuit. Find
Rin, Av(oc), Rout, Av, Avs, Ai, Ais, and Ap. (Hint: The equivalent resistance “looking into” the
collector of transistor Q2 may be regarded as being infinite.)
LOAD
Figure 10-39.
10-34. The primary disadvantage of the common-gate amplifier is _________________ (its 0o
of phase shift between its input and output, its relatively low Rin, its Rout of 0 ).

10-35. The magnitude of the open-circuit voltage gain of the common-gate amplifier is equal to
that of the ______________ (common-drain, common-source) amplifier.
Section 10-6
10-36. In general, the op amp noninverting amplifier circuit can be used as a superior
replacement for the common-__________________ (collector, base, emitter) BJT
amplifier.
10-37. In general, the op amp noninverting amplifier circuit can be used as a superior
replacement for the common-__________________ (gate, source, drain) FET amplifier.
10-38. Determine Rin, Rout, Av(oc), Av, and Avs for the noninverting op amp amplifier circuit given
in Fig. 10-40(a).
in Fig. 10-40(b).
10-40. Assume that resistor R2 in Fig. 10-40(a) is changed to 100 k. All other components are
unchanged. If vIN is a 0.1-V peak sine wave riding on a 0.5-V DC level, sketch the vIN
and vLOAD waveforms. Repeat the problem if vIN is a 1-V peak sine wave riding on a 5-V
DC level.
10-41. Assume that resistor R2 in Fig. 10-40(b) is changed to 100 k. All other components are
unchanged. If vIN is a 0.01-V peak sine wave riding on a 0.05-V DC level, sketch the vIN
and vLOAD waveforms. Repeat the problem if vIN is a 0.1-V peak sine wave riding on a 1-
V DC level.
Figure 10-40.

in Fig. 10-41. What is the purpose of capacitor C1? What is the function of resistor RB?
10-42
Figure 10-41.
Design Problems
10-43. A non-inverting amplifier circuit like that shown in Fig. 10-41 is to be designed with an
Rin of 200 k, an Av(oc) of about 51, and an Rout of approximately 0 . It is to be
operated from a 12-V DC power supply. Draw the schematic diagram and specify the
nearest standard 1% resistor values.
10-44. A 2N4124 (hfe = 120) is to be used in the common-collector amplifier circuit shown in
Fig. 10-42. Establish a collector current of about 1 mA. The bleeder current through the
voltage divider should also be about 1 mA. VB should be set to VCC/2. Rin should be
greater than or equal to 1.5 k. Rout should be 50  or less. The open-circuit voltage
gain Av(oc) must be close to 1. Specify the nearest standard 5% resistor values. Be sure
to include a final analysis (DC and AC) of the circuit using the standard resistor values
you specified.

Figure 10-42.
10-45. An engineer captured the waveforms at the input and at pin 6 as indicated in Fig. 10-43.
Based on the waveforms we may conclude that (a.) the load resistance rL is too small, (b.)
resistor R1 is shorted, (c.) resistor R1 is open, or (d.) the negative DC power supply
connection is missing.
10-46. Once the circuit in Fig. 10-43 is made to function properly, determine the peak voltage
across the load, and sketch the resulting waveform. Also determine the peak voltage at
pin 2 and sketch the resulting waveform.
Figure 10-43.

10-47. The output waveform at pin 6 in Fig. 10-43 is a flat line at +13.7 V. Based on this result
we may conclude that (a.) capacitor C1 is open, (b.) capacitor C1 is shorted, (c.) resistor
R1 is open, or (d.) the positive DC power supply connection is missing.
10-48. The output waveform at pin 6 in Fig. 10-43 is a flat line at -13.7 V. Based on this result
we may conclude that (a.) capacitor C1 is open, (b.) capacitor C1 is shorted, (c.) resistor
R1 is open, or (d.) the positive DC power supply connection is missing.
EDA Problems
10-49. Use Multisim to simulate the common-base amplifier given in Fig. 10-18(a). Use a C1 of
220 F and a C2 of 22 F. The BJT is a 2N3904, and the signal source Vs is a 1V peak,
1-kHz sine wave. Use an AC voltage source from the signal voltage source family.
Perform a transient analysis and obtain the waveforms for vs and vload. (Hint: According
to the analysis conducted in Example 10-10, Avs is 1.79, which means the peak voltage
across rL should be about 1.79 V.)
10-50. Use Multisim to create (by performing a transient analysis) the waveforms illustrated in
Fig. 10-30. Use a C1 of 22 F and an LM324 op amp. The signal source should have a
frequency of 1 kHz, an amplitude of 0.1 V, and a DC offset of 1 V. Use an AC voltage
source from the signal voltage source family.
10-51. Simulate the Multisim circuit provided in Fig. 10-44. Determine Av(oc) and Av. [Hint: The
open-circuit gain can be determined by making rL a large value (e.g., 10 MΩ)].
Figure 10-44.

11
Differential and Cascaded Amplifiers
D ifferential amplifiers are used to amplify the difference between two ground-referenced
signals or two floating (ungrounded) signals. The usefulness of this capability often
baffles students beginning their study of electronics. However, let us consider the op
amp. It is an incredibly versatile device. It is easy to use and can be employed to construct
inverting and non-inverting amplifiers. One of the reasons the op amp is so adaptable is that it
sports a differential input. Specifically, the op amp design incorporates a differential amplifier as
its input stage. We need to understand the performance capabilities and limitations of
differential amplifiers. Differential amplifiers form an important fourth amplifier category. We
elevate and simplify our amplifier analysis to promote the analysis of more complex circuits.
This allows us to “walk through” cascaded amplifiers employing discrete components and
reduces our efforts to investigate all manner of challenging applications in our later work.
Instrumentation amplifiers offer a direct-coupled solution to capture differential signals while
promoting high levels of (common-mode) noise rejection.
In this chapter, we explore:
◼ Simplified BJT/FET Amplifier Analysis

◼ Differential Amplifiers Using Discrete Devices
◼ Common-Mode Voltage Gain and CMRR
◼ The Op Amp Differential Amplifier
◼ Cascaded Amplifier Systems
◼ BJT and FET Cascaded Amplifier Systems
◼ Op Amp Cascaded Amplifier Systems
◼ Instrumentation Amplifiers
◼ Inside the Op Amp

• Employ approximations to find the Av of discrete amplifiers.
• Analyze discrete differential amplifiers.
• Define common-mode gain and the common-mode rejection ratio (CMRR).
• Analyze a discrete amplifier to find its differential voltage gain, its common-mode
gain, and its CMRR.
• Analyze and explain the operation of the op amp differential amplifier.

• Describe and analyze cascaded amplifiers employing discrete devices.
• Describe and analyze cascaded amplifiers employing integrated-circuit operational
amplifiers.
• Describe and analyze instrumentation amplifiers.
• Explain the internal operation of the IC op amp.
11-1 Simplified BJT/FET Amplifier Analysis

Up to now, we have taken a formal approach to the analysis of BJT and FET amplifiers.
Specifically, we found Rin, Av(oc), and Rout for a given amplifier circuit, and inserted the specific
values into our universal amplifier model. The universal amplifier model was then used to find
Av, Avs, Ai, Ais, and Ap. While this is a viable approach, many times we just need to know Av.
Our intent here is to show how to find it with a minimum of hassle. Consider the common-
emitter amplifier shown in Fig. 11-1(a). The formal approach to determine Av requires that we
find the output resistance Rout and the open-circuit voltage gain Av(oc). These are given by Eqs.
11-1 and 11-2, respectively.
Rout = RC (11-1)
Vout
Av(oc) = = − g m RC (11-2)
Vin
The (output loaded) voltage gain Av is provided by Eq. 11-3.
Vload rL
Av = = Av(oc) (11-3)
Vin rL + Rout
Let us perform some algebra. Specifically, we substitute Eqs. 11-1 and 11-2 into Eq. 11-3.
Vload rL rL r R
Av = = Av(oc) = ( − g m RC ) = − g m L C (11-4)
Vin rL + Rout rL + RC rL + RC
The parallel combination of rL and RC!
Through the wonders of algebra, we see that Av can be determined by finding the parallel
combination of the load rL and the collector resistor RC. This is made obvious by simplifying the
common-emitter amplifier circuit as shown in Fig. 11-1(b) and solving for Av directly. This
leads us to Eq. 11-5.
Vload = -gmVberC = -gmVinrC
Vload
Av = = − g m rC (11-5)
Vin
284 DIFFERENTIAL AND CASCADED AMPLIFIERS

Note that the collector-to-ground resistance rC is the parallel combination of RC and rL. The
same approach can be taken in the analysis of the common-source amplifier. Further, it can also
be extended to the common-base and common-gate amplifiers. A summary is provided in Fig.
11-2.
The Common-Emitter Amplifier AC Equivalent Circuit

Q1
R out = R C
+ +
+ RC Vout rL Vload V
Vin A v(oc) = out = - gmR C
- - Vin
-
V rL
A v = load = A v(oc)
Vin rL + R out
(a) The formal analysis.
Hybrid-pi Model Ic
B C
rC = RC || r L
+ + g Vbe +
m
Vin Vbe r rC V load = -gmVin rC
Vload
= g Vin
- m = -gm rC Vin
- -
V
E A v = load = -gm rC
Vin
(b) The direct analysis details.

Q1
rC = RC || r L
+
+ rC V
Vload A v = load = -gm rC
Vin Vin
-
-
(c) The direct analysis.

Figure 11-1.
Simplified BJT/FET Amplifier Analysis 285

Using r and r D to find A v
C
BJT Land FET World
Q1 Q1
rC = RC || r + rD = RD || r
L L
+
+ rC V
+ V
Vload Vload
Vin
A v = load = -gm rC Vin rD A v = load = -gm rD
Vin Vin
-
- -
-
(a) Common emitter. (b) Common source.
Using r and r D to find A v (continued)

C
BJT Land FET World
Q1 Q1
+ rC = RC || r L + rD = RD || r L
+ +
Vin rC Vload V Vin rD Vload V
RE A v = load = gm rC RS A v = load = gm rD
- Vin - - Vin
-
(c) Common base. (d) Common gate.
Figure 11-2.
If no emitter bypass capacitor is used, we have the AC equivalent circuit shown in Fig. 11-3(a).
Again, we resolve the parallel combination of the RC and rL into its equivalent collector-to-
ground resistance rC, as indicated in Fig. 11-3(b). The hybrid-pi model is included as illustrated
in Fig. 11-3(c). We write a Kirchhoff's voltage law equation for Vin and solve it for Vbe.
Vin = Vbe + gmVbeRE = (1 + gmRE)Vbe
Vin
Vbe = (11-6)
( 1 + g m RE )
Next, we write an equation for the load voltage Vload.

Vload = -gmVbe rC = -gmrCVbe (11-7)
We substitute Eq. 11-6 into Eq. 11-7 and solve for the output loaded voltage gain Av (= Vload/Vin).
Vin g m rC
Vload = − g m rCVbe = − g m rC =− Vin
( 1 + g m RE ) ( 1 + g m RE )
Vload g m rC
Av = =− (11-8)
Vin ( 1 + g m RE )

The Common-Emitter Amplifier with
No Emitter Bypass Capacitor
Q1 Q1
+ +V + + +V +
rL rC
be
- RC Vload be
- Vload
Vin Vin = RC || rL
RE - RE -
- -
(a) The unsimplified output. (b) The simplified output.

Hybrid-pi Model I c
B C Vin = Vbe + gmVbeRE = (1 + gm R E)Vbe
+ Vin
+ g Vbe + Vbe =
Vbe r
m
rC (1 + g m R E )
Vload
Vin Vload = -gmVbe rC = -gm rCVbe
- -
Vin
+ E Vload = -gm rC
(1 + g m R E )
RE g Vbe
-
m Vload g m rC
- Av = =−
Vin 1 + g mR E
(c) Finding A v.
Figure 11-3.
The common-source amplifier (with part of its source resistor bypassed) behaves in a similar
fashion. A summary of the BJT common-emitter amplifier and the FET common-source
amplifier is given in Fig. 11-4.
Using r Cand r Dto find A v
- Unbypassed Emitter and Source Terminals
BJT Land FET World
Q1 Q1
rC = RC || r L + rD = RD || r L
+
+ rC Vload g m rC
+ Vload g m rD
Vload
Av = =− rD Vload Av = =−
Vin
Vin
RE Vin 1 + g mR E R S1 Vin 1 + g m R S1
-
- -
-
(a) Common emitter. (b) Common source.
Figure 11-4.

The common-collector amplifier (emitter follower) and the common-drain amplifier (source
follower) are also simplified in the same fashion. Consider the emitter follower given in Fig. 11-
5(a). The parallel combination of its emitter resistor RE and AC equivalent load resistance across
its output rL are combined to form the equivalent emitter-to-ground AC resistance rE. This is
indicated in Fig. 11-5(b). The BJT’s hybrid-pi model is included as shown in Fig. 11-5(c). We
apply Kirchhoff's voltage law to develop Eq. 11-9 for Vin.
Vin = Vbe + Vload (11-9)
Next, we solve Eq. 11-9 for Vbe.
Vbe = Vin - Vload (11-10)
Examination of Fig. 11-5(c) leads us to Eq. 11-11 for Vload.
Vload = gmVberE = gmrEVbe (11-11)
We substitute Eq. 11-10 into Eq. 11-11 to eliminate Vbe.
Vload = gmrEVbe = gmrE(Vin – Vload)= gmrEVin – gmrEVload (11-12)
We solve Eq. 11-12 for Vload and divide both sides by Vin to arrive at Eq. 11-13.
Vload + gmrEVload = gmrEVin
Vload(1 + gmrE) = gmrEVin
g m rE
Vload = Vin
1 + g m rE
Vload g m rE
Av = = (11-13)
Vin 1 + g m rE
As the summary in Fig. 11-6 reveals, there is virtually no difference when we adapt these
principles to the source follower. All we must do is replace rE with the equivalent source-to-
ground resistance rS1. (We use rS1 to distinguish between the FET’s equivalent source-to-ground
resistance and the AC equivalent signal source resistance rS.)

The Emitter Follower
Q1 Q1
+ +V + +
Vbe
be
- + - +
Vin
RE rL
Vin rE
Vload Vload
= RE || rL
- - -
-
(a) The unsimplified output. (b) The simplified output.

Hybrid-pi Model I c Vin = Vbe + Vload
B C
+ Vbe = Vin - Vload
+ g Vbe
m
Vbe r Vload = gm rEVbe
Vin
- Vload = gm rE (Vin– Vload)
+ E + = gmrE Vin – gmrEVload
r
E g Vbe Vload
m g m rE
- - - Vload = Vin
1 + g m rE
Vload g m rE
Av = =
Vin 1 + g m rE
(c) Finding A v.
Figure 11-5.
The Emitter and Source Followers

BJT Land FET World
Q1 Q1
rE = RE || r L rS = RS || r L
+ Vload g mrE
+ Vload g m rS1
+ Av = = Vin
+ Av = =
Vin rE Vin 1 + g mr E rS1 Vload Vin 1 + g mrS1
Vload
- -
- -
(a) Emitter follower. (b) Source follower.
Figure 11-6.

Example 11-1. Find the (output loaded) voltage gain Av of the common-emitter amplifier
given in Fig. 11-7.
Solution: We note that emitter bias is used and determine the collector current IC.
VEE − 0.7 V 6 V - 0.7 V
IC = = = 0.7067 mA
RE 7.5 k
Next, we find the BJT’s transconductance gm.
IC 0.7067 mA
gm = = = 27.18 mS
26 mV 26 mV
We determine the equivalent collector-to-ground resistance rC.
rC = RC || rL = 3.6 k || 10 k = 2.647 k
Now we determine Av.
Vload
Av = = − g m rC = −(27.18 mS)(2.647 k) = -71.95  -71.9
Vin
Figure 11-7.

Example 11-2. The common-emitter amplifier given in Fig. 11-7 has been converted to a
common-base amplifier as shown in Fig. 11-8. Find its Av.
Solution: The DC equivalent circuit is nearly identical to that for the common-emitter
amplifier provided in Fig, 11-7. Consequently, the collector current IC remains 0.7067 mA.
VEE − 0.7 V 6 V - 0.7 V

IC = = = 0.7067 mA
RE 7.5 k
Since the BJT’s collector current is the same, the transconductance gm is also unaffected.
IC 0.7067 mA
gm = = = 27.18 mS
26 mV 26 mV
We determine the equivalent collector-to-ground resistance rC. The values are unchanged.
rC = RC || rL = 3.6 k || 10 k = 2.647 k
Vload
Av = = g m rC = (27.18 mS)(2.647 k) = 71.95  71.9
Vin
Figure 11-8.

Example 11-3. Find the voltage gain (Av) of the source follower provided in Fig. 11-9.
Assume the JFET has an IDSS of 25 mA and a gfso of 4000 S.
Solution: First, we find the BJT’s emitter current.

VEE − 0.7 V 12 V - 0.7 V
I D = IC  = = 3.767 mA
RE 3 k
Next, we find the JFET’s gm.
ID 3.767 mA
g m = g fso = (4000 S) = 1553 S
I DSS 25 mA
Since the equivalent resistance “looking into” the BJT’s collector is so large, the source-to-
ground resistance is essentially equal to rL.
rS1 = rL = 12 k
Vload g m rS1 (1553 S )(12 k)

Av = = = = 0.949
Vin 1 + g m rS1 1 + (1553 S )(12 k)
Figure 11-9.

11-2 Differential Amplifiers Using Discrete Devices
A differential amplifier is an amplifier circuit that is designed to amplify the difference between
two separate input signals. The need for this capability eludes most beginning electronics
students. The usefulness of a differential input will become clear as our studies progress. Trust
us60. However, the differential amplifier is important to us because (linear integrated circuit)
operational amplifiers employ a differential input. This permits them to be used as inverting
amplifiers (like common-emitter and common-source amplifiers) and non-inverting amplifiers
(like the common-base and common-gate amplifiers). Consider Fig. 11-10. The differential
amplifier has a non-inverting input (+), an inverting input (-), and an output.
The Differential Amplifier
Differe ntial input Output resistance
re sistance
Non-inverting Rout
input +
+ + +
+ + A
vD Rin vd(oc)v D vOUT
Output
-
- - -
-
Inverting -
input Ope n-circuit diffe re ntial voltage gain
(a) The symbol. (b) The e quiv alent circuit.
The diffe re ntial input v oltage
+
+ +
+
vD v OUT = A
v2 vd(oc)v D
- - -
-
+ KVL is applied around the
v1 input circuit.
- -v2 + v D + v 1 = 0
The KVL equation is solved for
the differential input voltage.
vD = v2 - v1
(c) De ve loping the differential input v oltage.
Figure 11-10.
60 The rules for teenagers never trust anyone over 30 and never trust a man who doesn’t drink (comedian W.C. Fields) do not
apply here.
Differential Amplifiers Using Discrete Devices 293

The schematic symbol that is provided in Fig. 11-10(a) is used to represent an amplifier with a
differential input and a differential output. A differential amplifier can be modeled as a voltage-
controlled voltage source as shown in Fig. 11-10(b). It is important to note that its controlling
input voltage is the differential voltage vD that exists between its non-inverting and inverting
input terminals. Its open-circuit differential voltage gain is denoted Avd(oc). The differential
amplifier has an equivalent differential input resistance (Rin) that exists between its non-
inverting and its inverting input terminals. It also has an output resistance Rout. As with any
voltage amplifier, it is desirable to have a large Rin and a small Rout.
The differential input voltage vD is defined in Fig. 11-10 (c). A Kirchhoff's voltage law equation
is written starting at the negative terminal of voltage source v2 and moving in a clockwise
direction.
-v2 + vD + v1 = 0
Solving for vD yields Eq. 11-14.
vD = v2 – v1 (11-14)
Since vD is given by the difference between the two input voltage sources, it is called the
differential input voltage.
That Ubiquitous Differential Input

The versatility provided by a differential input is emphasized in Fig. 11-11. By applying an
input signal to the non-inverting input terminal, we obtain a non-inverting amplifier as shown in
Fig. 11-11(a). Similarly, if the input signal is applied to the inverting input terminal, we have an
inverting amplifier as depicted in Fig. 11-11(b). In both cases, the unused input terminal is
connected to ground. Cool! What could be easier?
The Universal Differential Amplifier
+ -
+ +
vIN vIN
- - - +
(a) A non-inv erting amplifie r. (b) An inve rting amplifie r.
Figure 11-11.

The BJT Differential Amplifier
The basic BJT differential amplifier is shown in Fig. 11-12 (a). The circuit is symmetrical. The
electrical characteristics of transistors Q1 and Q2 are assumed to be identical. Their respective
collector resistors are also assumed equal in value. Emitter bias is used, and the two transistors
share a common emitter resistor. The base of transistor Q1 forms the inverting input, while the
base of transistor Q2 is the non-inverting input. The circuit’s output voltage is the differential
output voltage taken between the two collectors. It is important to note the signal sources (v1 and
v2) are direct coupled. This means they provide a path for the DC base current to flow up from
ground. The DC equivalent circuit is indicated in Fig. 11-12(b). The current that flows down
through the shared emitter resistor is called the tail current IT.
We apply Kirchhoff's voltage law to obtain an equation for the tail current. Inspection of Fig.
11-12(b) leads us to Eq. 11-15.
0.7 V + ITRE – VEE = 0
VEE − 0.7 V
IT = (11-15)
RE
Since both sides of the differential amplifier are matched, the two emitter currents are equal.
This means IE1 = IE2 = IE. The tail current is equal to IE + IE = 2IE. Alternatively, we can say
the emitter currents are equal to one-half of the tail current. This is reflected in Eq. 11-16.
DC
Figure 11-12.
I T VEE − 0.7 V
IE = = (11-16)
2 2 RE

Once we know the emitter current IE, we can approximate the collector current IC. The collector-
to-ground voltages [indicated in Fig. 11-12(b)] can be determined by Kirchhoff's voltage law.
VC1 = VC2 = VCC – ICRC (11-17)
The DC output voltage VOUT is the difference between the two collector-to-ground voltages.
VOUT = VC1 – VC2 (11-18)
Example 11-4. Perform a DC analysis on the BJT differential amplifier given in Fig. 11-
12(a). The quantities of interest include IT, IE, IC, VC, VOUT, VB, and VE. Assume the BJTs are
silicon units, and the left and right halves of the circuit are symmetrical.
Solution: The various quantities are indicated in Fig. 11-12(b). We find the tail current by
using Eq. 11-15.
VEE − 0.7 V 15 V - 0.7 V

IT = = = 1.907 mA
RE 7.5 k
Equation 11-16 provides us with the emitter current. We also assume the collector and emitter
currents are approximately equal.
IT 1.907 mA
IC  I E = = = 0.9533 mA
2 2
We use Eq. 11-17 to find VC and Eq. 11-18 to determine VOUT.
VC = VC1 = VC2 = VCC – ICRC = 15 V – (0.9533 mA)(7.5 k) = 7.85 V

VOUT = VC1 – VC2 = 7.85 V – 7.85 V = 0 V
Determination of VB and VE is made by inspection of Fig. 11-12(b).
VB = VB1 = VB2 = 0 V
VE = VE1 = VE2 = -0.7 V

The Small-Signal Analysis of the BJT Differential Amplifier
The AC equivalent circuit of the BJT differential amplifier is developed in Fig. 11-13. As we
work through its analysis, you will see that we draw on many of the relationships developed
previously for the common-emitter, common-base, and common-collector amplifiers61. We set
the DC supplies to zero as indicated in Fig. 11-13(b). Since we have two separate AC signal
sources, we shall employ the principle of superposition to find the output voltage Vout. We set V2
equal to zero as noted in Fig. 11-13(c). As far as Q1 is concerned, transistor Q2 has become a
common-base amplifier. We also remind ourselves in Fig. 11-13(c) the equivalent resistance
“looking into” the emitter is 1/gm.
Small-Signal Analysis of the BJT Differential Amplifier

V CC
15 V
RC RC RC
7.5 k RC
7.5 k
+ + Vout -
Vout
-
- Q1 Q2 + - Q1 Q2 +
+ + + +
V1 V2 V1 V2
- - - -
RE
RE
7.5 k
-VEE
-15 V
(a) (b)
RC RC
+ Vout -
+
- Q1 Q2 + - Q1
+ + RC Vc1
V1 V2 = 0 V1
- - rE
rIN(EMITTER) = 1
~ -
RE gm
= 1
gm
A small re sistance
(c) (d)
Figure 11-13.
61Go with it. This can be a good review. Do NOT let it be your worst nightmare!

Because rIN(EMITTER) is so low, the emitter resistor RE disappears from the analysis. Transistor
Q1’s equivalent circuit is that for a common-emitter amplifier with an unbypassed emitter
resistor. This is shown in Fig. 11-13(d). The open-circuit voltage gain Av(oc) can be found by
using Eq. 9-53, which can be modified easily to apply to Fig. 11-13(d). For convenience, we
have repeated Eq. 9-53 as Eq. 11-19.
Vout − g m RC
Av(oc) = = (11-19)
Vin 1 + g m RE
Our “Vout” is Vc1, our “Vin” is V1, and our “RE” is rE = 1/gm. Applying these substitutions
provides us with Eq. 11-20.
Vc1 − g m RC − g m RC − g m RC − g m RC
Av(oc) = = = = = (11-20)
V1 1 + g m rE  1  1+1 2
1 + g m  

 gm 
Because the BJTs are matched and operated at the same DC collector current, we assume that
their transconductances are equal. Solving Eq. 11-20 for Vc1 leads us to Eq. 11-21.
g m RC
Vc1 = − V1 (11-21)
2
Although we have set source V2 equal to zero, a signal will also appear at the collector of
transistor Q2. Consider Fig. 11-14(a). Transistor Q1 has its emitter connected to the emitter of
transistor Q2. As far as Q2 is concerned, its emitter is being driven by an emitter follower, which
has an output resistance of 1/gm. Transistor Q1 “sees” its emitter being loaded by the rIN(EMITTER)
of transistor Q2, which is also equal to 1/gm. Therefore, the voltage at the emitters is equal to
V1/2. This is illustrated in Fig. 11-14(b). Transistor Q2 will behave like common-base amplifier
as emphasized in Fig. 11-14(c). The open-circuit voltage gain of a common-base amplifier is
given by Eq. 9-22, which has been repeated below as Eq. 11-22.
Vout
Av(oc) = = g m RC (11-22)
Vin
In this case, our “Vout” is Vc2, and our “Vin” is V1/2.
Vc2
Av(oc) = = g m RC (11-23)
V1 / 2
Solving Eq. 11-23 for Vc2 leads us to Eq. 11-24.
V1 g m RC
Vc2 = g m RC = V1 (11-24)
2 2

Small-Signal Analysis of the BJT Differential Amplifier
(continued)
An e mitte r follower with
an output re sistance of 1/g
m
The load on the emitter

followe r is the input
re sistance of the common- Rout
Q1 RC The emitter-to-ground
base amplifier. 1 gm
- v oltage
+ + +
Q2 V1
V1 rL V1
+
- - 1 gm 2
RC Vc2
r
-
IN(EMITTER)
-
= 1
gm
(a) (b)
g m RC
- V1
2 g m RC
Q2 RC V1
RC 2
+ +
V1 RC V1 V1
Vc2 = g m RC
2
2
- - g m RC - Q1 Q2 +
= V1
2 +
V1 V2 = 0
-
V1
RE
2
(c) (d)
Figure 11-14.
A summary of the relationships developed thus far is depicted in Fig. 11-14(d). Transistor Q1
acts like a common-emitter amplifier with a gain of –gmRC / 2 with an input that is equal to V1.
Transistor Q2 behaves like a common-base amplifier with a gain of gmRC, but with an input of
only V1/2. Consequently, the magnitude of the signal at the collector of transistor Q1 is equal
to the magnitude of the signal at the collector of transistor Q2.
To continue the analysis via superposition requires we set V1 equal to zero. We the find Vc2 and
Vc1 produced by V2 acting alone. Because the circuit is symmetrical, it is easy to find Vc2 and
Vc1. We simply take our previous work and change the subscripts appropriately. This takes us
to Eqs. 11-25, and 11-26.

g m RC
Vc2 = − V2 (11-25)
2
V2 g m RC
Vc1 = g m RC = V2 (11-26)
2 2
The last step in the application of the superposition theorem is to sum the individual voltage
components algebraically.
g m RC g R
Vc1 = Vc1 + Vc1 = − V1 + m C V2 (11-27)
2 2
g m RC g R
Vc 2 = Vc2 + Vc2 = V1 − m C V2 (11-28)
2 2
The output voltage [as defined in Fig. 11-12(a)] is equal to the difference between Vc1 and Vc2.
g m RC g R g R g R 
Vout = Vc1 − Vc 2 = − V1 + m C V2 −  m C V1 − m C V2 
2 2  2 2 
We distribute the minus sign, collect the terms, and factor out gmRC.
g m RC g R g R g R
Vout = − V1 + m C V2 − m C V1 + m C V2 = g m RCV2 − g m RCV1
2 2 2 2
= g m RC(V2 − V1 ) (11-29)
The differential input voltage is V2 – V1. If we divide the left and right sides of Eq. 11-29 by the
differential input voltage, we obtain the open-circuit differential voltage gain Avd(oc).
Vout
Avd(oc) = = g m RC (11-30)
(V2 − V1 )
The next quantity of interest is the differential amplifier’s output resistance Rout. Recall that the
output resistance of an amplifier is given by the ratio of its output voltage to its output current.
The analysis is conducted with the amplifier’s input signal source(s) set to zero. This definition
has been repeated as Eq. 11-31.
Vout
Rout = (11-31)
I out V1 =V 2 = 0
The definition has been applied to the AC equivalent circuit of our differential amplifier as
indicated in Fig. 11-15(a). The hybrid-pi models for the BJTs have been depicted in Fig. 11-
15(b). Since the base-emitter signals are zero, the voltage-controlled current sources are also
zero, which means they act like open circuits. The circuit can be simplified as shown in Fig. 11-
15(c). The resulting output resistance of the differential amplifier is given by Eq. 11-32.

BJT Differential Amplifier Output Resistance
RC RC
RC RC
Rout
Rout Q1
- +
- Q1 Q2 + g mVbe g mVbe
Vbe =0 Vbe
r =0 r
V1 V2 =0 =0
=0 =0
Q2
RE RE
(a) (b)
Rout
= 2RC
RC RC
RC RC
Rout
(c)
Figure 11-15.
Rout = 2 RC (11-32)
The last quantity of interest is the equivalent input resistance presented to the signal sources V1
and V2. Since both halves of the circuit are symmetrical, we need only analyze the Q1 half as
shown in Fig. 11-16. Since we have a common-emitter amplifier with an unbypassed emitter
resistance, we may employ the relationship for rIN(BASE) given by Eq. 9-46. It has been repeated
below as Eq. 11-33.
rIN(BASE) = rπ + βrE (11-33)
Since the equivalent emitter-to-ground resistance rE is 1/gm, we may substitute this relationship
into Eq. 11-33. This takes us to Eq. 11-34.

The Input Resistance of the BJT Differential Amplifier
The input resistance of a common-emitter
Rin(-) +
amplifier with an unbypassed emitter-to-
ground resistance is:
- Q1
rIN(BASE) = r + rE
+ RC Vc1 1
V1 The emitter-to-ground resistance is
gm
- rE  1  
1 rIN(BASE) = r +    = r +
= -  gm  gm
gm

Recall that r =
gm
Substitution produces our equation forrIN(BASE)

rIN(BASE) = r + r = 2r
Rin(-) = Rin(+) = r IN(BASE)
Figure 11-16.
 1  β
rIN(BASE) = rπ + β   = rπ + (11-34)
 gm  gm
Since we have defined r to be equal to /gm, we may substitute this into Eq. 11-34.
rIN(BASE) = rπ + rπ = 2rπ (11-35)
The equivalent input resistance looking into the inverting input Rin(-) is equal to the equivalent
input resistance looking into the non-inverting input Rin(+). These quantities are equal to rIN(BASE).
Rin(-) = Rin(+) = rIN(BASE)
Rin(-) = Rin(+) = 2r (11-36)
Example 11-5. Perform a small-signal AC analysis on the BJT differential amplifier given
in Fig. 11-17. Find gm, r, Avd(oc), Rout, Rin(-), and Rin(+). Use the DC collector current (IC = 0.9533
mA) determined in Example 11-4. Assume the BJTs are silicon units, hfe is 150, and the left and
right halves of the circuit are symmetrical.
Solution: First, we determine the small-signal parameters.

IC 0.9533 mA
gm = = = 36.67 mS
26 mV 26 mV

 150
r = = = 4.091 k
g m 36.67 mS
We apply Eq. 11-30 to find the open-circuit differential voltage gain Avd(oc).
Vout
Avd(oc) = = g m RC = (36.67 mS)(7.5 k) = 275.0
(V2 − V1 )
We use Eq. 11-32 to find Rout.

Rout = 2RC = (2)(7.5 k) = 15 k
We conclude our analysis by employing Eq. 11-26 to find the input resistances.
Rin(-) = Rin(+) = 2r = (2)(4.091 k) = 8.182 k
Figure 11-17.
11-3 Common-Mode Voltage Gain and CMRR

The differential input voltage (vD or Vd) is the difference between the voltages that appear
between the non-inverting input and ground, and the inverting input and ground as depicted in
Fig. 11-18(a). Ideally, a differential amplifier should provide an output voltage that is
proportional to the product of vD and its open-circuit differential voltage gain Avd(oc). If voltage
source v1 and voltage source v2 are equal, the differential input voltage is zero. Under this
condition, the output voltage should also be zero. This situation is given in Fig. 11-18(b).
Common-Mode Voltage Gain and CMRR 303

Figure 11-18.
However, although there is differential input voltage of zero, the non-inverting and inverting
inputs are still connected to voltage sources, as shown in Fig. 11-18(c). Since the voltage
sources v1 and v2 are equal, we can consider the non-inverting and inverting inputs to be tied
together to a common signal source. The voltage produced by the equivalent voltage source is
called (unremarkably) the common-mode input voltage (vCM or Vcm). In Fig. 11-18(c), we see
the common-mode voltage source. The voltage gain that is provided by the differential amplifier
on the common-mode input voltage is called the open-circuit common-mode voltage gain
Avcm(oc). The open-circuit common-mode voltage gain is defined by Eq. 11-37.
Vout
Avcm( oc ) = (11-37)
Vcm

Ideally, the output voltage should be zero, which means the ideal value of the common-mode
voltage gain is zero. In a real differential amplifier, it will be made as small as possible. The
reason why this task is so formidable becomes clear when we look at the basic differential
amplifier shown in Fig. 11-17. Any imbalance between the left- and right-hand sides of the
differential amplifier will result in a non-zero Avcm(oc). The degree to which Avcm(oc) approaches
zero depends on how well the resistors and transistors are matched, and how well they track one
another with temperature changes. The frequency of the common-mode voltage is also
important. At high frequencies, stray capacitances and wire inductances can alter the circuit
balance.
The common-mode voltage gain is compromised further when a single-ended output is used.
This means the output becomes referenced to ground as depicted in Fig. 11-19(a). Note that
transistor Q2 no longer requires a collector resistor. A ground-referenced output eases the
interface requirements to the rest of the electronic system. The symbol for an amplifier with a
differential input and a single-ended output is provided in Fig. 11-19(b). (This is the usual
configuration for integrated–circuit op amps. Consequently, the symbol in Fig. 11-18(b) is the
symbol used to represent op amps.) Unfortunately, a single-ended output reduces the
differential voltage gain by one-half. The open-circuit differential voltage gain for a differential
amplifier with a single-ended output is given by Eq. 11-38.
Vout g R
Avd ( oc ) = = m C (11-38)
V2 − V1 2
By applying the relationships developed in Section 11-1, it is easy to determine Avd, which
applies when a load is connected across the output. We simply change RC to rC.

The BJT Differential Amplifier with a Single-Ended Output
V CC
15 V
No colle ctor resistor
is re quired. Vout = A vd(oc) Vd
RC
7.5 k +
+
+
V2 Vd +
+ Vout
Vout - -
- -
+
- Q1 Q2 + -
V1
+ +
-
V1 V2
- -
RE
7.5 k
(b)
V out g R
A vd(oc) = = m C
-VEE V2 − V1 2
-15 V V load g r
A vd = = mC
V2 − V1 2
R out = RC
R in(-) = Rin(+)= 2r

(a)
Figure 11-19.
V load g r
Avd = = mC (11-39)
V2 − V1 2
The output resistance for a differential amplifier with a single-ended output is also halved.
Rout = RC (11-40)
The input resistance of the differential amplifier is unaltered. Equation 11-41 is identical to Eq.
11-36.
Rin(-) = Rin(+) = 2r (11-41)

To develop an equation for the common-mode voltage gain, it is helpful to contrast the
differential signal path from the common-mode signal flow in a differential amplifier. In Fig.
11-20(a), an equivalent differential voltage source is developed. The differential signal path is
described in Fig. 11-20(b). Essentially, no signal flows through the emitter resistor, but
exchanges between the emitters. The common-mode situation is depicted in Fig. 11-20(c).
Since the base terminals of the two transistors are at the same potential, their emitters are also at
the same potential. In this case, the common-mode signal current flows down through the
emitter resistor. To simplify the common-mode signal analysis, we create the equivalent circuit
shown in Fig. 11-20(d). Since our output signal is taken at the collector of transistor Q1, we are
not interested in transistor Q2. Therefore, we split the circuit into two parts.
Finding the Common-Mode Voltage Gain
+
+
+
V2 Vd +
Vout
- -
- -
+ - Q1 Q2 +
V1
-
Diffe re ntial signal R E

+ + path
= Vd
- -
+
Vout
-
Equivale nt diffe re ntial
- +
Vd
signal source
(a) (b)
RC Politely ignore
RC
the transistor
+ Q 2 side .
+
Vout Q1 Vout
- Q1 Q2 + - - - Q2 +
+ + + +
Vcm Vcm Vcm Vcm
Ie
- Ie - - -
+ Ie
+
Ve Ve 2R E 2R E
RE
- -
Same
Ve
(c) (d)
Figure 11-20.

To keep the emitter-to-ground AC voltage Ve the same in both cases, we double the values of the
emitter resistors. This should make sense. In the original circuit in which RE is shared, two
equal instantaneous emitter currents flow through it.
Ve = 2IeRE
When we split the circuit, we have a single emitter current flowing through an emitter resistor
that is doubled in value.
Ve = Ie2RE = 2IeRE
The simplified AC equivalent circuit for transistor Q1 is given in Fig. 11-21. Since we have an
unbypassed emitter resistance (2RE), the (common-mode) voltage gain is given by an equation
similar in form to Eq. 11-19.
Vout − g m RC R
Avcm(oc) = = − C (11-42)
Vcm 1 + g m 2 RE 2 RE
Again, if we use the equivalent collector-to-ground resistance rC, we can solve for Avcm directly
via Eq. 11-43.
Vload − g m rC r
Avcm = = − C (11-43)
Vcm 1 + g m 2 RE 2 RE
Common-Mode Voltage Gain Equivalent Circuit
Q1 + +
g mVbe
+
RC r
Vout Vbe RC
+ Vout
+
= Vcm -
Vcm 2R E - 2R E
- - -
Figure 11-21.

The Common-Mode Rejection Ratio (CMRR)
The common-mode rejection ratio (CMRR) is a parameter that is used to describe the
effectiveness of a differential amplifier. Since op amps are differential amplifiers, the CMRR
parameter is provided by many manufacturers on their op amp data sheets. The common-mode
rejection ratio is defined by Eq. 11-44. It is the magnitude of the ratio of the differential voltage
gain to the common-mode voltage gain.
Avd
CMRR = (11-44)
Avcm
Quite often, the common-mode rejection ratio is expressed in decibels.
Avd
CMRR(dB) = 20log (11-45)
Avcm
Example 11-6. Perform a DC analysis on the BJT differential amplifier given in Fig. 11-22.
The quantities of interest include IT, IE, IC, VC1, and VC2. Assume the BJTs are silicon devices
with identical electrical characteristics.
Solution: We find the tail current by using Eq. 11-15.
V EE − 0.7 V 12 V - 0.7 V
IT = = = 2.216 mA
RE 5.1 k
Equation 11-16 provides us with the emitter current. We also assume the collector and emitter
currents are approximately equal.
IT 2.216 mA
IC  I E = = = 1.108 mA
2 2
We use Eq. 11-17 to find VC1.

VC1 = VCC – ICRC = 12 V – (1.108 mA)(5.1 k) = 6.35 V
Determination of VC2 is made by inspection of Fig. 11-22.

VC2 = VCC = 12 V

Single-Ended Output BJT Differential Amplifier
V CC
12 V
RC
5.1 k
+
Vout
- Q1 Q2 + -
+ +
V1 V2
- -
RE
5.1 k
-VEE
-12 V
Figure 11-22.
Example 11-7. Perform an AC analysis on the BJT differential amplifier given in Fig. 11-
22. The quantities of interest include Avd(oc), Rin(-), Rin(+), Rout, Avcm(oc), CMRR, and CMRR(dB).
Assume the BJTs are matched and have an hfe of 150.
Solution: We use the collector current of 1.108 mA determined in Example 11-6 to find the
small-signal parameters.
IC 1.108 mA
gm = = = 42.62 mS
26 mV 26 mV
 150
r = = = 3.520 k
gm 42.62 mS
Equation 11-38 provides us with the open-circuit differential voltage gain Avd(oc).
Vout g R (42.62 mS)(5.1 k)

Avd ( oc ) = = m C = = 108 .7
V2 − V1 2 2
We use Eq. 11-41 to find Rin(-) and Rin(+).

Rin(-) = Rin(+) = 2r = (2)(3.520 k) = 7.04 k
Equation 11-40 gives us Rout.

Rout = RC = 5.1 k
The common-mode voltage gain Avcm(oc) is given by Eq. 11-42.

Vout − g m RC R 5.1 k
Avcm(oc) = = − C =− = −0.5
Vcm 1 + g m 2 RE 2 RE 2(5.1 k)
We conclude the analysis by finding the CMRR and CMRR(dB) as given by Eqs. 11-44 and 11-
45, respectively. Note the output loaded gains, or the open-circuit gains can be used for this
calculation. Just be sure to use one or the other.
Avd Avd(oc) 108.7
CMRR = = = = 217 .4
Avcm Avcm(oc) - 0.5
Avd
CMRR(dB) = 20 log = 20 log CMRR = 20log(217.4) = 46.7 dB
Avcm
What Good is Common-Mode Rejection Ratio, What Does it Mean, and

Why Should We Care?
To really understand common-mode rejection, we offer Fig. 11-23(a). The voltage at the non-
inverting input (V2) is 5.01 V, while the voltage at the inverting input (V1) is 4.99 V. The
differential input voltage VD is determined easily.
VD = V2 – V1 = 5.01 V – 4.99 V = 0.02 V
The common-mode voltage is the average value of the input voltages. The common-mode
voltage is defined by Eq. 11-46.
V1 + V2
VCM = (11-46)
2
In Fig. 11-23(a), the common-mode voltage is found by using Eq. 11-46.
V1 + V2 4.99 V + 5.01 V
VCM = = = 5.00 V
2 2
The differential input voltage can be represented by using two equivalent voltage sources equal
to VD/2, with an equivalent common-mode voltage source connected between them as shown in
Fig. 11-23(b). With this equivalent representation, the voltages at the noninverting input and
inverting input are identical to the ones shown in Fig. 11-23(a). This is emphasized in Fig. 11-
23(c).

Representing the Differential and Common-Mode Voltages
VD = V2 - V1 = 5.01 V - 4.99 V = 0.02 V The diffe re ntial source
is split into two separate +
sources. VD
= 0.01 V
+
+ 2 +
+
V2 VD
V1 + V2 + +
5.01 V - - VCM =
-
VD
2 = 0.01 V
+ 2
= 5.00 V
V1
common-mode
4.99 V
v oltage source
(b)
(a)
Same
V2 = 5.01 V
Vd +
2
+ + +
VD -
= 0.01 V Vd
2 + Vd
+ - -
Same + +
VD = 0.02 V Vcm
2
+ + - -
VCM VD - -
= 0.01 V
2
= 5.00 V
Same
V1 = 4.99 V
(c) (d)
Figure 11-23.
We can apply this same approach to representing AC differential and common-mode voltages.
This is depicted in Fig. 11-23(d). If the AC differential signal source has an average value of
zero, one might suspect the common-mode voltage should also be zero. This is often not the
case, however. Quite often, the common-mode voltage is produced by electrical noise coupling
into input signal lines. In the North America most of the common-mode noise is at the power
line frequency of 60 Hz. In Europe and many other countries, the common-mode noise is at their
power-line frequency of 50 Hz. However, common-mode noise can also be present at other
frequencies. The advantage offered by the equivalent circuit shown in Fig. 11-23(d) is we can
set the values of the common-mode voltage, and the differential input signal independently. It
also provides an approach to using EDA to analyze noise problems via simulation. We shall
gain greater insight by using EDA. We shall see that the common-mode rejection that is
provided by the differential amplifier eliminates electrical noise. Have you ever heard that
annoying hum coming from a public address system or the loudspeakers of your stereo system?
An amplifier with a differential input can reject that kind of noise pickup. This is illustrated in
Fig. 11-24.

Understanding Common-Mode Noise
Power-line noise is induced
into the signal line s.
An amplifie r with a
single -ended input
Signal to be amplifie d.
+
Vout
+
Vs -
single -ended input High-frequency signal rides
on the low-fre que ncy noise .
= Noise +
+
Vout
Vn -
+
Vs
Signal
(a)
Power-line noise is induced
into the signal line s.
diffe re ntial input
+ +
Vd +
Vout
- - -
Signal
Signal
Vd +
diffe re ntial input A "cle an" amplifie d
= 2
- + + output signal.
Vd +
+ - Vout
+ Vd - -
2
Vcm -
-
Noise
(b)
Figure 11-24.

Employing EDA
We can simulate the differential amplifier (Fig. 11-22) analyzed in Example 11-7 using
Multisim. The Multisim schematic diagram has been captured as illustrated in Fig. 11-25.
Non-inverting Input
Figure 11-25.
The common-mode signal source has a peak value of 100 mV and a frequency of 100 Hz. The
differential input signal has a peak value of 10 mV and been split into two separate 5-mV
sources. The differential input signal has a frequency of 1 kHz. Notice the inverting and non-
inverting inputs have been labeled using text. The output is at the collector of transistor Q1 and
has also been labeled using an on-page connector. Since the transistor models are identical, the
BJTs are matched precisely in the simulation.
The signal plus noise that appears at the inverting input is illustrated in Fig. 11-26. It is
important to observe the common-mode noise62 is much larger than the 1-kHz signal.
62 “Noise” is defined to be any unwanted signal. In the classroom this could be a professor with a penchant for anecdotal stories
or bad jokes.

The small 1-kHz input signal rides on the
much larger 100 Hz common-mode noise.
Figure 11-26.
The oscilloscope is used to capture the amplifier’s output signal. Figure 11-27(a) shows the
output signal rides on a DC level (VC). By using AC coupling and increasing the sensitivity from
5 V/DIV to 500 mV/DIV, we can see the output is “clean” since the differential amplifier rejects
the common-mode noise.
The output is “clean” since the

The output rides on a DC level common-mode is rejected.
(a) (b)
Figure 11-27.

Figure 11-27 illustrates the output waveforms using our old friend the oscilloscope. Of course,
the oscilloscope displays amplitude versus time. In Fig. 11-25 we have modeled a problem,
which allowed us to specify the differential input voltage as well as the common-mode voltage.
However, in practice we may only know the combination. Suppose we measure the input
voltage (Fig. 11-26) and we need to use the measurements to determine the common-mode
voltage gain as well as the differential voltage gain. That would be rather difficult. We would
need to determine how much of the input voltage (Fig. 11-26) is vD and how much is vCM.
There is an instrument called a spectrum analyzer that displays amplitude versus frequency. A
virtual spectrum analyzer is included in the Multisim suit of instruments [see Fig. 11-28].
Figure 11-28.
When the spectrum analyzer is connected to the input as indicated in Fig. 11-28, it will display
the spectral components of the input waveform. The display is shown in Fig. 11-29. Figure 11-
29(a). When the cursor is moved to the 1-kHz component, we see that ½ of the differential
input signal is 4.749 mV. When the cursor is moved to the common-mode voltage, we see that
its value is 96.054 mV [see Fig. 11-29(b)].

Cursor
Differential
(a)
Input
Signal
Common-Mode
Voltage
(b)
Figure 11-29.
The spectrum analyzer can be connected to the output. The Start Frequency is changed to 0 Hz
(which is DC). Edit any of the frequency setpoints like Span, Start, and End and then depress
Enter. Edit Range or Resolution and the click on Set. Much more will be said about the
spectrum analyzer in Chapter 12. Figure 11-30 depicts the results when the output is measured.

DC
Figure 11-30
The spectrum analyzer does not provide phase information, and the amplitude of the common-
mode signal in the output is barely discernible. Consequently, the minus sign given to the
common-mode output (-39.980 mV) is largely a matter of faith. The 1-kHz signal at the
inverting input is only one-half of the total differential input signal. Therefore, it must be
doubled to calculated Avd(oc). Hence, a two (2) appears in the denominator of Avd(oc). These
values agree favorably with the results obtained in Example 11-7. (Specifically, we determined
that Avd(oc) = 108.7.) and Avcm(oc) = -0.5).

The signal-to-noise ratio (S/N) at the input reveals the 1-kHz input signal is slightly less than ten
percent of the noise level. Thanks to the large common-mode rejection ratio (CMRR), we see
that the output signal-to-noise ratio is 25.7 to 1. A vast improvement made possible by a
differential amplifier.
Further Improvements
The common-mode rejection ratio can be improved further by using a constant-current source
to establish the tail current for the differential amplifier. Recall that the common-mode voltage
gain is inversely related to the size of the emitter-to-ground resistance. (Refer back to Eq. 11-
42.) We also recall the equivalent resistance “looking into” the collector of a transistor is
extremely large. Consequently, miniscule common-mode voltage gains, and extremely large
common-mode rejection ratios can be realized. This is the standard approach taken by integrated
circuit designs. Fig. 11-31 presents a differential amplifier with a constant-current source. The
constant-current source consists of transistor Q3, zener diode D1, resistor R1 and resistor RE. The
bias conditions are close to those of Fig. 11-28. The signal and common-mode levels are
identical.
Figure 11-31
The circuit was simulated with the spectrum analyzer used to monitor its output. The results are
shown in Fig. 11-32. The DC and signal output are close to the original circuit values.
However, the common-mode voltage that appears at the output has been reduced from 96.54 mV
to only 151 µV!

DC = 6.629 V
Signal Output = 1.011 V
Common-Mode Voltage
at Output = 151 uV
Figure 11-32
11-4 The Op Amp Differential Amplifier

In Fig. 11-33(a) we see an op amp differential amplifier circuit. The reference designators R1
and R2 have been duplicated intentionally. This is done to indicate matched resistor values.
Figure 11-33(b) reminds us the gain applied to a signal at the noninverting input terminal is (1 +
R2/R1). However, the gain applied to a signal at the inverting input is –R2/R1 [see Fig. 11-33(c)].
Therefore, to provide equal gains on both input terminals, it is necessary to attenuate (reduce) the
signal applied to the noninverting input terminal. This is accomplished by using a resistive
voltage divider as shown in Fig. 11-33(d).
To analyze the op-amp differential amplifier, we use the principle of superposition. This means
we find the output voltage (vOUT) produced by v1 acting alone. We repeat the analysis to
determine the output voltage vOUT created by v2 acting alone. We then determine the output
voltage vOUT by finding the algebraic sum of vOUT and vOUT. This is demonstrated in Fig. 11-
34.

The Op Amp Differential Amplifier
R1 R2
10 k  200 k  The gain on a signal

applied here is:
+ R2
v +1
2 +V S R1 +V S
- 15 V 15 V
3 7 3 7
+ +
6 6
LF411 + LF411 +
2 rL 2 rL
- vLOAD - vLOAD
4 2 k 4 2 k
-V S - -V S -
-15 V -15 V
R1 R2 R1 R2
10 k  200 k  10 k  200 k 
+
v
1
-
(a) (b)
A voltage divider is used
R1 to attenuate the signal to
match the magnitude of the
gain on the non-inverting input
10 k  + to the magnitude of the gain
+ on the inverting input.
R2
v v2
+V S 2
200 k  +V S
15 V - 15 V
3 - 3
7 7
+ +
6 6
LF411 + LF411 +
2 rL 2 rL
The gain on a signal - vLOAD - vLOAD
4 2 k 4 2 k
applied here is:
− 2
R -V S - -V S -
R1 -15 V -15 V
R1 R2 R1 R2
10 k  200 k  10 k  200 k 
+
v
1
-
(c) (d)
Figure 11-33.
In Fig. 11-34(a) we set v1 to zero by replacing it with a short circuit. This creates a parallel
equivalent resistance from the non-inverting input to ground. However, since the inputs to an op
amp draw no signal current, there will be no voltage drop across the combination. This means
the non-inverting input terminal will remain at ground potential. Equivalently, we have an
inverting amplifier. The voltage gain (-R2/R1) will be unaffected. This takes us to Eq. 11-47.
R2
 =−
vOUT v1 (11-47)
R1
The Op Amp Differential Amplifier 321

Analyzing the Op Amp Differential Amplifier Using Superposition
The parallel combination has no R2
v = v
effect on the gain since the non-inverting R1 2
R1+ R 2 2
input terminal draws no current.
10 k +
+V S
15 V + R2
3 v v2
7 2
200 k +V S
+
- 15 V
R1 R2 6 - 3 7
10 k LF411 +
200 k
+
v =0V 2 6
2 - v R2 LF411
4 OUT = − v
+
R1 1
2
-VS - - v R2
4 OUT = v
-15 V R1 2
R1 R2
-VS -
-15 V
10 k 200 k R2
+
v 200 k
1
- R1
R2 v R1 + R 2 v
v
10 k OUT = 1 + =
(a) R1 2 R1 2
v =0V
1
v R1 + R 2 R2
OUT = v
R1 R1+ R 2 2
R1 R2
v R2
OUT =
v
10 k 200 k R1 2
+ (b)
v2 +V S
- 15 V
3 7
+
v v + vOUT
6 OUT = OUT
LF411
+
2
- v R2 R2 R
4 OUT = (v -v ) v v + 2 v2
R1 2 1 OUT = −
R1 1 R1
-VS -
-15 V R2
R1 R2 v (v -v )
OUT =
R1 2 1
10 k 200 k
+
v1
-
(c)
Figure 11-34.
In Fig. 11-34(b) v1 has been set to zero by replacing it with a short. Clearly, this results in a non-
inverting amplifier configuration. However, the non-inverting input terminal is connected to a
voltage divider. Since the non-inverting input draws no current, we may find v2 by applying
simple voltage division. This provides us with Eq. 11-48.
R2
v2 = v2 (11-48)
R1 + R2
With reference to Fig. 11-34(b) we develop vOUT.
 R   R + R2 
 = 1 + 2 v2 =  1
vOUT v2 (11-49)
 R1  R1 

Next, we substitute Eq. 11-48 into Eq. 11-49, and observe that the (R1 + R2) factors cancel.
 R + R2   R1 + R2   R2  R2
 =  1
vOUT v2 =   v2 = v2 (11-50)
 R1   R1   R1 + R2  R1
To obtain vOUT we add vOUT and vOUT algebraically.

R2 R R
 + vOUT
vOUT = vOUT  = − v1 + 2 v2 = 2 (v2 − v1 ) (11-51)
R1 R1 R1
The open-circuit differential voltage gain [Fig. 11-34(c)] is given by Eq. 11-52.
vout R
Avd ( oc ) = = 2 (11-52)
v2 − v1 R1
Since the op amp’s output serves as the output of the differential amplifier circuit, the output
resistance of the differential amplifier circuit is also zero.
Rout = 0 (11-53)
Because Rout is zero, the Avd of the amplifier circuit is equal to its Avd(oc).
vload R
Avd = = 2 (11-54)
v2 − v1 R1
The input resistance of the inverting input Rin(-) is equal to R1 as illustrated in Fig. 11-35(a).
However, the input resistance of the non-inverting input Rin(+) is equal to R1 + R2 as also shown
in Fig. 11-35(a). The input resistances are stated by Eqs. 11-55 and 11-56.
Rin ( − ) = R1 (11-55)
Rin ( + ) = R1 + R2 (11-56)
The imbalance in the impedance levels will cause unequal loading on identical signal sources.
This will cause degradation in the circuit’s common-mode rejection. One solution is to buffer
the inputs of the differential amplifier circuit with voltage followers as depicted in Fig. 11-35(b).
The Op Amp Differential Amplifier 323

The Op Amp Differential Amplifier Input Resistances
Rin(+)= R1 + R2
+ R1
10 k
R2
200 k
+
v
2 +V S
- 15 V
3 7
+
6
LF411
+
2
- 4 v
OUT
-VS -
-15 V
- R1 R2
200 k
10 k
+ Rin(-) = R1
v
1
-
(a) The op amp differential amplifier has unequal input impedances
+V S
15 V
2 7
-
R1 R2
6
+
LF411
10 k 200 k
3
+ 4
+V S
+ -VS 15 V
v -15 V 3
2
+ 7
- 6
LF411
+
2
+V S - 4 v
OUT
- 3
+
15 V
7
-VS
-15 V
-
R1 R2
6
LF411
+ 10 k 200 k
v 2
1
- 4
-
-VS
-15 V
(b) Voltage followers serve as buffers to eliminate the problem. (Since

voltage followers have unity voltage gain, the overall circuit gain
is unaffected.)
Figure 11-35.
It is possible to use a quad operational amplifier (such as an AD713) to implement Fig. 11-35(b).
This means only one integrated circuit is required, and the fourth op amp is an uncommitted
spare. Since the Rout of the voltage followers is zero, the input resistance imbalance of the op
amp differential amplifier is unimportant. Further, the infinite input resistance of the followers
becomes the input resistance of the circuit’s inverting and non-inverting inputs.

Rin( − ) = Rin( + ) =  Ω (11-57)
Example 11-8. Determine the Avd(oc), Avd, Rout, Rin(-) and Rin(+) of the op amp differential
amplifier circuit given in Fig. 11-35(a).
Solution: Equations 11-52 and 11-54 provide us with Avd(oc) and Avd, respectively. They are
equal in value since Rout is zero.
R2 200 k
Avd(oc) = Avd = = = 20
R1 10 k
Equation 11-53 provides us with Rout.
Rout = 0 
The input resistances are unmatched as indicated by Eqs. 11-55 and 11-56.
Rin(-) = R1 = 10 k
The resistance “looking into” the non-inverting input is considerably larger.
Rin(+) = R1 + R2 = 10 k + 200 k = 210 k
11-5 Cascaded Amplifier Systems

A cascaded voltage amplifier system block diagram is depicted in Fig. 11-36. A multiple-stage
amplifier system is cascaded when the output of a given amplifier is used to drive the input of
the next successive stage. This arrangement makes it possible to achieve huge voltage gains.
The input to stage 1 is the input voltage to the system Vin. The output voltage of the first stage V1
is also the input voltage to the second stage. Similarly, the output voltage of the second stage V2
is also the input voltage to the third stage. The ultimate output of the system is Vload. We define
the (output loaded) system voltage gain as Eq. 11-58.
Vload
Av = (11-58)
Vin
The overall voltage gain Av can be described in terms of the product of the individual loaded
voltage gains. This relationship is given by Eq. 11-59.
Cascaded Amplifier Systems 325

Vload  V1  V2  Vload 
Av = =    
Vin  Vin  V1  V2 
Vload
Av = = Av1 Av 2 Av 3 (11-59)
Vin
Equation 11-59 was developed to show the overall voltage gain of a cascaded voltage amplifier
system is given by the product of the individual (loaded output) voltage gains offered by each
stage. This is an important concept and it has been extended to encompass n stages by Eq. 11-
60.
Vload
Av = = Av1 Av 2 Av 3  Avn (11-60)
Vin
Av is the overall voltage gain of the cascaded system, Av1 is the voltage gain of the first stage, Av2
is the voltage gain of the second stage, and Av3 is the voltage gain of the third stage, and Avn is the
voltage gain of the nth stage. In each instance, we are dealing with the (output) loaded voltage
gains. Internally, the input resistance of a successive voltage amplifier stage loads down the
output of the stage driving it.
A Cascaded Voltage Amplifier System

rs Load
Voltage Voltage Voltage
Amplifier Amplifier Amplifier
+ + + +
+ 1 k Stage 1 Stage 2 Stage 3
V Vin V1 V2 rL Vload
s
10 k
-
- - - -
Signal Source
Figure 11-36.
Decibel Voltage Gains Add in Cascaded Systems

While the product of the individual gains produces the overall voltage gain, the use of decibel
gains is simpler. Decibel voltage gains are additive. This is indicated in Eq. 11-61. (The
required logarithm property is provided in Fig. 8-12. The logarithm of a product is equal to the
sum of logarithms of the individual terms.)
Vload
Av(dB) = 20 log = 20 log Av1 Av 2 Av 3 = 20 log Av1 + 20 log Av 2 + 20 log Av 3
Vin

Av(dB) = Av1(dB) + Av 2(dB) + Av3(dB) (11-61)
Let us see if this really works. Consider Examples 11-9 and 11-10.
Example 11-9. Given the amplifier in Fig. 11-35, determine the overall voltage gain Av if
Av1 is 10, Av2 is 100, and Av3 is 1. Also, determine the overall voltage gain in decibels.
Solution: To find Av, we use Eq. 11-59.

Vload
Av = = Av1 Av 2 Av 3 = (10)(100 )(1) = 1000
Vin
Next, we determine Av(dB).
Av(dB) = 20 log Av = 20log(1000 ) = 20(3) = 60 dB
Example 11-10. Given the amplifier in Fig. 11-35, determine the individual stage voltage
gains in decibels if Av1 is 10, Av2 is 100, and Av3 is 1. Also, determine the overall voltage gain in
decibels.
Solution: First, we find the individual decibel gains.
Av1(dB) = 20 log Av1 = 20log(10) = 20(1) = 20 dB

Av 2(dB) = 20 log Av 2 = 20log(100) = 20(2) = 40 dB
Av3(dB) = 20 log Av3 = 20log(1) = 20(0) = 0 dB
Now we can employ Eq. 11-61 to find Av(dB).
Av(dB) = Av1(dB) + Av 2(dB) + Av3(dB) = 20 dB + 40 dB + 0 dB = 60 dB
As can be seen, the approaches demonstrated in Examples 11-9 and 11-10 yield the same result.
If the individual stage gains are given in decibels, a system analysis is a matter of simple addition
to determine the overall, or net, result.
11-6 BJT and FET Cascaded Amplifier Systems

Besides creating the means for achieving large voltage gains, cascaded systems also provide the
capability of tailoring the amplifier system’s input resistance Rin and output resistance Rout. This
is emphasized in Fig. 11-37. The input resistance of the first stage establishes the input
resistance of the amplifier system. Since FETs offer a large input resistance, an FET input stage
is a good choice. The common-emitter amplifier can provide large voltage gains. Consequently,
it has been selected as the second stage in our cascaded system. The third stage sets the output
resistance of the system. As we saw in Section 10-1, the BJT emitter follower offers a low
output resistance. In fact, it offers the lowest output resistance when compared to the other BJT
and FET configurations. It therefore makes good sense to use a BJT emitter follower as our
output stage.
Cascaded Amplifier Systems 327

A Cascaded BJT/FET Amplifier Design Strategy
R in R out
rS
+ +
Vs rL Vload
Input Stage Gain Stage Output Stage
- -
Use an FET stage to give Use a BJT e mitte r

a large input resistance. follower stage to giv e a
low output resistance.
Use a BJT CE stage to

giv e a large v oltage gain.
Figure 11-37.
Yikes! Did I Sleep Through a Chapter? 63

A circuit, which embodies the design strategy depicted in Fig. 11-37, is given in Fig. 11-38. Do
not let its apparent complexity overwhelm you. We shall describe the functions of each of the
individual components to dispel all the mysteries. The first scary thing we notice is the absence
of the (familiar) collector resistor designator (RC), the missing drain resistor reference designator
(RD), and the lack of emitter resistor reference designators (RE). “Real” circuits use only
numbered reference designators such as those indicated in Fig. 11-38. Now that we have
recovered from our initial shock, let us begin to examine the circuit more closely.
63 No, you did not necessarily sleep through a chapter. Figure 11-38 represents a significant increase in complexity, when
compared to our other endeavors. Do not panic, but seat belts should always remain fastened.

A BJT/FET Cascaded Amplifier System
+
C6 VCC
2.2 F 15 V
R4
Q1 7.5 k
C1 2N5457 C3 Q3
rS
1 F 10 F 2N3904
100  C2 Q2
C5
+ + 10 F 2N3904 + 22 F
Vs
+ R1 R7 +
Vin +
150 k 10 k +
- R3
Q4 5.1 k R8 rL
- R5
2N3904 5.6 k  V
7.5 k load
430
R2
R6 -
15 k C4
13 k + 100 F
C7
2.2 F
-VEE
+
-15 V
Figure 11-38.
Transistor Q1 is a source follower since the input signal is applied to its gate terminal, and its
output signal is taken from its source terminal. Constant-current source biasing (transistor Q4) is
being used to establish its DC operating point. Transistor Q2 is a common-emitter amplifier. Its
input signal is at its base terminal, and its output signal is taken from its collector terminal.
Partial emitter bypassing is used. This means AC negative feedback is being used to establish its
voltage gain. Transistor Q3 serves as an emitter follower. Its input signal is at its base terminal,
and its output signal is produced at its emitter terminal. Since each of the stages share the same
DC power supplies, it is possible interactions between them could be produced. In an extreme
case, oscillations could be created. When oscillations occur, an amplifier system generates
signals. This is a severe problem. To prevent this, power supply decoupling is used.
Specifically, capacitors C6 and C7 are called power supply decoupling (or bypass) capacitors.
Their purpose is to ensure the DC power supplies (VCC and VEE) act like short circuits to the AC
signals.64 Capacitors C1, C2, C3, and C5 serve as coupling capacitors. Capacitor C4 is an emitter
bypass capacitor. The capacitors are polarized electrolytics. They must be installed as shown.
64 Power supply connections often have a parasitic inductance. The inductance depends on the current density. On a printed
circuit (printed wiring) board, narrow traces tend to have more inductance. To minimize the inductance wider traces are used.
In complex systems power and ground planes (rectangular sheets of copper) are used in multiple-layer board designs. Power
supply decoupling can be at the power connection point or physically close to the stage that draws the most current. It is up to
the circuit designer to develop specifications for the board designer.
BJT and FET Cascaded Amplifier Systems 329

After this initial inspection, we are ready to perform a serious analysis. The first step is to
perform a DC analysis. Approximations are encouraged to reduce the task. BJT and FET DC
biasing are covered in Chapter 6.
Consequently, the appropriate biasing relationships are illustrated in Fig. 11-39 without
explanation. You should understand the analysis. Treat Fig. 11-39 as a biasing review. Study
the calculations presented in Example 11-1165.
The DC Analysis of the BJT/FET Cascaded Amplifier System

R4 VCC
Q1 7.5 k 15 V
2N5457 Q3
2N3904
Q2
2N3904
R1 R7
150 k 10 k
R3
Q4 5.1 k R8
R5
2N3904
7.5 k
430
R2 VA
R6
15 k
13 k -VEE
-15 V
The Q1 Stage Re lationships The Q2 Stage Re lationships The Q3 Stage Re lationships
VEE − 0.7 V VEE − 0.7 V VEE − 0.7 V

ID1 = IS1 = IC4  IE4 = IC2  IE2 = IC3  IE3 =
R2 R5 + R6 R8
VD1 = VCC VB2 = 0 V VB3 = 0 V
VG1 = 0 V VE2 = -0.7 V VE3 = -0.7 V
VB4 = 0 V
VC2 = VCC – IC2R4 VC3 = VCC
 ID 
VGS = VGS(O FF)1 − 
IDSS  VA = -VEE + IC2 R6

VS1 = VC4 = -VGS
Figure 11-39
Example 11-11. Perform a DC analysis of the cascaded amplifier system given in Fig. 11-
38 using the DC equivalent circuit provided in Fig. 11-39.
65 To ignore this suggestion may result in sleepless nights, a loss of appetite, and a slight headache when a quiz, or an
examination develops. At the extreme, your vital organs may also start leaking internally, but this is rare.

Solution: We use the relationships provided in Fig. 11-39. First, we analyze the transistor Q1
stage.
VEE − 0.7 V 15 V - 0.7 V
I D1 = I S1 = I C 4  I E 4 = = = 0.9533 mA
R2 15 k
VD1 = VCC =15 V
VG1 = 0 V
To find VGS1, we must turn the data sheet for the 2N5457. According to the manufacturer,
VGS(OFF) ranges from –0.5 to –6 V, and its corresponding IDSS ranges from 1.0 to 5.0 mA. We use
the values to determine the range of possible VGS values. Recall that FETs with the minimum
IDSS value will also have the minimum (magnitude) VGS(OFF). The converse is also true. This
permits us to find the range in the possible values of VGS.
 I D1   0.9533 mA 
VGS = VGS(OFF)1 −  = (−0.5V) 1 -  = −11.8 mV
 I DSS   1 mA 
 I D1   0.9533 mA 
VGS = VGS(OFF)1 −  = (−6 V) 1 -  = −3.38 V
 I DSS   5 mA 
Since VS1 = VC4 = -VGS, we see that the source-to-ground, and the collector-to-ground voltages
can range from 0.0118 to 3.38 V.
0.0118 V  VS1 = VC4  3.38 V
We continue the analysis, by examining transistor Q4. We already know its collector-to-ground
voltage can range from 0.0118 to 3.38 V. We also know its collector current is 0.9533 mA. By
inspection of Fig. 11-39, we determine its emitter-to-ground voltage VE4, and its base-to-ground
voltage VB4.
VE4 = -0.7 V
VB4 = 0 V
Now we shall conduct an analysis of the transistor Q2 stage. Note that VA is the voltage at the
junction between resistors R5 and R6 with respect to ground.
VEE − 0.7 V 15 V - 0.7 V

IC 2  I E 2 = = = 1.065 mA  1.06 mA
R5 + R6 430  + 13 k
VB2 = 0 V
VE2 = -0.7 V
VC2 = VCC – IC2R4 = 15 V – (1.065 mA)(7.5 k) = 7.01 V
VA = -VEE + IC2R6 = -15 V + (1.065 mA)(13 k) = -1.16 V

The negative value of VA means electrolytic capacitor C4 has its positive terminal connected to
ground. We conclude the DC analysis by investigating transistor Q3.
VEE − 0.7 V 15 V - 0.7 V

IC3  I E3 = = = 1.907 mA  1.91 mA
R8 7.5 k
VB3 = 0 V
VE3 = -0.7 V
VC3 = VCC = 15 V
The AC equivalent circuit can be developed next. By replacing the coupling and bypass capacitors with
short circuits, we obtain the AC equivalent circuit shown in Fig. 11-40. The DC constant-current source
symbol has been used to replace transistor Q4 and resistor R2. A DC constant-current source acts like an
open circuit to an AC signal. The emitter bypass capacitor C4 effectively shorts out emitter resistor R6.
Therefore, resistor R6 disappears.
The AC Equivalent Circuit of the BJT/FET Cascaded Amplifier System
Q1 Q3
rS 2N5457 2N3904
100  Q2
+ 2N3904
+ R1 R4 R7
Vs
Vin 150 k 7.5 k 10 k +
- R3
- 5.1 k R8 rL
V
R5 7.5 k 5.6 k  load
430
-
The DC constant-curre nt
source acts like an ope n
circuit to the AC signal.
Figure 11-40.
The AC equivalent circuit is simplified further as indicated in Fig. 11-41. The pertinent
equations and relationships have also been defined. (Figure 8-44 provides the common-emitter
relationships while Fig. 9-10 shows the BJT and FET follower equations.) Again, treat this as a
review, but study it carefully.

The Simplified AC Equivalent Circuit
R in
Q1 Q3
rS 2N5457 R out
2N3904
100  Q2
+ 2N3904 +
+ R1 V2 R4 || R 7
Vs
Vin 150 k + 4.286 k
- R3 +
V1 -
- 5.1 k R8 rL
V
- R5 7.5 k 5.6 k  load
430
-
The Q1 Stage Re lationships The Q2 Stage Re lationships The Q3 Stage Re lationships
rB3 = R4 || R7
Rin = R1 rE3 = R8 || rL
I
rIN(BASE) 3   rE3 g m3 = C3
rIN(BASE) 2  R5 26 mV
rC2 = R4 || R7 || rIN(B ASE) 3 1 r
rS1 = R3 || rIN(B ASE) 2 R out = + B3
 R4 || R7 g m3 
ID1 I
g m1= g fso g m2 = C2 rE3 = R8 || rL
IDSS 26 mV
Vout g m3 R 8
V1 g m1rS1 V g r A v(oc) 3 = =
A v1 = = A v2 = 2 = _ m2 C2 V2 1 + g m3R 8
Vin 1 + g m1rS1 V1 1 + g m2 R 5
Vload g r
A v3 = = m3 E3
V2 1 + g m3 rE3
Figure 11-41.
Example 11-12 shows us how to make an AC analysis of a cascaded amplifier such the one
indicated in Fig. 11-37. For each stage, we must find the equivalent resistance connected across
its output. For a stage “buried” within the system, the equivalent resistance across its output
includes the input resistance of the stage it drives. Once the equivalent resistance across the
output of a stage is determined, its (output loaded) voltage gain can be found. This strategy is
repeated for each of the three stages in the cascaded system.
Example 11-12. Perform an AC analysis of each of the cascaded amplifier stages in the
amplifier system given in Fig. 11-38 using the simplified AC equivalent circuit provided in Fig.
11-41. Specifically, determine the input resistance Rin of the cascaded amplifier, determine the
voltage gain of the first stage (transistor Q1) Av1, the voltage gain of the second stage (transistor
Q2) Av2, the open-circuit voltage gain of the third stage (transistor Q3) Av(oc)3, and the (output
loaded) voltage gain provided by the third stage Av3. Complete the problem by finding the
overall (unloaded voltage gain) Av(oc) and the (output loaded voltage gain) Av of the cascaded
amplifier system.
Solution: We use the relationships provided in Fig. 11-41. First, we analyze transistor Q1.
Since an FET has a large gate-to-source resistance, the equivalent input resistance of the
common-drain stage is equal to R1. This establishes the input resistance of the cascaded
amplifier system.

Rin = R1 = 150 k
The impedance “looking into” the base terminal of transistor Q2 (denoted rIN(BASE)2) places a load
across the output of the source follower (transistor Q1) stage. To compute rIN(BASE)2, we need to
know the BJT’s small-signal current gain. In Example 11-10, we determined that Q2’s DC
collector current is 1.06 mA. According to the manufacturer’s data sheet, the 2N3904 has a
minimum hfe of 100 when IC = 1 mA. We shall use this minimum hfe value for .
  hfe = 100
rIN(BASE)2 = R5 = (100)(430 ) = 43 k

The total equivalent source-to-ground equivalent resistance rS1 is given by the parallel
combination of R3 and rIN(BASE)2.
rS1 = R3 || rIN(BASE)2 = 5.1 k || 43 k = 4.559 k
Before we can find the voltage gain of the source follower, we must determine the gm of the
2N5457. According to the manufacturer, gfso can range from 1000 to 5000 S. We shall use the
minimum transconductance to determine the minimum voltage gain. Recall that FETs with the
minimum gfso will also have the minimum IDSS (and in this case that would be 1 mA).
I D1 0.9533 mA
g m1 = g fso = (1000 S) = 976.4 S
I DSS 1.0 mA
Now we can determine the minimum (loaded output) voltage gain of the source follower.
V1 g m1rS1 (976 .4 S)(4.559 k)
Av1 = = = 0.8166
Vin 1 + g m1rS1 1 + (976 .4 S)(4.559 k)
This completes our analysis of the first (Q1) stage. Now we proceed to the second (Q2) stage.
Since the equivalent resistance “looking into” the base terminal of transistor Q3 (rIN(BASE)3) loads
down the collector of transistor Q2, we must determine its value. Since we know a 2N3904 has a
minimum hfe of 100 at an IC of 1 mA, both Q2 and Q3 shall be assumed to have a  of 100.
rE3 = R8 || rL = 7.5 k || 5.6 k = 3.206 k
rIN(BASE)3 = rE3 = (100)(3.206 k) = 320.6 k
Now we can determine Q2’s equivalent collector-to-ground resistance rC2.
rC2 = R4 || R7 || rIN(BASE)3 = 4.286 k || 320.6 k = 4.229 k
Transistor Q2 has an IC of 1.06 mA. This knowledge allows us to compute its gm.
IC 2 1.06 mA
g m2 = = = 40.77 mS
26 mV 26 mV

Now we ascertain the (loaded output) voltage gain of the second (Q2) stage AV2.
V2 g m 2 rC 2 (40.77 mS)(4.229 k)

Av 2 = = − = −9.305  −9.31
V1 1 + g m 2 R5 1 + (40.77 mS)(430 )
Suppressing the urge to go outside for a long walk to rethink our career options, we move to the
last stage. Since the impedance “looking into” the collector of transistor Q2 is very large, the
base-to-ground resistance “seen” by transistor Q3 is given by the parallel combination of resistors
R4 and R7.
rB3 = R4 || R7 = 4.286 k
Next, we find the transconductance of the third (Q3) stage.
IC3 1.907 mA
g m3 = = = 73.35 mS
26 mV 26 mV
The output resistance of the third stage is the output resistance of the cascaded amplifier system.
1 r 1 4.286 k
Rout = + B3 = + = 13.63  + 42.86   56.5 
g m3  73.35 mS 100
The open-circuit voltage gain of the third stage shall be determined next.
Vout g m3 R8 (73.35 mS)(7.5 k)

Av ( oc )3 = = = = 0.9982
V2 1 + g m3 R8 1 + (73.35 mS)(7.5 k)
Next, we find the (output loaded) voltage gain of the third stage. We recall from our previous
calculations that rE3 is 3.206 k.
Vload g m3 rE 3 (73.35 mS)(3.206 k)

Av 3 = = = = 0.9958
V2 1 + g m3 rE 3 1 + (73.35 mS)(3.206 k)
This concludes our analysis of the individual stages. We finish the problem by determining the
overall open-circuit and output loaded voltage gains for the cascaded amplifier system.
Av(oc) = Av1Av2Av3(oc) = (0.8166)(-9.305)(0.9982) = -7.5848  - 7.58

Av = Av1Av2Av3 = (0.8166)(-9.305)(0.9958) = -7.567  - 7.57
As a final comment, we remind the reader that the cascaded amplifier can be represented using
our general amplifier model. This point is illustrated in Fig. 11-42 along with the various
amplifier relationships.

Using the General Voltage Amplifier Model
for the BJT/FET Cascaded Amplifier System
rS Rout
V rL
+ A v = load = A v(oc)
+ + 56.49  Vin rL + R out
100  +
Vs Rin rL V V R in
Vin A v(oc)V load A vs = load = A v
- in
150 k 5.6 k Vs rS+ R in
-7.58V
- in
-
- i A v(oc) R in
A i = out =
Signal Source Cascade d Voltage Amplifier Load i in rL + Rout
i rS
A is = out = A i
is rS+ R in
P
A p = out = A v A i
Pin
Figure 11-42.
11-7 Op Amp Cascaded Amplifier Systems
An op amp cascaded amplifier system is shown in Fig. 11-43. All three of the AD713 op amps
are included in the same 14-pin DIP (Dual In-line Package). The AD713 is described as a quad
BiFET op amp. “Quad” obviously means there are four separate op amps in the package. The
“BiFET” description means FETs are typically used as the differential input stage, while BJTs
are used throughout the balance of the design. All four op amps share common power supply
terminals (pins 4 and 11). Capacitors C2 and C3 provide power supply decoupling. Note that
capacitive input coupling via capacitor C1 has been incorporated to block any DC level
associated with the signal source. Resistor R1 provides a DC bias path to ground and sets the
amplifier’s input resistance simultaneously.
Resistors R2, R5, R6, and R7 provide DC bias current compensation. Bias current compensation
requires that the equivalent resistance to ground seen by each input terminal must be equal. The
details will be explained later. For now, we simply point out that these resistors will have no
effect on the AC signal. (That means we can ignore them. That also means we do not need any
new formulas.)

An Op Amp Cascaded Amplifier System
R4
100 k
rS C1 AR 1A
1 F +V S
100  C2
3 15 V
+ + R3 +
+ 1 6 4
AD713 - 2.2 F AR 1C
+ R6 10
2 10 k 7
Vs
Vin R1 - AD713 +
AR 1B 100 k 8
150 k 5 AD713 +
- R2 + C3
11 9
- + - rL
150 k Vload
R5 5.6 k
2.2 F R7
10 k -VS -
-15 V 100 k
AR 1D
12 AD713N (Top View)
+
14
AD713 N/C
13
-
14 13 12 11 10 9 8
SPARE
- -
+ +
+ +
- -
1 2 3 4 5 6 7
Figure 11-43.
Also, notice in Fig. 11-43 that one of the four op amps in the AD713 is an uncommitted spare.
The input terminals of the spare op amp are connected to ground. This is a “good practice”.
There are two reasons for this. First, unconnected (floating) input pins could build up an
electrical charge that could damage the integrated circuit. Second, unconnected input pins could
pick up electrical noise signals and amplify them greatly. This can create (or contribute to)
electrical noise problems in the amplifier system.
Example 11-13. Perform a DC analysis of the op amp cascaded amplifier system given in
Fig. 11-43.
Solution: We perform the DC analysis by simple inspection. First, we note the DC power
supplies are connected. Second, we make sure that each op amp input terminal has a DC bias
path to ground. No problems exist. Cool, we are done! Hang on to your calculator.
Op Amp Cascaded Amplifier Systems 337

The AC equivalent circuit can be developed next. By replacing the coupling capacitor with a
short circuit, we obtain the AC equivalent circuit shown in Fig. 11-44. Voltage followers are
used as the input and output stages. An inverting amplifier stage is used to provide the system
voltage gain. Since op amps offer output resistances of nearly zero, there are no output loading
effects to complicate the analysis. (Hey, you just must love op amps!)
No effect on the AC signal.
No effect on the AC signal.
Figure 11-44.
Example 11-14. Perform an AC analysis of the op amp cascaded amplifier system given in
Fig. 11-43. Specifically, find Rin, Rout, Av1, Av2, Av(oc)3, and Av3 Complete the analysis by finding
Av(oc) and Av of the cascaded amplifier system. Use the AC equivalent circuit provided in Fig. 11-
44.
Solution: The input resistance Rin of the cascaded amplifier system is equal to the input
resistance of the first (AR1A) stage.
Rin = R1 = 150 k
The output resistance Rout of the amplifier system is equal to the output resistance of the third
(AR1C) stage. Since the output resistance of an op amp is approximately zero, all we must do is
make a simple statement.
Rout  0 
Since the first stage is an op amp voltage follower, it offers a voltage gain of unity. Again, since
the output resistance of an op amp is nearly zero, there is no output loading effect. The voltage
gain of the first stage Av1 is another simple statement.
Av1  1
Thanks to negative feedback and the fact the output resistance of an op amp is approximately
zero, it is easy to find the voltage gain of the second stage Av2.

R4 100 k
Av 2 = − =− = −10
R3 10 k
The third stage is another op amp voltage follower. It offers a voltage gain of unity. There are
no output loading effects since the op amp’s output resistance is zero. Consequently, its open-
circuit voltage gain Av(oc)3 and its (output) loaded voltage gain are both approximately unity.
Av(oc)3 = Av3  1
The voltage gain of the cascaded amplifier system is given by the product of the individual stage
gains.
Av(oc) = Av1 Av2 Av(oc)3 = (1)(-10)(1) = -10
Av = Av1 Av2 Av3 = (1)(-10)(1) = -10
Without a doubt, the op amp cascaded amplifier system is much easier to analyze than the
BJT/FET cascaded amplifier system. Further, the design is straight forward, and the
performance is superior. Modern designs favor the use of integrated circuits wherever and
whenever possible.
11-8 Instrumentation Amplifiers

Figure 11-45 shows the classic three-op amp implementation of an instrumentation amplifier.
An instrumentation amplifier is a direct-coupled, differential amplifier with matched input
resistances (Rin(+) is equal to Rin(-)), and a differential voltage gain that can be adjusted by
varying a single resistor without degrading the amplifier’s common-mode rejection. The
constraint on the gain adjustment means the differential amplifiers shown in Fig. 11-35 are not
instrumentation amplifiers. A gain adjustment in either circuit requires changing the values of
two resistors. (Typically, this means changing the resistors in the R2 positions.) However, the
differential amplifier in Fig. 11-35(b) makes Rin(+) is equal to Rin(-) and serves as a dandy segue66
to the instrumentation amplifier.
66 Pronounced “Segway”, but a segue is a smooth transition from one topic or section to the next. A Segway is a quite cool two-
wheeled motorized personal vehicle.
Instrumentation Amplifiers 339

An Instrumentation Amplifier
+ Va
AR1
+
V2 _
R R
- R
100 k 100 k
100 k +
R
G AR3 +
20 k R _ V
- out
R R
100 k
_ Vb 100 k 100 k
AR2
+
+
V1
-
Figure 11-45
We shall analyze the circuit in Fig. 11-45 to determine the gain equation. (We shall discover the
voltage gain can be adjusted by changing the gain resistor RG. However, it is important to see
how this result is determined.) The voltage transfer function can be found by applying the
superposition theorem. First, we shall set V1 equal to zero, and then find the components of Va
and Vb produced by V2 acting alone [see Fig. 11-46(a)].

Using Superposition
+ Va
AR1
+
V2 _
R R
- R
+
R AR3 +
G
R _ V
- out
R R
_ Vb
AR2
+
The V2 source is effectively
V1 = 0 connected here because
the differential voltage
(a.)
between the inverting and
the non-inverting inputs of AR1
is zero.
+ Va
+ AR1 RG R
V2 _
- R +
V2 _ Vb
- AR2
R
G +
A virtual ground
provided by AR2
(b.) (c.)
Figure 11-46.
The inverting input terminal of AR2 is a virtual ground since it behaves as an inverting amplifier.
As can be seen in Fig. 11-46(b), AR1 acts like a non-inverting amplifier with V2 as its input and
Va as its output. Equation 11-62 yields Va.
 R 
Va = 1 + V2 (11-62)
 RG 
Because the differential voltage between the inverting and non-inverting input terminals of an op
amp is approximately zero, the V2 source is effectively connected to AR2 as indicated in Fig. 11-
46(c). AR2 works as an inverting amplifier and its output voltage is Vb.
R
Vb = − V2 (11-63)
RG

We find the components of Va and Vb produced by V1 with V2 equal to zero in a similar fashion
[see Fig. 11-47]. In this case, AR1 serves as an inverting amplifier while AR2 behaves as a non-
inverting amplifier. Equations 11-64 and 11-65 are based on this observation.
R
Va = − V1 (11-64)
RG
 R 
Vb = 1 + V1 (11-65)
 RG 
We find Va and Vb by summing the components algebraically.

 R  R
Va = Va + Va = 1 + V2 − V1 (11-66)
 RG  RG
R  R 
Vb = Vb + Vb = − V2 + 1 + V1 (11-67)
RG  RG 
Using Superposition Continued

+ Va
AR1
V2 = 0 _
R R
+
R AR3 +
G
R _ V
- out
R R
_ Vb
AR2
+
+
V1
-
Figure 11-47.
The output stage of the circuit is a unity-gain differential amplifier with Va and Vb as its inputs.
Hence, we can write the equation for VOUT directly.
Vout = Va − Vb (11-68)
We obtain the equation for VOUT in terms of V1 and V2 by substituting in Eqs. 11-66 and 11-67
for Va and Vb, respectively.

 R  R  R  R  
VOUT = Va − Vb = 1 + V2 − V1 − − V2 + 1 + V1 
 RG  RG  RG  RG  
We distribute the minus sign through the Vb terms. Then we distribute the V1 and V2 voltages.
 R  R R  R  R R R R
= 1 + V2 − V1 + V2 − 1 + V1 = V2 + V2 + V2 − V1 − V1 − V1
 RG  RG RG  RG  RG RG RG RG
The V1 and V2 terms are collected.

2R 2R  2R   2R   2R 
= V2 + V2 − V1 − V1 = 1 + V2 − 1 + V1 = 1 + (V2 − V1 )
RG RG  RG   RG   RG 
The differential voltage gain (Avd) is obtained by dividing both sides by (V2 –V1). (Because the
Rout of AR3 is zero, Avd(oc) and Avd are equal.)
Vout  2R 
Avd = = 1 +  (11-69)
(V2 − V1 )  RG 
Figure 11-49.
Resistor RG is typically used as the gain-setting resistor. The attractive feature here is RG can be
varied without affecting the common-mode rejection of the circuit. While it is possible to build
an instrumentation amplifier using op amps, the usual approach in to use integrated circuit
versions. Consider Examples 11-15 and 11-16.

Example 11-15. Determine the differential voltage gain of the instrumentation amplifier
circuit given in Fig. 11-49.
Solution: We observe in Fig. 11-49 that R = 100 k and RG = 20 k and invoke Eq. 11-69
Vout  2R   2(100 k) 

Avd = = 1 +  = 1 +  = 11
(V2 − V1 )  RG   20 k 
Example 11-16. An Analog Devices AD620 is described as a low-cost, low-power (draw)

instrumentation amplifier. It is employed in the circuit shown in Fig. 11-50. Determine the
differential voltage gain of the instrumentation amplifier circuit given in Fig. 11-50.
Solution: We observe in Fig. 11-50 that RG = 499 . The manufacturer has indicated
elsewhere that R = 24.7 k. We use Eq. 11-69.
Vout  2R   2(24.7 k) 

Avd = = 1 +  = 1 +  = 100
(V2 − V1 )  RG   499  
Figure 11-50.
Using EDA to Investigate the AD620 Instrumentation Amplifier
The model for AD620 instrumentation amplifier is included in the Multisim library. As can be
seen in Fig. 11-51, it is in the Instrumentation Amplifier Family of the Analog Group.
Figure 11-51.
The Multisim circuit is given in Fig. 11-52. The AD620 template does not identify the function
of the pins. Consequently, data sheet package information has been pasted on the schematic
diagram. The common-mode voltage is 1 V peak at 60 Hz. The differential input signal is 10
mV peak at 1 kHz. The voltage gain (Avd) was calculated in Example 11-16 to be 100.
Figure 11-52.
Even though there is a common-mode voltage that is 100 times larger than the differential input
signal, the output signal is noise free. The circuit was simulated, and the oscilloscope display is
provided in Fig. 11-53.

Figure 11-53.
The output waveform is 1 V peak, which is perfect. The gain of 100 on a peak differential input
voltage of 10 mV peak produces an outputvoltage of 1 V peak. As we have seen previously, a
spectrum analyzer can be used to investigate circuit performance more fully. A virtual spectrum
analyzer has been attached as indicated in Fig. 11-54.
Figure 11-54.
Edit the start end frequencies as indicated in Fig. 11-55. Click on Enter. Edit the Range and
Resolution. Run the simulation. By dragging the cursor to the positions shown, the peak values
of the spectral components at 1 kHz and 60 Hz can be determined. Click on the left and right
arrows to get close as possible to the nominal frequencies.

Figure 11-55.
We shall use the values provided by the spectrum analyzer to compute the common-mode
rejection ratio.
This result is plausible. The manufacturer’s data sheet (Fig. 11-50) indicates a CMRR(dB) of
100 dB minimum with an Avd of 10.

Noise Reduction
We have seen that an instrumentation amplifier rejects common-mode noise. In general, it is
good practice to minimize noise sources where practical, or at least attenuate noise trying to
“creep” into our system.
Electromagnetic Interference (EMI), as its name suggests, is composed of an electric field and a
magnetic field [see Fig. 11-56.] It can produce common-mode noise as well as normal-mode
(differential) noise. The electric field is orthogonal to the magnetic field and both are orthogonal
to the direction of propagation67.
EMI Source Wavelength
Elect
roma
gneti
cW aves
Figure 11-56.
The source of the EMI could be a switching DC voltage regulator, a power-carrying electrical
conductor, or an electric motor. A varying magnetic field that links with an electrical conductor
will induce a voltage in that conductor. As can be seen in Fig. 11-57(a), if two parallel
conductors are used to carry a signal, the (red) conductor closest to the source will have larger
induced voltage levels. By adding up the little equivalent voltages in series, and determining the
voltage difference at the amplifier’s input, we calculate 3 mV. The receiving instrumentation
amplifier will respond as if it is being delivered a normal differential signal. This produces an
error. If the wires are twisted as indicated in Fig. 11-57(b), the induced voltages average out.
The normal-mode voltage is zero in that case. A cable that contains three twisted pairs is shown
in Fig. 11-57(c).
67 Orthogonal is a fancy term for “involving right angles”.

Interference
(Primarily
Magnetic)
Signal Amplifier
Source - 1 mV - 1 mV - 1 mV - 1 mV - 1 mV - 1 mV Input
+ + Normal-
+ + + + +
+ Mode Noise
0V 3 mV
_ _
- 0.5 mV + - 0.5 mV + - 0.5 mV + - 0.5 mV + - 0.5 mV + - 0.5 mV +
(a)
Interference
(Primarily
Magnetic)
Signal Amplifier
Source - 1 mV - 1 mV - 1 mV - 1 mV - 1 mV - 1 mV Input
+ + Normal-
+ + + + +
+ Mode Noise
0V 0 mV
_ _
- 0.5 mV + - 0.5 mV + - 0.5 mV + - 0.5 mV + - 0.5 mV + - 0.5 mV +
(b)
(c)
Figure 11-57.

The electric field component of the EMI noise can be viewed as capacitive coupling. This tends
to produce a common-mode noise component. A twisted pair is susceptible to electric field
coupling [see Fig. 11-58]. The stray capacitances are distributed over the entire length of the
wire. However, to provide a (conceptual) approximation, lumped capacitances are shown.
+ EMI Electric Field Coupling

+
- Common-Mode Stray Capacitances
VCM
Noise Source + VCM
- -
Figure 11-58.
To minimize EMI electric field coupling, a conductive foil shield is placed around the twisted
pair. Remember the “magic” ingredient for capacitance is to have two electrical conductors
separated by an insulator. To minimize that effect, shielding is used. A cable is shown in Fig.
11-59(a). Figure 11-59(b) illustrates the stray capacitances that exist inside the cable.
Capacitance C1 represents the capacitance between the Signal Hi and the shield. Similarly, C2
depicts the capacitance between the Signal Lo and the shield. There is also capacitance between
the two signal conductors. It is designated C3. The electrical schematic of the cable is given in
Fig. 11-59(c). In practice only one side of the shield is usually connected to ground. Any
external capacitive coupling to the shield will then be taken to ground via the drain wire.
Signal Hi
C1 C3
Signal Lo
C2
Shield
(a) (b)
(c)
Figure 11-59.
To observe capacitive coupling effects, you may merely touch the center conductor of an
oscilloscope probe. With the oscilloscope sensitivity set to a few millivolts per division, you will
see a 50 or 60 Hz sine wave on its screen. The AC power wiring has capacitively coupled the
noise to you. (An audio amplifier can also be used and then you will hear a loud 50 or 60 Hz
hum.)
Another option to grounding the shield is to drive it to the common-mode voltage. This means
both sides of the internal stray capacitances will be at the same potential. This prevents
degradation in the CMRR due to non-ideal stray capacitances within the cable. Let us see why
this occurs and how this done.
Active Guard Drive
The input portion of an instrumentation amplifier is shown in Fig. 11-60. The two input op amps
have a zero-differential voltage between their inverting and non-inverting inputs. This means v2
appears at the top of the gain-setting resistor RG while v1 appears at its bottom. This means the
voltage across RG is the differential voltage vD.
+ +
+ 0_V
v2 _ _
v2
R
RG
R
v1
+ _
0_V
+
+
v1 _
Figure 11-60.
In Fig. 11-61 we model the differential input voltage and the common-source voltage. To
promote clarity, the common-mode voltage source has been reversed to place its ground on its
right side. The gain resistor RG is implemented by using two RG/2 resistors in series. Our
immediate goal is to find voltage vx.
Kirchhoff’s voltage law is applied around the upper loop. Starting at the negative terminal of
common-mode voltage source, we move up and encounter the negative terminal of the upper
differential source. We reach the non-inverting input terminal of the upper op amp. Its
differential input voltage is zero. Since two-equal-valued resistors in series are used for RG, they
are each equal to RG/2 and drop one-half of the differential input voltage.

After we cross over the upper resistor, we reach the positive terminal of vx and then our ground
starting point, which means we set the equation to zero. We write the Kirchhoff’s voltage law
equation and solve for vX.
The voltage at the junction of the two resistors is equal to the common-mode voltage. As we
shall see that voltage can be used to drive the shield.
+ +
+ 0_V
vD _
_
2 R
v+D
+
_ _vx+ _+ 2
vCM v_D 2
+ R
vD + _
_
2 0_V
+
Figure 11-61.
In Fig. 11-62(a) the model of the differential signal source and the common-mode voltage source
is included. Observe the source resistance (rS) for the differential voltage source is incorporated.
Capacitor C1 is the stray capacitance of the Hi input signal lead to the shield. Similarly,
capacitor C2 represents the stray capacitance from the Lo input signal lead to the shield. To
focus on the effects of the CMRR, the superposition theorem is used to set the differential input
signal source to zero [see Fig. 11-62(b)]. Figure 11-62(c) describes the problem. The stray
capacitances are rarely equal. This means the AC voltage division that occurs will deliver
unequal portions of the common-mode noise to the non-inverting and inverting inputs of the
instrumentation amplifier. Consequently, the CMRR will be degraded.

+
+
-
- +
+ -
-
(a)
+
- +
(b)
+
+
-
-
+
(c)
Figure 11-62.
Figure 11-62(d) shows an approach to maintain a high CMRR by making the stray capacitances
irrelevant. Instead of taking the shield to ground, it is driven to the common-mode voltage.

The implementation in indicated in Fig, 11-62(e). A voltage follower is used to buffer the gain
resistors. The op amp should be a high-speed, wide-bandwidth unit. This is because common-
mode noise can occur at frequencies much higher than 60 Hz. The op amp should be able to
drive large capacitive loads. Shielded cables quite often have several picofarads per unit length
(e.g., picofarads per foot or picofarads per meter). The common-mode rejection of an
instrumentation amplifier is tremendous at low frequencies but degrades at higher frequencies.

11-9 Inside the Op Amp
The IC op amp is a simply marvelous tool. It is a physically small “block of voltage gain”,
which through the use negative feedback and very few external components, allows us to
construct amplifiers with outstanding characteristics. The op amp’s internal design consists of a
cascaded amplifier system. However, circuit design techniques are employed that would be
difficult or impossible to use in a discrete circuit design. Let us examine the inside of an op amp
to dispel some of its mystery. This exercise will help us understand more fully its applications
and limitations68. The fundamental block diagram of an IC op amp is illustrated in Fig. 11-63.
Figure 11-63 indicates the op amp circuitry has been broken down into four basic cascaded
stages: an input differential amplifier with a differential output, a current mirror, an inverting
current-to-voltage converter, and a unity-gain, push-pull emitter follower output stage. In the
text to follow, we investigate the function and operation of each of these stages. The equivalent
circuits we shall present are very rudimentary and are merely representative of the kinds of
circuits employed.
Fundamental Block Diagram of the IC Op Amp
Differential input
and output
vIN2
+ Input
Frequency compensation
capacitor
Unity voltage gain stage
Differential that is used to provide
Amplifier output drive current
CC
i C1 i C2
i C2 - i C1 Push-Pull vOUT
Current High-Gain
Inverting Emitter
Mirror
Amplifier Followers
Serves as a current-to-voltage
vIN1 converter
- Provides a single output

current equal to the difference
between its two input currents
Figure 11-63.
A typical pnp BJT differential input stage has been depicted in Fig. 11-64(a). Observe that it is
biased by a constant-current source. The actual constant-current source found in most IC op
amps is rather complex and so the details have been omitted for clarity.
68 Not to mention its proper “care and feeding”!

Inside the Op Amp 355
The tail current established by the constant-current source is usually a rather small value. (This
helps keep the non-inverting and inverting input bias currents small e.g., nA. The reason is
simple - if the emitter and collector currents are small, the base currents must be small as well.)
The values shown in Fig. 11-64(a) are typical of those reported for the LM324 op amp.
Specifically, the tail current is 6 A, and the pnp input transistors offer a DC of about 66, which
means their base currents will be about 45 nA.
Constant-current source biasing is employed for three main reasons. First, it provides an
extremely stable Q point. Second, as mentioned in Section 11-3, constant-current source biasing
improves the common-mode rejection of a differential amplifier. Third, transistors take up less
real estate than resistors on a silicon substrate.
To understand how the differential amplifier processes both DC and AC inputs, we offer the two
worst-case conditions depicted in Fig. 11-64 (b) and (c). In Fig. 11-64(b) we see that if vIN2 is 1
V more positive than vIN1, then iC1 will be equal to the tail current IT, and iC2 will be zero.
Specifically, Q1 will be conducting fully, and Q2 will be in cutoff. The converse situation is
shown in Fig. 11-64(c).
The situations shown in Fig. 11-64(b) and (c) represent saturation, which is a non-linear mode of
operation. The main point to note is the tail current is shared between the two transistors and is
exchanged between their two collectors.

Operation of the Input Differential Amplifier
15 V 15 V
Model of actual
IT current source IT
6 A 6 A OFF
ON
iB iB
+ + + -
45 nA 0.7 V 0.7 V 45 nA 0.7 V 0.3 V
-
Q1 Q 2 - -+ -
Q1 Q 2 + + +
- + vIN1 = 0 V
vIN2 = 1 V
 DC1 = 66  DC2 = 66 -
-
i C1 i C2 I C1 I C2
3 A 3 A Non-inverting input 6 A 0 A
Inverting input
(a) (b)
15 V
IT
6 A ON
OFF
- +
0.3 V 0.7 V
+ - + Q1 Q 2 - +
+
vIN1 = 1 V vIN2 = 0 V
-
-
i C1 i C2
0 A 6 A
(c)
Figure 11-64.
As we can see in Fig. 11-63, the output of the differential amplifier is directed into a current
mirror. This amazing circuit provides a single current that is equal the difference between the
two collector currents. The operation of the current mirror is described in Fig. 11-65. First, we
note that transistor Q3 has a short between its collector and base, which effectively leaves only
the base-emitter p-n junction. Consequently, transistor Q3 is called a “diode-connected” BJT.
Since both BJTs are constructed on the same piece of silicon substrate, their electrical
characteristics are matched closely. A current forced into the collector of Q3 must develop a
corresponding base-emitter voltage vBE3 that complies with Q3’s V-I transfer characteristic.
Observe that BJT Q4 has its base-emitter connected in parallel with that of BJT Q3. The two
BJTs have the same base-emitter voltage. Since the two BJT’s have virtually identical V-I
characteristics, iC4 must match, or mirror, the current that flows through Q3.

The Current Mirror
1
A current of 2 microamps i C3
i B3 + i B4 ~= 0 i C4
is directed into the
=2A =2A
collector of Q3
6
Q3 Q4 The collector current
A "diode connected" BJT + + of Q4 matches (mirrors)
vBE3 = vBE4
the collector current of Q3 .
- 4 -
10.0  A 10.0  A
i C3 i C4
8.0  A 8.0  A
6.0  A 6.0  A
2 5
4.0  A 4.0  A The transfer characteristic
Q3 must obey its of Q4 matches the transfer
transfer characteristic. characteristic of Q3 .
2.0  A 2.0  A
0 200 400 600 800 0 200 400 600 800
v BE3 (mV) 3 v BE4 (mV)

A base-emitter of 600 mV
is established by the
collector current.
Figure 11-65.
The current mirror has been added to the differential input stage as indicated in Fig. 11-66(a).
The only difference is the emitters of transistors Q3 and Q4 have been taken to a negative 15-V
DC power supply rather than ground. This has no effect on the operation of the current mirror.
The Q1 collector current iC1 is directed into the collector of Q4. This makes iC4 equal to iC1.
Since Q4 mirror’s the Q3 collector current we can write:
iC4 = iC3 = iC1
By applying Kirchhoff’s Current Law (KCL) to the node indicated in Fig. 11-66(a), we see a
differential current is formed.
iDIF = iC2 - iC1
Note that we have assumed arbitrarily that iC2 is greater than iC1. This means the differential
current flows out of the node. If is iC1 greater than iC2, the current will flow into the node, which
means iDIF will be negative. This situation is indicated in Fig. 11-66(b). Transistor Q1 is
conducting and transistor Q2 is in cutoff.69
69 This just happens to be a non-linear boundary. However, iDIF will be negative anytime iC1 is greater than iC2.
Operation of the Input Differential Amplifier and the Current Mirror
15 V 15 V
IT IT
6 A
Q1 + -
Q2 0.7 V 0.3 V
+ - + + +
- - Q1
Q2 + + +
v IN1 v IN2 v IN1 =0 V v IN2 = 1 V
- - - -
i C1 i C2 > i C1 i C1 = 6  A i C2 = 0  A
Node
i C3 = i C1
i C1 i C1
i DIF = i C2 - i C1 = 6 A i DIF = i C2 - i C1
Q3 Q4 The curre nt diffe re nce Q3 Q4 = 0 A - 6 A
i C3 = i C1 is obtaine d by applying = -6  A
KCL to the indicate d node.
Because of the
curre nt mirror action
(a) (b)
Figure 11-66.
In Fig. 11-67 we see the third stage, which is a high-gain inverting voltage amplifier. It has an
impedance Zf that provides negative feedback. Because the amplifier offers a large voltage gain,
we can regard its input to be a virtual ground. Further, its input resistance is so large the current
directed into its input terminal flows through the feedback impedance. Again, because the
amplifier’s input is a virtual ground, the voltage developed across the feedback impedance
creates the output voltage vOUT70. The circuit arrangement forms what can be best described as
an inverting current-to-voltage converter.
An Inverting Current-to-Voltage Converter
Zf
+ -
-
+
+ v
OUT = -i Z f
A high-gain voltage amplifier

-
with a large input resistance
Virtual ground
Figure 11-67.
70 This same line of reasoning was used in Section 9-13, which introduced the op amp inverting amplifier circuit. It should
therefore be familiar. If not, considering reviewing Section 9-13. We will wait right here for you.
In Fig. 11-68(a) we see how a single BJT can be used to create a simple, high-voltage-gain,
inverting amplifier. A constant-current source is used to establish a reasonable DC collector
current, and therefore, it also produces a reasonable transconductance gm. Now, when we recall
the AC equivalent resistance of a current source can be extremely large, the voltage gain can also
be extremely large (e.g., greater than 1000). This becomes clear when we remember the voltage
gain of a common-emitter amplifier is –gmrC. This is also detailed in Fig. 11-68(a).
Transistor Q5 serves as the heart of the inverting current-to-voltage converter as shown in Fig.
11-68(b). Observe that the feedback impedance is a capacitor. The capacitor (typically just a
few picofarads) provides dominant-pole frequency compensation. The capacitor is used to
prevent the op amp from going into oscillation. When an amplifier oscillates it generates an AC
signal that is quite often at a high frequency (e.g., several megahertz). Chapter 13 in Volume
Three reveals why oscillations in an amplifier are undesirable and how dominant-pole frequency
compensation works.
The output stage of the op amp is a unity-gain buffer. Consequently, the output of the inverting
current-to-voltage converter has been called vOUT. The same signal appears at the output of the
buffer and has been called vOUT.

Adding the Inverting Current-to-Voltage Converter
rC
Inverting current-to-voltage converter
Figure 11-68.
The unity-gain buffer stage is described in Fig. 11-69. First, we see in Fig. 11-69(a) that two
complementary (npn and pnp) BJTs are employed. The input signal is applied at their base
terminals, and the output is taken from their emitters. Hence, the BJTs are being used as emitter
followers. This provides a low output impedance. The circuit arrangement is called push pull.
This is covered in Chapter 15 in Volume Three extensively. It is used to provide a relatively
large output current (e.g., 40 mA in the case of the LM324 op amp). The push-pull circuit is also
noted for its efficiency. Specifically, it tends to minimize power losses. In Fig. 11-69(b) we see
that BJT Q7 conducts on the positive half-cycles and Q6 is in cutoff. Current is pushed down
through the load (rL). In Fig. 11-69(c) we see that BJT Q6 conducts on the negative half-cycles
and Q7 is in cutoff. Current is pulled up through the load (rL). The complete circuit is shown in
Fig. 11-69(d).

Diodes D1 and D2 are used to bias the base-emitters of the two BJTs. Since the diodes are
conducting, their AC resistance is low. This permits the AC signal vOUT to reach the base
terminal of Q7. Do not let the concept worry you at this point. It is described thoroughly in
Chapter 15 in Volume Three.
Adding the Output Buffer to Complete the Op Amp Internal Circuit

15 V 15 V
Positive half-cycle
Q7 Emitte r followe rs Q7
PUSH
0 t ON Curre nt is pushe d down
through the load.
+ + + OFF +
v IN rL vL v IN rL vL
0 t
Q6 Q6
- - - - The unity-gain buffer
is a complementary
-15 V -15 V 15 V push-pull emitter
follower stage.
(a) (b)
IT I BIAS
Q7
Q1 Q2
+ - D1
v IN1 +
- D2 v OUT
15 V i C1 i C2
Negativ e half-cycle CC -
Q6
PULL + +
t Q7 v IN2 +
0 OFF Curre nt is pulle d up
- Q5
through the load.
+ Q4 i C1 i DIF = i C2 - i C1 v OUT
+ ON
v IN rL vL Q3
0 t
Q6 -
- -
-15 V
-15 V
(c) (d)
Figure 11-69.
Working through the op amp’s equivalent circuit is a significant achievement! We now have
greater insight as to how the op amp accomplishes its amazing behavior.

Drill Problems
Section 11-1
11-1. Determine IC, gm, rC, and Av for the common-emitter amplifier in Fig. 11-70.
Figure 11-70.
11-2. Determine IC, gm, rC, and Av for the common-emitter amplifier in Fig. 11-70. Assume
that RE has been changed to 4.3 k and rL is 5.6 k.
11-3. Determine IC, gm, rC, and Av for the common-base amplifier in Fig. 11-71.
Figure 11-71.

11-4. Determine IC, gm, rC, and Av for the common-base amplifier in Fig. 11-71. Assume that
RE has been changed to 4.7 k and rL is 6.8 k.
11-5. The JFET in Fig. 11-72 has an IDSS of 20 mA and a gfso of 2200 S. Find ID, the JFET’s
gm, the equivalent source-to-ground resistance (rS1), and AV.
11-6. The JFET in Fig. 11-72 has an IDSS of 30 mA and a gfso of 2700 S. The emitter resistor
RE has been changed to 1.5 k. Find ID, the JFET’s gm, the equivalent source-to-ground
resistance (rS1), and AV.
Figure 11-72.
Section 11-2
11-7. What is meant by the term “differential amplifier”? Why is it important to understand the
concept of a differential amplifier?
11-8. Some regard an amplifier with a differential input to be “universal”. What is meant by
that description?
Note: Odd-numbered problems 11-9 and 11-11 are dependent, while even-numbered problems
11-10 and 11-12 are dependent.
11-9. Perform a DC analysis of the differential amplifier given in Fig. 11-73. Specifically,
determine IT, IE, IC, VC, VOUT, VB, and VE. Assume the BJTs are silicon devices and the
left and right halves of the circuit are symmetrical.
11-10. Perform a DC analysis of the differential amplifier given in Fig. 11-73. Assume the DC
supply voltages have been changed to 20 V. Determine IT, IE, IC, VC, VOUT, VB, and VE.
Assume the BJTs are silicon devices and the left and right halves of the circuit are
symmetrical.

Figure 11-73.
11-11. Using the DC collector current determined in Prob. 11-9, find gm, r, Avd(oc), Rout, Rin(+),
and Rin(-) for Fig. 11-73. Assume the BJTs have an hfe of 180.
11-12. Using the DC collector current determined in Prob. 11-10, find gm, r, Avd(oc), Rout, Rin(+),
and Rin(-) for Fig. 11-73. Assume the BJTs have an hfe of 120.
Section 11-3
11-13. If the left and right halves of the circuit in Fig. 11-73 are matched, what is its open-circuit
common-mode voltage gain Avcm(oc)? If the collector resistor for Q1 is 10.1 k, while the
collector resistor for Q2 remains 10 k, would this still be true? Explain briefly.
11-14. What is the difference between differential amplifiers with a differential output versus
those with a single-ended output? How do their respective common-mode voltage gains
compare?
Note: Odd-numbered problems 11-15 and 11-17 are dependent, while even-numbered
problems 11-16 and 11-18 are dependent.
11-15. Perform a DC analysis of the differential amplifier given in Fig. 11-74. Determine IT, IE,
IC, VC1, and VC2. Assume the BJTs are silicon devices with identical electrical
characteristics.

11-16. Perform a DC analysis of the differential amplifier given in Fig. 11-74 if the DC supplies
are changed to ±15V. Determine IT, IE, IC, VC1, and VC2. Assume the BJTs are silicon
devices with identical electrical characteristics.
Figure 11-74.
11-17. Using the collector current, you determined in Prob. 11-15, find gm, r, Avd(oc), Rin(+), Rin(-),
Rout, Avcm(oc), CMRR, and CMRR(dB). Assume the BJTs in Fig. 11-74 are matched with
an hfe of 110.
11-18. Using the collector current, you determined in Prob. 11-16, find gm, r, Avd(oc), Rin(+), Rin(-),
Rout, Avcm(oc), CMRR, and CMRR(dB). Assume the BJTs in Fig. 11-74 are matched with
an hfe of 180.
11-19. Given the general circuit shown in Fig. 11-75, assume that V1 is 7.02 V and V2 is 7.05 V.
Determine the differential voltage and the common-mode voltage.
11-20. Given the general circuit shown in Fig. 11-75, assume that V1 is 3.04 V and V2 is 2.96 V.
Determine the differential voltage and the common-mode voltage.

Figure 11-75.
Note: Problems 11-21, 11-22, and 11-23 are dependent.
11-21. Perform a DC analysis of the differential amplifier given in Fig. 11-31. First, determine
the voltage across RE. (Hint: The devices are silicon and the 5.1-V zener diode is in
breakdown.) Now determine the emitter current through Q3 and its approximate collector
current. This is the tail current for the differential pair. Assume that Q1 and Q2 have
matched electrical characteristics and determine their respective collector currents. What
are their respective collector-to-ground voltages? Find the approximate base-to-ground
voltages for Q1 and Q2. Find VC3, VB3, and VE3. (Hint: The base terminal is the zener
voltage drop more positive than the –VEE voltage of -12 V.) Find the voltage drop across
resistor R1 (VR1) and the resulting current through it (IR1). Determine the current through
the zener diode and be sure to include the result of Q3’s base current.
11-22. Using the results of the DC analysis performed in Prob. 11-21, use the computed
collector currents to find gm and r for each of the three BJTs. (Note that an hfe of 110 is
to be used for all three BJTs.) Also find rO for Q3. Find Avd(oc), Rout, Rin(+), and Rin(-) for
Fig. 11-31. Be sure to include the effects of RB when you compute the input resistances.
11-23. The impedance “looking into” the collector of Q3 is quite large and is given by Eq. 9-47:
 β RE 
rIN(COL)  1 +  rO
 rπ + rB + RE 
This is the equivalent emitter-to-ground resistance (rE) of the differential pair. Use the
approximation given by Eq. 11-42 to compute the open-circuit common-mode voltage
gain. (Hint: Avcm(oc)  -RC/2rE where rE is rIN(COL)3.) Compute the CMRR and CMRR(dB)
for Fig. 11-31.
Section 11-4
11-24. Determine the Avd(oc), Avd, Rout, Rin(-) and Rin(+) of the op amp differential amplifier circuit
given in Fig. 11-76.
11-25. Determine the Avd(oc), Avd, Rout, Rin(-) and Rin(+) of the op amp differential amplifier circuit
given in Fig. 11-76 if R1 is changed to 150 k and R2 is changed to 560 k.

11-26. Why are voltage followers sometimes used to buffer the inverting and non-inverting
inputs of an op amp differential amplifier? Explain briefly.
Figure 11-76.
Section 11-5
11-27. Given the amplifier in Fig. 11-77, determine the overall voltage gain Av if Av1 is 30, Av2 is
-250, and Av3 is 1. Also, determine the overall voltage gain in decibels.
11-28. Given the amplifier in Fig. 11-77, determine the individual stage voltage gains in decibels
if Av1 is 30, Av2 is -250, and Av3 is 1. Also, determine the overall voltage gain in decibels.
11-29. Given the amplifier in Fig. 11-77, the first stage has a gain of 22 dB, the second stage has
a gain of 43 dB, and the third stage has a gain of -0.3 dB. Determine the overall voltage
gain in decibels. What is the overall straight ratio voltage gain? (Hint: Eq. 8-35 beckons
your recollection.)

Figure 11-77.
Section 11-6
11-30. Capacitors C6 and C7 in Fig. 11-38 are called ______________ or ______________
capacitors.
11-31. Briefly explain the function of capacitors C6 and C7 in Fig. 11-38. Specifically, why are
they necessary?
Note: Even-numbered problems 11-32, 11-34, and 11-36 are dependent, while odd-numbered
problems 11-33, 11-35, and 11-37 are dependent.
11-32. Given the cascaded amplifier in Fig. 11-38, assume the DC power supplies have been
lowered to  12 V. Using the relationships provided in Fig. 11-39, perform a DC
analysis. Assume that VGS(OFF) for the 2N5457 ranges from -0.5 to -6 V, and its IDSS
ranges from 1.0 to 5.0 mA.
11-33. Given the cascaded amplifier in Fig. 11-38, assume the DC power supplies have been
lowered to  10 V. Using the relationships provided in Fig. 11-39, perform a DC
analysis. Assume that VGS(OFF) for the 2N5457 ranges from -0.5 to -6 V, and its IDSS
ranges from 1.0 to 5.0 mA.
11-34. Continue the analysis of the cascaded amplifier begun in Prob. 11-32. Perform a
complete AC analysis using Fig. 11-41 as a guide. Specifically, determine the Rin, Rout,
Av(oc) and Av for the cascaded amplifier system. Assume the hfe for both 2N3904
transistors is 85 (because of the reduced collector current). The gfso for the 2N5457
ranges from 1000 to 5000 S.
11-35. Continue the analysis of the cascaded amplifier begun in Prob. 11-33. Perform a
complete AC analysis using Fig. 11-41 as a guide. Specifically, determine the Rin, Rout,
Av(oc) and Av for the cascaded amplifier system. Assume the hfe for both 2N3904
transistors is 80 (because of the reduced collector current). Assume the gfso of the
2N5457 is 1000 S.
11-36. Using your answers to Prob. 11-34, complete the AC analysis of the cascaded amplifier
system by finding Av, Avs, Ai, Ais, and Ap. Use Fig. 11-42 as a guide.
11-37. Using your answers to Prob. 11-35, complete the AC analysis of the cascaded amplifier
system by finding Av, Avs, Ai, Ais, and Ap. Use Fig. 11 -42 as a guide.
Section 11-7
11-38. Perform an AC analysis of the op amp cascaded amplifier system given in Fig. 11-78.
Specifically, find Rin, Rout, Av1, Av2, Av(oc)3, and Av3 Complete the analysis by finding
Av(oc) and Av of the cascaded amplifier system. Assume the maximum output voltage
swing for the LM324 is from VS – 2V to -VS + 0.5V. What is the maximum undistorted
peak-to-peak output voltage? What is the corresponding maximum peak-peak input
voltage?
11-39. Perform an AC analysis of the op amp cascaded amplifier system given in Fig. 11-78.
However, resistors R1 and R2 have both been changed to 470 k. Resistors R3 and R5
remain at 20 k each, but resistor R4 is now at 470 k. All other components remain the
same. To conduct the AC analysis, find Rin, Rout, Av1, Av2, Av(oc)3, and Av3 Complete the
analysis by finding Av(oc) and Av of the cascaded amplifier system. Assume the maximum
output voltage swing for the LM324 is from VS – 2V to -VS + 0.5V. What is the
maximum undistorted peak-to-peak output voltage? What is the corresponding
maximum peak-peak input voltage?
11-40. What is the function of resistors R2, R5, R6, and R7 in Fig. 11-78?
Figure 11-78.

Section 11-8
11-41. What are the key advantages of the instrumentation amplifier (e.g., Fig. 11-45) over the
op amp differential amplifier circuit [e.g., Fig. 11-35(a)]? What is the sole advantage of
the instrumentation amplifier in Fig. 11-45 over the differential amplifier with buffered
inputs in Fig. 11-35(b)?
11-42. Determine the differential voltage gain of the instrumentation amplifier in Fig. 11-79.
Figure 11-79
11-43. Determine the differential voltage gain of the Analog Devices AD620 instrumentation
amplifier in Fig. 11-50 if RG is 1 k.
11-44. An instrumentation amplifier has a gain equation of:
Vout  2R 
Avd = = 1 + 
(V2 − V1 )  RG 
If R is 49.9 k, find the required RG if Avd is to be 500. Show your work neatly.
11-45. Briefly explain why signal conductors should be twisted. How does a twisted pair affect
normal-mode noise? How does it affect common-mode noise?
11-46. Capacitive coupling responds primarily to the __________(magnetic field, electric field)
component of EMI noise.
11-47. An aluminum foil shield is placed around a twisted pair to reduce the
__________(magnetic field, electric field) component of EMI noise.
Section 11-9
11-48. List the names of the four basic functional blocks found inside the typical op amp.
11-49. In Fig. 11-64(b), assume the tail current IT is 20 A and iC1 is 12 A. Determine iC2 and
iDIF.
11-50. In Fig. 11-64(b), assume the tail current IT is 20 A and iC1 is 5 A. Determine iC2 and
iDIF.
11-51. What is the purpose of the frequency compensation capacitor CC? Explain briefly.
Design Problems
11-52. An op amp differential amplifier is to have a differential voltage gain of 200, an output
resistance of 0 , and an input resistance (Rin+ or Rin-) of at least 100 k. An LM324
(Fig. 11-76) op amp is to be used with a DC power supply of ±12 V. Draw a complete
schematic diagram of your design.
11-53. An op amp differential amplifier is to have a differential voltage gain of 200, an output
resistance of 0 , and the input resistances (Rin+ and Rin-) are both to be equal 200 k.
An LM324 op amp is to be used with a DC power supply of ±15 V. Draw a complete
schematic diagram of your design.
Note: The troubleshooting problems are based on the cascaded amplifier system given in Fig.
11-80. The LM324 op amp is used. The LM324 has a typical output voltage range from VS –
2V to -VS + 0.5V. It also has a typical output current limit of ± 40 mA.
11-54. To troubleshoot a system, we must first understand its operation when it is working
normally. Determine the peak value of Output A in Fig. 11-80. Also, find the peak
voltages you would expect to find at pins 1 and 7 of the LM324 op amp in Fig. 11-80.
11-55. The cascaded system in Fig. 11-80 has Output B across the load rL. Determine the most
reasonable cause. Explain the reasoning behind your selection briefly.
a. Resistors R1 and R2 are each 47 k instead of 470 k.
b. Resistor R8 is not installed, or possibly open.
c. Resistor R8 is 20 k instead of 200 k.
d. The load resistance is wrong. It is 100  instead of 10 k.
11-56. The cascaded system in Fig. 11-80 has Output C across the load rL. Determine the most
11-57. The cascaded system in Fig. 11-80 has Output D across the load rL. Determine the most

Figure 11-80.
EDA Problems
11-58. Use Multisim to perform a transient (time-domain) analysis of the cascaded amplifier
system given in Fig. 11-80 with a 1-V peak sinusoidal input at a frequency of 1 kHz.
Determine Av for the system.
11-59. Use Multisim to perform a transient (time-domain) analysis of the cascaded amplifier
system given in Fig. 11-80 with a 1-V peak sinusoidal input at a frequency of 1 kHz. Use
simulations to solve Problems 11-55 through 11-57.
11-60. Employ Multisim to determine the DC voltages VD1, VG1, VS1, VC4, VE4, VC2, VE2, VB2, VC3,
VB3, and VE3 with respect to ground. Determine Av for the discrete cascaded amplifier
circuit given in Fig. 11-38. Replace the 2N5457 n-channel JFET with a 2N3822 n-
channel JFET. Do not include capacitors C6 and C7. Multisim does not “like” ideal
capacitors placed in parallel with ideal voltage sources. Be sure to AC couple both
channels of the oscilloscope.
11-61. Simulate the AD620 instrumentation amplifier application circuit provided in Fig. 11-50.
Set v2 to 50 mV peak at a frequency of 1 kHz. Set v1 to 20 mV peak at a frequency of 1
kHz. Use Multisim to determine the differential voltage gain AVD. Use the two-channel
oscilloscope to verify the differential input voltage and output voltage waveforms
separately.
11-62. The common-mode rejection ratio degrades as the frequency of the common-mode
voltage increases. The common-mode noise is 5 kHz in Fig. 11-81. Use Multisim to
determine the common-mode rejection ratio.

Figure 11-81.
11-63. An active guard circuit is shown in Fig. 11-82. The OPA633 is a wide-bandwidth, unity-
gain buffer and serves as the shield driver. Note that its input is taken from the gain
resistor circuit. Use Multisim to verify the output of the buffer matches the common-
mode input voltage of 1-volt peak at 60 Hz.

Figure 11-82.

12
Frequency Response
T he primary purpose of a linear voltage amplifier is to take a small voltage signal and
make it larger. A linear amplifier should accomplish this without altering the shape of
its input signal. Further, the voltage amplifier should serve this function regardless of
the shape, size, or frequency of the applied input signal. We have noted the causes of non-
linear amplitude responses (e.g., clipping) in our previous studies. In this chapter, we examine
the effects of signal frequency. We shall see that amplifiers which employ coupling and
bypass capacitors (to eliminate negative feedback) have a limited low-end frequency response.
All amplifiers have a limited high-frequency response. Our studies in this chapter shall reveal
why this is true. In this chapter, we pursue:
◼ The Frequency Domain
◼ RC Filters and the RC Low-Pass Filter
◼ Poles and Zeros
◼ Bode Approximations
◼ RC High-Pass Filters
◼ Low-Frequency Roll-Off in RC-Coupled Amplifiers
◼ The Effects of the Emitter- and Source-Bypass Capacitors
◼ Single-Supply Op Amps and Low-Frequency Roll-Off
◼ BJT Device Capacitances and the BJT High-Frequency Model
◼ FET Device Capacitances and the FET High-Frequency Model
◼ The Miller Effect
◼ High-Frequency Roll-Off in BJT and FET Amplifiers
◼ High-Frequency Roll-Off in Frequency-Compensated Op Amps
◼ A MESFET is a GASFET or a GaAs MESFET

• Explain the frequency domain concept.
• Analyze RC high-pass filter circuits.
• Explain the characteristics of poles and zeros.
• Employ the Bode approximations to analyze RC high-pass filters.
• Describe the causes of low-frequency roll off in BJT and FET amplifiers.
• Analyze single-supply op amp circuits and predict their low-frequency –roll-off.
• Analyze RC low-pass filter circuits including the application of the Bode
approximations.
• Determine BJT and FET device capacitances from their data sheet information.
376 FREQUENCY RESPONSE
• Define the Miller effect.
• Predict the high-frequency roll-off in BJT and FET amplifiers.
• Predict high-frequency roll-off in (non-inverting) op amp circuits.
• Describe the characteristics of MESFETs.
• Use EDA to analyze the frequency response of amplifier circuits.
12-1 The Frequency Domain

When we examine a voltage or current whose amplitude varies with time, we are performing
an analysis in the time domain. However, we can also analyze how a quantity’s amplitude
varies with frequency. In this case, we are working in the frequency domain. The relationship
between the time and frequency domains is illustrated in Fig. 12-1. Complex waveforms are
non-sinusoidal. Complex periodic waveforms can be represented as a sum of sine waves71.
Conversely, we can say that a non-sinusoidal waveform contains these frequencies. Figure 12-
1 shows us that an oscilloscope is used to display amplitude versus time while a spectrum
analyzer is employed to display amplitude versus frequency. Harmonics are sine waves
whose frequency is an integer multiple of the fundamental waveform frequency. The
harmonic content of the complex waveform is made obvious when the spectrum analyzer is
used. A frequency domain analysis can provide a greater insight into the nature of a non-
sinusoidal waveform.
Many other quantities have amplitudes that vary with frequency. For example, at high
frequencies, the voltage gain of an amplifier tends to decrease as the signal frequency is raised.
In a similar fashion, the current and power gains, and the input and output impedances all vary
with the signal frequency. Frequency domain analysis is an extremely powerful tool. We use
it extensively.
71 Mathematically, the Fourier series expansion (taught in calculus) is used to accomplish this. Calculus is the area of
mathematics, which deals with limits, instantaneous rates of change, and the finding of areas and volumes. Among students
there is a widespread misunderstanding that calculus is hard. The truth is that calculus is the Latin term, for pebble.
Pebbles, of course, are small rocks. It is rocks that are hard. Calculus, on the other hand, is simply scary.
The Frequency Domain 377
The Time and Frequency Domains
Amplitude
Spectrum Analyzer Display

of the Complex Waveform
(Amplitude Versus Frequency)
Oscilloscope Display
1 kHz 3 kHz
of the Complex Waveform
(Amplitude Versus Time)
Frequency
Time
Figure 12-1.
Using Multisim to Demonstrate Time- and Frequency-Domain

Analyses
In Fig. 12-2(a) we have a circuit with three AC voltage sources in series. (Remember that
voltage sources in series add together.) The important distinction here is the sources are at
different frequencies. In this example a two-channel oscilloscope is selected from the suite of
virtual instruments. The oscilloscope displays the composite waveform in the time domain
[see Fig. 12-2(b)]. To contrast, a spectrum analyzer is also selected from the suite of virtual
instruments. It shows the spectral components of the composite waveform [see Fig. 12-2(c)].
Circuits and systems that have more than one frequency are classified as being non-linear.

Oscilloscope Spectrum Analyzer
(Time-Domain) (Frequency-Domain)
(a) Circuit
Figure 12-2.
The Frequency Domain 379

12-2 RC Filters and the RC Low-Pass Filter
RC filter circuits are used to alter or modify the frequency content of electrical signals. By
studying RC low-pass and RC high-pass filter circuits, we can acquire the knowledge
necessary to understand the frequency response limitations (and capabilities) of electronic
circuits. We start with the simple RC low-pass filter circuit shown in Fig. 12-3.
The RC Low-pass Filter

As its name implies, the RC low-pass filter circuit tends to pass low frequencies and reject
high frequencies. While we often describe voltage amplifiers in terms of their voltage gain, it
is customary to describe circuits and systems in terms of their voltage transfer function.
The voltage transfer function is a generic term, while voltage gain is a special case. In fact, the
voltage gain of an amplifier is its voltage transfer function. To avoid introducing additional
notation, we shall use Av(oc) to represent the open-circuit voltage transfer function of a filter.
(The use of Av(oc) implies that no current flows into or out of the terminals connected across the
capacitor.)
Vout
Av(oc) = (12-1)
Vin
The voltage transfer function of an RC low-pass filter circuit will have magnitudes of unity (1)
or less. Recall that voltages gains (transfer functions) that are less than one (1) are described
as voltage attenuation.
The RC Low-Pass Filter Circuit
+
+ R
V
Vin C out
-
-
Figure 12-3

Recall the capacitive reactance (Xc) of a capacitor is its opposition to the flow of AC
(sinusoidal) current and is measured in ohms. The magnitude of the capacitive reactance is
inversely related to the signal frequency as given by Xc = 1/2fC. This means at sufficiently
low frequencies a capacitor acts like an open circuit. At adequately high frequencies, the
capacitor can be thought of as a short circuit. These limits can be applied to the low-pass filter
to determine the corresponding limits on its voltage transfer function. This is indicated in Fig.
12-4.
At low frequencies, no current will flow through resistor R since the capacitor behaves like an
open circuit. This means no voltage will be dropped by the resistor and all of Vin will appear
across the output. This will make the voltage transfer function unity. At high frequencies, the
output voltage will approach zero since the capacitor behaves like a short circuit. (All of Vin
will be dropped by the resistor.) Since Vout is zero, the voltage transfer function will also be
zero.
The RC Low-Pass Filter Circuit Voltage Transfer Function Limits
R
+
+
High Fre quencie s V C V ~
(~ out =0V
in = short)
-
- V 0V
R out
A v(oc) = ~
= ~
= 0
+ Vin Vin
+
V
Vin C out
R
- +
- +
C V ~
= Vin
Vin (~ out
= open)
- Vin
Low Freque ncie s V
- out
~
A v(oc) = = ~
= 1
Vin Vin
Figure 12-4
An RC Low-pass Filter Application
The usefulness of an RC low-pass filter is illustrated in Fig. 12-5. An analog audio signal has
been connected to the input of an amplifier. At the amplifier’s output, a high-frequency hiss is
heard in the background. Since the RC low-pass filter offers unity gain to low frequencies, the
desired signal passes through unaltered. Simultaneously, the circuit reduces the amplitude of
the high-frequency noise72. The output signal will be “clean”.
72High-frequency noise is present in all electronic systems. For example, with no audio signals, if you turn up the volume of
an amplifier, you will often hear a hiss. That is high-frequency noise. In the laboratory, this can be observed on the
displays of oscilloscopes. When the sensitivity (voltage gain) is increased, the oscilloscope trace will start to look “fuzzy”.
The RC Low-Pass Filter 381
Removing High-Frequency Noise with the RC Low-Pass Filter Circuit
Lower- Fre quency Signal
+
High- Fre que ncy Noise
R
+ + "Cle an" Output
Noisy Signal
V
Vin C out
- -
Figure 12-5
The RC low-pass filter circuit is important in analog signal processing. In addition, we shall
see that it occurs in various forms in every electronic circuit. It can help us understand the
high-frequency limitations of amplifiers.
Analyzing the RC Low-pass Filter

The RC low-pass filter circuit can be analyzed by applying voltage division. Our goal here is
to find its voltage transfer function. The AC analysis is like that for the simple resistive
voltage divider shown in Fig. 12-6(a) and the general impedance (Z) case depicted in
Fig. 12-6(b). In Fig. 12-6(c) we are reminded that impedances have magnitudes and phase
angles. The capacitive reactance Xc has a –j associated with it. The –j corresponds to a phase
angle of–90o. Consequently, we are going to have to “dust off” our phasor algebra to perform
the required analysis. The analysis of Fig. 12-6 (c) is reasonably simple.
Z2 − jX c
Vout = Vin = Vin
Z1 + Z 2 R − jX c
Vout − jX c X c  − 90
Av(oc) = = = (12-2)
Vin R − jX c 2 −1 Xc
R + X c2  − tan
R
As Eq. 12-2 indicates, we must divide the numerator phasor by the denominator phasor. To
accomplish the division, both the numerator and denominator have been placed in polar form.
We divide the denominator magnitude into the numerator magnitude and subtract algebraically
the denominator phase angle from the numerator phase angle.

Voltage Transfer Functions are Found by Using Voltage Division
R1
+
+ V
R2 out R2
V Vin A v(oc) =
Vin R2 out = =
R1 + R2 Vin R1 + R2
-
-
Z1
(a)
+
+ V
Z2 out Z2
V Vin A v(oc) =
Vin Z2 out = =
Z1 + Z2 Vin Z1 + Z2
-
-
(b)
R
+
+ - jXc V - jXc
out
V Vin A v(oc) =
Vin -jXc out = =
R - jXc Vin R - jXc
-
-
(c)
Figure 12-6
Example 12-1. Find the voltage transfer function Av(oc) for the RC low-pass filter shown
in Fig. 12-6(c). Specifically, find the magnitudes and phase angles of Av(oc) at the frequencies
of 1.06 kHz, 10.6 kHz, and 106 kHz. Assume that R is a 1.5-k resistor and the capacitor is a
0.01-F unit.
Solution: In each case, we must first find the capacitive reactance, and then employ Eq.
12-2 to find the magnitude and phase associated with the voltage transfer function Av(oc). We
examine the instance when f = 1.06 kHz.
1 1
− jX c = − j =−j = -j15.01 k  -j15.0 k
2fC 2 (1.06 X 10 )(0.01X 10 −6 )
3

Vout − jX c X c  − 90
Av(oc) = = =
Vin R − jX c Xc
R 2 + X c2  − tan −1
R
15.01 X 10 3  − 90 15.01 X 10 3  − 90

= = = 0.995  − 5.7
15.0 X 10 3 15.075 X 10 3  − 84.3
(1.5 X 10 3 ) 2 + (15.0 X 10 3 ) 2  − tan -1
1.5 X 10 3
At a frequency of 1.06 kHz, the voltage transfer is nearly unity (0.995), and produces a small
phase lag (-5.7o). (Remember negative phase angles are said to be lagging, while positive
angles are called leading.) Next, we repeat the analysis at f = 10.6 kHz.
Vout − jX c X c  − 90
Av(oc) = = =
Vin R − jX c Xc
R 2 + X c2  − tan −1
R
1.50 X 10 3  − 90 1.501 X 10 3  − 90

= = = 0.7071  − 45
1.50 X 10 3 2.121 X 10 3  − 45
(1.5 X 10 3 ) 2 + (1.50 X 10 3 ) 2  − tan -1
1.5 X 10 3
This case stands out as being unique in that at this frequency the magnitude of the
capacitive reactance is equal to the resistance. We complete the problem by conducting the
same analysis at 106 kHz. The analysis is conducted in the same fashion. For brevity, we
merely report the results.
-jXc  -j150 
Av(oc) = 0.0996 -84.3
The results of these calculations are illustrated in Fig. 12-7.
In the case where the input voltage has a peak value of one volt, the output voltage will have a
peak value that is equal to the magnitude of the voltage transfer function. Further, the input
voltage is taken as the reference. This means it is defined as having a phase shift of zero
degrees.
Consequently, the phase shift exhibited by the output voltage will be equal to the phase shift
inherent in the voltage transfer function. These points are illustrated in Fig. 12-7.
The reader should note the times axes have not been drawn to scale. (This was done for the
purpose of clarity.)
Lowpass Filter Analysis Results
v out = A v (oc) v in
Frequency = 1.06 kHz
=A v (oc)(1 V  0 )
Input = 1 V peak 0
= (0.996 V  -5.7  )(1 V 0 )
Output = 0.996 V peak -5.7
= 0.996 V -5.7 
R
1.5 k Frequency = 10.6 kHz
+ Input = 1 V peak 0
+ Output = 0.707 V peak -45
C V
Vin out
0.01  F
-
-
Frequency = 106 kHz

Input = 1 V peak 0
Output = 0.0996 V peak  -84.3
Figure 12-7
Semi-log Plots
The frequencies of analysis shown in Fig. 12-7 are a factor of ten apart. A factor of ten change
in frequency is referred to as a decade. Quite often, the frequency response of an electronic
system may be described over several decades (e.g., from 0.1 Hz to 100 MHz). It is not
feasible to use a linear frequency scale. Consequently, it is customary to use a logarithmic
(base 10) frequency axis. This is illustrated in Fig. 12-8. Note that log 0 is undefined73.
Therefore, 0 Hz cannot appear on the logarithmic frequency axis. The vertical axis is linear.
Consequently, the graph is called a semi-log plot. The vertical axis is usually scaled in
decibels (dB). The reason for the use of decibels will become clear as our work progresses.
73 In the general case, log x approaches negative infinity as the argument x approaches zero. For example, log 0.01 = -2,
log 0.0001 = -4, and log 10-12 = -12.
Graph paper that has the form indicated in Fig. 12-8 is called four-cycle semi-log graph paper.
It is called “four-cycle” since it can be used to plot data over four decades.
Semi-log Plots
70
Voltage Transfer
Function (or Voltage 60
Gain) Axis
50 .
Linear Scale 40
in decibels (dB)
30
20
10
0 1 2 10 100 1k 10 k
20 30 40 50 60 70 80 90 One of the
four decades
shown.
log 2 = 0.301
30.1% of the distance
of the scale between
1 and 10. Freque ncy Axis (Hz)
Figure 12-8
Both the magnitude and the corresponding phase shift of a voltage transfer function changes
with frequency. Consequently, two separate graphs are often used to describe the frequency
response of a given electronic circuit or system. A typical example is shown in Fig. 12-9. The
frequency response of the low-pass filter analyzed in Example 12-1 is depicted. The
magnitude of the voltage transfer function is in decibels. We are dealing with Av(oc) rather than
Av.
Av(oc)(dB) = 20 log Av(oc) (12-3)
Since the voltage transfer function was shown to be close to unity at low frequencies, the
voltage transfer function is nearly 0 dB [Fig. 12-7]. At 10.6 kHz, the voltage transfer function
has value of approximately –3 dB. One decade above 10.6 kHz (106 kHz) the voltage transfer
function is about –20 dB. These points will become clear shortly. Hang on.

Example 12-2. Find the magnitude in decibels of voltage transfer function Av(oc) for the
RC low-pass filter given in Fig. 12-7 at the frequencies of 1.06 kHz, 10.6 kHz, and 106 kHz.
For convenience, the low-pass filter circuit has been repeated in Fig. 12-9(a).
Solution: We simply apply Eq. 12-3 to the results of the analysis conducted in Example
12-1.
Av(oc)(dB) = 20 log Av(oc) = 20 log 0.995 = -0.0435 dB
Av(oc)(dB) = 20 log Av(oc) = 20 log 0.0.707 = -3.01 dB
Av(oc)(dB) = 20 log Av(oc) = 20 log 0.0996 = -20.0 dB
These points have been labeled in Fig. 12-9(b). The corresponding phase angles have been
graphed in Fig. 12-9(c).
Low-Pass Filter Frequency Response

0 -0.04 dB
-3.0 dB
10
A v(oc)
in dB
20 -20 dB
30
R
1.5 k
+ 40
+ 100 1k 10k 100k 1M
C V
Vin out 1.06 kHz 10.6 kHz 106 kHz
0.01  F Frequency (Hz)
- (b)
-
0
-5.7o
(a) Phase 20
Shift
in
40
Degrees
-45 o
60
80 -84.5 o
100
100 1k 10k 100k 1M
1.06 kHz 10.6 kHz 106 kHz
Frequency (Hz)
(c)
Figure 12-9
12-3 Poles and Zeros
When we analyze circuits and systems, it is the poles and zeros contained in the transfer
function that dictate the shapes of the amplitude and phase response as a function of frequency.
By examining the nature of poles and zeros, it becomes easier to understand the behavior of a
circuit or system frequency response. Further, we can then begin to comprehend “advanced”
topics such as the frequency compensation methods used to prevent an amplifier or a control
system from oscillating.
Zeros
When we encounter a jωRC term in the numerator of a transfer function, it is called a
zero. (The resistance R and the capacitance C may be the equivalents of series and/or parallel
combination.) An example is given by Eq. 12-4.
jωRC (12-4)
Recall that a “+j” is equivalent to an angle of +90o. Therefore, the zero contributes a constant
90o of phase lead and has a magnitude of ωRC. This is defined by Eq. 12-5.
RC90 (12-5)
The next thing to remember is the definition of the radian frequency ω as given by Eq. 12-6.
 = 2f (12-6)
Equation 12-6 reminds us that ω is directly proportional to the frequency, which means the
magnitude of the zero grows with increasing frequency. In fact, at DC (0 Hz) the zero has a
magnitude of zero – hence its name! The frequency at which the magnitude of the zero
goes to unity (1) is called the zero frequency fz74. Its definition is straight forward.
74 The corresponding radian frequency is indicated ωz.

As we saw previously, we usually employ decibels to describe the magnitude of a frequency
response. Consequently, Eq. 12-8 describes the amplitude response of the zero in decibels.
20log 2fRC 90 (12-8)
Normalized Frequency
To simplify our discussions of frequency response, it is helpful to normalize75 the frequency
response. We draw on Eq. 12-7 and invert (flip over) both sides.
1
2RC = (12-9)
fz
Next, we apply Eq. 12-9 to the magnitude of the zero in decibels.
 1   f
20log 2fRC = 20log [(2RC) f ] = 20log   f  = 20log
 f z   fz
Equation 12-8 can now be written in normalized frequency form as Eq. 12-10.
f
20log 90 (12-10)
fz
Let us now examine Eq. 12-10. The zero frequency fz is determined by the resistance and
capacitance. If the frequency f is one tenth of fz,, the magnitude of the ratio f/fz is 0.1, and the
decibel value becomes -20 dB as shown below.
f 0.1 f z
20log 90 = 20log 90 = 20log 0.1 90 = −20 dB 90
fz fz
If the frequency f is equal to fz, the ratio f/fz is 1, and the decibel value becomes 0 dB as shown
below.
f f
20log 90 = 20log z 90 = 20log 1 90 = 0 dB 90
fz fz
75 By “normalize” we mean the frequency f is referenced to the zero frequency fz. Then we can look at cases where f is
smaller, equal to, or many times fz. All zeros will behave the same way about their fz. The only “detail” is the actual zero
frequency.
Poles and Zeros 389

If the frequency f is equal to 10fz, the ratio f/fz is 10, and the decibel value becomes 20 dB as
shown below.
f 10 f z
20log 90 = 20log 90 = 20log 10 90 = 20 dB 90
fz fz
The amplitude and phase responses are plotted on a semi-log graph in Fig. 12-10. We can see
the zero has a constant slope of +20 dB per decade that passes through 0 dB at fz and has a
constant phase angle of 90o.
The Frequency Response of the Zero (jf/fz )
60
+20 dB/Decade
40
Slope
Amplitude
in dB
20
20
0.1f z fz 10 f z 100f z 1000f z
Frequency (Hz)
(a)
180
Phase 135 Constant 90 Degrees

of Phase Shift
Shift
in
90
Degrees
45
-45
0.1f z fz 10 f z 100f z 1000f z
Frequency (Hz)
(b)
Figure 12-10
The Second Form of a Zero
A second possible for of a zero exists as given by Eq. 12-11.
1 + jωRC (12-11)
As before, the zero frequency fz occurs when ωRC is equal to unity. Consequently, the zero
frequency is again given by Eq. 12-7. Further, using the same reasoning developed
previously, we can place the zero in normalized frequency form. However, this form is not
purely imaginary. It also has a real part. We must keep them separate.
 1  f
1 + j 2fRC = 1 + j (2RC) f = 1 + j  f = 1 + j
 fz  fz
To determine the magnitude of the zero, and its associated angle, we must make a rectangular-
to-polar conversion.
f
2 2
f  f  fz  f  f
1+ j = 12 +   tan-1 = 1 +   tan-1 (12-12)
fz  fz  1  fz  fz
We can now find the magnitude in decibels.

2
 f  f
20log 1 +   tan -1 (12-13)
 fz  fz
If we set the frequency f is one tenth of fz,, the magnitude of the ratio f/fz is 0.1, and the decibel
value, and the angle are both nearly zero.
2 2
 f  f  0.1 f z  0.1 f z
= 20log 1 + (0.1) tan -1 0.1
2
20log 1 +   tan -1
= 20log 1 +   tan -1
 fz  fz  fz  fz
= 20log 1 + 0.01 tan -1 0.1 = 20log1.004 99 tan -1 0.1
= 0.0432 dB 5.71  0.04 dB 5.7
If the frequency f is equal to fz, the ratio f/fz is 1, and the decibel value becomes about +3 dB,
and the angle is 45o as shown below.
2 2
 f  f  f  fz
= 20log 1 + (1) tan -11
2
20log 1 +   tan -1
= 20log 1 +  z  tan -1
= 20log 2 tan -11 = 3.01 dB 45
Poles and Zeros 391

If the frequency f is equal to 10fz, the ratio f/fz is 10, and the decibel value becomes about 20
dB, and the angle approaches 90o as shown below.
2 2
 f  f  10 f z  10 f z
= 20log 1 + (10 ) tan -110
2
20log 1 +   tan -1
= 20log 1 +   tan -1
= 20log10.05 tan -110 = 20.04 dB 84.3
Several other values have been included in Table 12-1. The amplitude and phase responses
(Eq. 12-13) are plotted on a semi-log graph in Fig. 12-11.
Table 12-1. The Zero (1 + jωRC) = (1+ jf/fz) Frequency Response
Frequency Amplitude Phase Angle
0.01fz 0 dB 0.57o  0o
0.1fz 0.04 dB  0 dB 5.7o  0o
fz 3.01 dB  3 dB 45o
10fz 20.04 dB  20 dB 84.3o  90
100fz 40 dB 89.4o  90o
In Fig. 12-11 we can see the zero is flat at 0 dB until it reaches the zero frequency fz at which
the amplitude has increased to about 3 dB. Beyond that point the amplitude response has a
constant of slope +20 dB per decade. The phase shift is zero degrees far below the zero
frequency. However, about one decade below fz, the phase starts increasing and reaches
+45oat fz. The phase continues to increase and nearly reaches +90o one decade above fz..
Beyond that point, it is essentially constant at 90o.

The Frequency Response of the Zero (1 + jf/fz)
80
60
+20 dB/Decade
Amplitude Slope
in dB
40
20
+3 dB
0
0.01fz 0.1f z fz 10 f z 100f z 1000f z
Frequency (Hz)
(a)
90 Degrees
100
80
Phase
Shift 45 Degrees
60
in
Degrees
40
20
0 Degrees
0
0.01fz 0.1f z fz 10 f z 100f z 1000f z
Frequency (Hz)
(b)
Figure 12-11
The Pole
Poles are the opposites of zeros. The amplitude of a zero grows with increasing frequency.
However, the amplitude of a pole decreases with increasing frequency. A zero offers a phase
lead (positive angles) while a pole provides a phase lag (negative angles). The simpler pole
form is given as Eq. 12-14.
1
(12-14)
jRC
First, let us examine the phase response of the pole.
Poles and Zeros 393

1 10 1(0 − 90) 1
= = =  − 90 (12-15)
jRC RC 90 RC RC
Therefore, the simple pole contributes a constant 90o of phase lag. Next, we look its
amplitude response in decibels.
Just as we saw with the zero, the “magic” condition is when ωRC = 1. This occurs at the pole
frequency fp. Its derivation is developed in the same manner as we found fz. Therefore, we
merely state the result as Eq. 12-16.
1
fp = (12-16)
2RC
The pole amplitude response in decibels is developed below.
1
20 log = 20 log1 − 20 log RC = 0 − 20 log RC = −20 log RC
RC
We place this result in normalized frequency form.
 1 
− 20 log RC = −20 log 2fRC = −20 log f (2RC ) = −20 log f   = −20 log f
 fp  fp
 
Thus, the amplitude of the simple pole in normalized frequency form is given by Eq. 12-17.
f
− 20 log (12-17)
fp
As we saw for the simple zero, when f = fp, the amplitude response will be at 0 dB. The slope
is -20 dB per decade as depicted in Fig. 12-12.

The Frequency Response of the Pole 1/j(f/fp)
20
-20 dB/Decade
0
Slope
Amplitude
in dB
-20
-40
60
0.1f p fp 10 f p 100f p 1000f p
Frequency (Hz)
(a)
0
Phase -45 Constant -90 Degrees

of Phase Shift
Shift
in
-90
Degrees
-135
-180
-225
0.1f p fp 10 f p 100f p 1000f p
Frequency (Hz)
(b)
Figure 12-12
The Second Form of a Pole [1/(1 + jωRC)]

The second pole form (Eq. 12-18) describes the simple low-pass RC filter we examined in
Section 12-276.
1
(12-18)
1 + jRC
76 This will become clear shortly. Notice that “obviously” was not used like “Obviously, the second pole form describes the
simple low-pass RC filter.” In the extreme, some physics folks enjoy the phrase, “It is intuitively obvious to the most
casual observer from an infinite distance.”
Poles and Zeros 395

We take the low-pass RC filter transfer function written in terms of resistance and capacitive
reactance, apply a little algebra and it becomes – wait for it – obvious it is the second form of a
pole.
We place Eq. 12-18 in normalized frequency form.
1 1 1 1
= = =
1 + j 2fRC 1 + j (2RC ) f  1  f
1 + j f 1+ j
 fp  fp
 
To determine the magnitude of the pole, and its associated angle, we employ a rectangular-to-
polar conversion.
1 1
=
f f
1+ j 2
fp  f  fp
12 +   tan -1
 fp  1
 
 f 
1 0 − tan -1
 f p 
10  1 f
= = =  − tan -1
2 2 2 fp
 f  f  f   f 
1+   tan -1 1+   1+  
 fp  fp  fp   fp 
     
1 f (12-19)
 − tan -1
2 fp
 f 
1+  
 fp 
 
We can now find the magnitude of the pole in decibels.

 
 
    2 
 
20log 
1   − tan -1 f = 20 log 0 − 20 log  1 +  f    − tan -1 f
 2  fp    fp   fp
  f      
    
 1+  f  
  p 

 2
  f   f
− 20 log 1 +    − tan-1 (12-20)
  fp   fp
  
 
As before, we shall find the magnitude in decibels of the pole and its attendant phase angle at a
frequency of 0.1fp, fp, and 10fp. Hence, for f = 0.1fp we have:
 2  2
  f   -1 f
 0.1 f p   0.1 f p
− 20 log 1 +    − tan = −20 log 1 +    − tan-1
  fp   fp   fp   fp
       
  

2

 
= −20 log 1 + (0.1)  − tan-1 0.1 = −20 log 1.01  − tan-1 0.1 = −0.0432 dB  − 5.71
For f = fp we obtain:
 2  2
  f   f   fp   fp
− 20 log 1 +    − tan -1
= −20 log 1 +    − tan-1
  fp   fp   fp   fp
       
 
= −20 log 1 + (1)


2

 
 − tan-11 = −20 log 2  − tan-11 = −3.01 dB  − 45
Similarly, for f = 10fp we find:

 2  2
  f   -1 f
 10 f p   10 f p
− 20 log 1 +    − tan = −20 log 1 +    − tan-1
  fp   fp   fp   fp
       
  

2

 
= −20 log 1 + (10)  − tan-110 = −20 log 101  − tan-110 = −20.04 dB  − 84.3
Several other values have been included in Table 12-2. The amplitude and phase responses
(Eq. 12-20) are plotted on a semi-log graph in Fig. 12-13.
Poles and Zeros 397

Table 12-2. The Pole 1/(1 + f/fp) Frequency Response
Frequency Amplitude Phase Angle
0.01fp 0 dB -0.57o  0o
0.1fp -0.04 dB  0 dB -5.7o  0o
fp -3.01 dB  -3 dB -45o
10fp -20.04 dB  -20 dB -84.3o  -90o
100fp -40 dB -89.4o  -90o
In Fig. 12-13 we can see the pole is flat at 0 dB until it reaches the pole frequency fp at which
the amplitude has decreased to about -3 dB. Beyond that point the amplitude response has a
constant of slope -20 dB per decade. The phase shift is zero degrees far below the pole
frequency. However, about one decade below fp , the magnitude of the phase starts
increasing and reaches -45oat fp. The phase lag continues to increase and nearly reaches -
90o one decade above fp. Beyond that point, it is essentially constant at -90o.
By comparing Tables 12-1 and 12-2, we see the magnitudes are identical. However, the
magnitude of the pole and the phase shift offered by the pole are both negative.

The Frequency Response of the Pole (1 + jf/fp)
0
-3 dB -20 dB/Decade
20 Slope
Amplitude
in dB
40
60
80
0.01fp 0.1f p fp 10 f p 100f p 1000f p
Frequency (Hz)
(a)
0 Degrees
20
-45 Degrees
Phase
Shift 40
in
Degrees
60
-90 Degrees
80
100
0.01fp 0.1f p fp 10 f p 100f p 1000f p
Frequency (Hz)
(b)
Figure 12-13
Compare Fig. 12-13 with Fig. 12-14 for the low-pass RC filter. They have precisely the same
to their amplitude and phase responses. Let us revisit the low-pass RC filter using the “pole-
zero” perspective to its analysis.
Poles and Zeros 399

The Low-Pass RC Filter Transfer Function - Revisited
The low-pass filter circuit analyzed in Section 12-2 has been repeated in Fig. 12-14. Let us
derive its transfer function. First, we apply voltage division, and then divide both sides by Vin.
1
j C
Vout = Vin
R+ 1
j C
1
Vout jC
Av ( oc ) = =
Vin R+ 1
j C
Next, we multiply the numerator and denominator by jωC.

1
jC jC 1
Av ( oc ) = =
R+ 1 jC jRC + 1
jC
Vout 1 1
Av ( oc ) = = = (12-21)
Vin 1 + jRC f
1+ j
fp
Thus, we see the transfer function of the RC low-pass filter offers a single pole and can be
placed in normalized frequency form. The pole frequency is given by Eq. 12-16. Employing
the R and C values given in Fig. 12-14, permits us to determine its value.
1 1
fp = = = 10.6 kHz
2RC 2 (1.5 k)(0.01 F)
So, now it should be clear that 1.06 kHz is 0.1fp, 10.6 kHz is fp, and 106 kHz is 10fp. Those
were the frequencies used in Example 12-1! The concepts should begin to make sense. One
last comment is in order. When a zero goes to zero, the transfer function goes to zero. When a
pole goes toward zero, the transfer function goes toward infinity – like an extremely long pole.
That is the rationale behind their names77.
77 Yes, the pole name explanation is somewhat rather lame, but it is the “standard” explanation. Do not blame this author!
Low-Pass Filter Frequency Response
0 -0.04 dB
-3.0 dB
10
A v(oc)
in dB
20 -20 dB
The pole fre quency is

10.6 kHz.
30
R
1.5 k
+ 40
+ 100 1k 10k 100k 1M
C V
Vin out 1.06 kHz 10.6 kHz 106 kHz
0.01  F Frequency (Hz)
- (b)
-
0
-5.7o
(a) Phase 20
Shift
in
40
Degrees
-45 o
60
80 -84.5 o
100
100 1k 10k 100k 1M
1.06 kHz 10.6 kHz 106 kHz
Frequency (Hz)
(c)
Figure 12-14
12-4 Bode Approximations78

The Bode plot (named after Dr. Hendrik W. Bode of Bell Telephone Laboratories) uses
straight lines to approximate the smooth frequency response curves. The Bode approximations
are shown in Fig. 12-15.
78 Bode is pronounced “BOH-dee” or your instructor may get angry - pronounced “ang-gree”.
Bode Approximations 401
The rules for drawing a Bode plot are straightforward. To approximate the gain amplitude
response, we have:
◼ Determine the pole frequency (fp) by using Eq. 12-16.
◼ For all frequencies below fp, the gain is approximated as zero decibels (0 dB).
◼ The gain decreases at a rate of –20 dB per decade as the frequency is increased
beyond fp.
The phase approximations are similar.
◼ The phase angle is zero degrees for all frequencies at least one decade below fp.
◼ The phase angle becomes negative and decreases linearly passing through –45o at fp
as the frequency increases.
◼ At one decade above fp, the phase angle reaches –90o, and remains –90o for all
frequencies beyond that point.
Inspection of Fig. 12-15(a) reveals the Bode approximation of the amplitude is very close to
the actual curve. (The worst-case error is at the corner frequency fp where the amplitude is
actually –3 dB rather than 0 dB.) However, Fig. 12-15(b) indicates the Bode approximation of
the phase response is not as good.

The Bode Approximation Has Been Placed on
the Actual Pole Frequency Response Curves
Bode approximation
0
Slope = -20 dB/decade

20
A v(oc)
(dB)
40
60
0.01fp 0.1fp fp 10fp 100fp
Frequency (Hz)
(a) Open-circuit voltage transfer function in decibels (dB).
Bode approximation
0
20
40
Phase Shift
(Degrees)
60
Bode approximation
80
100
0.01fp 0.1fp fp 10fp 100fp
Frequency (Hz)
(b) Phase shift in degrees.
Figure 12-15.
The Bode approximations can also be applied to the zero as shown in Fig. 12-16. The rules
are similar.
Bode Approximations 403

The Bode Approximations to the Frequency
Response of the Zero
80
60
Amplitude Slope = +20 dB/decade

in dB
40
Bode approximation
20
0
0.01fz 0.1f z fz 10 f z 100f z 1000f z
Frequency (Hz)
(a)
100
80
Phase
Shift
60
in Bode approximation
Degrees
40
Bode approximation
20
0
0.01fz 0.1f z fz 10 f z 100f z 1000f z
Frequency (Hz)
(b)
Figure 12-16
The rules for drawing a Bode plot are straightforward. To approximate the gain amplitude
response, we have:
◼ Determine the zero frequency fz by using Eq. 12-7.
◼ For all frequencies below fz, the gain is approximated as zero decibels (0 dB).
◼ The gain increases at a rate of 20 dB per decade as the frequency is increased
beyond fz.

The phase approximations are similar.
◼ The phase angle is zero degrees for all frequencies at least one decade below fz.
◼ The phase angle increases linearly passing through 45o at fz as the frequency
increases.
◼ At one decade above fz, the phase angle reaches 90o, and remains 90o for all
frequencies beyond that point.
We shall employ these approximations when we predict the frequency response of circuits and
systems.
12-5 RC High-Pass Filters

Now that we have become experts on the RC low-pass filters, we are ready to move on to the
RC high-pass filters. An RC high-pass filter is shown in Fig. 12-17. At sufficiently high
frequencies, the capacitor’s capacitive reactance is so low that we may approximate the
capacitor as a short circuit. Under this condition, we can see the input and output voltages will
be equal. This means the voltage transfer function is unity at those high frequencies. As the
frequency is lowered, the capacitive reactance of the capacitor will increase. At adequately
low frequencies, the capacitive reactance becomes large enough to regard the capacitor as an
open circuit. Under this condition, the output voltage will be zero. This means the voltage
transfer function will also be zero.
The RC High-Pass Filter Circuit Voltage Transfer Function Limits
C
(~
= short)
+
+
High Fre que ncie s V R V ~ V
in out = in
-
C - V Vin
out
A v(oc) = ~
= ~
= 1
+ Vin Vin
+
R V C
Vin out
(~
= open)
- +
- +
Vin R V ~
out =0V
-
Low Fre que ncie s - V 0V
out
A v(oc) = ~
= ~
= 0
Vin Vin
Figure 12-17
The analysis of the RC high-pass filter to obtain its transfer function can be accomplished by
employing voltage division.
RC High-Pass Filters 405

Vout R
Av(oc) = = (12-22)
Vin 1
R+
j C
We multiply the numerator and the denominator of the fraction by jωC to obtain Eq. 12-23.
Vout R jC jRC jRC

Av(oc) = = = = (12-23)
Vin 1 jC jRC + 1 1 + jRC
R+
jC
The RC high-pass filter transfer function has a simple zero in its numerator and a
denominator pole of the second form. With a little thought, it becomes clear that fz will be
equal to fp in this case.
1
fz = f p = (12-24)
2RC
The transfer function in Eq. 12-23 can be thought of as the product of a pole and a zero. This
means if they are expressed in decibels, we can add them together. Consequently, we may
employ graphical addition to obtain the overall amplitude response. In Fig. 12-18 we see the
Bode approximations of the zero and the pole are added together to give the composite
response, which is the amplitude response of the low-pass filter.

The High-Pass Filter Amplitude Response
40 40 dB
20 dB Each data point

20 Zero from the zero like
40 dB is -
Amplitude
in dB 0 dB
0
-20 dB
20
-40 dB
40
0.01f z 0.1f z fz 10 f z 100f z
40
Pole
20
Amplitude
in dB 0 dB 0 dB 0 dB
0
-20 dB
20
added to each
-40 dB corresponding pole
data point like -40 dB.
40
0.01f p 0.1f p fp 10 f p 100f p
40
20 dB
Zero 0 dB 40 dB
20
+ + + +
Pole 0 dB -20 dB -40 dB
Amplitude -20 dB
in dB
+ The sum (e.g.,
0
0 dB 40 dB - 40 dB) defines
-40 dB the composite response
(e.g., 0 dB) at the
20 + Low-End corresponding frequency.
0 dB Corne r Fre que ncy
40
0.01f L 0.1fL fL 10 fL 100f
L
Figure 12-17
At high frequencies, its transfer function is at 0 dB. When the frequency is lowered to fL, the
response develops a corner. Consequently, that unique frequency is called the low-end corner
frequency. It is given by Eq. 12-25.
1
fL = fz = f p = (12-25)
2RC
The actual amplitude response at fL will be at -3 dB. For frequencies below fL, the amplitude
response has a slope of +20 dB per decade.

If we also remember that when we have angles associated with the terms in the product, we
also add the angles. Therefore, we may also employ graphical addition to determine the
overall phase response. This is illustrated in Fig. 12-18.
The High-Pass Filter Phase Response

90
o o o o
Each 90-degree
o
+90 +90 +90 +90 +90 data point from
the zero is -
45
Phase Shift Zero
in Degrees
0
-45
-90
0.01fz 0.1f z fz 10 f z 100f z
45
o o
0 0
0
Phase Shift
in Degrees
Pole
-45
o
-45 o
-90
added to each
-90
corresponding pole
o data point like
-90
-90 degrees.
-135
0.01fp 0.1f p fp 10 f p 100f p
90
o
+90
o
+90 o
+90 +
45
+ + -90
o
Phase Shift o The sum (e.g.,
0 o
0 o 90 degrees - 90 degrees)
in Degrees +90
0 defines the composite
+ response (e.g., 0 degrees)
Zero -45
o o at the corresponding
+90
-45
+ Low-End frequency.
Pole +
Corne r Fre que ncy o
-90
-90
0.01fL 0.1fL fL 10 fL 100f
L
Figure 12-18
To illustrate the power of this graphical approach, the actual frequency response plots and the
Bode approximations are provided in Fig. 12-19. The actual frequency response plots were
obtained by placing Eq. 12-23 in polar form and graphing the resultant equation (Eq. 12-27).
We have placed Eq. 12-27 in normalized frequency form. (The algebra is identical to that
illustrated previously!)

f f
j 90
Vout jRC fz fz
Av(oc) = = = =
Vin 1 + jRC f 2
1+ j  f 
fp 1+   tan -1 f
 fp  fp
 
2
f  f   f 
Av(oc)(dB) = 20 log − 20 log 1 +    90 − tan-1 (12-27)
fz    f p 
 fp  
High-Pass Filter Frequency Response Low-Pass Filter Frequency Response

0 0
Bode
Approximation
10 10
Amplitude Amplitude
in Decibels 20 in Decibels 20
30 30
40 40
High-End
Corner Frequency
50 50
0.01fL 0.1fL fL 10 fL 100f 1000f 0.001fH 0.01fH 0.1fH fH 10 fH 100f H
L L
Frequency in Hertz Frequency in Hertz
100 0
80 Bode -20
Approximation
Phase Shift Phase Shift
60 -40
in Degrees in Degrees
40 -60
20 -80 High-End
Corner Frequency
0 -100
0.01fL 0.1fL fL 10 fL 100f 1000f 0.001fH 0.01fH 0.1fH fH 10 fH 100f H
L L
Frequency in Hertz Frequency in Hertz
Figure 12-19
To help contrast the differences (and similarities) between the high-pass and low-pass filter
responses, the low-pass filter response has been included in Fig. 12-19. Also note that when
dealing with low-pass filters, it is also customary to specify it high-end corner frequency fH,
which is equal to its pole frequency fp.

12-6 Low-Frequency Roll-Off in RC-Coupled Amplifiers
Remember that input and output coupling capacitors are used to block the DC bias levels while
simultaneously acting like short circuits to the AC signal. In Fig. 12-20, we see a common-base
BJT amplifier, and a common-gate FET amplifier. Both circuits incorporate input and output
coupling capacitors. In Fig. 12-20(b), we emphasize that bypass capacitor C3 does not affect the
low-end frequency response. Its purpose is to prevent the signal from causing variations in VDD.
Amplifiers Which Use Input and Output Coupling Capacitors
-VEE VCC V DD
-15 V 15 V
RE RC C2 RD
7.5 k 3.6 k 47  F C2
rS C1
Q1 C1
100  100  F + rS Q1 +
+ + + +
+ rL Vload + + rL Vload
+ R1
Vs Vs
5 k Vin
Vin - RS V DD -
- -
- - R2 +
C3
1 1
rIN(EMITTER) = rIN(SOURCE) =
gm gm
Ignore the decoupling
Rin = RE || rIN(EMITTER)  r IN(EMITTER) Rin = RS || rIN(SOURCE) capacitor. It has no effect on
the low-frequency roll-off.
Rout = RC Rout = RD
V V
A v(oc) = out = g m R C A v(oc) = out = g m R D
Vin Vin
(a) Dual-supply common-base amplifier. (b) Single-supply common-gate amplifier.
Figure 12-20.
Figure 12-21(a) depicts a non-inverting amplifier employing an op amp. While op-amp based
designs often have a direct-coupled input and output, it may be necessary to capacitively couple
its input, and/or its output if DC levels are present. Recall that resistor R3 is necessary to provide
a DC bias path to ground. An op amp inverting amplifier with coupling capacitors is shown in
Fig. 12-21(b).

Op Amp Non-Inverting and Inverting Amplifiers
Amplifiers with Coupling Capacitors
R2 Rin = R3
200 k Rout = 0 
+V S V R2
15 V A v(oc) = out = 1 +
R1 Vin R1
2 7
- C2
V
A v = load = 1 +
R2
10 k Vin R1
6 +
LF411 +
rs C1
3 rL
+ Vload
+ 4 2 k
600  +
-VS -
+
Vin -15 V
Vs R3
- 10 k Sets the input resistance and
- provides a dc bias path to
ground.
(a) Op amp non-inverting amplifier.
R2 R in = R1
200 k Rout = 0 
+V S V R2
A v(oc) = out = _
C1 R1 15 V Vin R1
rs
2 7
+ - C2
V R
A v = load = _ 2
600  + 10 k Vin R1
6 +
+ LF411 +
Vs Vin 3 rL
+ Vload
4 2 k
-
- -VS -
-15 V
(b) Op amp inverting amplifier.
Figure 12-21.
We may use our universal voltage amplifier model to represent amplifiers such as those shown in
Figs. 12-20 and 12-21. This is indicated in Fig. 12-22(a). The coupling capacitors have not been
replaced with short circuits. We can no longer simply ignore them. As the frequency of the
signal source is lowered, the capacitive reactance (Xc) of the coupling capacitors will become
significant. Subsequently, some of the input signal will be lost across capacitor C1, and some of
the amplifier’s output signal will be lost across capacitor C2. The signal losses will increase as
the frequency is lowered. This is what causes low frequency roll-off in an RC-coupled
amplifier. Its voltage gain falls off as the frequency is lowered.
Low-Frequency Roll-Off in RC-Coupled Amplifiers 411

Analyzing the Effects of the Input and Output Coupling Capacitors
rS C1 R out C2
+
+
+ 1 k A
v(oc)V1 + 3 k +
+ + +
R in 150V1
Vs rL
20 k - V2 Vload
Vin V1 10 k
-
- - - -
(a) Employing the voltage amplifier model.
V1 R in
=
C1 Vs R in + r s
rS
(~
= short)
+
+ 1 k +
High Fre que ncie s
R in
Vs 20 k V1
Vin
rS C1
- -
+ + -
+ 1 k +
R in 0V
Vs V1 V1
20 k C1 ~
= ~
= 0
Vin rS Vs Vs
(~
= open)
- - +
- + 1 k +
R in
V 20 k V1 ~
=0V
Low Fre quencies s Vin
- -
-
(b) Examining the high-pass nature of the input circuit.
Figure 12-22.
Observe in Fig. 12-22(a) that we have defined Vin and V1. The input signal to the amplifier is Vin,
while V1 is that portion of the input signal that reaches Rin. It is V1 that is amplified. The high-
and low-frequency limits on the input circuit are illustrated in Fig. 12-22(b). At high
frequencies, the input coupling capacitor C1 acts like a short circuit and V1 will be equal to Vin.
In a simple RC high-pass filter, the maximum value of the voltage transfer function is unity.
However, as shown in Fig. 12-22(b), the maximum value of the voltage transfer function of the
input circuit is limited by the voltage division that occurs between Rin and rS. As the frequency is
lowered, more and more of the input signal will be lost across C1. The voltage transfer function
magnitude will approach zero. With this intuitive feel for the behavior of the input circuit, let us
make a more in-depth analysis. Our next step will to be to determine the pole frequency
produced by capacitor C1. It will be designated as fp1.

In all cases, the pole frequency can be found by determining the Thevenin equivalent
resistance "seen" by the capacitor (RTH). We then find the pole frequency by using Eq. 12-28.
1
f pn = (12-28)
2πRTHn C n
In Eq. 12-28, fpn is the pole frequency produced by capacitor Cn while RTHn is the Thevenin
equivalent resistance "seen" by that capacitor. Once we know the pole frequency fpn, we also
know the zero frequency fzn.
For simple RC high - pass filters :

(12-29)
f zn = f pn
Equation 12-29 reminds us the zero frequency fzn for capacitor Cn is equal to the pole frequency
fpn. Figure 12-23 shows us how to find the Thevenin equivalent resistances. Notice that in both
cases, the Thevenin equivalent resistance is given by the sum of the two circuit resistances.
Many beginning students jump to the wrong conclusion that the equivalent resistance seen by the
capacitor is the parallel combination of the two resistors. The correct way to view the situation is
to consider the path the capacitor’s discharge current would take through the circuit. Do not let
the ground connection distract you.
Using Thevenin's Theorem to Find the Pole Frequencies

rS C1 Voltage Amplifie r M ode l R out C2
+
+
+ + +
+ A v(oc)V1
Vs R in rL
V1 - Vload
-
- -
C1 C2
+ +
RTH1 = r S + R in RTH2 = R out + r L

rS R out
R in rL
Vs = 0 V A
v(oc)V1 = 0 V
1
1 f p2 =
f p1 = 2 RTH2C2
2 RTH1C1
Figure 12-23.

The voltage transfer function for the input circuit is given by Eq. 12-30.
 f 
 j 
V1 Rin  f z1 
= (12-30)
V s Rin + rS  f 
1 + j f 
 p1 
The bracketed portion of Eq. 12-30 establishes the frequency response. The coefficient in front
of it determines the maximum value of the transfer function. Except for the maximum value
being less than unity, the pole and zero create a frequency response that is identical to the simple
RC low-pass filter. These points are depicted in Fig. 12-24. Recall that a gain of unity
corresponds to 0 dB, while a gain of less than unity equates to a negative dB value.
Input Circuit Bode Approximations

High-pass filter Input circuit
transfer function transfer function
 f 
C f rs C1  j 
j V1 R in  f z1 
fz + =
A v(oc) = + + Vs R in + rs  f 
R f Vs
Rin
V1 1 + j f 
1+ j  p1
fp
- - RTH1 = r s + R in
1
fL = fp = fz = f L1 = f p1 = f z1 =
1
2  RC
2 RTH1C1
High-Pass 0.1 f L1 f L1 10 f L1 Input

0.1 f L fL 10 f L Circuit
Filter 0 dB
0 dB R in Amplitude
Amplitude
20log Response
Response R in + rs
-20 dB fL = fz = fp -20 dB f L1 = fz1 = fp1
Slope = +20 dB/decade Slope = +20 dB/decade
High-Pass Input
o Filter o Circuit
90 Phase 90 Phase
Response Response
o fL = fz = fp o f L1 = f z1 = fp1
45 45
o o
0 0
0.1 f L fL 10 f L 0.1 f L1 f L1 10 f L1
Figure 12-24.

The analysis of the output circuit is like the input circuit analysis. The circuit and the results of
the analysis are presented in Fig. 12-25. In this case, we have defined fz2 and fp2 to be the zero
and pole produced by capacitor C2, respectively.
Analyzing the Effects of the Output Coupling Capacitor
Output circuit
R out C2 transfe r function
+
 f 
A + 3 k +  j 
v(oc)V1 rL
+ Vload
=  fz2 
150V1 rL V2 rL + R out  f 
- V2 Vload 1 + j f 
10 k  p2
RTH2 = R out + r L
- -
f L2 = f p2 = f z2 = 1
2 RTH2C2
0 dB 0.1 f L2 f L2 10 f L2 Output
rL o Circuit
20log 90 Phase
r L + Rout
Output Response
Circuit fL2 = fz2 = fp2
o
-20 dB Amplitude 45
Slope = +20 dB/decade Response
fL2 = fz2 = fp2 o

0
0.1 f L2 f L2 10 f L2
Figure 12-25.
Figure 12-25 provides us with Eq. 12-31. The zero and pole frequencies produced by capacitor
C2 are denoted fz2 and fp2. They are also defined by Eqs. 12-29 and 12-28, respectively.
 f 
 j 
Vload rL  f 
= z2
(12-31)
V2 rL + Rout  f 
1 + f 
 p2 
The transfer function provided by Eq. 12-32 is obtained by inspection of Fig. 12-25.
V2 = Av(oc)V1
V2
Av ( oc ) = (12-32)
V1

Putting It All Together
The overall voltage transfer function from the signal source to the load is voltage gain Avs and is
a function of frequency. This shall be designated Avs[f]. The theory of cascaded voltage
amplifier systems may be applied to determine Avs[f]. Specifically, it is the product of the
individual transfer functions as illustrated in Fig. 12-26. This result is restated by Eq. 12-33.
Finding the Overall Transfer Function

The indiv idual transfer functions of e ach "stage " is define d.
 f   f 
 j   j 
V1 R in  f z1  V2 Vload rL  f z2 
= = A v(oc) =
Vs R in + rS  f  V1 V2 rL + R out  f 
1 + j f  1 + j f 
 p1   p2 
rS C1 Rout C2
+
+ + A v(oc)V1 + +
+
Rin +
Vs V1 V2 rL Vload
-
- - - -
The ov erall transfer function is the product of the indiv idual transfer functions.
 f   f 
 j   j 
V  V  V  V  R in  f z1  rL  f z2 
A vs f  = load =  1  2  load  = A v(oc)
Vs  Vs  V1  V2  R in + rS 1 + j f  rL + R out 
1+ j
f 
 
f p1   f p2 
 
 f  f 
 j  j 
rL R in  f z1   f z2 
= A v(oc)
rL + R out R in + rS  f  f 
1 + j f  1 + j f 
 p1   p2 
 f  f 
 j  j 
f z1   f z2 
= A vs 
 f  f 
1 + j f  1 + j f 
 p1   p2 
Figure 12-26.
 f  f 
 j  j 
Vload f z1   f z2 
Avs  f  = = Avs  (12-33)
Vs  f  f 
 1 + j f  1 + j f 
 p1   p2 

Let us ponder this result carefully. The term Avs is the voltage gain from the signal source to the
loaded output. It includes the effects of both input and output loading. When it was developed,
we assumed the input and output coupling capacitors behaved like short circuits. We now refer
to Avs as the mid-band voltage gain. Equation 12-33 is valid to describe Avs as a function of
frequency. This means it describes the low-end frequency roll-off as well as the behavior of the
amplifier in the mid-band frequency range. We are dealing with transfer function products. This
means the decibel gains and phase shifts are additive. The frequency response of the amplifier is
easy to describe as illustrated in Fig. 12-27.
The Low-End Frequency Response of an RC-Coupled Amplifier
Developing the Amplitude Response Developing the Phase Response
20 log Avs o log f
0
o
-180
0 dB log f
+
+
f L1
0 dB log f o
180
o
90
+ 0
o log f
f L2
0 dB log f
+
o
180
o
90
o log f
0
|| ||
Mid-band Frequency
Response
20 log Avs o f L1 f L2
0 log f
20 dB /decade
o
-180
40 dB /decade Mid-band Frequency

Response Begins
0 dB log f One Decade Abovef L2
f L1 f L2
Composite Amplitude Response Composite Phase Response

Figure 12-27.

When we add the amplitude responses, we find that the amplitude response has a slope of +20
dB/decade for frequencies below fL2. When the frequency is lowered additionally to fL1, the
amplitude response slope changes to +40 dB/decade. The phase response assumes we are
dealing with an inverting amplifier. The phase shift in the mid-band frequency range is therefore
–180o. The phase shift associated with a corner frequency begins influencing the phase shift one
decade above and one decade below the corner frequency. Since each corner frequency can
ultimately contribute 90o of phase shift, we have a total phase lead of 180o. Consequently, phase
lead cancels the -180o of phase lag associated with the inverting amplifier. This means the
composite phase response is approximately zero degrees at sufficiently low frequencies.
Analyzing an Op Amp Inverting Amplifier

R2
200 k
C1 +V S
rs 15 F R1 15 V
2 7 C2
+ - 8 F
600  + 10 k
6 +
+ LF411 +
Vs Vin 3 rL
+ Vload
4 2 k
-
- -VS -
-15 V
Figure 12-28.
Example 12-3. Use the Bode approximations to sketch the low-frequency response of the
op amp inverting amplifier given in Fig. 12-28. Specifically, determine Rin, Rout, Av, Avs,
Avs(dB), fL1, and fL2. Use the straight-line Bode approximations to sketch the amplitude, and
phase response.
Solution: Many of the defining equations are provided in Fig. 12-21(b).
Rin = R1 = 10 k
Rout = 0 
R2 200 k
Av(oc) = Av = − =− = −20
R1 10 k
Rin 10 k
Avs = Av = (−20) = −18.9
Rin + rS 10 k + 600 

Avs(dB) = 20 log Avs  = 20 log 18.9 -180 = 25.5 dB -180
The mid-band voltage gain has a phase angle of –180o associated with it as noted above. We
recall that the input and output low-end corner (fL) , zero (fz), and pole( fp) frequencies are
equal.
RTH1 = Rin + rS = 10 k + 600  = 10.6 k
1 1
f L1 = f z1 = f p1 = = = 1.001 Hz  1 Hz
2πRth1C1 2 (10.6 k)(15 F)
RTH2 = Rout + rL = rL = 2 k
1 1
f L2 = f z 2 = f p2 = = = 9.95 Hz  10 Hz
2πRTH 2 C 2 2 (2 k)(8 F)
The two corner frequencies are approximately one decade apart. The frequency response has
been illustrated in Fig. 12-29.
Figure 12-29.
12-7 The Effects of the Emitter- and Source-Bypass

Capacitors
The emitter- and source-bypass capacitors are used to eliminate AC negative feedback. This
prevents the voltage gain reduction that occurs when AC negative feedback is employed. At
high frequencies, the coupling and bypass capacitors behave like short circuits. As the frequency
is lowered, the capacitive reactances will increase.
The Effects of the Emitter- and Source-Bypass Capacitors 419

By design, the emitter- and source bypass capacitors are sized such that their reactances will
become significant while the reactances of the input and output coupling capacitors are still
negligibly small. This means that the emitter- and source-bypass capacitors will dominate the
low-end frequency response. Consequently, we assume that the bypass capacitors will act like
opens while the input and output coupling capacitors act like short circuits. In Fig. 12-30, we see
the high-, and low-frequency equivalent circuits for the common-emitter amplifier. The open-
circuit voltage gain will vary with frequency. It will be denoted as a function of frequency
Av(oc)[f]. At sufficiently high frequencies, the open-circuit voltage gain is given by Eq. 12-34.
V2
Av(oc)[f] = = − g m RC (12-34)
V1
The open-circuit voltage gain of the common-emitter amplifier will roll off as the frequency is
lowered and become defined by Eq. 12-35.
V2 g m RC
Av(oc)[f] = =− (12-35)
V1 1 + g m RE
The Common-Emitter Amplifier

V2
A v(oc) [f] = = - gm R C
V1
VCC High Fre quencie s Q1

rS
+
+ RC
Vs + V2
R1 RC
C2 V1 R1 R2
-
C1 + + - -
rS
Q1
+ V2
+
Vs + + Q1
R2 RE rS
V1 C3 +
-
- Low Freque ncie s + RC
- Vs + V2
V1 R1 R2
RE
-
- -
V2 gm RC
A v(oc) [f] = = -
V1 1 + gm R E
Figure 12-30

The common-source amplifier behaves in precisely the same fashion. Its low- and high-
frequency open-circuit voltage gains are given by Eqs. 12-36 and 12-37, respectively. The
equivalent circuits are provided in Fig. 12-31.
V2
Av ( oc )  f  = = − g m RD (12-36)
V1
V2 g m RD
Av ( oc )  f  = =− (12-37)
V1 1 + g m RS
The Common-Source Amplifier

V2
A v(oc) [f] = = - gm R D
V1
V DD
High Fre quencie s Q1
rs
+
R1 RD
C2 + RD
Vs + V2
V1 R1 R2
+ +
rs C1 Q1 -
- -
+ V2
+ +
R2 +
Vs RS C3 Q1
V1 rs
- - +
-
Low Freque ncie s + RD
Vs + V2
V1 R1 R2
RS
-
- -
V2 gm RD
A v(oc) [f] = = -
V1 1 + gm R S
Figure 12-31.
The frequency response of the open-circuit voltage gain for the common-emitter amplifier is
given in Fig. 12-32. The frequency response of the open-circuit voltage gain for the common-
source amplifier is identical.

The Common-Emitter Open-Circuit Voltage Gain Frequency Response
20 log { A v(oc) [f] } = 20 log V2
V1
= 20 log gm R C
slope = 20 dB/de cade
gm RC
20 log
1 + gm R E
log f
f z3 f p3
Figure 12-32.
Observe that the gain does not continue to fall off as the frequency is lowered. It reaches a limit
and becomes a constant. Also, notice the pole frequency fp3 is not equal to the zero frequency fz3.
The response is like, but not the same as, the simple RC high-pass filter. To determine the
frequency response completely, we must find the pole and zero frequencies.
Finding Those Poles and Zeros!

For simple circuits that contain a single capacitor, and whose low-end frequency response rolls
off forever, like the simple high-pass RC filter, the pole and zero frequencies are equal. For
circuits with a single capacitor that limits the low-frequency voltage gain to a finite value, the
pole and zero frequencies will not be equal.
The approach for finding the pole frequencies for a common-emitter amplifier is illustrated in
Fig. 12-33. As before, each pole frequency fpn will be determined by the Thevenin equivalent
resistance (RTHn) “seen” by each capacitor (Cn). The Thevenin resistance approach has been
extended to the finding of the pole frequency fp3 produced by the emitter bypass capacitor C3.
Equation 12-38 reminds us how to find the equivalent resistance looking into the emitter.
1 r 1 r
RTH 3 = rIN ( EMITTER)  + B  if B is negligibly small (12-38)
gm  gm 
Recall that rB is the equivalent base-to-ground resistance “seen” by the base terminal of the BJT.
In Fig. 12-33, it is given by Eq. 12-39.
rB = rS || R1 || R2 (12-39)
Figure 12-33 reveals the equations for finding the three pole frequencies are based on Eq. 12-28
[fpn = 1/(2RTHnCn)].

Finding the Pole Frequencies for the Common-Emitter Amplifier
1
f p2 =
2 RTH2C2
VCC
1 C2
f p1 = C1 Rout = RC
2 RTH1C1
+
R1 RC
+ RTH2 = Rout + rL
RTH1 = rS + Rin
rS Q1
+ + rL
Vs R2 RE C3
- Rin = R1||R 2||r RTH3  1/gm
1
f p3 =
2 RTH3 C3
Figure 12-33.
Before we discover how to determine the zero frequency for the emitter circuit, we examine the
construction of the frequency response of Av(oc)[f] for the common-emitter amplifier in Fig. 12-
34. Our purpose is to understand how the frequency response is shaped by the contributing pole,
zero, and low-frequency open-circuit voltage gain Av(oc-LF).

Developing the CE Amplifier's Frequency Response
Low Frequency Gain
gm RC
20 log
1 + gm R E
0 dB log f
+
slope = 20 dB/decade
Ze ro Response
0 dB log f
f z3
+
f p3
0 dB log f
Pole Response
slope = - 20 dB/de cade
20 log { A v(oc) [f]}
= 20 log V2 Composite Re sponse

V1
= 20 log gm R C
slope = 20 dB/decade
gm RC
20 log
1 + gm R E
low-fre que ncy
v oltage gain log f
f z3 f p3
Figure 12-34.
The low-frequency open-circuit voltage gain is regarded to be constant. In Fig. 12-34 we
observe the zero produces a 0 dB (unity) response until the zero frequency (fz3) is reached.

At that point, it produces a response with a slope of 20 dB/decade. The pole indicated in Fig. 12-
34 produces a 0 dB (unity) response until the pole frequency (fp3) is reached. At the pole
frequency, the pole response develops a slope of –20 dB/decade. When the separate response
terms are added together, we obtain the composite response.
At low frequencies, the composite response has a constant low-frequency gain. As the frequency
is raised, the composite response obtains a 20-dB/decade slope because of the zero. When the
pole frequency is reached, the –20-dB/decade slope associated with the pole cancels the 20-
dB/decade slope produced by the zero. Consequently, the composite response flattens (becomes
horizontal). Observe that we have developed the frequency response originally presented in Fig.
12-32.
We now develop a relationship for finding the zero frequency (fz3) by examining the nature of the
composite frequency response produced in Fig. 12-34. Consider Fig. 12-35. The indicated high-
frequency (mid-band) voltage gain of 1000 was selected for convenience. (From our experience,
we know that is too large to be typical of a single-stage, common-emitter BJT amplifier.)
Finding the Zero from the CE Amplifier's Frequency Response

A v(oc)
(1000) 60 dB
1000 Hz fz fp
= 1 Hz =
1000 A v(oc-LF) A v(oc)
100 Hz
(100) 40 dB = 1 Hz
100
A v(oc-LF)
fz 10 Hz
(10) 20 dB = = 1 Hz
A v(oc-LF) 10
(1) 0 dB
1 Hz 10 Hz 100 Hz 1 kHz
fz fp
Frequency
Figure 12-35.

Examination of Fig. 12-35 reveals that the ratio of fz to Av(oc-LF) is a constant. (In this case, it is 1
Hz.) At the pole frequency, the ratio of fp to Av(oc) will be equal to the ratio of fz to Av(oc-LF).
Solving for fz, produces Eq. 12-40.
Av(oc− L F)
fz = fp (12-40)
Av(oc)
This revelation leads us to a simple, but powerful procedure.

◼ Examine the circuit and find the low-frequency voltage gain (Av(oc-LF)). This
accomplished by treating the emitter- (or source-) bypass capacitor as an open circuit.
◼ Examine the circuit and find the high-frequency (mid-band) voltage gain. This is
achieved by treating the capacitor as a short circuit.
◼ Determine the Thevenin equivalent resistance seen by the capacitor, and use Eq. 12-
28 [fpn = 1/(2RTHnCn)] to find the pole frequency.
◼ Employ Eq. 12-40 to find the zero frequency.
◼ If required, sketch the frequency response using the Bode approximations.
The open-circuit voltage gain equation of the common-emitter amplifier as a function of
frequency is given by Eq. 12-41. Another significant difference here is the numerator is 1 + f/fZ
rather than just jf/fz as appears in numerator of the transfer function for a simple RC high-pass
filter.
 f   f 
1 + j  1 + j 
V f z3  g m Rc f z3 
Av ( oc )  f  = 2 = Av ( oc − LF )  =−  (12-41)
V1  f  1 + g m RE  f 
1 + j f  1 + j f 
 p3   p3 
Do we need to use Eq. 12-41? No, fortunately, we only use it to define the open-circuit voltage
gain frequency response. Let us see how to sketch the frequency response.
Sketching the Frequency Response Using the Bode Approximations

Assume that we have analyzed a common-emitter amplifier [Fig. 12-36(a)] and determined its
poles and zeros. At that point, it is then possible to sketch the amplifier's frequency response.
The mid-band band voltage gain is Avs and is expressed in decibels as shown in Fig. 12-36(b).
As the frequency is lowered, we reach the (dominant) pole frequency (fp3) produced by the
emitter bypass capacitor C3, and the response slope becomes 20 dB/decade. As we continue to
lower the frequency, we reach pole (and zero) produced by the output coupling capacitor C2.
The frequency response then assumes a slope of 40 dB/decade. This is depicted in Fig. 12-36(c).

We lower the frequency a little more and we reach the zero frequency (fZ3) produced by the
emitter bypass capacitor. This causes the slope to become 20 dB/decade again as shown in Fig.
12-36(d). When we continue to lower the frequency to reach the pole and zero produced by the
input coupling capacitor C1 the slope becomes 40 dB/decade again. This is illustrated in the
complete response given in Fig. 12-36(e).
Using the Bode Approximations
VCC
Produce s pf 1 = fz1 Produce s fp2 = f z2
R1 RC C2
C1 + Produce s fp3 > fz3
rs Q1
+ and fp3 is the highest
(a) +
R2 RE pole fre que ncy
Vs + rL
C3
-
M id-band A
vs M id-band A
vs
20 dB/de cade 20 dB/de cade
40 dB/de cade
fp2
fp3 fz2 fp3
log frequency scale log frequency scale

(b) (c)
M id-band A
vs M id-band A
vs

40 dB/de cade
fp2 fp1 fp2
fz3 fz2 fp3 fz1 fz3 fz2 fp3
log frequency scale log frequency scale

(d) (e)
Figure 12-36.

Example 12-4. Use the Bode approximations to sketch the low-frequency response of the
common-emitter amplifier given in Fig. 12-37(a). Specifically, determine Rin, Rout, Av(oc), Av, Avs,
Avs(dB), fp1, fz1, fp2, fz2, fp3, Av(LF) and fz3. Use the straight-line Bode approximations to sketch the
amplitude frequency response.
Solution: The DC analysis and the determination of the small-signal parameters have been
performed previously. Consequently, gm and r are provided in Fig. 12-37(a).
Rin = R1|| R2 || r = 8.2 k || 1.5 k || 1.32 k = 646.7 
Rout = RC = 4.3 k
Av(oc) = -g m RC = −(91.2 mS)(4.3 k) = -392.2
rC = RC||rL = 4.3 kΩ || 10 kΩ = 3.007 kΩ
Rin 646.7 
Avs = Av = (−274 .2) = −142 .3
Rin + rS 646.7  + 600 
Avs(dB) = 20 log Avs = 20 log 142.3 = 43.1 dB

Avs(dB)  = 43.1 dB -180
The mid-band voltage gain is 43.1 dB and has been labeled on the amplitude frequency response
as shown in Fig. 12-37(b). Next, we find the pole fp1 and zero fz1 produced by coupling capacitor
C1. (Note this polarized capacitor has its positive terminal tied to the base of transistor Q1. This
is done because signal source is assumed to have DC level of zero volts.)
RTH1 = Rin + rS = 646.7  + 600  = 1246.7 
1 1
f p1 = = = 3.87 Hz  4 Hz
2RTH 1C1 2 (1246 .7 )(33 F)
Figure 12-37.

The zero frequency fz1 is equal to the pole frequency fp1.
fz1 = fp1  4 Hz
The analysis steps for the output coupling capacitor C2 are identical.
RTH2 = Rout + rL = 4.3 k + 10 k = 14.3 k
1 1
f p2 = = = 0.445 Hz  0.4 Hz
2πRTH 2 C 2 2 (14.3 k)(25 F)
fz2 = fp2  0.4 Hz

Now we begin our analysis of the emitter bypass capacitor C3. First, we shall find the pole
frequency it produces.
1 1
RTH 3  = = 10.965 
g m 91.2 mS
1 1
f p3 = = = 44.0 Hz  40 Hz
2RTH 3 C 3 2 (10.965 )(330 F)
We find the low-frequency output-loaded voltage gain Av(LF).
We employ the magnitude of the low-frequency output loaded voltage gain Av(LF) to find the
zero frequency associated with capacitor C3. (The magnitudes of the voltage gains are used.
Even so, the negative signs will cancel if included.)
Because they are much less than one decade apart, the zero fz3 at 1 Hz will effectively cancel
the pole frequency fp2 at 0.4 Hz. This means the ultimate roll-off has a slope of 40 dB/decade.
The pole frequency of 40 Hz produced by the emitter bypass capacitor C3 dominates the low-
end frequency response as illustrated in Fig. 12-37(b).
12-8 Single-Supply Op Amps and Low-Frequency Roll-Off

All the op amp circuits we have investigated thus far have incorporated a dual-polarity power
supply. This permits the op amp to handle both positive and negative signals. However, there
are many applications that require the use of a single-polarity, DC power supply. Notebook
computers, cellular telephones, and portable consumer electronics, such as MP3 and CD
players, are designed to use a single-polarity battery operation. Consequently, op amp
manufacturers have improved single-supply op amp designs to provide output voltage swings
that are only a few millivolts above or below the supply rails. These op amps also draw
minimal standby current (to extend battery life) and operate on extremely low DC voltage
levels (e.g., 3 volts). Some of the models offered by Analog Devices have been illustrated in
Fig. 12-38.
Single-Supply Op Amps, and Low-Frequency Roll-off 429

60
8.5
Figure 12-38.
Figure 12-38(a) emphasizes the attributes of a "single-supply" op amp, while Fig. 12-38(b)
provides examples of some of the products offered by Analog Devices. The typical power
supply voltage options are listed, the current draw per op amp, and the maximum output
current the op amps can deliver to their load. The gain bandwidth product will be significant
when we investigate the high-frequency response limitations. It will be defined later.

When an op amp is biased using a dual-polarity power supply, the op amp can amplify bipolar
input signals. If we were to ground its negative supply terminal, the output of the op amp can
then only go positive. A bipolar signal would be distorted (at best) into a half-wave rectified
waveform. To avoid this distortion, the op amp must be biased up. Specifically, its input and
output must ride on a DC level. These points are depicted in Fig. 12-39.
A Single-Supply Op Amp MUST Be Biased Up

+ supply
+
0 + +
-
0
-
- supply
(a)
+ supply
+
0 + +
-
0
-
(b)
+ + supply
only
+
+ only
0
(c)
Figure 12-39.
Figure 12-40 describes the external circuitry required to make a single-supply op amp operate
properly. The strategy underpinning a single-supply design is straightforward.
1. Op amps are direct coupled internally, which means they amplify DC and
AC signals.
2. A voltage follower offers a gain of one (unity).
3. By biasing the non-inverting input of a DC voltage follower to VCC/2, the
output will also be biased to VCC/2.
4. Coupling capacitors can be used to block the DC levels at the inputs and
outputs.

5. Since capacitor act like shorts to the AC signal and open circuits to DC, it is
possible to give an amplifier a gain of one to DC, and a higher gain to the
AC signal.
The non-inverting single-supply design is developed in Fig. 12-40.
Figure 12-40.
Let us analyze the single-supply, non-inverting amplifier circuit shown in Fig. 12-40(b). The
DC equivalent circuit is shown in Fig. 12-40(a). This is true because the capacitors will act
like open circuits to DC. The mid-band equivalent circuit has been indicated in Fig. 12-41.
The capacitors and the DC power supply have been replaced with short circuits. This places
the bias resistors R1 and R2 in parallel across the amplifier's input. The op amp's power supply
connections go directly to ground. They have been omitted to prevent confusion.

Since the op amp's non-inverting input terminal acts like an open circuit, the amplifier's input
resistance Rin equals the parallel equivalent resistance the bias resistors R1 and R2. The op amp
establishes the circuit's output resistance Rout to be zero ohms. Because the output resistance is
zero ohms, the amplifier's open-circuit voltage gain Av(oc) and its output loaded voltage gain Av
are equal. Now let us consider the low-end frequency response.
The Mid-Band AC Equivalent Circuit

rS Rout = 0 
3
+
600  + R1 || R2 1
LM324 +
+ 50 k
Vs Vin 2 rL
- Vload
10 k
-
- -
R4
51 k
Rin = R1 || R 2 R3
2 k R4
Av(oc) = Av = 1 +
R3
Figure 12-41.
The input and output capacitors will behave as described previously. However, capacitor C3
acts just like the emitter bypass capacitor. Specifically, at low frequencies, capacitor C3 is
essentially an open circuit. This means the low-frequency output loaded voltage gain Av(LF)
is unity (1) because the circuit becomes a voltage follower. This makes the frequency
response analysis straightforward. All we must do is find the pole frequencies. In each case,
we find the Thevenin equivalent resistance "seen" by each capacitor. This is described in
Fig.12-42. Let us proceed to Example 12-5.

Finding the Thevenin Equivalent Resistances
C1
+
22  F C2
RTH1 = Rin + rs 10  F
rS +
3 Rout
+ RTH2
600  1 = Rout + rL
R1 || R 2 LM324
50 k 2 rL
Vs = 0 - 11 10 k
Rin
RTH3
= R3 R4
51 k 
R3
2 k
C3 +
4.7  F
Figure 12-42.
Example 12-5. Analyze the single-supply non-inverting amplifier shown in Fig. 12-43(a)
[repeated from Fig. 12-40(b)]. Specifically, perform a DC analysis followed by a mid-band
AC analysis to determine Rin, Rout, Av, Avs, and Avs(dB). Determine the poles and zeros
produced by capacitors C1, C2, and C3). Use the straight-line Bode approximations to sketch
the amplitude response.
Solution: By inspection of Fig. 12-43(a), it is clear the DC analysis is straightforward. The
voltage division between (equal-valued) resistors R1 and R2 places the non-inverting input
terminal at VCC/2. The op amp's output voltage will also be equal to VCC/2 since the circuit
acts like a DC voltage follower. Because the differential input voltage of an op amp is
approximately zero, the voltage at the op amp's inverting input terminal will also be equal to
VCC/2.
VCC 12 V
V pin 3 = V pin 2 = V pin1 = = =6V
2 2
We use the mid-band equivalent circuit in Fig. 12-41 to conduct the mid-band analysis.
100 k
Rin = R1 || R2 = = 50 k
2
Rout = 0 
R4 51 k
Av(oc) = Av = 1 + =1+ = 26.5
R3 2 k

Rin 50 k
Avs = Av = (26.5) = 26.2
Rin + rS 50 k + 600 
Avs(dB) = 20 log Avs  = 20 log 26.2 0 = 28.4 dB 0
The mid-band voltage gain has a phase angle of 0o associated with it as noted above. Now we
determine the pole frequencies associated with each of the capacitors. We also note the zeros
associated with capacitors C1 and C2 are equal to their respective pole frequencies.
RTH1 = Rin + rS = 50 k + 600  = 50.6 k
1 1
f p1 = = = 0.143 Hz
2πRTH 1C1 2 (50.6 k)(22 F)
fz1 = fp1 = 0.143 Hz  0.14 Hz

1 1
f p2 = = = 1.59 Hz
2πRTH 2 C 2 2 (10 k)(10 F)
fz2 = fp2 = 1.59 Hz  1.6 Hz

Now we pursue the effects of capacitor C3.
RTH3 = R3 = 2 k
1 1
f p3 = = = 16.9 Hz  17 Hz
2RTH 3 C 3 2 (2 k)(4.7 F)
Our next step is to determine the zero associated with capacitor C3.
f p3 Av(oc− LF) (16.9 Hz)(1)
f z3 = = = 0.639 Hz  0.64 Hz
Av(oc) 26.5
Note that since Rout of the op amp is 0 Ω, we can use either the open-circuit low-frequency
gain (Av(oc-LF)) or the output-loaded low-frequency gain (Av(LF)). The pole frequency produced
by the bypass capacitor C3 dominates the low-end frequency response as illustrated in Fig. 12-
43(b). As we observed in the case of the common-emitter amplifier, the ultimate low-end roll-
off is 40 dB/decade. The zero associated with capacitor C3 produces this effect.

Figure 12-43.
The Single-Supply Inverting Amplifier
The single-supply inverting amplifier is illustrated in Fig. 12-44(a). Its DC equivalent circuit
[Fig.12-44(b)] is identical to that of the single-supply non-inverting amplifier. Its mid-band
equivalent circuit is given in Fig. 12-44(c).
The low-end frequency response is controlled by the input and output coupling capacitors, C1
and C2, respectively. Capacitor C3 is a decoupling capacitor. Its role is to keep the AC signal
out of the DC power supply. It does not affect the low-end frequency response. The complete
analysis of Fig. 12-44(a) is illustrated in Example 12-6.

The Single-Supply Inverting Amplifier
R4 VCC
C1 51 k 12 V
2.2  F
rS R3
+ 2 4 C2
- 10  F
600  + 2 k 1 +
LM324 +
+
Vs Vin 3 rL
+ Vload
11 10 k
-
- -
R
1
VCC
100 k 12 V
C3 + R2
4.7  F 100 k
(a) The complete circuit.
R4 VCC R4
51 k 12 V 51 k
rS R3
2 4 2
- -
1 600  + 2 k 1
LM324 LM324
+ +
3 Vs Vin 3
+ + rL
11 Vload
- 10 k
-
-
R
1
VCC
100 k 12 V
R2
100 k
(b) The dc equivalent circuit. (c) The mid-band equivalent circuit.
Figure 12-44.

Example 12-6. Analyze the single-supply inverting amplifier given in Fig. 12-44(a).
Specifically, perform a DC analysis followed by a mid-band AC analysis to determine Rin,
Rout, Av, Avs, and Avs(dB). Determine the poles and zeros produced by capacitors C1 and C2.
Use the straight-line Bode approximations to sketch the amplitude response.
Solution: By inspection of Fig. 12-44(b), it is clear the DC analysis is straightforward.
The voltage division between (equal-valued) resistors R1 and R2 places the non-inverting input
terminal at VCC/2. The op amp's output voltage will also be equal to VCC/2 since the circuit
acts like a DC voltage follower. Because the differential input voltage of an op amp is
approximately zero, the voltage at the op amp's inverting input terminal will also be equal to
VCC/2.
VCC 12 V
V pin 3 = V pin 2 = V pin1 = = =6V
2 2
We use the mid-band equivalent circuit in Fig. 12-44(c) to conduct the mid-band analysis.
Rin = R3 = 2 k
Rout = 0 
R4 51 k
Av ( oc ) = Av = − =− = −25.5
R3 2 k
Rin 2 k
Avs = Av = (−25.5) = −19.6
Rin + rS 2 k + 600 
Avs(dB) = 20 log Avs  = 20 log 19.6 -180 = 25.9 dB -180

The mid-band voltage gain has a phase angle of -180o associated with it as noted above. Now
we determine the pole frequencies associated with each of the coupling capacitors. We recall
that the zeros associated with capacitors C1 and C2 are equal to their respective pole
frequencies.
RTH1 = Rin + rS = 2 k + 600  = 2.6 k
1 1
f p1 = = = 27.8 Hz
2RTH 1C1 2 (2.6 k)(2.2 F)
fz1 = fp1 = 27.8 Hz  28 Hz

1 1
f p2 = = = 1.59 Hz
2RTH 2 C 2 2 (10 k)(10 F)
fz2 = fp2 = 1.59 Hz  1.6 Hz

Capacitor C3 provides power supply decoupling. It has no effect on the amplifier's frequency
response. Its function is to minimize inexplicable operation, and head-scratching
bewilderment in front of the boss. The amplifier's frequency response has been illustrated in
Fig. 12-45.

Figure 12-45.
EDA Will Improve Your Attitude
Even with approximations, determining the frequency response can be tedious. The work we
have done helps us develop a "feel" for how an amplifier should behave. That is extremely
important. We need to understand the problem well enough to have the computer model it
accurately. It is easy to be led astray when a computer simulation provides a solution you
really like. We must always analyze computer results critically. A computer eliminates the
tedium - NOT the need to understand.
We shall use Multisim to generate the frequency response plots for the inverting amplifier
given in Fig. 12-44(a) and analyzed in Example 12-6. The Multisim circuit is given in Fig. 12-
46. The Bode plotter is in the suite of virtual instruments. It will generate the amplitude and
phase response for the circuit between its input (IN) and output (OUT) terminals. The Bode
plotter ignores the signal source connected to the amplifier’s input.

Bode Plotter
Figure 12-46.
The Bode plotter results are shown in Fig. 12-47. The initial (I) frequency is 100 mHz and the
final (F) frequency is 1 MHz. The horizontal axis is scaled logarithmically. The vertical axis
(Magnitude) is also scaled logarithmically from -100 dB to +100 dB. In Fig. 12-47(a) the mid-
band frequency response is determined to be 25.85 dB by using the cursor. It was calculated
to be 25.9 dB in Example 12-6. The cursor was moved to the left to find the low-end
dominant corner frequency in Fig. 12-47(b). It is 3 dB down from the mid-band voltage gain.
This occurs at 28.943 Hz and was calculated to be about 28 Hz in Example 12-6. In Fig. 12-
47(c) the cursor was moved to the left to a frequency one decade below the corner frequency
and the magnitude was 20 dB less. This serves as a “sanity check” to verify the slope is +20
dB/decade from 2.894 Hz to 28.943 Hz.

Midband
(a.)
-3dB Corner
Frequeny
(b.)
-20 dB one decade below

the corner frequency
(c.)
Figure 12-47.
Phase was selected as the Mode in Fig. 12-48. The phase response was not required in
Example 12-6. However, it is easy to obtain using the Bode plotter. Let us see if it makes
sense.

(a.)
(b.)
(c.)
Figure 12-48.
By clicking on Phase. we obtain the corresponding phase response. Figure 12-48(a) confirms
there will be a -180o phase shift in the mid-band frequency range. The phase shift becomes
close to -135o at the dominant corner frequency (-180o + 45o) as shown in Fig. 12-48(b). The
input and output signals are nearly in phase as both high-filter sections contribute their
maximum phase shift as indicated in Fig. 12-48(c). (That would be -180o + 90o + 90o.)

12-9 BJT Device Capacitances and the BJT High-
Frequency Model
The BJT has three fundamental capacitances as depicted in Fig. 12-49. These device
capacitances limit the BJT's high-frequency response. We shall see how this happens as our
work progresses. The capacitance between the base and the emitter (Cbe) is the diffusion
capacitance associated with the forward-biased base-emitter p-n junction. It tends to be the
largest of the three capacitances. The capacitance between the collector and the base (Ccb) is a
junction capacitance associated with the reverse biased collector-base p-n junction. (Diffusion
and junction capacitances are explained in Chapter 3 of Volume 1.) The capacitance between
the collector and the emitter (Cce) is described as a header capacitance. It is often less than a
picofarad. We shall generally disregard it. These small (a few picofarads) capacitances have
always been present. However, at low frequencies their capacitive reactances are so large that
they could be regarded as open circuits.
BJT Device Capacitances

The three BJT device capacitances
limit the BJT's high-frequency response.
C cb
The base-emitter capacitance is a diffusion
capacitance associated with the forw ard-
biased base-emitter p-n junction. (It is the
largest of the three capacitances.)
C ce
C be The collector-base capacitance is a junction
capacitance associated with the reverse-
biased collector-base p-n junction.
The collector-emitter capacitance is a header

capacitance associated with the physical
construction of the BJT. (It is the smallest of
the three capacitances and is often ignored
since it is often less than 1 pF.)
Figure 12-49.
Our next problem is to discover how to use a BJT data sheet to determine Ccb and Cbe. A
partial data sheet for a 2N3904 BJT is provided in Fig. 12-50.
BJT Device Capacitances and the BJT High-Frequency Model 443

Figure 12-50.
Finding the BJT Capacitances

h fe
Emitter 40 dB (100) (100)(3 MHz) = 300 MHz
open
C cb 20 dB (10) (10)(30 MHz) = 300 MHz
(1)(300 MHz) = 300 MHz

C obo = C cb
0 dB (1)
3 MHz 30 MHz 300 MHz
fT
(a) (b)
Figure 12-51.
The output capacitance Cobo, is the output capacitance of the BJT in its common-base
configuration. The capacitance is measured with the emitter terminal open as illustrated in
Fig. 12-51(a). We shall use the approximation given by Eq. 12-42.
Ccb  Cobo (12-42
The input capacitance Cibo is of limited value. It is measured with the base-emitter p-n
junction forward biased by only 0.5 V. The collector terminal is also open. The actual base-
emitter diffusion capacitance will be much larger when the BJT is being used as an amplifier.
Because the diffusion capacitance is difficult to measure directly, it is specified indirectly by
using the current gain-bandwidth product fT. The Bode plot of a BJT's current gain (hfe)
versus frequency is indicated in Fig. 12-51(b). Observe the BJT's current gain rolls off with a
slope of 20 dB/decade. A constant value results when the BJT’s straight-ratio current gain is
multiplied by its corresponding frequency.
The resulting constant is called the current gain-bandwidth product. The subscript "T" is used
to denote that fT is the transition frequency where the gain goes from positive to negative dB
values. (Negative dB values mean the BJT becomes a current attenuator.) The BJT's
collector-base capacitance Ccb and its base-emitter capacitance produce the frequency response
shown in Fig. 12-51(b). Equation 12-43 shows us how to find Cbe using fT and Ccb.
gm
C be = − C cb (12-43)
2πf T
Once we have determined Ccb and Cbe, we incorporate them into the BJT's hybrid-pi model as
shown in Fig. 12-52(a).
Example 12-7. A 2N3904 BJT has an IC of 2 mA and an hfe of 100. Using the data
provided in Fig. 12-50, find Ccb and Cbe. Use these capacitances to create a high-frequency
model for the 2N3904.
Solution: First, we determine gm and r.
IC 2 mA
gm = = = 76.92 mS
26 mV 26 mV
h fe 100
rπ = = = 1.30 k
gm 76.92 mS
From the data sheet in Fig. 12-50, we see that Cobo is 4 pF. We use Eq. 12-42 to find Ccb.
Ccb  Cobo = 4 pF
We extract fT from the data sheet and employ Eq. 12-43 to find Cbe
gm 76.92 mS
C be = − C cb = − 4 pF = 40.81 pF - 4 pF = 36.8 pF
2πf T 2 (300 MHz)
This example shows us the base-emitter diffusion capacitance is much larger than the
collector-base junction capacitance. In general, this will always be true for BJTs that are
operated in their active (amplifying) region of operation. The high-frequency hybrid-pi model
for the 2N3904 has been indicated in Fig. 12-52(b).
BJT Device Capacitances and the BJT High-Frequency Model 445

12-7
Figure 12-52.
12-10 FET Device Capacitances and the FET High-

Frequency Model
The FETs also have three device capacitances as indicated in Fig. 12-53(a). In the case of the
JFET, Cgs and Cdg are junction capacitances associated with the reverse-biased p-n (channel)
junction between the gate and the drain. The capacitance between the drain and source (Cds) is a
header capacitance. Cgs and Cdg for a MOSFET are created by the capacitance between the
metallized gate and the junction. (Recall that a silicon dioxide layer exists between the gate and
the channel. The silicon dioxide layer acts like a dielectric.)
The capacitances associated with the FET are measured under ac short-circuit condition. In Fig.
12-53(b), we see that an AC short circuit placed between the drain and source terminals. Ciss is
the input capacitance for a common-source FET as measured with a short circuit placed between
its drain and source terminals. This places Cgs in parallel with Cdg. Since capacitances in parallel
add, we obtain Eq. 12-44.
Ciss = Cgs + Cdg (12-44)

FET Device Capacitances
C dg
JFET
C ds
C gs The three FET device capacitances
limit the FET's high-frequency response.
The drain-source capacitance is a header
capacitance associated with the physical
construction of the FET. (It is the smallest of
C dg MOSFET the three capacitances and is often ignored
since it is often less than 1 pF.)
The FET capacitances are measured under

ac short-circuit conditions.
C ds
C gs
(a)
C dg C dg
AC short
C ds
C gs AC short
Ciss = Cgs + Cdg Coss= Cds + Cdg
(b) (c)
Figure 12-53.
The measurement of an FET's common-source output capacitance Coss as measured with a short
between its gate and source terminals is illustrated in Fig. 12-53(c). Again, since capacitances in
parallel add, we obtain Eq. 12-45.
Coss = Cds + Cdg (12-45)
Manufacturers also provide a third capacitance called the common-source reverse transfer
capacitance Crss. This capacitance is equal to the drain-to-gate capacitance as defined by Eq. 12-
46.
Crss = Cdg (12-46)
The individual device capacitances can be determined as defined in Fig. 12-54(a). They have
been added to the FET's hybrid-pi model to produce the FET high-frequency model.
FET Device Capacitances and the FET High-Frequency Model 447

Yes, the FET high-frequency model is the same as the BJT high-frequency model. Consider
Example 12-8.
12-8
Figure 12-54.
Example 12-8. A 2N5457 n-channel JFET has an ID of 2 mA. Using the data provided
below, create a high-frequency model for the 2N5457.
IDSS = 5.0 mA gfso = 5000 S Crss = 3.0 pF Ciss = 7.0 pF
Solution: First, we determine gm and r by using the relationships in Fig. 12-54(a).

ID 2 mA
g m = g fso = (5000 S) = 3.16 mS
I DSS 5 mA
r   
From the data provided above, we see that Crss is 3 pF. Cdg is easy to find.

Cdg = Crss = 3 pF
We complete our analysis by determining Cgs.

Cgs = Ciss - Cdg = 7.0 pF - 3.0 pF = 4.0 pF
The high-frequency hybrid-pi model for the 2N5458 has been drawn in Fig. 12-54(b). This
example shows us the capacitances are smaller than those of a similar BJT. This is one of the
reasons FETs typically offer a better high-frequency response than BJTs.
12-11 The Miller Effect

The most intimidating parts of the high-frequency BJT and FET models are the feedback
capacitances Ccb and Cdg, respectively. It is possible to mathematically reflect the effects of the
feedback capacitances by placing equivalent capacitances across the models' input and output
terminals. This is called the Miller Effect79. The only drawback to this technique is that it
results in an approximation. To determine the equivalent Miller input impedance, we refer to
Fig. 12-55. The inverting voltage amplifier has a feedback impedance, called Zf, connected
between its input and output terminals. To simplify the analysis, we ignore Rin temporarily. We
also assume the amplifier's output loaded voltage gain Av is unaffected by Zf. This is the
questionable part that weakens the analysis. However, it produces a simple result with
reasonable accuracy for most practical problems. Our goal is to find the equivalent input
impedance due the feedback impedance Zfi. First, we apply Ohm's law and note the voltage
across Zf is Vin - Vload.
Vin − Vload Vin − AvVin (1 − Av )Vin
I= = =
Zf Zf Zf
To find Zfi we first divide both sides by Vin, and then invert both sides of the resulting equation.
This takes us to Eq. 12-47.
I (1 − Av )
=
Vin Zf
Vin Zf
Z fi = = (12-47)
I ( 1 − Av )
79 This is not to be confused with the compulsion (known as "Miller time") to drink a certain American domestic beer after
completing a particularly challenging assignment.
The Miller Effect 449

Reflecting the Feedback Impedance
to the Input Via Miller's Theorem
+ Vin - Vload -
Z fi Zf
I
+
+
Vin
Vload = A V
rL v in
- -
Vin − Vload Vin − A v Vin (1 − A v )Vin

I= = =
Zf Zf Zf
I (1 − A v )
=
Vin Zf
Vin Zf
Zfi = =
I (1 − A v )
M ille r equiv alent input circuit
+
+
Vin Z fi
Vload
rL
- -
Figure 12-55.
Miller's theorem can be used to reflect Zf across the amplifier's output (Zfo). This is described in
Fig. 12-56. The derivation is like that for Zfi. First, we apply Ohm's law to obtain the current I
that flows through Zf.
Vload  1 
Vload − 1 − 
Vload − Vin Av  Av 
I= = = Vload
Zf Zf Zf
We divide both sides by Vload and manipulate the numerator.

 Av − 1 
 
I  Av   Av − 1 
= = 
Vload Zf  Av Z f 
Vload  Av Z f 
Z fo = =  (12-48)
I  Av − 1
Reflecting the Feedback Impedance

to the Output via Miller's Theorem
- Vin - Vload + Z fo
Zf I
+
+
Vin
Vload = A V
rL v in
- -
Vload −Vload 1
1− Vload
Vload − Vin Av Av
I= = =
Zf Zf Zf
1 Av − 1
1−
I Av Av
= =
Vload Zf Zf
Vload Av
Zfo = = Zf
I Av − 1
M iller e quiv ale nt output circuit
+
+
Vin
Z fo Vload
rL
- -
Figure 12-56.
The Miller Effect 451

We have developed Miller's theorem for a general feedback impedance Zf. Now we apply
Miller's theorem to the specific case of a feedback capacitance (like Ccb or Cdg). First, we shall
go to Eq. 12-47
1
−j
Zf -jX c 2πfC f 1
Z fi = = = =−j
( 1 − Av ) ( 1 − Av ) ( 1 − Av ) 2πf(1 − Av )C f
Examine this result carefully. The equivalent feedback capacitance that appears across the
input will be much larger since it is multiplied by (1 - Av).
Cfi = (1 - Av)Cf (12-49)
Now let us consider Eq. 12-58. For voltage gains with a magnitude of ten or more, we may
approximate Zfo.
Av Z f Av Z f 1
Z fo =  = Z f = −j
Av − 1 Av 2fC f
This result indicates that we may approximate the equivalent capacitance that appears across
the output as Cf when Av has a magnitude of ten or more. The exact relationship and our
approximation are provided in Eq. 12-50. Figure 12-57 provides a summary.
Av − 1
C fo = Cf Cf (12-50)
Av
The Miller Effect Input and Output Capacitances

Cf M ille r equiv alent M ille r equiv alent
input capacitance output capacitance
A −1
Cfi = (1 - Av)Cf Cfo = v Cf  Cf
Av
+
+ +
Vin
Vload
+
rL Vin
Cfi Cfo Vload
rL
- -
-
-
Figure 12-57.

12-12 High-Frequency Roll-Off in BJT and FET Amplifiers
To perform a high-frequency analysis of a BJT or FET amplifier, we invoke Miller's theorem.
Consider the common-emitter BJT amplifier shown in Fig. 12-58(a). Its high-frequency
equivalent circuit has been drawn in Fig. 12-58(b). (The values for Ccb and Cbe were determined
using the procedure given in Example 12-7.) The input and output are plagued by stray
capacitances. These shunt capacitances are produced by the wiring and/or the printed circuit
board traces. Typical values have been indicated. However, their actual values depend on the
physical layout of the circuit. Let us begin the process of simplifying the high-frequency
equivalent circuit and then predicting the amplifier's high-frequency performance.
The Common-Emitter Amplifier

High-Frequency Analysis I C = 2.39 mA
VCC h fe = 120
20 V
g m = 92.0 mS
R1 RC r = 1.30 k
C2
8.2 k  4.3 k Cobo = 4 pF
25 F
f T = 300 M Hz
C1
+
rS 33 F Q1
+ 2N4124 rL
600  +
+ RE 10 k
Vs R2 + V load
1 k C3
1.5 k
330 F -
-
(a)
Input stray wiring capacitance Output stray wiring capacitance

Cw1 Cw2
C cb
10 pF 5 pF
4 pF
R 1 || R 2
rs 1.268 k
+ 600  C be r gmVbe +
1.30 k RC rL V load
Vs
44.8 pF (92.0 mS)Vbe
10 k
4.3 k -
-
(b)
Figure 12-58.
High Frequency Roll-Off in BJT and FET Amplifiers 453

We begin the analysis [of Fig. 12-58(a)] by finding the collector current of the amplifier using
our approximate analysis.
R2 1.5 k
VB = VCC = (20 V) = 3.093 V
R1 + R2 8.2 k + 1.5 k
VE = VB - 0.7 V = 3.093 V -0.7 V = 2.393 V
V E 2.393 V
IC  I E = = = 2.393 mA  2.39 mA
RE 1 k
Knowledge of IC allows us to find gm.

IC 2.393 mA
gm = = = 92.03 mS  92.0 mS
26 mV 26 mV
The data sheet for the 2N4124 indicates that it has a minimum hfe of 120 at a collector current of
2 mA. We shall let  equal 120. Now we can find r.
 120
r = = = 1304   1.30 k
gm 92.03 mS
The data sheet also yields a Cobo of 4 pF and an fT of 300 MHz. Recalling the procedure
illustrated in Example 12-7 produces Ccb and Cbe.
Ccb = Cobo = 4 pF
gm 92.03 mS
C be = − C cb = − 4 pF = 48.82 pF - 4 pF = 44.8 pF
2πf T 2 (300 MHz)
These calculations support the values indicated in Fig. 12-58(a). With reference to Fig. 12-58(b),
we find the mid-band voltage gain Av.
Av = -gmrC = -gm(RC || rL)
= -(92.03 mS)(4.3 k || 10 k) = -(92.03 mS)(3.007 k) = -276.7
We can now find the Miller input capacitance Cfi.
Cfi = (1 - Av)Cf = (1 - Av)Ccb
= [1 - (-276.7)][4 pF] = (277.7)(4 pF) = 1110.9 pF
Because Av is so large, we can approximate the Miller output capacitance. We use Eq. 12-50.

Av − 1
C fo = C f  C f = C cb = 4 pF
Av
The simplified high-frequency equivalent circuit is provided in Fig. 12-59(a). Capacitances in

parallel add. Consequently, we may resolve the capacitances across the input into a single
equivalent input capacitance Cin.
Cin = Cw1 + Cbe + Cfi = 10 pF + 44.8 pF + 1110.9 pF = 1166 pF
In a similar fashion, we find the equivalent output capacitance Cout.
Cout = Cw2 + Cfo = 5 pF + 4 pF = 9 pF
Obviously, the input capacitance is much larger than the output capacitance.
Figure 12-59.
We next find the Thevenin equivalent resistances "seen" by Cin and Cout as defined in Fig. 12-
59(b). To find RTH(in), we replace Vs with a short circuit. This places all three resistances in
parallel.
RTH(in) = rs || (R1 || R2) || r = 600  || 1.268 k || 1.30 k = 310.1 
To find RTH(out), we replace the dependent current source with an open circuit. This leaves us
with RC and rL in parallel.
RTH(out) = RC || rL = 4.3 k || 10 k = 3.004 k
Both the input and output behave like low-pass filters. Consequently, their respective pole and
corner frequencies are equal. We use the Thevenin equivalent resistances to find the input and
output corner frequencies. First, we shall determine the input corner frequency.
1 1
f H (in ) = = = 440 kHz
2RTH (in ) C in 2 (310 .1 )(1166 pF)
High Frequency Roll-Off in BJT and FET Amplifiers 455

Now we find the output corner frequency.
1 1
f H(out) = = = 5.89 MHz
2πRTH(out)C out 2 (3.004 k)(9 pF)
The output corner is much higher than the input corner frequency. Clearly, the input corner
frequency dominates. The high-end frequency response has been illustrated in Fig. 12-60. The
amplifier's mid-band analysis is straightforward.
Rin = R1 || R2 ||r = 1.268 k || 1.30 k = 641.9
Rin 641.9 
Avs = Av = (−276 .7) = −143 .0
rs + Rin 600  + 641.9 
Avs(dB) = 20 log Avs = 20 log 143.0 = 43.1 dB
This result has also been included in Fig. 12-60.
The High-Frequency Bode Plot

M id-band Avs = 43.1 dB
-20 dB/decade
-40 dB/decade
fp(in) fp(out)
fH(in) fH(out)
440 kHz 5.89 M Hz

log frequency scale
Figure 12-60.
Because the FET is represented by the same high-frequency equivalent circuit as the BJT, the
frequency response analysis of a common-source amplifier is virtually identical. However, the
FET device capacitances (particularly Cgs) are small when compared to a similar BJT.

Further, voltage gain provided by a common-source amplifier is typically much smaller than the
voltage gain of a common-emitter amplifier. This means the Miller effect will be much less
severe. Consequently, the FET's small device capacitance and low voltage gain results in a much
smaller input capacitance Cin. The FET's will therefore exhibit a much better high-end frequency
response than the BJT.
12-13 High-Frequency Roll-Off in Frequency-Compensated

Op Amps
We shall see in Chapter 13 of Volume 3 that some amplifiers will tend to exhibit high-frequency
oscillation. Specifically, even without an applied input signal, a signal will appear at their
output. An amplifier that generates its own output signals is said to oscillate. This is not a good
thing. The unwanted signal consumes energy unnecessarily, may produce distortion, and can
generate interference in other nearby electronic systems. To prohibit a high-gain op amp from
going into oscillations, manufacturers will often include a small (e.g., 5-30-pF) capacitor on the
integrated circuit. The addition of this capacitor produces a frequency-compensated op amp.
(The strategy behind this is explored in Chapter 13 of Volume 3.) The aspect that interests us at
this moment is the op amp's frequency response. A typical response is illustrated in Fig. 12-61.
We see that the op amp has a gain-bandwidth product fT that is analogous to the current gain-
bandwidth product of the BJT [Fig. 12-51(b)].
With a little scrutiny of Fig. 12-61, we see the gain-bandwidth product is a constant. At any
frequency beyond the open-loop high-end corner frequency fH(OL), the product of the voltage
gain and the corresponding frequency is equal to the gain-bandwidth product fT. This leads us to
Eq. 12-51.
Av(OL)fH(OL) = AvfH = fT (12-51)
High-Frequency Roll-Off in Frequency-Compensated Op Amps 457

The Frequency-Compensated Op Amp Frequency Response
Ope n-loop gainAV(OL)
-20 dB/decade slope
(100,000) 100 dB (100,000)(10 Hz) = 1 MHz
Ope n-loop (no fee dback)
op amp
+
(10,000) 80 dB (10,000)(100 Hz) = 1 MHz
-
(1,000) 60 dB (1,000)(1,000 Hz) = 1 MHz
(100) 40 dB (100)(10,000 Hz) = 1 MHz
(10) 20 dB (10)(100,000 Hz) = 1 MHz
(1) 0 dB (1)(1,000,000 Hz) = 1 MHz

100 Hz 1 kHz 10 kHz 100 kHz fT
fH(OL) 1 M Hz
10 Hz Frequency Gain-bandwith
Ope n-loop product
High-e nd Corne r
Figure 12-61.
Equation 12-51 tells us we can find the bandwidth of an op-amp amplifier circuit easily. We use
the gain-bandwidth product. Consider Example 12-9.
Example 12-9. The op amp in the non-inverting amplifier circuit given in Fig. 12-62(a) has a
gain-bandwidth product of 1 MHz. Find the amplifier's voltage gain Av and high-end corner
frequency fH. Use the Bode approximations to sketch its (amplitude) frequency response.
Solution: First, we determine Av. (We also find the voltage gain in decibels to produce the
Bode approximation.)
R2 220 k
Av = 1 + =1+ = 23
R1 10 k
Av(dB) = 20 log Av = 20 log 23 = 27.2 dB

We use Eq. 12-51 to find the corner frequency fH.
f T 1 MHz
fH = = = 43.5 kHz
Av 23
The Bode approximation of the amplifier's frequency response is given in Fig. 12-62(b). As
shown, we can superimpose the closed-loop response on the open-loop response.

Figure 12-62.
We conclude our treatment of frequency response with Fig. 12-63. The highest low-end corner
frequency is dominant. In a similar fashion, the lowest high-end corner frequency is also said to
be dominant. The difference between the two frequencies is defined to be the amplifier’s
bandwidth (BW). In the case of the direct-coupled op amp circuit, such as that in Fig. 12-63(a), fH
establishes the bandwidth.
The Bandwidth
20 dB/de cade -20 dB/de cade
M id-band Avs
A vs (dB) - 3 dB
Low-end roll-off High-end roll-off
is produced by is produced by
coupling and device and stray
bypass capacitors. BW = fH _ fL w iring capacitance.
40 dB/de cade -40 dB/de cade
fL fH log fre quency scale
Figure 12-63.
12-14 A MESFET is a GASFET or a GaAs MESFET

At microwave frequencies (those above 1 GHz), metal-semiconductor FETs called MESFETs
are used. These devices are JFETs that are constructed using gallium arsenide (GaAs).
Subsequently, MESFETs are often referred to as GASFETs. Not to be undone in the acronym
battle, some professionals describe the devices as GaAs MESFETs.
The basic structure of the MESFET is given in Fig. 12-64 along with its schematic symbol. The
gate-channel junction forms a Schottky barrier junction. (Schottky, or hot-carrier, diodes are
explained in Chapter 3 of Volume 1.)

As in “regular” JFET circuits, the gate-to-source is reverse biased to place the device in its
depletion mode of operation. The gate signal controls the conduction of the current between the
source and drain. The MESFET offers superior performance over silicon-based devices in radio
frequency (RF) applications. Consequently, most RF circuit designers use MESFETs to the
exclusion of silicon devices in transmitter output stages, and RF input stages. The device package
designs are optimized for good high-frequency performance.
The MESFET/GASFET Structure, Schematic Symbol, and Packages

Gallium arsenide is used to construct a high-speed (microwave) JFET.
Gate (G) Schottky junction
Source (S) metal Drain (D)

D
-
n+ n channel n+
G
p- substrate
Gallium arsenide semiconductor is use d

because of its high carrie r mobility. S
(a) (b)
Drain Drain
3-le ad plastic M acro-T package 4-le ad plastic M acro-X package
Source Source
Source
Gate Gate
(c)
Figure 12-64
The key advantage of the MESFET is the higher mobility of the carriers in the channel as
compared to the silicon-based MOSFET. The higher carrier mobility of the MESFET gives it a
large transconductance at elevated frequencies and its ability to perform well at microwave
frequencies. The disadvantage of the MESFET structure is the presence of the Schottky gate. It
limits the forward bias gate to the turn-on voltage of the Schottky junction. This turn-on voltage is
usually 0.7 V for GaAs Schottky diodes. The means the positive enhancement voltage (VGS) for
the n-channel GaAs MESFET should be less 0.5 V.

Drill Problems
Section 12-1
12-1. An oscilloscope displays ____________ on its vertical axis and _______________ on its
horizontal axis, while a spectrum analyzer displays ____________ on its vertical axis and
_______________ on its horizontal axis.
12-2. A non-sinusoidal waveform contains _______________, which are integer multiples of
its fundamental frequency.
12-3. A non-sinusoidal waveform has a period of 0.1 ms and it contains a second harmonic.
What is the frequency of its second harmonic?
Section 12-2
12-4. The voltage transfer function of a voltage amplifier is called its ___________________.
12-5. An RC low-pass filter tends to _____________ (pass, reject) high frequencies.
12-6. Analyze the low-pass RC filter indicated in Fig. 12-6(c). Find the magnitudes and phase
angles of its voltage transfer function at 723 Hz, 7.23 kHz, and 72.3 kHz. Assume that R
is 100  and the capacitor is 0.22 F. Hint: Use Example 12-1 as a guide.
12-7. Analyze the low-pass RC filter indicated in Fig. 12-6(c). Find the magnitudes and phase
angles of its voltage transfer function at 159 Hz, 1.59 kHz, and 15.9 kHz. Assume that R
is 2 k and the capacitor is 0.05 F. Hint: Use Example 12-1 as a guide.
12-8. At frequencies that approach 0 Hz the voltage transfer function of a low-pass RC filter
approaches ___________ and as the frequency approaches infinity, the voltage transfer
function goes toward ______________.
12-9. The phase angle associated with the voltage transfer function of an RC low-pass filter is
__________ (leading, lagging).
12-10. A low-pass RC filter, such as that shown in Fig. 12-9(a) has an R of 3 k and a C of 0.05
F. Calculate its voltage transfer function in decibels and its corresponding phase angle
in degrees at 106 Hz, 500 Hz, 1.06 kHz, 5 kHz, 10.6 kHz, 106 kHz, 500 kHz, and 1 MHz.
Summarize your calculations in tabular form and graph the magnitude and phase angle on
four-cycle semi-log paper. Use Fig. 12-9(b) and (c) as a guide, respectively.
12-11. A low-pass RC filter, such as that shown in Fig. 12-9(a) has an R of 2 k and a C of 0.05
F. Calculate its voltage transfer function in decibels and its corresponding phase angle
in degrees at 159 Hz, 500 Hz, 1.59 kHz, 5 kHz, 15.9 kHz, 159 kHz, 500 kHz, and 1 MHz.
Summarize your calculations in tabular form and graph the magnitude and phase angle on
four-cycle semi-log paper. Use Fig. 12-9(b) and (c) as a guide, respectively.

Section 12-3
12-12. The phase angles associated with zeros are ______________ (leading, lagging).
12-13. A simple zero is given by j0.1ω. Determine the phase angle associated with it. Find the
zero frequency fz (in Hz) at which its magnitude will be equal to 0 dB.
12-14. A simple zero is given by j2ω. Determine the phase angle associated with it. Find the
zero frequency (in Hz) at which its magnitude will be equal to 0 dB.
12-15. A zero has the form 1 + j0.1ω. Determine the zero frequency fz (in Hz) at which its
magnitude will be 3 dB. Find the corresponding phase angle at fz.
12-16. A zero has the form 1 + j2ω. Determine the zero frequency fz (in Hz) at which its
magnitude will be 3 dB. Find the corresponding phase angle at fz.
12-17. The phase angles associated with poles are ______________ (leading, lagging).
12-18. A pole has the form 1/j0.5ω. Determine the phase angle associated with it. Find the pole
frequency fp (in Hz) at which its magnitude will be equal to 0 dB.
12-19. A pole has the form 1/j4ω. Determine the phase angle associated with it. Find the pole
frequency fp (in Hz) at which its magnitude will be equal to 0 dB.
12-20. A pole has the form 1/(1 + jf/100). What is its magnitude in decibels, and its attendant
phase angle in degrees when the frequency is 100 Hz?
12-21. A pole has the form 1/(1 + jf/330). What is its magnitude in decibels, and its attendant
phase angle in degrees when the frequency is 100 Hz?
12-22. A low-pass RC filter, such as that shown in Fig. 12-14(a) has an R of 3 k and a C of
0.05 F. Calculate its pole frequency fp.
0.05 F. Calculate its pole frequency fp.
Section 12-4
0.05 F. Calculate its high-end corner frequency fH and use the Bode approximations to
sketch its amplitude and phase responses on four-cycle semi-log paper. (This will be the
Bode approximation to the actual response curves developed in Prob. 12-10.)
0.05 F. Calculate its high-end corner frequency fH and use the Bode approximations to
sketch its amplitude and phase responses on four-cycle semi-log paper. (This will be the
Bode approximation to the actual response curves developed in Prob. 12-11.)
12-26. A low-pass RC filter, such as that shown in Fig. 12-14(a) has an R of 4.7 k and a C of
100 pF. Calculate its high-end corner frequency fH and use the Bode approximations to
sketch its amplitude and phase responses on four-cycle semi-log paper.
100 F. Calculate its high-end corner frequency fH and use the Bode approximations to
sketch its amplitude and phase responses on four-cycle semi-log paper.

Section 12-5
12-28. As the frequency approaches zero, the voltage transfer function of an RC high-pass filter
approaches _______________, and as the frequency approaches infinity, the voltage
transfer function of an RC high-pass filter approaches _______________.
12-29. A jωRC term in the numerator of a voltage transfer function is called a
______________ (pole, zero) while a (1 + jωRC) term in the denominator of a voltage
transfer function is called a ______________ (pole, zero).
12-30. Find the pole (fp), zero (fz), and low-end corner frequency (fL) for the RC high-pass filter
shown in Fig. 12-17. Assume that R is 2 k and C is 5 F. Find the magnitudes of the
voltage transfer function as a straight ratio and in decibels at f = 0.1fL, f = fL, and f
= 10fL. Also, find the corresponding phase angles.
12-31. Find the pole (fp), zero (fz), and low-end corner frequency (fL) for the RC high-pass filter
shown in Fig. 12-17. Assume that R is 10 k and C is 22 F. Find the magnitudes of the
voltage transfer function as a straight ratio and in decibels at f = 0.1fL, f = fL, and f
= 10fL. Also, find the corresponding phase angles.
12-32. Use the Bode approximations to sketch the amplitude and phase response of the RC high-
pass filter analyzed in Prob. 12-30.
12-33. Use the Bode approximations to sketch the amplitude and phase response of the RC high-
pass filter analyzed in Prob. 12-31.
12-34. An RC high-pass filter (Fig. 12-17) has an R of 50 k and a C of 47 F. Use the Bode
approximations to sketch its amplitude and phase response.
12-35. The pole of an RC high-pass filter can contribute a maximum phase shift of
____________ (0o, +90o, or -90o) while its zero can contribute a maximum phase shift of
____________ (0o, +90o, or -90o).
Section 12-6
12-36. Coupling capacitors act as RC __________ (low-pass, high-pass) filters.
12-37. Low-pass RC filters offer a phase ____________ (lead, lag), while high-pass RC filters
provide a ____________ (lead, lag).
12-38. Perform an analysis of the common-base amplifier shown in Fig. 12-20(a). Perform a
DC analysis first. Find the approximate IC, VC, VE, and VB. Determine the BJT's
transconductance gm. Calculate the amplifier's Rin, Rout, Av(ov), Av, and Avs. Also, find Avs
in decibels. Determine the Thevenin equivalent resistance (RTH1) "seen" by C1 and find
the pole fp1 and the zero fz1. Determine the Thevenin equivalent resistance (RTH2) "seen"
by C2 and find the pole fp2 and the zero fz2. Complete the problem by using the Bode
approximations to sketch the amplifier’s low-end frequency response.
12-39. Perform an analysis of the non-inverting amplifier shown in Fig. 12-65. Find Rin, Rout, Av,
Avs, and Avs(dB). Also determine RTH1, fL1, RTH2, and fL2. Use the Bode approximations to
sketch the amplifier’s low-frequency amplitude and phase responses. Four-cycle semi-
log paper is suggested with the dominant low-end corner frequency located at the center
of the frequency scale.

Figure 12-65.
Figure 12-66.
12-40. Perform an analysis of the inverting amplifier shown in Fig. 12-66. Find Rin, Rout, Av, Avs,
and Avs(dB). Also determine RTH1, fL1, RTH2, and fL2. Use the Bode approximations to
sketch the amplifier’s low-frequency amplitude and phase responses.
12-41. The ___________ (highest, lowest) low-end corner frequency is said to be dominant.
12-42. If the dominant corner frequency is to be lowered, the coupling capacitor values should
be ____________ (decreased, increased).
Section 12-7
12-43. The emitter bypass capacitor is used to eliminate ___________ (positive, negative)
feedback, but tends to make Av(oc) _____________ (increase, decrease) as the signal
frequency is lowered.
12-44. The pole and zero frequencies associated with the emitter bypass capacitor of a common-
emitter amplifier ___________ (will, will not) be equal.

47
Figure 12-67.
12-45. Perform a DC analysis of the amplifier given in Fig. 12-67. Find VB, VE, IC, and VC using
approximations. Determine the small signal BJT parameters gm and r. Determine the
amplifier AC parameters Rin, Rout, Av(oc), rC, Av, and Avs. Also determine Avs(dB). Find the
low-frequency output loaded voltage gain Av(LF). Find the Thevenin equivalent resistance
(RTH1) "seen" by capacitor C1, and the pole frequency (fp1) produced by capacitor C1.
Find the Thevenin equivalent resistance (RTH2) "seen" by capacitor C2, and the pole
frequency (fp2) produced by capacitor C2. Find the Thevenin equivalent resistance (RTH3)
"seen" by capacitor C3, and the pole frequency (fp3) produced by capacitor C3. Use the
low-frequency output loaded voltage gain to determine the zero frequency fz3. Employ
the Bode approximations to sketch the low-end amplitude frequency response. The poles
and zeros may be rounded to one significant digit since they are to be located on our
graph.
12-46. Suppose VCC in Fig. 12-67 has been increased to 20 V. Perform a DC analysis of the
amplifier. Find VB, VE, IC, and VC using approximations. Determine the small signal
BJT parameters gm and r. Determine the amplifier AC parameters Rin, Rout, Av(oc), rC, Av,
and Avs. Also determine Avs(dB). Find the low-frequency output loaded voltage gain
Av(LF). Find the Thevenin equivalent resistance (RTH1) "seen" by capacitor C1, and the
pole frequency (fp1) produced by capacitor C1. Find the Thevenin equivalent resistance
(RTH2) "seen" by capacitor C2, and the pole frequency (fp2) produced by capacitor C2.
Find the Thevenin equivalent resistance (RTH3) "seen" by capacitor C3, and the pole
frequency (fp3) produced by capacitor C3. Use the low-frequency output loaded voltage
gain to determine the zero frequency fz3. Employ the Bode approximations to sketch the
low-end amplitude frequency response. The poles and zeros may be rounded to one
significant digit since they are to be located on our graph.
Section 12-8
12-47. Explain briefly why single-supply op amps are required.
12-48. Name three key attributes of a single-polarity op amp.

12-49. Explain why the input of a single-supply op amp must be biased up.
Figure 12-68.
12-50. Analyze the single-supply non-inverting amplifier shown in Fig. 12-68. Draw the DC
equivalent circuit and perform a DC analysis. Draw the mid-band equivalent circuit and
determine Rin, Rout, Av, Avs, and Avs(dB). Find the Thevenin equivalent resistance (RTH1)
"seen" by capacitor C1. Compute the pole frequency fp1 associated with capacitor C1.
Repeat the analysis for capacitor C2 by finding RTH2 and fp2, and for capacitor C3 by
finding RTH3 and fp3. Determine zero frequency produced by capacitor C3. Use the Bode
approximations to sketch the mid-band and low-end (amplitude only) frequency
response. Assume Vs produces a 2-kHz, 20-mV peak AC signal. Sketch the waveforms
that would appear at pins 3 and 1 of the op amp as monitored using a direct-coupled
oscilloscope.
12-51. Analyze the single-supply inverting amplifier shown in Fig. 12-69. Draw the DC
equivalent circuit and perform a DC analysis. Draw the mid-band equivalent circuit and
determine Rin, Rout, Av, Avs, and Avs(dB). Find the Thevenin equivalent resistance (RTH1)
"seen" by capacitor C1. Compute the pole frequency fp1 associated with capacitor C1.
Repeat the analysis for capacitor C2 by finding RTH2 and fp2. Use the Bode
approximations to sketch the mid-band and low-end frequency response. Assume Vs
produces a 2-kHz, 150-mV peak AC signal. Sketch the vs waveform and the waveform
that appears at pin 1 of the op amp as monitored using a direct-coupled oscilloscope.

Figure 12-69.
Section 12-9
12-52. The three BJT device capacitances tend to limit its __________ (low-, high-) frequency
response.
12-53. The base-emitter diffusion capacitance is typically ___________ (larger, smaller) than
the collector base junction capacitance.
12-54. The collector-emitter header capacitance is typically the ___________ (largest, smallest)
of the three BJT device capacitances.
12-55. A BJT has an IC of 1.5 mA and an hfe of 200. It also has a Cobo of 5 pF and an fT of 250
MHz. Find gm, r, Ccb, and Cbe. Draw the BJT 's high-frequency model and label it
completely.
12-56. A BJT has an IC of 2.5 mA and an hfe of 300. It also has a Cobo of 8 pF and an fT of 350
MHz. Find gm, r, Ccb, and Cbe. Draw the BJT 's high-frequency model and label it
completely.
Section 12-10
12-57. The three FET device capacitances tend to limit its __________ (low-, high-) frequency
response.
12-58. The drain-source header capacitance is typically the ___________ (largest, smallest) of
the three FET device capacitances.
12-59. An FET has an ID of 10 mA. The FET has an IDSS of 20 mA, a gfso of 12,000 S, a Crss of
4.5 pF, and a Ciss of 8 pF. Find gm, r, Cdg, and Cgs. Draw and label completely the
schematic for the FET's high-frequency model.

12-60. An FET has an ID of 6 mA. The FET has an IDSS of 25 mA, a gfso of 15,000 S, a Crss of
3.5 pF, and a Ciss of 6 pF. Find gm, r, Cdg, and Cgs. Draw and label completely the
schematic for the FET's high-frequency model.
12-61. In general, the FET device capacitances tend to be ___________ (larger, smaller) than
those for a comparable BJT, which makes the FET's high-frequency response
____________ (better, worse) than the BJT's.
Section 12-11
12-62. An inverting voltage amplifier offers a voltage gain (Av) of -200. It has a feedback
capacitance (Cf) of 10 pF. Use Miller's theorem to determine the equivalent capacitance
(Cfi) across the amplifier's input and output (Cfo).
12-63. An inverting voltage amplifier offers a voltage gain (Av) of -150. It has a feedback
capacitance (Cf) of 4 pF. Use Miller's theorem to determine the equivalent capacitance
(Cfi) across the amplifier's input and output (Cfo).
Section 12-12
Note: Problems 12-64 and 12-65 lead you through the detailed analysis of common-emitter
and a common-source amplifier, respectively. It is recommended that both problems be
attempted. This will permit you to contrast the high-frequency performance of the two devices.
12-64. Analyze the common-emitter amplifier shown in Fig. 12-70(a). Perform an approximate
DC analysis to find VB, VE, IC, and VC. Determine the small-signal parameters gm and r.
Find the BJT device capacitances Ccb, and Cbe. Assume the input wiring capacitance Cw1
is 8 pF, and the output wiring capacitance Cw2 is 7 pF. Draw the high-frequency AC
equivalent circuit. Find the mid-band voltage gains Av and Avs. Also find Avs(dB).
Employ Miller's theorem to determine the Miller input and output capacitances Cfi and
Cfo, respectively. Find the amplifier's equivalent input and output capacitances Cin and
Cout, respectively. Draw the simplified high-frequency AC equivalent circuit. Determine
the Thevenin equivalent resistance "seen" by Cin and then find the input corner frequency
fH(in). Find the Thevenin equivalent resistance "seen" by Cout and then find the output
corner frequency fH(out). Use the Bode approximations to sketch the amplifier's high-end
frequency response.
12-65. Analyze the common-source amplifier shown in Fig. 12-70(b). The 2N3797 n-channel
MOSFET has an IDSS of 6 mA and a VGS(OFF) of -7 V. Perform an approximate DC
analysis to find VB, VE, IC, ID, VD, VG, and VC. Determine the small-signal parameters gm
and r. Find the MOSFET device capacitances Cdg, and Cgs. Assume the input wiring
capacitance Cw1 is 8 pF, and the output wiring capacitance Cw2 is 7 pF. Draw the high-
frequency AC equivalent circuit. Find the mid-band voltage gains Av and Avs. Also find
Avs(dB). Employ Miller's theorem to determine the Miller input and output capacitances
Cfi and Cfo, respectively. Find the amplifier's equivalent input and output capacitances Cin
and Cout, respectively. Draw the simplified high-frequency AC equivalent circuit.
Determine the Thevenin equivalent resistance "seen" by Cin and then find the input corner
frequency fH(in). Find the Thevenin equivalent resistance "seen" by Cout and then find the
output corner frequency fH(out). Use the Bode approximations to sketch the amplifier's
high-end frequency response.

Figure 12-70.
12-66. A cascode amplifier is shown in Fig. 12-71. The cascode amplifier is a design scheme to
produce a wide bandwidth amplifier. The first stage (Q1) serves as a common-emitter
amplifier while the second stage (Q2) is configured as a common-base amplifier. The
two BJTs are identical.

12-66
R4
Figure 12-71.
(a.) Draw the DC equivalent circuit and perform an approximate DC analysis.

Find VB1, VE1, IC1, IC2, VB2, and VE2. Notice the two transistors are in series as
far as their DC collector (and emitter) currents are concerned.

(b.) Find gm and r. Since the transistors have identical characteristics and
experience the same collector current, their AC parameters will also be identical.
(c.) Draw the mid-band equivalent circuit which includes the hybrid pi models.
Determine the AC collector-to-ground resistance for each transistor. Find the
mid-band Av1, Av2, Av ,and Av(dB). The key to this circuit’s success is the common-
emitter stage has a voltage gain of only -1. This reduces the Miller capacitance
across the input substantially.
(d.) Assume the input wiring capacitance Cw1 (across Q1's input) is 8 pF, and the
output wiring capacitance Cw2 (across Q2's output) is 7 pF. Draw the high-
frequency equivalent circuit. Use Miller’s theorem to reflect the collector-to base
capacitance across the input of transistor Q1. Simplify it. Find the high-end
corner frequencies associated Q1's input and Q2's output. If you analyzed the
common-emitter amplifier in Fig. 12-70(a), compare your results here with those
of Prob. 12-64.

Section 12-13
12-67. A non-inverting amplifier employs an op amp with a gain-bandwidth product of 2 MHz.
If the amplifier circuit offers a closed-loop voltage gain (Av) of 100, what is the high-end
corner frequency fH? (Assume the input loading is negligibly small such that Av = Avs.
Use the Bode approximations to sketch the amplifier's high-end frequency response.
12-68. A non-inverting amplifier employs an op amp with a gain-bandwidth product of 1.5
MHz. If the amplifier circuit offers a closed-loop voltage gain of 50, what is the high-end
corner frequency fH? Use the Bode approximations to sketch the amplifier's high-end
frequency response.
12-69. An op amp has a gain-bandwidth product of 3 MHz. It is to be used in a non-inverting
audio (20 Hz to 20 kHz) amplifier. What is the maximum closed-loop gain it can provide
if fH is to be 20 kHz?
12-70. An op amp has a gain-bandwidth product of 1.5 MHz. It is to be used in a non-inverting
audio (20 Hz to 20 kHz) amplifier. What is the maximum closed-loop gain it can provide
if fH is to be 20 kHz?
Section 12-14
12-71. A MESFET is a special microwave device constructed from _______________ (silicon,
gallium arsenide, silicon-germanium).
12-72. A GASFET incorporates a ___________________ (silicon, Schottky) gate-channel p-n
junction.
12-73. True or false? The MESFET has a greater transconductance than a regular MOSFET at
elevated frequencies.
12-74. The positive enhancement voltage for an n-channel GaAs MESFET is ______________
(higher than, lower than, like) that for an n-channel silicon E-MOSFET.

Design Problems
12-75. An op amp is to be used in a non-inverting, single-supply amplifier design, such as the
circuit illustrated in Fig. 12-72. The DC supply voltage is 15 V. The input resistance is
to be 200 k. The voltage gain Av should be approximately 46 dB. The signal source
has an rS of 100 , and the load resistance rL is 3 k. The low-end dominant-pole
frequency to be established by capacitor C3 at 40 Hz. Size capacitor C1 to provide a pole
frequency at 0.4 Hz, and capacitor C2 to provide a pole frequency at 4 Hz. Use standard
5%-tolerance resistor values, and standard capacitor values.
15 V
rS C1
100  3
+ + C2
4
+ 1
Vs
R1 LM324 +
C4
- 2
- 11 rL
15 V
+ 3 k
R4
R2 R3
Ibleeder
R5
+ C3
Figure 12-72.
(a.) The voltage-divider bias network has been modified to include power supply
decoupling. The bleeder current through resistors R2 and R3 is to be 100 µA.
Determine the total resistance (R2 + R3). Determine the value of each resistor
if the bias voltage is to be 7.5 V.
(b.) Draw the mid-band equivalent circuit of the bias network assuming the 15-V
DC power supply and capacitor C4 act like short circuits. Size resistor R1 so
the amplifier’s input resistance (Rin) is 200 kΩ.
(c.) The amplifier’s voltage gain Av(dB) is to be about 46 dB. Determine the
corresponding straight-ratio voltage gain Av. Size resistors R4 and R5 to
provide the desired voltage gain.
(d.) Determine RTH3 for capacitor C3. Its pole frequency fp3 is to be dominant and
close to 40 Hz. Find the nearest standard value for C3.
(e.) Find RTH2 for capacitor C2. Size C2 such the it provides a pole frequency at
least one decade below the dominant pole frequency.

(f.) Calculate RTH1 for capacitor C1. Find the required (nearest upper standard
value) of C1 to establish a pole frequency of about 0.4 Hz.
(g.) The decoupling capacitor C4 should provide a pole frequency about one
decade lower than the dominant corner frequency. This capacitor does not
affect the amplifier bandwidth. It is used to prevent the signal and any
additional noise from disturbing the DC power supply. Hint: RTH4 involves
R1,R2, R3, and rS.
12-76. An op amp is to be used in a inverting, single-supply amplifier design, such as the circuit
illustrated in Fig. 12-69. The DC supply voltage is 15 V. The input resistance is to be 20
k. The voltage gain Av should be approximately -200. The signal source has an rs of
100 , and the load resistance rL is 3 k. The low-end dominant-pole frequency to be
established by capacitor C2 at 40 Hz. Size capacitor C1 to provide a pole frequency at 4
Hz. Capacitor C3 will remain a 4.7-F unit. All other component values are unchanged.
Use standard 5%-tolerance resistor values, and standard capacitor values. Draw the
complete schematic diagram.
12-77. The non-inverting amplifier in Fig. 12-43(a) has no output signal. Its DC power supply
has been changed to 28 V. When a DC bias check is made, it is noted that pin 3 is at 14
V, but pin 1 is at 26.5 V. Select the possible failure(s) from the following alternatives
and explain your reasoning: (a) capacitor C1 is open, (b) capacitor C2 is shorted, (c)
capacitor C3 is shorted, or (d) the load rL is shorted to ground.
12-78. The inverting amplifier in Fig. 12-44(a) has an output signal that is distorted severely.
(With a sinusoidal input signal, its output looks like a corrupted half-wave rectified sine
wave.) Select the possible failure(s) from the following alternatives and explain your
reasoning: (a) capacitor C1 is open, (b) capacitor C2 is shorted, (c) capacitor C3 is shorted,
or (d) the load rL is shorted to ground.
12-79. The inverting amplifier in Fig. 12-44(a) has an output signal that is distorted severely.
(With a sinusoidal input signal, its output looks like a corrupted half-wave rectified sine
wave.) Select the possible failure(s) from the following alternatives and explain your
reasoning: (a) capacitor C1 is open, (b) capacitor C2 is shorted, (c) capacitor C3 is open, or
(d) resistor R1 is either open or missing.
EDA Problems
12-80. Using Multisim enter the schematic diagram for the op amp non-inverting amplifier
circuit given in Fig. 12-68(a). Use the virtual oscilloscope to capture the vIN and vLOAD
waveforms. Determine Av. Use the Bode Plotter to determine the mid-band voltage gain
in decibels and the high-end corner frequency fH. Also obtain the phase response. What
is the phase shift at your measured fH?
12-81. Using Multisim enter the schematic for the cascode amplifier provided in Fig. 12- 81.
Use Multisim to perform a DC analysis to obtain the voltages and collector current as
requested in Prob. 12-66. Use the Bode Plotter to find the mid-band voltage gain and
high-end corner frequency fH.

Answers to Selected Odd-Number Problems for Volume Two
Chapter 7
7-1. One, a good DC bias design should provide a stable DC operating point that is independent
of device parameter tolerance and temperature and two, a good DC bias design should provide
the maximum, undistorted output signal swing;
7-3. VCE = 6 V, IC = 0.5 mA, and RC = 12 kΩ; 7-5. Saturation; 7-7. VDS = 3 V, ID =7.5 mA, RD =
400 Ω (390 Ω ± 5%); 7-9. Circuit saturation; 7-11. VEBO = 6 V means the emitter is positive
relative to the base which is a reverse bias (the BJT base-emitter doping levels are like those for
a zener diode); 7-13. The BJT current gain ßDC increases as temperature of the device is raised;
7-15. A BJT’s leakage current increases as the device temperature is raised; 7-17. At low values
of drain current, the drain current exhibits a positive temperature coefficient; 7-19. The reverse
leakage current IGSS of a JFET has a positive temperature coefficient; 7-21. ßDC = 50:
IB = 23.89 µA, IC = 1.19 mA, VCE = 4.02 V, ßDC = 200: IB = 23.89 µA, IC = 4.778 mA,
VCE = 1.08 V; 7-23. DC negative feedback requires the DC voltage or current to be stabilized be
sampled. The circuit arrangement should automatically counter any increase or decrease in the
sampled voltage or current. 7-25. The bias line equation is VGS = -VGG = -0.5 V, ID(max) = 7.76
mA produces a VDS = 1.032 V and ID(min) = 0.5 mA produces a VDS = 14.1 V;
7-27. ßDC = 50: IB = 11.32 µA, IC = 0.566 mA, VCE = 3.755 V and for ßDC = 200: IB = 6.056 µA,
IC = 1.211 mA, VCE = 2.335 V; 7-29. ID = 18.5 mA, VGS = -6.5 V, VDS = 6.5 V
ID (mA)
18.5 mA Q
6.5 V VGS (volts)
7-31. VTH = 1.25 V, RTH = 900 Ω, for ßDC = 50: IB = 20.83 µA, IC = 1.042 mA, VCE = 2.385 V,
VC = 2.917 V, VE = 0.5313 V, VB = 1.231 V and for ßDC = 200: IB = 5.345 µA, IC = 1.069 mA,
VCE = 2.317 V, VC = 2.862 V, VE = 0.5452 V, VB = 1.245 V; 7-33. VB = 1.25 V, VE = 0.55 V,
IC = 1.078 mA, VC = 2.843 V, the approximate values are close to exact analysis results obtained
in Prob. 7-31; 7-35. Negative; 7-37. ID(SAT) = 1.685 mA and VDS(OFF) = 15 V do not depend on the
JFET characteristics, for ID(min) = 0.2 mA: VD = 13.88 V, VS = 0.660 V, VG = 0 V,
VGS = -0.660 V, VDS = 13.22 V, and for ID(max) = 1.35 mA: VD = 7.44 V, VS = 4.455 V, VG = 0 V,
VGS = -4.455 V, VDS = 2.985 V;
476 DISCRETE AND INTEGRATED ELECTRONICS

7-39. Neither an n-channel DE-MOSFET nor a p-channel DE-MOSFET can be biased into their
enhancement mode using a self-bias circuit. The self-bias circuit can only provide depletion-
mode bias; 7-41. ID = 1.2 mA, VD = 12.56 V, VS = 5.64 V, VG = 0 V, VGS = -5.64 V (graph
indicates -5.8 V which is only a 2.8% difference) and VDS = 6.92 V;
1.2 mA
-5.8 V
7-43. These do not depend on the FET characteristics RTH = 66.7 kΩ, VTH = 4 V,
ID(SAT) = 1.46 mA, and VDS(OFF) = 12 V, for IDSS(min) = 2 mA, VGS(min) = -1 V, ID(min) = 0.71 mA,
VGS(min) = -0.40 V, VD = 10.6 V, VS = 4.40 V, VG = 4 V, VDS = 6.18 V, for IDSS(max) = 9 mA,
VGS(max) = -7 V, ID(max) = 1.34 mA, VGS(max) = -4.30 V, VD = 9.32 V, VS = 8.30 V, VG = 4 V
VDS = 1.02 V;
7-45. Either depletion or enhancement mode;

7-47. ID = 1.59 mA, VD = 11.8 V, VS = 8.12 V, VG = 4.30 V, VGS = -3.82 V, VDS = 3.70 V, ID(SAT)
= 2.11 mA, VDS(OFF) = 15 V, the DE-MOSFET is in its depletion mode of operation and ID < IDSS;
7-49. For ßDC = 100: IC = 0.938 mA, VCE = 6.93 V, VC = 6.19 V, VE = -0.7 V, VB = 0 V, for ßDC
= 300: IC = 0.940 mA, VCE = 6.89 V, VC = 6.17 V, VE = -0.7 V, VB = 0 V; 7-51. VB = 0 V,
VE = -0.7 V, IC = 0.942 mA, VC = 6.17 V; 7-53. For IDSS(min) = 2 mA and VGS(min) = -1 V: IE = IC
= IS = ID = 1.43 mA, VG = 0 V, VB = 0 V, VD = 7.71 V, VE = -0.7 V, VGS = -0.154 V,
VC = VS = 0.154 V, and VDS = 7.55 V, for IDSS(max) = 9 mA and VGS(max) = -7 V: IE = IC = IS = ID
= 1.43 mA, VG = 0 V, VB = 0 V, VD = 7.71 V, VE = -0.7 V, VGS = -4.21 V, VC = VS =4.21 V, and
VDS = 3.50 V; 7-55. At 25oC, VB = 0.930 V, at 50oC, VB = 0.882 V, at 75oC, VB = 0.835 V;
7-57. VB = -1.6 V, VE = -0.9 V, IC = 0.692 mA, VC = -6.81 V, VCE = -5.91 V; 7-59. (a) RE = 2 kΩ,
(b) VC = 11 V, (c) VRC = 9 V, (d) RC = 9 kΩ use 9.1 kΩ, (e) VB = 2.7 V, (f) I = 0.5 mA,
(g) R2 = 5400 Ω use 5.6 kΩ, (h) R1 = 36 kΩ; 7-61. VCE = VCE(OFF) = VCC = 15 V, IC = 0, the BJT
is in cutoff because the base-emitter bias is zero; 7-63. VCE = VCE(OFF) = VCC = 15 V, IC = 0, the
BJT is in cutoff because the base-emitter bias is zero; 7-65. VCE = 0 V, VBE = 0.7 V,
IRC = 2.97 mA; 7-67. VB = 2.17 V, VE = 1.47 V, IC = 1.96 mA, IB = 16.3 µA, VC = 15 V;

Chapter 8
8-1. The open-circuit voltage gain Av(oc) is 40 and if the input voltage is doubled, the voltage gain
remains equal to 40; 8-3. An ideal voltage amplifier has an infinite input resistance Rin and an
output resistance Rout of zero ohms; 8-5. As the load decreases, the voltage drop across Rout
increases; 8-7. Av = rL Av(oc)/(rL + Rout) = 175.3; 8-9. To minimize output loading, the output
resistance should be small relative to the load resistance; 8-11. Av = 159.4, Avs = 132.8;
8-13. Av = 56.3, Avs = 9.39; 8-15. To minimize input loading effects, the amplifier input
resistance should be large relative to the source resistance; 8-17. Ai = 28.17; 8-19. Ais = 23.48;
8-21. Av = 120, Ai = 80, Ap = 9600; 8-23. False; 8-25. Ap = 4500, Av(dB) =43.5 dB,
Ai(dB) = 29.5 dB, Ap(dB) = 36.5 dB; 8-27. 20 µV rms = -34.0 dBmV,
950 µV rms = -0.446 dBmV, 1200 µV rms = 1.58 dBmV; 8-29. 0.008 V rms = -41.9 dBV
120 mV rms = -18.4 dBV, 5 V rms = 14.0 dBV; 8.31. Av = 5130, Av(dB) = 74.2 dB;
8-35. Av1 = 30 = 29.5 dB. Av2 = 190 = 45.6 dB, Av3 = 0.9 = -0.915 dB,
Av(dB) = 29.5 dB + 45.6 dB + (-0.914 dB) = 74.2 dB; 8-37. Av = 0.3708, Av(dB) = -8.618 dB;
8-39. Av = 56.23; 8-41. Av = 0.2512; 8-43. 42 dB, Vout = 70.8 V rms; 8-45. Av(dB) = 30 dB,
Vout = 79.4 V rms; 8-47. 57 kΩ; 8-49. Rout = 10.10 Ω; 8-51. Av(dB) = 57 dB, Av = 707.9, not
acceptable as the gain is too large.
Chapter 9
9-1. Superposition theorem; 9-3. Opens, shorts; 9-5. Current, current; 9-7. Voltage, current;
9-9. rπ is the AC equivalent resistance between the base and emitter terminals, rO is the AC
equivalent resistance between the collector and emitter terminals, gm is the AC transconductance
which relates the controlling base-emitter voltage to the controlled collector current;
9-11. yis is the common-source, short-circuit input admittance, yrs is the common-source, short-circuit
reverse transfer admittance, yfs is the common-source, short-circuit forward transfer admittance, and yos is
the common-source, short-circuit output admittance, yrs and yos are often regarded to be negligibly small;
9-13. hfe is approximately equal to , so hfe is 80; 9-15. The second harmonic is 6 kHz, the third
harmonic is 9 kHz, and the fourth harmonic is 12 kHz; 9-17. At IC = 0.25 mA, gm = 9.62 mS, for
IC doubled to 0.5 mA, gm = 19.2 mS; 9-19. ic = gmvbe = 600 µA p-p, and the DC collector current
IC = gmVT = 0.520 mA; 9-21. At ID = 20 mA, gm = 4.47 mS and at ID = 5 mA, gm = 2.24 mS;
9-23. gm = 11.6 mS @ ID = 15 mA, and gm = 21.2 mS @ ID = 50 mA; 9-25. gm = 42.4 mS @ ID =
20 mA and gm = 21.2 mS @ ID = 5 mA; 9-27. rπ = 3.33 kΩ; 9-29. At IC = 4 mA, gm = 153.8 mS
and rπ = 682.5 Ω and at IC = 2 mA, gm = 76.9 mS and rπ = 1.37 kΩ; 9-31. rπ = ∞ Ω;

9-33.
9-35. rO = 40 kΩ @ IC = 5 mA and rO = 20 kΩ @ IC = 10 mA; 9-37. rO = 50 kΩ;

9-39. VA = 266.7 V and rO = 133.3 kΩ @ IC = 2 mA; 9-41. gm = 19.2 mS, rπ = 7.80 kΩ, and
rO = 400 kΩ,
9-43. rO = 10 kΩ @ ID = 15 mA, VA = 150 V, rO = 30 kΩ @ ID = 5 mA;

9-45. rO = 13.33 kΩ @ ID = 30 mA, VA = 400 V, rO = 80 kΩ @ ID = 5 mA; 9-47. The
approximate DC analysis of the common-emitter amplifier shown in Fig. 9-77(b) yields VB =
3.581 V, VE = 2.881 V, IC = 1.601 mA, VC = 13.43 V, VCE = VC – VE = 10.55 V;
9-49. gm = 61.57 mS, rπ = 1.624 kΩ; 6-51. Rin = 879.6 Ω, Av(oc) = -560.3, Rout = 9.1 kΩ;
9-53. Av = -293.3, Avs = -263.4, Ai = -25.80, Ais = -2.63, Ap = 7567; 9-55. Rin = 470 kΩ,
Av(oc) = -6.469, Av = -5.154, Avs = -5.132, Ai = -96.51, Ais = -0.4089, and Ap = 497.4;
9-57. Less than;

9-59. Given the 2N5457 has the maximum parameters: IDSS(max) = 5 mA, VGS(OFF-max) = - 6 V,
gfso = 5000 µS, and VDD = 15 V in Fig. 9-35, we analyze the amplifier circuit.
15 V
To obtain the bias line, the gate circuit is Thevenized, VTH = 3.719 V and RTH = 225.6 kΩ. The
bias line equation is VGS = 3.179 – 6200ID . It is plotted on the JFET transfer characteristic
curve.
The intersection between the transfer curve and the bias line indicates the DC operating point
and by inspection VGS = -3.17 V and ID = 1.11 mA. (More accuracy is achieved by using the
quadratic formula solution alternative presented in Chapter 7.) The two points for plotting the
bias line are also indicated. First, when VGS = 0 V, ID = 0.6 mA and second, when ID is zero,
VGS = VTH = 3.719 V. The rest of the analysis is conducted. VG = 3.72 V, VS = 6.89 V,
VD = 11.3 V, gm= 2.357 mS, rπ = ∞ Ω, Rin = 225.6 kΩ, Rout = 3.3 kΩ, Av(oc) = -7.778,
Av = -5.848, Avs = -5.822, Ai = -131.9, Ais = -0.5822, and Ap = 771.4;
9-61. VB = 2.70 V, VE = 2.00 V, IC = 1.00 mA, VC = 5 V, VCE = 3.00 V; 9-63. gm = 38.46 mS,
rπ = 3.90 kΩ, rO = 200 kΩ; 9-65. rIN(BASE) = 303.9 kΩ, Rin = 1469 Ω (exact) and
1476 Ω (approximate), rIN(COL) = 9.436 MΩ, Rout = 9.989 kΩ (exact) and 10 kΩ (approximate),
Av(oc) = -4.936 (exact) and -5 (approximate); 9-67. Av = -3.291, Avs = -1.333, Ai = -0.2418,
Ais = -0.09793, and Ap = 0.9481; 9-69. Decrease; 9.71. Rin = 225.6 kΩ, Rout = 3.3 kΩ,
Av(oc) = -2.565, Av = -1.929, Avs = -1.920, Ai = -43.086, Ais = -0.1920, and Ap = 82.73;
9-73. Rin = 242.18 kΩ, Rout = 4.7 kΩ, Av(oc) = -6.082, Av = -4.631, Avs = -4.593, Ai = -74.77,
Ais = -0.6124, and Ap = 346.3; 9-75. Approaches infinity; 9-77. Infinite; 9-79. Voltage-controlled
voltage source; 9-81. Surface Mount Technology; 9-83. A DC bias path to ground; 9.85. Do not
have a ground pin; 9-87. ± 3V or 6 Vp-p; 9-89. ± 5V is the common-mode input voltage range
9-91. vLOAD = ± 10V; 9-93. ± 667 µV; 9-95. Rin = 20 kΩ, Rout = 0 Ω, Av(oc) = -13.5, Av = -13.5,
Avs = -13.43, Ai = -36, Ais = -0.1791, and Ap = 486; 9-97. The inverting input terminal of an op
amp in an inverting amplifier circuit is said to be a “virtual ground” because (1) the non-
inverting input is at ground potential and (2) the op amp differential input voltage is assumed to
be zero; 9-99. Rin = 30 kΩ, Rout = 0 Ω, Av(oc) = -10, Av = -10, Avs = -9.677, vLOAD = 0.5 V peak,
@ vIN = 50 mV peak, vLOAD = 0.4839 V peak @ vS = 50 mV peak; 9-101. Op amps are direct
coupled which means they can operate on DC levels. The inverting amplifier has a gain of -10.
If vIN = -0.2 VDC means vLOAD = 2 VDC and if vIN = +0.3 VDC means vLOAD = -3 VDC;
9-103. Av = -20
Input Output
0.5 V 10 V
0.3 V 6V
0.1 V 2V
0V
~~ t 0V
~~ t
Input Output
2.15 V 0V t
2.00 V
~~
1.85 V Saturated
-13 V
0V
~~ t
9-105. Common-source FET amplifier; 9-107. Op amp inverting amplifier design with
Rin = 100 kΩ and Av = -2 requires R1 = 100 kΩ and R2 = 200 kΩ; 9-109. Capacitor C3 is shorted
which makes the voltage across RE zero, and the BJT will be saturated so no signal will appear
across the load; 9-111. Alternative (e) should be selected – either non-inverting input is open or
the positive power supply connection is missing.

Chapter 10
10-1. Opens, shorts; 10-3. Base, emitter; 10-5. VB = 8 V, VE = 7.3 V, IC = 1.698 mA,
VC = VCC = 16 V, VCE = VC – VE = 8.70 V; 10-7. gm = 65.31 mS, rπ = 2.603 kΩ;
10-9. rE = 2.312 kΩ, rIN(BASE) = 395.6 kΩ, Rin = 4.058 kΩ, rB = 190.7 Ω, rIN(EMITTER) = 16.43 Ω,
Rout = 16.37 Ω (approximately 1/gm = 15.31 Ω), Av(oc) = 0.9965; 10-11. Av = 0.9932,
Avs = 0.7969, Ai = 0.8061, Ais = 0.1594, Ap = 0.8006; 10-13. ID = 1.192 mA, VD = 15 V, VG = 0 V,
VS = -VGS = 2.547 V, Rin = RG = 680 kΩ, gm = 2002 µS, Rout = 499.6 Ω, Av(oc) = 1 (The load is an
open circuit so there is no voltage drop across Rout.); 10-15. Av = 0.9600, Avs = 0.9558,
Ai = 54.40, Ais = 0.2390, Ap = 52.22; 10-17. The source follower is a better choice compared to
the emitter follower to be used as an input buffer of a cascaded system; 10-19. Rin = ∞ Ω,
Rout = 0 Ω, Av(oc) = Av = Avs = 1; 10-21. The primary disadvantage of a common-base amplifier is
its low input resistance. The low Rin produces a significant load on the signal source;
10-23. VB = 0 V, VE = -0.7 V, IC = 1.963 mA, VC = 3.056 V; 10-25. gm = 75.5 mS,
rπ = 3.311 kΩ; 10-27. rIN(EMITTER) = 13.25 Ω, Rin = 13.18 Ω, Rout = 1.5 kΩ, Av(oc) = 113.3;
10.29. Av = 95.78, Avs = 19.98, Ai = 0.1539, Ais = 0.1218, Ap = 14.74; 10-31. Av(dB) = 39.6 dB,
Avs(dB) = 26.0 dB, Ai(dB) = -16.3 dB, Ais(dB) = -18.3 dB, Ap(dB) = 11.7 dB;
10-33. ID = 1.10 mA, gm = 1923 µS, rIN(SOURCE) = 520 Ω, Rin = 520 Ω, Av(oc) = 13.08,
Rout = 6.8 kΩ, Av = 8.346, Avs = 1.233, Ai = 0.3617, Ais = 0.3082, Ap = 3.019;
10-35. Common source; 10-37. Common gate; 10-39. Rin = ∞ Ω, Rout = 0 Ω, Av(oc) = Av = Avs = 3;
10-41.
Input Output
0.06 V 0.66 V
0.05 V 0.55 V
0.04 V 0.44 V
0V
~~ t 0V
~~ t
Input Output
Saturated
2.00 V 13 V
11 V
1.00 V
0V t 0V t
10-43. RB = 200 kΩ, R1 = 10 kΩ, R2 = 499 kΩ; 10-45. Resistor R1 is open (c); 10-47. Capacitor
C1 is shorted (b).

Chapter 11
11-1. IC = 0.8431 mA, gm = 32.43 mS, rC = 2.379 kΩ, Av = -77.14; 11-3. IC = 0.7679 mA,
gm = 29.53 mS, rC = 1.919 kΩ, Av = 56.66; 11-5. ID = 4.767 mA, gm = 1.074 mS, rS1 = 20 kΩ,
Av = 0.9555; 11-7. A differential amplifier provides an output voltage that is proportional to the
difference between its two input signals and all op amps sport a differential input; 11-9. The AC
sources act like short circuits to the DC bias. IT = 1.13 mA, IE = 0.565 mA, VC = 6.35 V,
VOUT = 0 V, VB = 0 V, VE = -0.7 V; 11-11. IC = 0.565 mA and ß = 180, gm = 21.73 mS,
rπ = 8.283 kΩ, Avd(oc) = 217.3, Rout = 20 kΩ, Rin(+) = Rin(-) = 16.567 kΩ; 11-13. Avcm(oc) = 0 if the
left and right sides are matched perfectly, if the collector resistors are unequal, the gains
associated with each transistor will not be equal and the common-mode voltage gain will not be
zero; 11-15. IT = 0.9417 mA, IC ≅ IE = 0.4708 mA, VC1 = VC2 = 6.35 V; 11-17. IC = 0.4708 mA
and ß = 110, gm = 18.11 mS, rπ = 6.075 kΩ, Avd(oc) = 108.6, Rout = 10 kΩ, Rin(+) = Rin(-) = 16.567
kΩ, Avcm(oc) = -0.5, CMRR = 217.2, CMRR(dB) = 46.74 dB; 11-19. VD = 30 mV, VCM = 7.035 V;
11-21. VRE = 4.4 V, IC3 ≅ IE3 = 2.2 mA, IT = 2.2 mA, IC1 = IC2 = 1.1 mA, VC1 = 6.39 V,
VC2 = 12 V, VB1 = VB2 = 0 V, VC3 = -0.7 V, VB3 = -6.9 V, VE3 = -7.6 V, VR1 = 18.9 V,
IR1 = 20.77 mA; 11-23. rE = 6.152 MΩ, Avcm(oc) = -4.145 X 10-4, Avd(oc) = 107.89,
CMRR = 260.29 X 103, CMRR(dB) = 108.3 dB; 11-25. Avd = Avd(oc) = 3.733, Rout = 0 Ω,
Rin(-) = 150 kΩ, Rin(+) = 710 kΩ; 11-27. Av = -7500, Av(dB) = 77.5 dB; 11-29. Av(dB) = 64.7 dB,
Av = 1718; 11-31. Capacitors C6 and C7 are bypass capacitors that are used to insure the DC
power supplies act like short circuits to the AC signals, which minimizes the possibility of
interaction between amplifier stages; 11-33. Q1/Q4: ID1 = IS1 = IC4 ≅ IE4 = 0.620 mA,
VD1 = 10 V, VG1 = VB4 = 0 V, VGS(min) = -0.1063 V, VGS(max) = -3.887 V, VS1 = VC4 ranges from
0.1063 V to 3.887 V, Q2: IC2 ≅ IE2 = 0.6925 mA, VB2 = 0 V, VE2 = -0.7 V, VA = -0.9978 V,
Q3: IC3 ≅ IE3 = 1.24 mA, VB3 = 0 V, VE3 = - 0.7 V, VC3 = 10 V; 11-35. Q1: Rin = 150 kΩ,
rIN(BASE)2 =34.4 kΩ, rS1 = 4.442 kΩ, gm1(min) = 787.4 µS, Av1 = 0.7777, Q2: rE3 = 3.206 kΩ,
rIN(BASE)3 = 256.5 kΩ, rC2 = 4.216 kΩ, gm2 = 26.63 mS, Av2 = -9.017, Q3: rB3 = 4.286 kΩ,
gm3 = 47.69 mS, Rout = 74.54 Ω, Av(oc)3 = 0.9972, Av3 = 0.9935, system: Av(oc) = -6.993,
Av = -6.967; 11-37. Av = -6.901, Avs = -6.897, Ai = -184.9, Ais = -0.1232, Ap = 1276;
11-39. Rin = 470 kΩ, Rout = 0 Ω, Av1 = 1, Av2 = -23.5, Av(oc)3 = 1, Av3 = 1, Av(oc) = Av = -23.5, the
maximum undistorted output voltage is 26 Vp-p and the maximum input voltage is 1.106 Vp-p;
11-41. The instrumentation amplifier given in Fig. 11-45 has matched inverting and non-
inverting input resistances and can have its voltage gain changed using a single resistor (RG)
without degrading the CMRR when compared to the op amp differential amplifier in Fig. 11-
35(a). The op amp differential amplifier in Fig. 11-35(b) has matched inverting and non-
inverting input resistances, but requires two resistors to be changed to change Avd, which could
degrade the CMRR unless the resistors are matched precisely; 11-43. Avd = 50.4; 11-45. Twisting
two signal conductors together tends to make magnetic and electric field coupling uniform. The
induced normal-mode voltage should be zero and the common-mode voltage will be the same for
both signal leads; 11-47. Electric field; 11-49. iC2 = 8 µA, iDIF = 4 µA; 11-51. The capacitor Cc
serves as the feedback element in the inverting current-to-voltage converter and provides
frequency compensation additionally to avoid oscillation;

11-55. Alternative c. The voltage gain is too large; 11-57. Alternative d. Clipping is produced
by current limiting because rL is too small.
Chapter 12
12-1. An oscilloscope display amplitude versus time while a spectrum analyzer displays
amplitude versus frequency; 12-3. 20 kHz; 12-5. A low-pass filter rejects high frequencies;
12-7. At f = 159 Hz, -jXc = -j 20.02 kΩ, Av = 0.9950 ∠ -5.07o, at f = 1.59 kHz, -jXc = -j 2.002 kΩ,
Av = 0.7071 ∠ -45o at f = 15.9 kHz, -jXc = -j 200.2 Ω, Av = 0.9960 ∠ -85.28o ; 12-9 Lagging;
12-11.
Frequency Av(dB) Angle (degrees)
159 Hz -0.0432 -5.71
500 Hz -0.1410 -17.5
1.59 kHz -3.01 -45.0
5.00 kHz -10.4 -72.4
15.9 kHz -20.0 -84.3
159 kHz -40.0 -89.4
500 kHz -50.0 -89.8
1 MHz -56.0 -89.9
12-13. fZ = 1.592 Hz and a constant +90o phase angle; 12-15. fZ = 1.592 Hz and a +45o phase
angle at fZ; 12-17. Lagging; 12-19. fp = 0.0398 Hz and a constant -90o phase angle; 12-21. At f
100 Hz with a pole frequency (fp) of 330 Hz, the magnitude will be -0.3815 dB and a phase angle
of -16.86o; 12-23. fp = 1.061 kHz; 12-25. fH = fp = 1.592 kHz;
40
20
-20
A V(oc)
(dB)
-40
-60
-80
15.9 159 1.59k 15.9k 159k

fH
Frequency (Hz)
-45
Angle
(Degrees)
-90
15.9 159 1.59k 15.9k 159k

fH
Frequency (Hz)

12-27. fH = fp = 0.0339 Hz = 33.9 mHz;
40
20
-20
A V(oc)
(dB)
-40
-60
-80
0.339 3.39 33.9 339 3390

fH
Frequency (mHz)
-45
Angle
(Degrees)
-90
0.339 3.39 33.9 339 3390

fH
Frequency (mHz)
12-29. Zero, pole; 12-31. fz = fp = fL = 0.7234 Hz, at f = 0.1fL, Av(oc) = 0.995,

Av(oc)(dB) = -20.0 dB, ∠ 84.3o , at f = fL, Av(oc) = 0.707, Av(oc)(dB) = -3.01 dB, ∠ 45o
at f = 10fL, Av(oc) = 0.995, Av(oc)(dB) = -0.0432 dB, ∠ 5.71o; 12-33.
40
20
-20
A V(oc)
(dB)
-40
-60
-80
7.23 72.3 723 7230 72300

fL
Frequency (mHz)
90
45
Angle
(Degrees)
0
7.23 72.3 723 7230 72300

fL
Frequency (mHz)

12-35. Maximum phase shift for a pole is -90o and +90o for a zero; 12-37. Low-pass RC filters
offer a phase lag, while high-pass RC filters provide a phase lead; 12-39. Rin = R3 = 20 kΩ,
Rout = 0 Ω, Av = 24.5, Avs = 24.3, Avs(dB) = 27.7 dB, RTH1 = 20.2 kΩ, fL1 = 20.2 Hz,
RTH2 = 20.2 kΩ, fL2 = 1.06 Hz;
12-41. Highest; 12-43. Negative, decrease; 12-45. VB = 2.171 V, VE = 1.471 V, IC = 1.961 mA,
VC = 7.352 V, gm = 75.44 mS, rπ = 1.591 kΩ, Rin = 862.0 Ω, Rout = 3.9 kΩ, Av(oc) = -294.2,
rC = 2.806 kΩ, Av = -211.7, Avs = -189.7, Avs(dB) = 45.6 dB, Av(LF) = 3.677, RTH1 = 962.0 Ω,
fp1 = 4 Hz, RTH2 = 13.9 kΩ, fp2 = 0.2 Hz, RTH3 = 13.26 Ω, fp3 = 40 Hz, fz3 = 0.7 Hz;

12-47. Single-supply op amps are typically found in portable, battery-operated equipment;
12-49. A single-supply op amp’s input must be biased up so the op amp can operate on bipolar
signals; 12-51. Vpin3 = Vpin2 = Vpin1 = 7.5V, Rin = 20 kΩ, Rout = 0 Ω, Av = -10, Avs = -9.95,
Avs(dB) = 20 dB, RTH1 = 20.1 kΩ, fp1 = 3.6 Hz, RTH2 = 20 kΩ, fp2 = 0.36 Hz;
12-53. Larger; 12-55. gm = 57.7 mS, rπ = 3.467 kΩ, Ccb = 5 pF, Cbe = 31.7 pF;

5
3.47 57.7
31.7
12-57. High-frequency; 12-59. gm = 8.485 mS, rπ = ∞ Ω, Cdg = 4.5 pF, Cgs = 3.5 pF;
4.5
3.5 (8.485 mS)
12-61. Smaller, better; 12-63. Cfi = 604 pF, Cfo = 4.03 pF; 12-65. VB = 0 V, VE = -0.7 V,
IC = ID = 2.103 mA, VD = 6.799 V, VG = 0 V, VC = 2.856 V, gm = 1.776 mS, rπ = ∞ Ω,
Cdg =0.8 pF, Cgs = 7.2 pF, rD = 2.806 k Ω, Av = -4.983, Avs = - 4.980, Avs(dB) = 13.9 dB,
Cfi = 4.784 pF, Cfo = 0.8 pF, Cin = 19.984 pF, Cout = 7.8 pF, RTH(in) = 599.6 Ω,
RTH(out) = 2.806 k Ω, fH(in) = 13.281 MHz, fH(out) = 7.272 MHz;
Cdg
rS 0.8 pF
(1.776 mS)Vgs
+ 600 Ω
gmVgs
Vs _ Cw1 RG Cgs RD Cw2 rL
8 pF 1 MΩ 7.2 pFs 3.9 kΩ 7 pF 10 kΩ

40
20 13.5 dB
0 -20 dB/decade
-20 -40 dB/decade

A Vs
(dB)
-40
-60
-80
70k 700k 7M fH(in) 70M

fH(out)
Frequency (Hz)
12-67. fH = 20 kHz;
12-69. Av = 150; 12-71. Gallium arsenide; 12-73. True; 12-75.

15 V
rS C1
100 W
2.0 µF
+ 3
+ 4 C2
15.0 µF
+ 1
Vs
R1 LM324 +
200 kΩ C4
- 1.5 µF 2
- 11 rL
15 V
+ 3 kW
R4
R2 R3 200 kΩ
75 kΩ 75 kΩ
R5
1 kΩ
+ C3
4.0 µF
12-77. Answer (c), capacitor is shorted which gives the amplifier a DC gain of 26.5 to the 14 V
bias at the op amp’s non-inverting input terminal. The op amp is saturated; 12-79. Answer (d), if
R1 is open, there will be no DC bias so the amplifier cannot operate on negative-going signals.

Index to Volume Two Cascaded amplifier, 120, 235, 325 - 327
Cascode amplifier, 251, 469 – 472y
A______________________ Clipping, 3 - 4
Active device, 98 CMRR, common-mode rejection ratio, 309 -
311
Ai, current gain, 105-106
Collector-voltage feedback bias, 20 – 23
Ais, current gain from signal source to
loaded output, 106-107 Collector-voltage feedback bias, summary,
23
Ap, power gain, 108-109
Common base, 286
Attenuator, voltage, 122 - 123
Common-base amplifier summary, 257
Av, output-loaded voltage gain, 102 - 103
Common emitter, 286
Av(oc), open-circuit, or unloaded voltage
gain, 101 - 102 Common emitter, no emitter bypass
capacitor, 287
Av, output-loaded voltage gain, 102 - 103
Common-emitter amplifier poles and zeros,
B______________________ 422-426
ß, AC current gain, BJT, 141 Common gate, 286
Common source, 286
Bias current compensation, 336
Common source, no source bypass
Bias line (equation), FET, 14 - 19 capacitor, 287
Biasing, PNP BJTs, 64 – 65 Common-mode voltage, 304, 311
BiFET op amp, 336 Common-mode voltage gain, 304 - 308
BJT fixed base bias, 12 – 13 Comparison, common-base/common-gate,

263
Bode approximations, 401 – 403 Comparison, emitter/source follower, 247,
Bode approximations, common-emitter 289
amplifier, 426 - 427 Constant-current source bias, FET, 55 – 60
Bode approximation, pole, 403 Controlled source, 99
Bode approximation, zero, 404 - 405 Current mirror, 358 – 359

Current-to-voltage converter, inverting, op
Buffer, 235 amp, 359 - 360
Bypass capacitor, 234
D______________________
C______________________ Decoupling capacitor, 234, 329
Capacitances, BJT device, 443 – 445 dBm, relative dB scale referenced to 1 mW
Capacitances, FET device, 446 – 448 in 600 ohms, also called the Volume Unit
(VU) scale and designated dBu, 118 – 119

dBV, relative dB scale referenced to 1 Emitter follower, open-circuit voltage gain,
Vrms, 118 241 – 242
dBmV, relative dB scale referenced to 1 mV Emitter follower summary, 246
rms, 117
F______________________
Decade, 385
FET common-gate amplifier, 263 - 264
Decibels (dB), 112 - 115
FET source follower, 246
Dependent source, 99
Filter, low-pass, RC, 380 - 382
Differential amplifier, 283, 293 – 294
Frequency domain, 377 - 378
Differential amplifier, BJT, 295 – 303
Differential amplifier, op amp, 320 – 325 G______________________
Differential input, op amp, 357 gfso, transconductance, real component of
yfs, FET, 148 - 149
Dominant-pole frequency compensation,
360 gm, transconductance, transfer conductance,
mutual conductance, BJT, 144 – 147
Drain-voltage feedback bias, MOSFET, 27 -
31 gm, transconductance, transfer conductance,
mutual conductance, FET, 148 - 149
E______________________
gm, E-MOSFET transconductance, 149 -150
EDA bias circuit analysis, 65 – 69
Guard, active drive, 351 - 354
EDA Bode plotter, 439 - 442
H______________________
EDA common-mode rejection, 314 – 316
h-parameter, small-signal BJT model, 135-
EDA common-mode rejection with
138
spectrum analyzer, 316 – 320
hfe, common-emitter, short-circuit (forward)
EDA instrumentation amplifier, 345 - 347
current gain, 137-138, 141
EDA non-inverting amplifier, 271 - 274
hie, common-emitter, short-circuit input
Early Effect, 153 impedance, 136-138
Early voltage, VA, 153 - 154 High-pass filter, RC, 405 – 408
Emitter bias, BJT, 50 – 55 High-frequency roll-off, BJT amplifier, 453

– 457
Emitter bias, BJT, approximations, 54-55
High-frequency roll-off, frequency
Emitter bypass capacitor frequency effects, compensated op amp, 457 - 459
419 -420
hoe, common-emitter, open-circuit output
Emitter follower, 234 admittance, 137-138
Volume Two Index 493

hre, common-emitter, open-circuit reverse Op amp block diagram, 355
voltage gain, 137-138
Op amp voltage follower, 250 – 251
Hybrid-pi model, BJT, 139, 158
Op amp non-inverting amplifier, 265 - 268
I______________________ Open-circuit voltage gain, 100
IGSS, gate-to-source leakage current, 11 – 12 Output-loaded voltage gain, 102
Input loading effects, voltage amplifier, 103 Overdrive, 3-4
Instrumentation amplifier, 339
P______________________
IT, tail current, 295
Passive device, 98
J - K___________________ Phasor algebra, 382
Kirk Effect, 7 Poles, 393 - 399
L______________________ Push-pull output buffer, 361 - 362
Large-signal distortion, 143 - 144 Q______________________

Linear, amplifier, 98 Quadratic formula, 70 - 78
Linear voltage amplifier, 376
R______________________
Low-pass filter, AC circuit analysis, 382 –
rC, AC collector-to-ground resistance, 284 –
385
285
Low-pass filter, pole – zero analysis, 400 -
RC-coupled amplifiers, frequency response,
401
410 – 415, 417
M______________________ rD, AC drain-to-ground resistance, 286
MESFET, 459 rIN(BASE), 235 - 236
Midpoint Bias, 2 – 4 rIN(EMITTER), 237 - 240
Miller effect, 449 - 452 rIN(SOURCE), 246 - 247
N______________________ rO, output resistance, BJT and FET, 153 -

158
Noise reduction, 348
rπ, input resistance, BJT, 151 – 153
Normalized frequency, 389 - 390
rπ, input resistance, FET, 153
O______________________
Op amp bias resistor, 270 -271

S______________________ Twisted shielded pair, 350
Self-bias, JFET and DE-MOSFET, 39 - 43 U______________________

Semi-log plots, 385 – 386 Unloaded voltage gain, 101
Single-ended output, 305 – 306 V______________________
Single-supply op amp, 429 – 431
Voltage-divider bias, BJT, 31 – 38
Single-supply op amp, inverting amplifier,
Voltage-divider bias, BJT, summary, 34
436 - 439
divider bias, BJT, summary, approximate
Single-supply op amp, non-inverting
analysis, 37
amplifier, 431 - 436
Voltage-divider bias, FET, 43 - 50
Small-signal response, 142 - 143
SMT (Surface Mount Technology), 6 W______________________
SOIC (Small Outline Integrated Circuit), 6
SOT (Small Outline Transistor), 6
Source bypass capacitor frequency effects,
421
X - Y___________________
Straight-ratio voltage gain, 123
y-parameter model, FET, 139 – 141
Stray capacitances, 453
yfs, common-source, short-circuit forward
Superposition theorem, 134-135
transfer admittance, 140 - 141
T______________________ yis, common-source, short-circuit input
admittance, 140- 141
Temperature Compensation, BJT, 61 – 63,
65 – 69 yoe, common-source, short-circuit output
admittance, 140- 141
Thevenin’s Theorem, 32 – 33, 43 - 49
yrs, common-source, short-circuit reverse
Thevenin’s Theorem to find pole
transfer admittance, 140- 141
frequencies, 413
Time domain, 377 - 378 Z______________________
Transfer curves, FET, 7 – 9 Zero temperature coefficient, FET, 10 – 11
Transfer Curves, FET temperature effects, 9 Zeros, 388 - 393
– 11
Transfer function, voltage, 380, 383
Twisted pair, 349 – 350
Volume Two Index 495

Discrete and Integrated Electronics Volume Two Analysis and Design For Engineers and Engineering Technologists. 2 (2020)

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Discrete and Integrated Electronics Volume Two Analysis and Design For Engineers and Engineering Technologists. 2 (2020)

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Discrete and Integrated

Analysis and Design

Cover Photograph: Umberto on Unsplash

Copyright © 2020 by Stephen R. Fleeman

8 Voltage Amplifier Models 98

9 Inverting Voltage Amplifiers 133

10 Non-Inverting Voltage Amplifiers 233

11 Differential and Cascaded Amplifiers 283

12 Frequency Response 376

Answers to Selected Odd-Numbered Problems 475

1 Solid-State Physics and the P-N Junction 1

1-0 Study Objectives 2

2 Diodes and Circuit Analysis 51

2-0 Study Objectives 51

3-0 Study Objectives 104

4 DC Power Supplies: Rectification and Filtering 170

6 Field-Effect Transistors 332

Answers to Selected Odd-Numbered Problems 392

Who Should Read this  Illustrations to help you grasp every

7-1 Midpoint Bias

2 BJT AND FET BIASING

Cutoff Boundary VCC

I D(SAT) Q Cutoff Boundary VDD

4 BJT AND FET BIASING

Device Variations Due to Tolerance and Temperature 5

6 BJT AND FET BIASING

FET Parametric Variations Due to Tolerance

Device Variations Due to Tolerance and Temperature 7

For Maximum Transfer Curves:

8 BJT AND FET BIASING

FET Parametric Variations Due to Temperature

Device Variations Due to Tolerance and Temperature 9

10 BJT AND FET BIASING

At higher levels of drain current,

VGS(OFF) @ 25 o C Zero tempco point

5 Reference Volume 1, Section 3-3.

Device Variations Due to Tolerance and Temperature 11

ELECTRICAL CHARACTERISTICS (TA = 25 oC unless otherw ise noted.)

12 BJT AND FET BIASING

I C =  DC I B = (120)(7.944 A) = 0.953 mA

VCE = VCC − I C RC = 15 V - (0.9533 mA)(3.6 k) = 11.6 V

VCE = VCC − I C RC = 15 V - (2.86 mA)(3.6 k) = 4.70 V

BJT Fixed Base Bias 13

7-4 FET Bias Lines: Escaping the Math Attack!

What Makes BJT Analysis So Easy?

What Makes FET Analysis Different?

The Bias Line is Obtained by Plotting the Equation for VGS.

14 BJT AND FET BIASING

(a) The common-source amplifier. (b) The DC equivalent circuit.

Step 1: Analyze the Input.

VGS  -VGG (7-3)

Step 2: Transfer Across the Device.

FET Bias Lines: Escaping the Math Attack! 15

Step 3: Analyze the Output.

VDS = VDD – IDRD (7-5)

Finding the Drain Current Using a Bias Line

VGS (V) ID (mA)

(a) Graphing the transfer curve.

16 BJT AND FET BIASING

We use Eq. 7-5 to find VDS.

VDS = VDD – IDRD = 15 V – (9.8 mA)(820 ) = 6.964 V  6.96 V

The Analytical Method for Fixed-Gate Bias is Easier

FET Bias Lines: Escaping the Math Attack! 17