Birla Institute of Technology & Science, Pilani

Work Integrated Learning Programmes Division

Second Semester 2019-2020
M.Tech (Data Science and Engineering)
Comprehensive Exam (EC-3 Regular)

Course No. : DSEIDZG516

Course Title : Computer Organization and Software Systems
Nature of Exam : Open Book
Weightage : 40%
No. of Pages =
Duration : 150 minutes
No. of Questions =
Date of Exam :
Note to Students:
a) Assumptions made if any, should be stated clearly at the beginning of your answer.
b) For all problems relevant steps are to be shown.

1. [1Marks] Consider a processor which takes on the average 1.2 clock cycles to execute an
instruction. What would be the MIPS (Million Instructions Per Second) value of the CPU
if it is driven by a 480 MHz clock?
Ans:
MIPS = f/CPI*10^6 = 480 x 10^6/ 1.2* 10^6 = 400
Marks Distribution: Correct answer 1 marks. No partial Marking
2. [5Marks] In a smartphone, the length of the main memory address is 16-bits. Its L1
cache size is 2K-byte. This cache uses the LRU replacement algorithm and is organized
as a 4-way set-associative cache with 64 bytes per cache line. Consider the memory as
word addressable and the size of the word is 1 byte.
i) How many lines are there in the cache?
ii) How many sets are there in the cache?
iii) Calculate the number of bits in each of the Tag, Set, and Word fields of the memory
address.
iv) When a program is executed, the processor reads data sequentially from the
following word addresses:
128H, 144H, 176H, 180H, 129H, 170H
All the above addresses are shown in hexadecimal values. Assume that the cache is
initially empty. For each of the above addresses, indicate whether the cache access
will result in a hit or a miss. Justify your answer.
Ans: i) 32 lines
ii) 8 sets
iii) Tag : 7, Set : 3 and word : 6
iv)
128  0000 0001 0010 1000  S4, BLOCK4 == M
144  0000 0001 0100 0100  S5, BLOCK5 == M
176  0000 0001 0111 0110  S5, BLOCK4 == M
180  0000 0001 1000 0000  S6, BLOCK6 == M
129  0000 0001 0010 1001  S4, BLOCK4 == M
170  0000 0001 0111 0000  S5, BLOCK5 == M
 Marks distribution:
Part (i) = 0.5
Part (ii) = 0.5
Part (iii) = 1
Part (iv) = 3 (0.5 each)

3. [1 Marks] Consider the following C program segment. Assume that all the relevant
header files are added in the program. What is the output of the program?

Ans: It will print “Hello” and “World” but can’t say about the order.
Marks distribution: 1 marks for correct answer. No partial marking

4. [ 2 Marks] Which of the following statements about threads on a uniprocessor system is

TRUE or FALSE. Provide justification for your choice. Answer without justification
will not be awarded any marks.
i) Thread can contain multiple processes
ii) Every thread of a multi-threaded process has a separate address space
iii) Only one thread can be in running state at any given time
iv) Every thread has its own stack and a program counter
Ans:
i) F: Processes can contain multiple Threads
ii) F : Threads share address space
iii)T: CPU can handle one thread at a time
iv) T: thread has its own stack and a program counter but shares the address space.

Marks distribution: 0.5 marks each

5. [4 Marks] Consider a system with four processes P0, P1, P2 and P3 whose arrival time
and CPU - I/0 bursts are given in the table (Note: CPU burst is indicated with a number
which is underlined). Assume that the system uses round robin scheduling with time
quantum 3 clock cycles. Draw Gantt chart, and fill in the table. Also, find out average
turnaround time, waiting time and response time.
 Ans:
Process Arrival CPU- Finish Turnaround Waiting Response
time I/O Time Time Time Time
Burst
P0 0 4+2+6 31 29 17 0
P1 2 6+2+6 36 34 20 1
P2 4 8+3+5 45 41 25 3
P3 8 7+2+4 46 38 25 5
Average 35.5 21.75 2.25

Marks distribution : 1 marks for Gantt chart and 1marks each for TAT, WT and RT
6. [2 Marks] Identify the variables that support temporal and spatial locality of reference in
the following code segment:

Provide justification for your choice. Answer without justification will not be
awarded any marks.

Ans:
Spatial variables : marks  Justification : In every iteration, we are accessing the marks
array elements sequentially. Hence it provides locality of reference.
Temporal = sum, i, Avg
 Marks Distribution : 1 marks each.

7. [ 4 Marks ] The following pseudocode consists of 3 concurrent processes and 3 binary

semaphores. The semaphores are initialized as S0 = 1, S1 = 0, S2 = 0.

Assuming that the processes are scheduled as follows:

P1, P2, P0, P0, P2, P0, P2, P0
i) How many times will process P0 print ‘0’?
ii) How many times will process P2 print ‘1’?
iii) What will be the values of S0, S1 and S2, at the end of execution of above
sequence?
Ans: (i) Three times
(ii) Two time
(ii) s0 = 0, S1 = S2= 1
Marks distribution: 1 + 1+ 2

8. [1marks] MIPS uses large register file to store data variables. Name the technique of
putting less commonly used variables into memory and which pointer is used to point the
global area?
Ans: Spilling register and gp register

0.5 marks each.

9. [1marks] State whether the following statement is TRUE or FALSE with proper
justification.
The control unit of a CPU if micro programmed would be slower in executing machine
instructions than that of hardwired control unit.
Ans: True, microprogramed control unit is software based or hardwired control unit is
hardware based.

10. [5marks] In 1990, Simplex Company came up with a simple processor with a clock rate
of 4.5GHz and average CPI of 6. Later, they decided to upgrade the system by replacing
simple processor with 5 stage pipelined processor. Due to internal pipeline delay, the
processor clock is reduced to 2.5GHz. Assume that the new system does not implement
any techniques to avoid hazards. Find out the following:
i) Clock time in non-pipeline Processor
ii) Execution Time of non-pipeline Processor
iii) Clock time in pipeline Processor
 iv) Execution Time of pipeline Processor for 100 tasks
v) Speed up achieved in pipeline processor.
i) Clock time in non-pipeline Process
Frequency of the clock = 4.5 gigahertz
Cycle Time =1/f
=>1/(4.5 * 10^9 hertz) => 0.22ns
ii) Execution Time of non-pipeline Process
Non-pipeline execution time to process 1 instruction
= Number of clock cycles taken to execute one instruction
= 6 * 0.22 ns
= 1.32 ns

iii) Cycle Time in Pipeline Process

Frequency of the clock = 2.5 gigahertz
Cycle Time =1/f
=>1/(2.5 * 10^9 hertz) => 0.4ns

iv) Execution Time of pipeline Process

Since there are no stalls in the pipeline, so ideally one instruction is executed per
clock cycle. So, Pipeline execution time
= (0.5 ns * 5 ) + 99 * 0.5 ns =
v) Speed up = Non-pipeline execution time / Pipeline execution time
= 1.32 ns / 0.5 ns
= 2.64
Marks distribution: 1 marks each
11. [5marks] Consider the following snapshot of the system with five processes P0 to P4 and
3 resource types A, B, and C.

Answer the following questions with reference to Banker’s Algorithm. Show all the
necessary steps.
i) In total how many resource instances of each resource type is available in the
system?
Ans: [8 9 6]

ii) Compute NEED matrix.

Ans:
NEED= Max-
Allocation
A B C
4 2 1
2 0 0
4 5 0
 6 7 3
2 1 0

iii) Check whether the system is safe or not. If the system is safe, write the safe
sequence. If not, name all the processes in an unsafe state.
Sol: System is in deadlock state , process P0, P2,P3 are in unsafe state
iv) If a request from process P1 arrives for (0,4,2), can the request be granted? Give
reason in any case.
Sol: Request can’t be granted since the request is greater than the NEED or
System is already in unsafe state.
Marks distribution: 1+1+2+1
12. [3 Marks] Consider the following program for optimization. Line numbers 1 to 11 are
specified for your reference.

i) Which are the optimization techniques that can be used on the program? Identify
the line number and write the corresponding optimization technique.
ii) Write down the final optimized code.
Line 2: Dead code elimination
Line 3:
Line 5: Constant folding, code movement
Line 6:
Line 7 to 9 : Dead code elimination

Final code:
Program Ex1
n=5
t = 100
for i = 1 to 6
n=n+1
next
end

Marks Distribution: 0.5+0.5+0.5 +0.5 + 1 = 3Marks

13. [3 Marks] Consider a memory system of 1MBytes which uses the buddy system for
process allocation. The following is the request for memory by processes arriving in the
same order:
P1=50k, P2=150k, P3=90k, P4=130k, P5=70k, P6=80k, P7=120k, P8=180k, P9=60k.
i) Out of these processes, which will be the first process not to be allotted with
memory?
Ans: p7
ii) How many processes are unallocated? Name the processes.
Ans: 2 processes, P7 and P8
Justify your answers with the help of a memory allocation diagram.

Marks Distribution:
Part I – 1 mark
Part ii – 1 mark
Memory allocation diagram – 1 marks
14. [1 Marks] State whether the following statement is TRUE or FALSE with proper
justification.
A certain computer system has a CPU with a word length of 64 bits, 32 internal
registers and an address bus of width 60 bits. The system’s main memory is 1 GB. Then
the total memory occupied by the CPU internal register set is 32 bytes and to address
the main memory only 30 bits are required.
Ans: false . Total memory occupied by the register is 256 bytes and number of bits needed to
access the main memory is 30 bits

15. [2 Marks] Consider a system with byte addressable memory. The logical memory is
addressed using 32 bits. The frame size is equal 2KB. Each entry in the page table 2
bytes. What is the size of the page table in MBytes?
Ans: 4 Mbytes
Number of pages = 2^32 / 2 x 2^10 = 2^21
Page table size = Number of Pages X page table entry size
= 4MBytes