GaN based High Frequency Power Electronic Interfaces:

Challenges, Opportunities, and Research Roadmap

Matthew Baker1, Sarthak Jain2, and Mohammad B. Shadmand1
1
Electrical and Computer Engineering Department, University of Illinois at Chicago, USA
1
Intelligent Power Electronics at Grid Edge (IPEG) Research Laboratory
2
Amazon Lab126, Sunnyvale, CA, USA

Abstract— Many industrial applications demand high-efficiency
and high-power density power electronic interfaces (PEI),
resulting in adoption of emerging wide band gap (WBG) and
ultra-wide band gap (UWBG) semiconductor devices i.e. Silicon
Carbide (SiC), Gallium Nitride (GaN), Diamond, Gallium Oxide
(Ga2O3), and Aluminum Gallium Nitride (AlGaN). As GaN
devices continue to mature, there exist a need to collect the state-
of-the-art technologies on the properties of these devices and
2021 IEEE Power and Energy Conference at Illinois (PECI) | 978-1-7281-8648-1/21/$31.00 ©2021 IEEE | DOI: 10.1109/PECI51586.2021.9435203
inductors to be used for converters. This allows for an
improved power density of the physical system. The ultra-
wide band gap (UWBG) semiconductor devices i.e. Diamond,
Gallium Oxide (Ga2O3), Aluminum Gallium Nitride (AlGaN)
are also demonstrating the potential to support the realization
of PEIs with even higher levels of performance than WBG
devices such as SiC or GaN. However, the UWBG devices are

their ability to change the landscape of PEI for achieving MHz less mature compared to SiC or GaN devices. Thus, the focus
switching frequency. This paper presents a review of existing of this paper is on GaN devices.
modeling, switching techniques, and active gate drive circuits for
GaN devices towards miniaturization of PEI. These topics are
chosen as the traditional techniques are no longer meeting the TABLE. I: POWER TRANSISTOR MATERIAL PROPERTIES
demand for designing GaN-based high frequency PEI, Parameter Silicon Silicon Carbide Gallium Nitride
specifically the issues involving gate drive optimal design and
minimizing the electromagnetic interface (EMI) encounters and Frequency Low Medium High
remedies. Existing techniques in literature are reviewed and
categorized to explain the current state of GaN-based high Power Rating High High Medium
frequency PEI. Through an in-depth presentation of the Thermal
Medium High Low
research in this field, a clear connection between the current Conductivity
research and future trends is created. This is culminated in the On-State
High Medium Low
creation of a future research roadmap presenting the Resistance
opportunities of GaN-based PEI, the challenges to be overcome
in research, and the expected outcome of fully mature GaN. An
experimental test of a candidate GaN-based half-bridge is
presented that is demonstrating some of the highlighted existing
challenges towards achieving high frequency PEI.

Index Terms – high frequency power electronic, wide band gap,

GaN, SiC, active gate drive

I. INTRODUCTION
Gallium Nitride (GaN) as an emerging wide band gap
(WBG) device is becoming more mature and cost effective in Fig 1. Power vs Frequency plot of different power devices.
comparison with Silicon (Si) devices. Further, the field data
is demonstrating the improving reliability aspect of these
devices. GaN is competing with conventional Si devices and
Silicon Carbide (SiC) WBG devices in the power electronics
market. Si, SiC, and GaN all have unique attributes and
advantages in power electronics as described in [1] and simply
compared in Table I. To demonstrate the niche for GaN, Fig.
1 and Fig. 1 demonstrate the current state of the market, as
described in [2] and [3]. Two of the most important
advantages of GaN devices are the decreased Drain-to-Source
resistance (Rds) and intrinsic capacitances [4]. The reduced Rds
allows for reduced conduction loss, and the reduced
capacitance allows for faster switching speeds. This higher
Fig 2. Expected market growth of GaN applications.
switching frequency allows for smaller filter capacitors and

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 Fig 3. Categorization and association of articles considered in the Review.
While this increased switching frequency is a motivation
behind GaN based power converters, it is what introduced the
major challenges of GaN devices. Since converters ultimately
aim to operate at similar voltages to Si switches, the increased
switching frequency leads to a higher dv/dt and di/dt, which
leads to an increase in Electromagnetic Interference (EMI)
[5]. PCB design also becomes increasingly challenging, as the
board becomes a larger source of parasitic inductance than the
device itself. The parasitics can cause spikes during the
switching transient which can permanently damage
components in the power circuitry if they exceed their rated
limits. Thus, current research trends in GaN devices includes
different practices designed to navigate these problems and
allow for safe operation of these devices without failure. In
particular, the gate drive circuitry of GaN devices will be
explored and reviewed in this paper. Its prevalence in the
literature demonstrated the merits of investigating this topic,
as comparing the effectiveness of different gate drive
topologies and operations can provide a useful resource for
designers deciding the best course of action for their specific
needs. Thus, the main motivation and contribution of this
paper is to provide a review of existing techniques and
analytics as a comprehensive resource for GaN-based high
frequency power electronic interfaces (PEI) designers.
The totality of this review article can be seen in Fig. 3,
which shows the articles selected for consideration. This
article is concerned with both current state of GaN and the
future of GaN power converters. The articles in Fig. 3 were
selected to highlight topics pivotal to reaching maturation for
GaN. The major topics were chosen as circuit modeling,
switching techniques, and active gate drivers. To briefly
describe each: First, circuit modeling techniques cover the
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expected behavior of GaN devices including effects from
parasitics, as well as loss estimation. This primarily aims to
minimize unwanted effects of the device before physical
systems are created and analyze physical systems once
experiments are conducted. Second, switching techniques
explore the effect of switching schemes on converter
parameters, especially hard/soft switching investigations.
These often have the primary goal of reducing the switching
losses. Third, active gate drivers study GaN gate drive circuits
which change circuit parameters dynamically during turn-
on/off. These gate drivers maximize rise time while
minimizing voltage overshoot. The categorization into these
three topics aims to highlight where a given research topic
most impacts the field and group it with other topics,
ultimately providing a complete overview of the GaN
research trend.
The remainder of this paper is as followed: Section II covers
methods of circuit modeling for GaN devices, Section III
covers switching techniques, Section IV covers active gate
drivers and its peripheral design strategies, Section V presents
a future roadmap for GaN power electronics, and Section VI
is the conclusion.
II. GAN DEVICE MODELING
A. Switching Behavior
Modeling for GaN devices is an important aspect of any
research aiming to understand and improve GaN operations.
Modeling of GaN circuits, particularly the parasitic effects of
the components and PCBs, are crucial to maximize the utility
of these devices and ensuring they are being used as optimally
as possible. The high switching frequency of GaN devices
 impose additional concern on the overshoot of the device
transients, as overshoot increases with frequency. To prevent
harmful voltage/current overshoot, these switching behaviors
need to be accurately modelled and accounted for when
designing a system.
An example of detailed parasitic modeling is seen in [6],
which considers a traditional gate drive circuit for GaN
devices. In this study, the circuit is used to demonstrate a
double pulse test for a GaN half-bridge. This model includes
two GaN switches, modeled with their intrinsic resistance and
capacitive components. Additionally, the gate drive
components are included for both switches, including the gate
drive resistor and the parasitic gate drive inductance. The
parasitic inductance size is dominated by the trace on the
PCB; to minimize inductance, the trace is kept as short in
length as possible as well as reducing the area of the power
loop. With this basic model, a double pulse test is used to
model the turn-on process for the device. This breaks down
the turn-on into four stages and includes the equivalent circuit
for each stage. This allows designers to dissect the circuit and
tune parameters as needed. For example, increasing the drive
resistor to minimize voltage overshoot.
PCB design is especially important for GaN because of its
high switching frequency. As shown in [7], small increases in
the parasitic inductances of a PCB can cause voltage
overshoot, potentially to the point of malfunction if not
considered in PCB design. Thus, [7] demonstrates techniques
to utilize the inner layers of a PCB for the power loop to
decrease voltage overshoot, and increase the device switching
speed. Careful PCB design is essential to any GaN board, as
using traditional Si methods will lead to extreme ringing,
negating the advantages promised by GaN switches.
Modeling techniques also demonstrate the differences of
switching signals under differing circumstances; [8] examines
noise in soft switching vs hard switching, and [9]
demonstrates the switching behavior of GaN versus SiC.
Finally, the modeling techniques can be used during
operation, as [10] uses model predictive control during turn-
on to pick an optimal switching profile.
B. Loss Characterization and Estimation
Loss Characterization is another major modeling category
for GaN drivers. Minimizing loss is a top priority for using
WBG devices, and it is often the most important factor.
Therefore, the method used to observe losses is important to
obtain correct data. Simple studies of loss estimation can be
examining the thermal behavior of current chokes as in [11],
in comparing combinations of GaN and SiC in the transistor
and diode of a boost converter [12]. More in depth loss
estimations are seen in [13], where loss characterization is
examined for soft switching techniques. This characterization
uses the Piecewise Linear Electrical Circuit Simulation
(PLECS), a non-SPICE based model of the GaN device to
simulate switching losses based on the switch voltage and
current. The loss characterization needs to account for hard vs
soft switching techniques as they have an immediate impact
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on how losses are calculated. Soft switching techniques can
eliminate the switching losses as the control loop waits until
either the voltage or current goes to zero before the device
transitions to the next state. Therefore, any characterization
strategy must be sure to account for hard vs soft switching
operation used by the converter to ensure all losses are
included in the final loss calculation.
Another source of losses in GaN transistors is due to the
parasitic output capacitance Coss. These losses are covered
extensively in [14]. Coss losses can persist even when other
losses can be eliminated by using soft switching, meaning
additional techniques must be implemented specifically for
Coss. The device in [14] dramatically reduced the cause of
these losses and determined they were due to carbon-related
defects in the carbon doped GaN (GaN:C) layer between the
GaN drain and substrate. As such, when a modified device
was fabricated to reduce this defect, the Coss losses were
dramatically improved. This finding also suggested improved
manufacturing with a multilayer III-Nitride buffer, instead of
the typical single GaN:C layer, could mitigate the effects of
dynamic Rds losses. This implies dramatic improvement of
GaNs manufactured with this process, as Rds losses would not
increase as the device ages.
Loss estimation procedures are essential to any GaN study
aiming to improve converter efficiency for high frequency
applications. The low Rds of GaN compared to Si is one of the
main selling points of GaN transistors. Thus, implementing
these advanced approaches and investigating the cause of
switch loss only improve this natural advantage of GaN over
Si.
III. SWITCHING TECHNIQUES
Soft switching techniques for GaN devices becomes critical
as switching frequencies approach and exceed MHz band. At
these frequencies, switching loss begins to take precedent
over conduction loss due to the increased number of switching
events per time period. Therefore, soft switching techniques
are a significant research topic in high frequency GaN
converters. A comparison is shown in [15] between hard
switching and soft switching for GaN converters. Here, when
tested from 100kHz-750kHz, it is shown soft switching can
reduce power loss by 70-95% depending on the frequency.
This improvement clearly demonstrates the necessity of soft
switching in high frequency applications.
There are two forms of soft switching, zero-current
switching (ZCS) and zero-voltage switching (ZVS) [16].
ZVS is the dominant approach in literature. Two detailed ZVS
approaches are seen in [17, 18]. The ZVS method in [17], uses
slope-sensing to determine when ZVS should occur. The
controller relies on an interval of ‘Partial-ZVS’ immediately
after the output current of the full bridge changes from
positive to negative or vice versa. By detecting this change,
the controller can determine voltage is zero and switching can
be finalized. The controller adaptively modifies its deadtime
to minimize this subinterval. Another WBG specific ZVS
strategy is seen in [18] which proposes a 300V to 5kV DC-
 TABLE. II: ACTIVE GATE DRIVER TOPICS
Active Gate Drive
Reference Features Disadvantages
Method
Allows for coarse and fine tuning of variable Only a general strategy is presented so situational
[24] Variable Resistance
resistors for maximally utilized gate drive profile applications still need additional development
Variable External testing board to easily test Active gate Can only test other Active gate river strategies as it does
[25]
Voltage/Resistance drivers which vary voltages of resistances not propose a new strategy itself
Op-amp based voltage dividers and drive voltage Requires many additional circuit elements to incorporate
[26] Variable Voltage
to drive power switch op amps
Implemented FPGA into gate drive IC for user No demonstration yet it can be incorporated in a ‘plug-
[27] Variable Resistance
friendly programming and-play’ manner
Utilizes lookup table for gate drive circuits, Look up table incurs additional processing time and
[28] Variable Current
specifically for non-insulating gate device resources
Suppress cross talk interference between switches
Additional profile optimization is necessary for reducing
[29] Variable Resistance on same leg by dynamically changing both drive
crosstalk
resistors during turn on/off
Implement model-based design which
approximates transient waveform, allowing fewer Since optimization occurs before assembly, cannot
[30] Variable Resistance
required resistances steps and thus less processing account for changing converter conditions
power per cycle
Particle Swarm Optimization for selecting gate
driver resistors, allowing for efficient selection of All possible profiles options (64^60) need not be as
[31] Variable Resistance
resistors amongst incredibly large number of numerous as this approach considers
options
Demonstrates ability to quickly re-optimize gate
Method is only applicable to similar converters and
[32] Variable Resistance drive profiles for different load currents without
situations
retuning entire circuit

DC converter. This is achieved through a two-stage system, a
GaN full bridge inverter and a SiC half-wave Cockcroft-
Walton rectifier. The stages are connected through an AC link
inductor. This approach demonstrates a sufficiently large link
inductor can guarantee ZVS for the first stage of the converter.
Another promising soft switching approach is seen in [19]
with an altered divided-voltage-type gate driver sub circuit in
parallel to the traditional divided-voltage-type gate driver.
This allowing faster realization of the gate drive voltage and
reduction of switching losses. ZVS strategies frequently
implement resonant circuits, as seen in [20-22], while [23]
presents a novel quasi-resonant driver through MagCap
“MAGnetic”/“CAPacitive” power transfer. In [21], soft
switching is used in a class E inverter switching at 13.56 MHz,
demonstrating the high switching frequencies currently
attainable by GaN. While the focus of this review is on GaN,
it should be noted that GaN designers should not ignore gate
driver advances designed for other materials. A
comprehensive overview of resonant gate drivers of Si and
GaN is presented in [20], which shows how resonant gate
drivers are utilized in both Si and GaN applications.
Additionally, [22] explains the resonant gate drive strategies
used for SiC can be adapted for GaN. Despite designing an
integrated circuit for SiC, [22] boasts universality for all
resonant gate drive circuits through adjusting the integrated
circuit drive voltage.
IV. ACTIVE GATE DRIVERS
A major area of investigation to improving GaN device
performance is active gate drivers. In Table II, a survey of
active gate driver circuits can be seen from the literature. A
conventional gate driver circuit can be seen in Fig. 4. This gate
driver was run, using the testbed seen in Fig. 5, at 1kHz and
100kHz. The resulting transients can be seen in Fig. 6. As is
seen in the waveforms, there are high frequency oscillations
caused by the low bus voltage. Additionally, the system is
unable to change the gate drive profile once the circuit is
constructed. This is where active gate drivers differ from
conventional drivers. They adaptively change the gate
resistance, voltage, or current of the driver while the device is
switching [24]. Active gate drivers typically rely on additional
operations by the microcontroller to quickly vary a circuit
parameter in the transient time period where di/dt and dv/dt
are the greatest. A demonstration example of the operation of
an active gate driver is presented in [24]. This active gate
driver varies the pull-up and pull-down resistance of the gate
driver. It implements two parallel sub circuits, a main driver
and a fine driver. The main driver always matches the polarity
of the PWM signal while the fine driver can switch
independently. The gate drive strategy is working to minimize
losses by starting with a low input resistance, and gradually
increasing it during the rise time to prevent overshoot as the
gate drive voltage reaches its steady state.
As seen in Table II, variable resistance approaches
dominate active gate driver strategies. The methods in [24, 25,
27, 29-32] all rely on control circuitry to dynamically change
the turn-on/turn-off resistance from a pre-established set of
resistances. A generic, abstract implementation of this
circuitry is seen in Fig. 7. An example of variable resistance
is [29] which uses ten potential resistances from 0.125-ȍ
While resistance ranges are carefully selected, little
discussion exists in the literature to determining the size and
values of these resistance options. Since active gate drivers,
especially those aiming to fit a voltage profile, must quickly

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decide on the resistance values applied, it is an open research
question on how to optimally select resistor to reduce
computational effort while maintaining the control objective.
Though less prevalent, variable voltage [25, 26] and variable
current [28] active gate drivers are not absent from recent
literature. Research appears to deviate away from voltage and
current variance however, likely due to the additional
measures and components needed for precise control, such as
the numerous op-amps needed in [26].
Active gate driver strategies mainly vary from each other in
two ways. First is the method controllers use to determine the
instantaneous resistance. Second is the waveform parameters
which are being optimized. Active gate driver controllers
often create a drive profile for a switch and apply this profile
each switching instance [24, 29-31]. An arbitrary example of
a resistance profile is seen in Fig. 8. The method in [27] uses
load current sensing to activate the required profile, and [32] Fig. 4. Schematic of conventional half bridge GaN gate driver.
its shows a profile can be quickly changed for a changing load Resistances are selected based on preferred design process and all
current. Differing profiles of resistors selection methods are included inductances are parasitic.
optimized for a specific task, which can have numerous valid
goals. In [24, 32] the system is designed to prevent voltage
overshoot and minimize EMI, [27] aims to improve surge
voltage and efficiency, [30] considers both EMI and switching
losses, while [29] minimizes crosstalk between switches on
the same leg. Active gate drive designers must carefully
consider the given application as no perfect strategy currently
exists which maximizes performance across all parameters.
Active gate drivers can also be used in testing and
characterization of traditional gate drivers as is seen in [25].
As shown from these works, active gate drivers play a
Fig. 5. Testbed of GaN H-Bridge Circuit before testing
pivotal role in the maturation of GaN in power electronics.
These active methods expand the utility of GaN further as
they address EMI and overshoot issues which must be
addressed at high switching frequencies. Research in active
gate drivers continues to be promising and will almost
certainly push GaN applications and other WBG and UWBG
devices to their theoretical limits as it become easier to
implement in place of conventional gate drivers.
V. RESEARCH ROADMAP
In the previous sections, the state-of-the-art research
concerning GaN was demonstrated. But as a maturing
technology, the future of GaN is needed in a comprehensive
review. Circuit modeling, switching techniques, and active
gate drivers are key to the review as they emphasize issues of Fig. 6. Overshoot voltage and Oscillations of preliminary GaN HEMT
gate drive circuit at 1kHz and 100kHz
particular importance to GaN, especially as it approaches
higher switching frequencies. Fig 9 shows a roadmap of the
trends and future outcomes of GaN power electronics. This The growth of the GaN market as previously shown in Fig.
roadmap shows the importance of each of these research 1 and 2 makes understand GaN’s trajectory important. The
topics, as they directly lead to improvements in important research covered in this review will allow for future power
figures of merit, such as converter power density and converters operating at high frequencies with GaN transistors
efficiency. As a roadmap, it is clear these topics will have a manufactured at prices rivaling the cost of Si today.
direct impact on the advancement of high frequency PEI. these converters will benefit from lower losses due to the
Advances in these topics, aided in advances in material reduced Rds on GaN and allow for smaller passive
science and reductions in the cost on manufacturing, will lead components, increasing the power density of electronics.
to a future where GaN is a major market in power electronics. These gains will be able to find useful applications in low,

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 devices must keep pace to ensure GaN is properly utilized.
Through this article, the present state of GaN is demonstrated,
and a hopeful path into the future is explored.
Future work could directly apply the strategies included in
this review article. For example, direct comparisons of active
gate driver techniques based on experimental circuits would
benefit the field, as typically active gate drivers are compared
only to conventional gate drivers. These tests could also lead
Fig. 7. Generic variable resistance active gate driver with n resistance
values. A controller decides resistance by selecting from the prechosen to a figure of merit to easily compare active gate drivers.
resistors as determined by the specific active gate driver. Another future topic would explore the economic
optimization of GaN converters. An optimization would
compare developed GaN power converters and examine the
returns of using GaN compared to Si at a certain power rating,
voltage level, etc. This would show where GaN is currently
economically superior to Si, but also where GaN is lacking
and in need of further development.
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