CO Part-A Important 2 marks Question Unit wise

1. Explain basic functional unit of a computer

Every Digital computer systems consist of five distinct functional units. These units
are as follows: 1.Input unit 2. Memory unit 3. Arithmetic logic unit 4. Output unit 5.
Control Unit.

Input Unit: An input device is usually a keyboard or mouse, the input device is the
conduit through which data and instructions enter a computer.
Memory unit: memory is used to store programs and data. There are two classes of
storage, called primary and secondary.
Out put Unit:- An output device is any piece of computer hardware equipment used to
communicate the results of data processing carried out by an information processing
system to the outside world.
Arithmetic-Logic Unit:- The arithmetic-logic section performs arithmetic operations,
such as addition, subtraction, multiplication, and division. Arithmetic-Logic Unit
usually called the ALU is a digital circuit that performs two types of operations—
arithmetic and logical.
Control Unit: All activities inside the machine are directed and controlled by the
control unit.
2. Difference between Reduced instruction set computing and Complex instruction set
computing
 3. What are the two I/O interfacing techniques?
The two I/O interfacing techniques are
1. Memory mapped I/O
2. I/O mapped I/O

4. Differentiate memory mapped I/O and I/O mapped I/O.

Memory mapped I/O I/O mapped I/O

In this technique, the total memory In this technique, different space is

address space is partitioned and part of allocated for I/O address apart from total
this space is allocated to I/O addressing. memory space.

5. List the Factors that affect performance of CPU

a) Processor clock:-A computer's processor clock speed determines how quickly
the CPU can retrieve and interpret instructions
b) Basic performance equation:-It refers to the calculation of the performance
or speed of a central processing unit (CPU).
It is given by T = (N*S)/R
T= Time required by the processor to execute a single program
N=Actual number of instructions
S=Steps required to execute single instruction
R=Clock cycle; R cycles/seconds
c) Pipelining:-Pipelining is a technique where multiple instructions are
overlapped during execution.Pipelining increases the overall instruction
throughput.
d) Super Scalar Operation:-In a superscalar computer,(CPU) managesmultiple
instruction pipelines to execute several instructions concurrently during a
clock cycle.
e) Instruction set: CISC and RISC
f) Optimizing Compiler:-Compiler optimizations can reduce the amount of work
performed
g) Performance measurement:-System Performance Evaluation Corporation”
(SPEC), Designed to provide performance measurements that can be used to
compare compute-intensive workloads on different computer systems SPEC
rating = Running time on the reference computer/ Running time on the
computer undertest
6. Draw and explain Single Bus structures

In a single bus structure, one common bus used to communicate between peripherals and
microprocessors. It has disadvantages due to the use of one common bus. Since the bus can
be used for only one transfer at a time, only two units can actively use the bus at any given
time.
7. What is an instruction register? (Nov/Dec 2016)
IR is the part of a CPU's control unit that holds the instruction currently being
executed or decoded. The output of the IR is available to control circuits which
generate the timing signals that control the various processing elements involved in
executing the instruction.
8. Give the formula for CPU execution time for a program.
CPU execution time for a program = CPU clock cycle for a program / Clock Rate

9. Distinguish pipelining from parallelism.

 Parallelism is simply multiple operations happening at the same time.
 Pipelining is a particular arrangement of functions, so that different portions of
an operation flow through a particular set of sub-functions, with the sub-
functions happening in parallel.
10. What are the functions of control unit?
The control unit co-ordinates and controls the activities among the functional units.
The basic function of control unit is to fetch the instructions stored in the main
memory, identify the operations, the devices involved in it and generate control
signals to execute the desired operations.

11. Define throughput and throughput rate.

Throughput is defined as the total amount of work done in a given time. Throughput
rate is defined as the rate at which the total amount of work done at a given time.

12. What do you mean by response time?

Response time or execution time is the total time required for the computer to
complete a task including disk accesses, memory accesses, I/O activities, operating
system overhead etc.

13. State the advantages of multiprocessor system.

 Improves cost / performance ratio of the system.
 Tasks are divided among the modules.
 If fault occurs in one processer, a second processor can take the
responsibility of performing the task which improves the reliability of the
system.
14. Define interrupts.
Interrupt is a process that causes a CPU to temporarily transfer control from its
current program to another program. It improves the computer’s IO performance.
15. Summarize the sequence of events involved in handling an interrupt request from a
single device.(April/May 2017)
 The device raises an interrupt request.
 The processor interrupts the program currently being executed.
 Interrupts are disabled by changing the control bits in the Processor Status
Register.
 The device is informed that its request has been recognized, and in response, it
deactivates the interrupt-request signal.
  The action requested by the interrupt is performed by the interrupt-service
routine.
 Interrupts are enabled and execution of the interrupted program is resumed.

Unit-2
1. How many 128x8 RAM chips are needed to provide a memory capacity of 2048
bytes?
Given RAM chip has 128 x 8 bits = 128 bytes
Number of chips=memory capacity/Available chip size
The number of chips to address a memory capacity of 2048 bytes = 2048/128
=16 chips
2. List various memory management requirements
Relocation , Sharing, Protection, Logical organization, Physical organization
3. What is meant by address mapping?
The correspondence between the main memory blocks and those in the cache is
specified by address mapping. There are three commonly used methods to translate
main memory addresses to cache memory addresses. They are:
 Direct mapping
 Associative mapping
 Set-associative mapping
4. What is cache memory?
A Cache memory is a small and very fast temporary storage memory. It is designed to
speed up the transfer of data and instructions. It is faster than RAM and the
data/instructions that are most recently or most frequently used by CPU are stored in
cache.
5. Define memory hierarchy.
In computer architecture, the memory hierarchy separates computer storage into a
hierarchy based on response time. Since response time, complexity, and capacity are
related, the levels may also be distinguished by their performance and controlling
technologies.
 6. State the advantages of virtual memory.
1. Virtual memory allows processes whose aggregate memory requirement is
greater than the amount of physical memory, as infrequently used pages can
reside on the disk
2. Virtual memory allows speed gain when only a particular segment of the
program is required for the execution of the program
3. It is very helpful in implementing multiprogramming environment.

7. What are the various memory technologies? (Nov/Dec 2015)

 SRAM (Static Random Access Memory)
 DRAM (Dynamic Random Access Memory)
 ROM (Read Only Memory)
 Flash Memory
 Magnetic Disk
8. Point out how DMA can improve I/O speed. (April/May 2015)
DMA allow the peripherals to directly communicate with each other using the
memory buses, removing the intervention of the CPU. During DMA the CPU is idle and it
has no control over the memory buses. So, the DMA controller takes control over the buses to
manage the transfer directly between the I/O devices and the memory unit for improving the
speed.
9. Define memory interleaving.(April/May 2017)
Memory interleaving is the technique used to increase the throughput. The memory
system issplit into independent banks, which can answer read or write requests independents
in parallel. There are two-address format for memory interleaving the address space. They
are: Low order interleaving, High order interleaving
10. Differentiate Programmed I/O and Interrupt I/O.(Nov/Dec 2014)
Sl.N Programmed I/O Interrupt I/O
o
1 The CPU manually checks if there are The CPU doesn't need to manually check for
any I/O requests available I/O When there is an I/O request available,
periodically. If there are no I/O the CPU is immediately notified using
requests. requests it keeps executing interrupts, and the request is immediately
its normal workflow. If there is any handled using
 I/O request, it handles the IO request. interrupt service routines.

11. What is the purpose of dirty/modified bit in cache memory? (Nov/Dec 2014)
A dirty bit or modified bit is a bit that is associated with a block of computer memory
and indicates whether or not the corresponding block of memory has been modified. Dirty
bits are used by the CPU cache and in the page replacement algorithms of an operating
system.

12. What is virtual memory? (Nov/Dec 2017)

Virtual memory is a memory management technique that is implemented using both
hardware and software and it uses main memory as a cache for secondary storage.
Techniques that automatically move program and data blocks into the physical main memory
when they are required for execution are called virtual memory techniques.
13. Define hit ratio. (Nov/Dec 2015)
The hit ratio is the fraction of accesses which are a hit. The miss ratio is the fraction of
accesses which are a miss. It holds that miss rate = 1 − hit rate. The (hit/miss) latency (also
known as access time) is the time it takes to fetch the data in case of a hit/miss.
14. Define hit rate and miss rate.
The fraction of memory accesses found in a level of the memory hierarchy is called hit rate.
The fraction of memory accesses not found in a level of the memory hierarchy is called miss
rate.
15. What is TLB?
Translation Look-aside Buffer (TLB) is a cache that keeps track of recently used address
mapping which tries to avoid an access to the page table.

16. What are the difference between DRAM and SRAM memory technology?
S.N DRAM SRAM
o

1 Single transistor is used to It uses six to eight transistors per

access the stored charge. bit.

2 It is much denser and cheaper It is high cost per bit.

per bit than SRAM.
3 It need periodic refresh. It need not to be refreshed.
4 The value cannot be kept The value can be kept
indefinitely. indefinitely.
17 What are the methods used to improving cache performance?
There are two different techniques available for improving cache performance:
 Reducing the miss penalty by adding an additional level to the hierarchy.
 Reducing the miss rate by reducing the probability that two different memory blocks
will content for the same cache location.

UNIT – 3
1. Define microprocessors?
A programmable integrated chip capable of performing arithmetic and logical
operations similar to that of a CPU. It is referred as CPU on a single chip. It
includes the ALU, register arrays, and control circuits on a singlechip.
2. Define microcomputer?
A computer that is designed using a microprocessor as its CPU. It
includesmicroprocessor, memory and I/O.
3. Define ROM?
A memory that stores binary information permanently. The information canbe
read from this memory but cannot be altered.
4. What is an ALU?
The group of circuit that provides timing and signals to all operation in
thecomputer and controls dataflow.
5. What is Micro controller?
A device that includes microprocessor, memory, and I/O signal lines on asingle
chip, fabricated using VSLI technology

6. Difference between microprocessor and microcontroller.

 MICROPROCESSOR
1. Microprocessor is a chip capable of
performing operations similar to CPU.
2. It contains ALU (Arithmetic Logic
Unit), CU (Control Unit), and Registers.
3. It is used for designing General
purpose computing Systems.
4. Microprocessor is CPU fabricated on
single chip.
E.g : 8085,8086
MICROCONTROLLER
1. Microcontroller is a chip capable
of performing
operations similar to Computer.
2. It contains Microprocessor ,
Memory, Interfacing circuits.
3. It is used for designing Specific
purpose Embedded Systems.
4. Microprocessor is Computer
fabricated on single chip.
E.g : 8051

7. What are the four primary operations of a MPU?

1. Memory read 2. Memory write 3. I/O read 4. I/O write

8. What do you mean by address bus?
A group of lines that are used to send a memory address or a device addressfrom the
MPU to the memory location or a peripheral. The 8085 microprocessorhas 16 address
lines.
8. How many memory locations can be addressed by a microprocessor with 14
address lines?
The8085 MPU with its 14-bit address is capable of addressing 214
=16,384(ie) 16K memory locations.
9. Why is the data bus bi-directional?
The data bus is bi-directional because the data flow in both directionsbetween the
MPU and memory and peripheral devices.
10. What is the function of the accumulator?

The accumulator is the register used to store the 8-bit data to perform
thearithmetic and logical operations.
11. Define control bus?
This is single line that is generated by the MPU to provide timing
ofvariousoperations.
12. What is a flag? The data conditions, after arithmetic or logical operations, are
indicated by setting or resetting the flip-flops called flags.
13. Why are the program counter and the stack pointer 16-bit registers?
Memory locations for the program counter and stack pointer have 16-ditaddress.
So the PC and SP have 16-bit registers.
14. Define memory word?
The number of bits stored in a register is called a memory word.
14. Specify the number of registers and memory cells required in a 128 x 4memory
chip?
15. Number of registers=128Memory cells required is 128 x 4=512
16. Explain the function of ALU and IO/M signals in the 8085 architecture?
The ALU signal goes high at the beginning of each machine cycle indicating the
availability of the address on the address bus, and the signal is used to latch the
low-order address bus. The IO/M signal is a status signal indicating whether the
machine cycle is I/O or memory operation. The IO/M signal is combined with the
RD and WR control signals to generate IOR, IOW, MEMW, MEMR.
17. If the 8085 adds 87H and 79H, specify the contents of the accumulator and the
status of the S, Z, and CY flag?
The sum of 87H and 79H=100H. Therefore, the accumulator will have 00H, and
the flags will be S=0, Z=1, CY=1.
18. Write down the control and status signals?

Two control signals and three status signalsControl signals: RD and WR Status
signals: IO/M, S1, S2
19. Define machine cycle?
Machine cycle is defined, as the time required completing one operation of
accessing memory, I/O, or acknowledging an external request
20. Define instruction cycle?
 Instruction cycle is defined, as the timerequired completing the execution of the
instruction.
21. Draw and explain the programming model of 8085.

A (8-bit) Flag (8-bit)

B (8-bit) C (8-bit)
D (8-bit) E (8-bit)
H (8-bit) L (8-bit)
Stack Pointer (SP) (16-bit)
Program Counter (PC) (16-bit)
Address Lines A0 – A15 Data Lines D0 – D7
22. What does memory-mapping and peripheral mapping mean?

Memory mapping is used for transfer of data from Registers to I/O port. It has
Store and Load functions .
Peripheral mapping is used for transfer of data from I/O device to
Microprocessor. It has IN and OUT functions .

23. What are the types of rotate instruction in 8085 Microprocessor.

There are 4 types of Rotate Instructions
1. RLC (Rotate Accumulator Left)
2. RAL (Rotate Accumulator Left through Carry)
3. RRC (Rotate Accumulator Right)
4. RAR (Rotate Accumulator Right through Carry)

24. List the addressing modes of 8085 with example.

There are 5 types of Addressing modes
Immediate Addressing mode
MVI B,01
Register Addressing mode
MOV A,B
Direct Addressing mode
LDA 8000
Implied Addressing mode
CMA
Register Indirect Addressing mode
STAX 8000

25. What is an instruction set? The entire group of instructions, determines what
functions the microprocessor can perform is called instruction set.
26. Give the functional categories of 8085 micro instructions?
o Data transfer operations
o Arithmetic operations
o Logical operations
o Branching operations
 o Machine control operations
27. Define Opcode and operand?
The operation to be performed is called Opcode. The data to be operated is called
operand.

28. Define the types of branching operations?

Jump: to test the conditions Call, Return, And Restart: Change the sequence of the
program
29. Define two-byte instruction with one example?
In a 2-byte instruction, the first byte specifies the Opcode; the second byte
specifies the operand. Example: Opcode operand MVI A, Dat

30. What is the machine control operations used in 8085 microprocessor?

HLT: Halt NOP: No Operation
UNIT-4

1. What is meant by polling?

Polling or device polling is a process which identifies the device that has interrupted the
microprocessor.
2.What is meant by interrupt?
Interrupt is an external signal that causes a microprocessor to jump to a specific subroutine.
3. Explain priority interrupts of 8085?
The 8085 microprocessor has five interrupt inputs.they are TRAP,RST 7.5,RST 6.5,RST
5.5,and INTR. these interrupts have a fixed priority of interrupt service. If two or more
interrupts go high at the same time,t he 8085 will service them on priority basis. the TRAP
has the highest priority followed by RST7.5,RST6.5,RST5.5 and INTR
4. What is DMA and why it is used?
Direct memory access (DMA) is a method that allows an input/output (I/O) device to send or
receive data directly to or from the main memory, bypassing the CPU to speed up memory
operations. The process is managed by a chip known as a DMA controller (DMAC).
5. What are the various registers used in 8259
It contains 3 registers commonly known as ISR, IRR, IMR  
Interrupt Request Register (IRR): It stores those bits which are requested for their interrupt
services.
Interrupt Service Register (ISR): It stores the interrupt levels which is currently being served.
Interrupt Mask Register (IMR): It stores interrupt levels that have to be masked. These
interrupt levels are already accepted by the 8259 microprocessor.
6. Match the following:
8255 - Programmable peripheral interface.
8279 - Programmable keyboard/display controller.
8254 - Programmable Interval Timer
8257- Direct Memory Access Controller
8251- Programmable Communication Interface
8259 - Programmable interrupt controller

7. Define serial and parallel data transfer

Sr. Key Serial Transmission Parallel Transmission

No.

1 Definition Serial Transmission is the type of On other hand Parallel

transmission in which a single Transmission is the transmission in
communication link is used to which multiple parallel links are
transfer the data from an end to used that transmit each bit of data
another. simultaneously.

2 Bit In case of Serial Transmission On other hand in case of Parallel

transmission only one bit is transferred at one Transmission, eight bits transferred
clock pulse. at one clock pulse.

3 Cost As single link is used in Serial
Efficient Transmission, comparatively low
cost is required for its
implementation hence it is cost
efficient.
On other hand multiple links need
to be implemented in case of
Parallel Transmission hence more
cost is required and hence it is not
cost efficient.

4 Performance As single bit gets transmitted per
clock in case of Serial
Transmission, its performance is
comparatively lower as compared
to Parallel Transmission.
However on other hand as already
mentioned that 8 bits get
transferred per clock in case of
Parallel transmission hence it is
more efficient in performance.

8.List various modes of DMA

Single Byte Transfer Mode/ Cycle Stealing:Once the DMAC becomes the bus master, it will
transfer only ONE BYTE and return the bus back to the microprocessor. As soon as the
microprocessor performs one bus cycle,

Block Transfer Mode.:In this mode, the DMAC is programmed to transfer all the bytes in one
complete DMA operation.

Demand Transfer Mode: It is very similar to Block Transfer, except that the DREQ must
active throughout the DMA operation.
Cascade Transfer Mode: In this mode, more than one DMACs are cascaded together. It is
used to increase the number of devices interfaced to the µP.
9. Give the commonly used priority modes? Fully Nested mode Automatic rotation
mode Specific rotation mode
10. What do you mean by control logic? This has two pins. INT as an output, and INTA
as an input. The INT is connected to the interrupt pin of the MPU.
11. What are the two modes of DMA execution? Slave Mode, Master mode
12. What are the signals used by the DMA controller? The Signals are: o HLDA o DMA
request o DMA acknowledge o AEN – address enable o ADSTB- address strobe 21.
Give the additional features of 8259A controller? Input triggering Interrupt Status Poll
Method

Unit-5: Part-A
1. What is the purpose of 8255 PPI?
The 8255A is widely used, programmable, parallel I/O device .It can be programmed
to transfer data under various conditions, from simple I/O to interrupt I/O.
2. List the operating modes of 8255A PPI?
Bit set Reset and I/O Modes
3. Specify the bit of a control word for the 8255, which differentiates between the I/O
mode and the BSR mode?
BSR mode D7=0, and I/O mode D5=1
4. What is the use of mode 2 in 8255A PPI?
The mode is used primarily in applications such as data transfer between two
computers or floppy disk controller interface.
5. List the major components of 8257 keyboard/display interface?
Keyboard section Scan section Display section MPU interface
6. What is the purpose for scan section in keyboard interface?
The scan section has a scan counter and four scan lines. These scan lines can be
decoded using a 4-to-16 decoder to generate 16 lines for scanning.
7. What is USART?
USART is an integrated circuit. It is a programmable device its function and
specifications for serial I/O can be determined by writing instructions in its internal
registers.
8. Define parallel to serial conversion?
In serial transmission an 8-bit parallel word should be converted in to a stream of
eight serial bits. This is known as parallel to serial conversion.
9. Define simplex transmission? In simplex transmission, data are transmitted in only
one direction. Example: transmission from a microcomputer to a printer.
10. Define Baud? The rate at which the bits are transmitted is called Baud.
11. List the major components of 8251A programmable communication interface?
Read/Write control logic Three buffer registers Data registers Control register
transmission receiver Data bus buffer Modem control
12. Write the steps necessary to initialize a counter in write operation?
Write a control word into the control register Load the low-order address byte
Load the high order byte
13. Give the various modes of 8254 timer?
Mode 0:interrupt or terminal count Mode 1:Rate generator Mode 3:square wave
generator Mode 4:software triggered strobe Mode 5:hardware triggered strobe
14. What is read back command in 8254 timer? The Read Back command in 8254 allows
the user to read the count and the status of the counter.
15. What is transmitter section in USART? The transmitter section accepts parallel data
from the MPU and converts them into serial data. It has two registers. A buffer
register and an output register
16. Give the different types of command words used in 8259A?
The command words of 8259A are classified in two groups
i. ∙Initialization Command Words (ICWs)(ICW1, ICW2, ICW.3, ICW4)
ii. ∙Operation command words (OCWs) (OCW1, OCW2, OCW3)

17. What is Key bouncing?

Key bouncing is the mechanical vibratory action of the contact making and breaking
when keys are pressed in keyboard. Microprocessor must wait until the key reach to a
steady state; this is known as Key bounce.
18. Write control word Register initialization instructions for the 8255A PPI to set
i)port B as an output port in mode 0
ii)port A as an output port in mode 1 for I/O
Ans: i. Port B as an output port in mode 0: 1 0 0 0 0 0 0 0->80
i. Port A as an output port in mode 1 for I/O: 1 0 1 0 0 1 0 0->A4
19. Define cycle stealing
Cycle stealing is a method of accessing computer memory (RAM) or bus without
interfering with the   CPU. It is similar to direct memory access (DMA) for allowing
I/O controllers to read or write RAM without CPU intervention.
20.  Define interrupt, list various hardware and software interrupts
Ans: Interrupt is the method of creating a temporary halt during program execution
and allows peripheral devices to access the microprocessor.
Hardware interrupt is caused by some hardware device such as request to start an I/O,
a hardware failure as a way to avoid wasting the processor’s valuable time in polling
loops, waiting for external events. Example, using any external device.
Software Interrupt is invoked by the use of INT instruction. This event immediately
stops execution of program and passes execution over to the INT handler. It occurs
when an application program terminates or requests certain services from the
operating system. Example, output on screen, execute file etc.