Volume 7, Issue 5, May – 2022 International Journal of Innovative Science and Research Technology

ISSN No:-2456-2165

Bypassing Multiplier Design Techniques

for Detecting Aging Effect
Shalo Thanga Dinah1, Dr.V.Jeyalakshmi2
Associate professor 2
Master of Engineering
Department of ECE College of Engineering,
Guindy Anna University Chennai, Tamilnadu, India

Abstract— In latest years, the requirement for portable
digital gadgets are gaining greater interest. Transportable
gadgets are demanding for low power. Multipliers play a
crucial role in maximum of the DSP implementations.
Thereupon it has become predominant to layout
multipliers utilizing much little power hence improve the
speed of the process. The major intention is in lowering
both the switching interest as well as dynamic power
depletion. Consequently the advanced multiplier design
would lower switching interest in addition to dynamic
power depletion. The various types of bypass multiplier is
the latest reliable multiplier layout which decreases
switching activities with development in structure. The
switching activities must not occur regularly and it can be
averted with the aid of the proposed bypassing logic. The
signal gets bypassed to the next stage and additions
related that were needed to get bypassed won’t get
activated.
Keywords:- Reliable Bypassing multiplier, Aging Effect,
Bypassing logic, AHL Circuit.
I. INTRODUCTION
The multiplier is an essential element for lots of DSP
implementations particularly in virtual filtering, FFT and
DCT. Therefore we were in a want to layout multipliers
which may lower power depletion in addition to switching
activities. Many DSP packages are in need of quicker
computations to upgrade their coefficients. The elements
such as adders, accumulators as well as registers devour a
particular quantity of power for many DSP packages. Hence,
the performance have to be elevated through customization
and structure development. So bypassing method is adopted
in this work and it is the one that is critical to layout. This
bypassing technique will outcome in very less power intake
but the structure is greater than common one. This approach
also decreases the delay of the layout. At architecture level,
low power layout is obtained because of this bypassing
method. Typically in most of the system, the two types of
power intake are static power depletion and dynamic power
utilization. The equation for overall power utilization is
stated as,
PU = αfcCLVDD2 + ISCVDD +IleakageVDD (1)
The first expression defines dynamic power utilization
and the other one defines static power utilization. Static
power dissipation occurs specifically because of leakage
current and dynamic power depletion happens predominantly
owing to charging process occurring in load capacitances.
While the switching interest (α) of the circuit rises the
dynamic power utilization also increases. With the aid of
minimizing the unnecessary switching, the power utilization
may get decreased. Therefore, bypassing process is used to
avoid needless switching activities. Bypassing technique
makes the switching activities to disable a few rows for
decreasing the switching power utilization. Similarly it is also
useful to decrease the propagation delay. The technique of
reducing the power by bypassing technique is based on the
possibility of switching. Greater the possibility of switching
greater might be the power depletion. The possibility of entry
bit being zero incidence is constant in normal distribution for
normal multipliers. But, it is able to change for actual
implementations that are having other distribution. When the
advanced design is implemented at any DSP system, it is
essential to examine ‟0” bit entry data for amount of power
depletion.
II. LITERATURE REVIEW
Ing-Chao Lin, Member, IEEE, Yu-Hung Cho, and Yi-
Ming Yang(2015) has proposed that the multiplier is capable
of providing varying delay hence regulate the AHL system
for decreasing execution depletion happening because of the
effect of aging. Furthermore, the advanced structure can be
carried out to the types of bypassing multiplier. The
experimental results shows that the advanced structure for
16x16 and 32x32 column bypassing multiplier can achieve as
much as 62.88% and 76.28% performance development,
respectively, in comparison with fixed-delay column-
bypassing multipliers.
Archana M V and Suresh Kumar E (2018) has proposed
that reliability is an essential layout problem in advanced
generation nodes. The overall performance of the structure is
affected notably through the transistor getting old and the
device may additionally fail because of long term delay
troubles. The aging effect gets better with the transistor
scaling. Bias temperature instability (BTI) is the primary
cause for transistor ageing. As a consequence of the impact,
the Vth that belongs to the system increases with time and the
speed of multiplier is also decreased. Different layout tactics
may be applied to decrease the effect of aging but it could
result in inefficiency of power and area. Timing violations
arise especially because of constant latency designs. So
variable latency layout multiplier is applied for dependable
operation under BTI effects. For correct selection of cycle
duration, Adaptive Hold Logic (AHL) and the recognition of
timing mistakes is done with the help of ECPL system.

IJISRT22MAY1813 www.ijisrt.com 1574

Volume 7, Issue 5, May – 2022 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165
K.Benarji Srinivas, Mohammed Aneesh Y (2014) has
proposed that multiplier is a vital element in every arithmetic
process in lots of DSP implementations. Hence it has become
crucial to layout multipliers utilizing lesser power and gives
higher velocity of the process. The ultimate aim of the
advanced design is in lowering switching interest and
additionally decreases the power depletion. Thus advanced
bypassing logic technique approach would decrease dynamic
power depletion and delay. The bypassing multiplier
technique is a latest reliable multiplier design which lowers
the activity of switching with structure optimization. The
adders with respect to the things that were needed to be
processed are required. While the possibility of incidence of
zeros is higher, the advanced multiplier layout is better on
considering power by 20% or greater.

Amala Maria Alex and Nidhish Antony(2016) has

proposed that trouble in forecasting the operand that has
more opportunity of no prevalence amongst the design
operand and this process is providing upward thrust to the
theory of various types of bypassing design. Blended
capabilities were integrated within the advanced version and
execution as well is associated with advanced multiplier
design with regard to latency and column bypass with respect
to power utilization. Column bypassing multiplier is finer
with respect to latency amongst all types of bypass
multipliers. The latest version offers better performance
regardless of the possibility. But the advanced architecture
gives decrement in switching activity efficaciously if
opportunity of incidence of 0 is better and this is suitable for
DSP implementations, additional power decrement is
possible.
III. BACKGROUND
There are four main concepts involved in this proposed
methodology
 Column Bypassing Multiplier
 Row Bypassing Multiplier
 Razor Flip Flop
 Adaptive Hold Logic (AHL)
A. Column Bypassing Multiplier
The column-bypassing design is one of the advancement
of the usual array multiplier (AM). The usual one is a quick
parallel design. This multiplier design contains (n − 1)
number of rows of carry save adder (CSA) where every row
consists of the same number of full adder (FA) blocks.
Within the array of CSA, every FA has the following outputs:
1) The sum bit moves below at once and
2) The carry bit moves towards the full adder that is at
bottom left side.
The bottom one is a ripple carry adder that is applied to
the process of distributing the carry bits. The FA present
inside the usual multiplier design are constantly mobile
irrespective of the entry circumstances. Low power
bypassing multiplier layout is projected where the full adder
functions are deactivated when the analogous bit inside the
multiplicand is zero.
Fig. 1: Column Bypassing Multiplier.
Assuming that the incoming bits are 11102* 10112, we
can conclude that for the full adders inside the primary and
tertiary crossways that atleast 2 out of 3 incoming series are
0. Consequently, the result of additions in each crossways
would be zero, hence the sum term result would be identical
to the tertiary term and that is considered to be the outcome
of the sum term of topmost FA. Subsequently, this is changed
for combining the three-state gates and a multiplexer. For the
choice of the multiplexer, the multiplicand bit may be applied
to select the result of the FA, hence the multiplicand bit could
be applied as the chooser of the three-state gate for switching
off the incoming route of the FA. The incoming bits of FA
are deactivated if the multiplicand bit is zero. The sum term
result of the present FA is identical to the sum bit result from
its top FA, thereby lowering the power utilization of the
design.
B. Row Bypassing Multiplier
This type of advanced multiplier design relies upon
quantity of 0’s inside the terms of the multiplier. Few rows of
adders inside the fundamental multiplier array are deactivated
within this particular advanced design throughout their
process for conserving the power. The 3 tristate buffers is
introduced with every full adder to prevent the input. Whilst
the specific full adder is being bypassed, tristate buffers are
useful in halting inputs. On the output part of sum and carry,
two 2:1 multiplexers are linked to interchange between the
path which is bypassed and normal path. Take into account a
multiplier consisting of multiplier bits as well as multiplicand
bits as depicted in fig.2 .An easier way to enhance overall
performance is if all partial products are observed to be 0,
entire row is bypassed to keep away from triggering to
decrease power. Therefore, two multiplexers are required to
implement the bypassing process that are in the adding unit.
The following partial product will be zero, if the jth bit is
zero.

IJISRT22MAY1813 www.ijisrt.com 1575

Volume 7, Issue 5, May – 2022
Fig. 2: Row Bypassing Multiplier
The signal transitions that are redundant gets removed
via disabling the adders whose partial product is found to be
zero. The requirement of additional correcting circuitry is the
primary disadvantage of row bypassing multiplier. As an
example, let the multiplier bit be 0. The first row outcome are
passed immediately to the tertiary row of CSA and the CSA
within the secondary row could be bypassed in this case. It
does not perform the addition operation and the outcome is
incorrect as the rightmost FA within the secondary row is
deactivated. To solve this issue, additional components are
needed to be added and extra components inclusive of a NOT
gate and AND gate are added.
C. Razor Flip Flop
To recognize the error properly and to remove the latency
path negligence, razor flip flop depends on an aggregate of
structural level and circuit level strategies. The concept of
razor is illustrated in fig for a pipeline level. A latch referred
to as shadow latch is directed through a delayed clock and it
is augmented with every flip flop in the layout. The
implementation result for the combination circuit can be
taken with the help of main flip flop by use of normal clock
sign and also implementation result will be taken by the
shadow latch with the use of a detained clock sign that is
comparatively moderate to the ordinary clock sign. A wrong
outcome is found by the main flip flop when the bit that is
taken by the shadow latch isn't the same as that of the
primary flip flop. While error takes place, this particular
system turns the signal of the error to be one so that the
process is executed again and it additionally informs the
AHL circuit that a mistake has happened.
The allowable working voltage is confined at layout
period in a way that under any situations, the latency would
not go beyond the setup time of the system to make sure that
the shadow latch would consistently takes the entry data
accurately. Then logical outcome from the shadow latch is
compared to the outcome of the former one, then a fault sign
is produced inside the subsequent cycles. Also logical data in
the later one is replaced into the former one and is made to be
available for the following process.
IJISRT22MAY1813
International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165
Fig. 3: Razor Flip Flop
D. Adaptive Hold Logic(AHL)
The key element of bypassing reliable multiplier is
adaptive hold logic system. Fig. 4 indicates the detailed
depiction of the AHL circuit. The main components that are
found in Adaptive Hold Logic circuit are an aging detector,
primary and secondary judging blocks, a multiplexer and a
Delay flip-flop. The detector is beneficial in finding the total
performance depletion of the system. A simple counter has
been utilized in implementing the aging indicator and it is
used for counting the amount of errors. The timing
contravention taking place could be determined with the help
of razor flip-flops that produces fault signals. It indicates that
the circuit has suffered massive timing depletion because of
aging effect. If fault take place often and go beyond a pre-
described threshold, the aging indicator will set the output
signal to one. If not, it will set the output sign to 0 to suggest
the aging impact continues to be not considerable, and no
activities are needed.
Fig. 4: Adaptive Hold Logic (AHL)
In this system, when amount of 0’s inside the
multiplicand bit is greater than a particular value n, primary
judging system of the AHL system would sign its result as 1.
Also when the amount of 0’s within the given multiplicand
bit is greater than the value n+1, second system would sign
its result as 1. Both the judging blocks are used to confirm
the number of period that are needed for the incoming series,
but among them one could be selected at once. At
preliminary level, the effect would not be remarkable so the
detector generates 0, hence the primary system is used.
www.ijisrt.com 1576
Volume 7, Issue 5, May – 2022 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165
Whilst the aging effect turns considerable after a particular or not an incoming patterns require one or two cycles whilst
time period, the other judging block is taken into there is an overall performance depletion inside the circuit.
consideration. On evaluating with the first judging block, we
will conclude that the other judging block permits only a V. SIMULATION AND RESULTS
little amount of patterns to turn out to be one cycle pattern
because it needs greater number of zeros inside the The design of Row and Column bypassing multiplier is
multiplicand. logically verified using Xilinx ISE 14.7. The performance
analysis is done to find which multiplier provides better
IV. PROPOSED SYSTEM results. The RTL Schematic of Column and Row Bypassing
Multipliers are depicted in Fig 6 and 7 respectively.
The advanced bypassing design and the Adaptive Hold
Logic system might be carried out simultaneously on the
arrival of incoming patterns. The Adaptive Hold Logic
system determines the number of period for the incoming
series depending on the count of 0’s present inside the
multiplicand bit. This particular system would sign the result
as 0 which deactivates the clock period that belongs to flip-
flops whilst the incoming samples needs more than one
period to finish. Otherwise for regular process, Adaptive
Hold Logic would produce the result as 1. The final outcome
might be carried to the razor flip flop as soon as the advanced
multiplier design ends the process. Also the duration is not
sufficient for the present operation to finish if any timing
contravention takes place and for this reason the
Fig. 6: RTL Schematic of Column bypassing multiplier
implementation outcome of the multiplier produces a wrong
final result.

Fig .7: RTL Schematic of Row bypassing multiplier

Fig. 5: Reliable Multiplier for Aging Awareness with AHL The Simulation results of Column and Row Bypassing
Multiplier using AHL with error and without error are shown
Hence, the Razor FF would produce a fault signal in below.
order to notify the device to execute the current process once
again with the use of cycles to make certain the operation is
accurate. The additional execution process occurring due to
timing contravention provoke to total average delay in this
situation. But, the Adaptive Hold Logic system could find out
correctly the number of incoming series that are needed in
many situations. Whilst the Adaptive Hold Logic circuit
predicts wrongly, only few of the incoming patterns may
result in timing contraventions.

The advanced reliable multiplier layout has some main

functions. First of all, the variable delay layout is the only
one that reduces the timing wastage of the non-vital paths.
Secondarily, even after the aging impact happens it can offer Fig. 8: Simulation Output with Error
dependable operations. The timing contraventions are
predicted by the use of razor flip flops and the process is re-
carried out using two cycles. The Adaptive Hold Logic
circuit makes use of the judging blocks to determine whether

IJISRT22MAY1813 www.ijisrt.com 1577

Volume 7, Issue 5, May – 2022 International Journal of Innovative Science and Research Technology
ISSN No:-2456-2165
correct functioning of the design. The incoming series for
every clock period is examined with the help of adaptive hold
logic circuit and the timing contraventions can be averted by
choosing proper clock cycle. Bypassing technique provides
better overall performance on comparison with other
multipliers. The total area taken by the column and row
bypassing multiplier is much less when compared with array
multiplier. Besides this, the bypassing multipliers has lesser
latency and more throughput.

REFERENCES

[1.] Aging-Aware Reliable Multiplier Design With

Adaptive Hold Logic by Ing-Chao Lin, Member,
Fig. 9: Simulation Output without Error IEEE, Yu-Hung Cho, and Yi-Ming Yang, IEEE
The implementation efficiency of the Row and Column Transactions on Very Large Scale Integration
Bypassing Multipliers is presented in Table I. This table (VLSI) Systems, vol. 23, no. 3, March 2015.
compares Row bypassing multiplier’s efficiency parameters [2.] Reliable Multiplier Design with Adaptive Hold
with that of Column bypassing multiplier’s parameters. Logic for Aging Awareness by Archana M V and
Suresh Kumar E, Proceedings of 2018 International
Conference on Emerging Trends and Innovations in
Parameter Column Bypassing Row Bypassing Engineering and Technological Research
Multiplier Multiplier
(ICETIETR).
Delay 7.156 8.084 [3.] K.Benarji Srinivas, Mohammed Aneesh Y, "Low
No. of lut’s 77 70 power and high speed Row and column Bypass
Full Adders 56 57 Multiplier”,2014 IEEE International conference on
Multiplexers 49 98 computational Intelligence and computing Research.
Table 1: Comparison analysis [4.] Sharvar S.Tantarpale, “Low-Cost Low- Power
Improved Bypassing Based Multiplier”,
From Table I, it is obvious that the Column bypassing
International Journal of Computer Science and
multiplier layout produces more decrement in area and
Communication Engineering IJCSCE Special issue
decrement in delay on comparison with Row bypassing
on “Recent Advances In Engineering &
multiplier. Also, the Column bypassing multiplier uses less
Technology” NCRACET 2013,pp(114-117).
number of full adders and multiplexers than Row bypassing [5.] M. C. Wen, S. J. Wang, and Y. N. Lin, Low power
multiplier. This shows that the Column bypassing multiplier
parallel multiplier with column bypassing, in Proc.
layout attains the finest area and delay. The decrement in IEEE ISCAS, May 2005, pp. 1638- 1641.
efficiency criteria is attained at the cost of performance [6.] D. Ernst et al., Razor: A low-power pipeline based
depletion in precision of the system. on circuit-level timing speculation, in Proc. 36th
VI. CONCLUSION Annual. IEEE/ACM MICRO, Dec. 2003, pp. 7-18.

An advanced reliable bypassing multiplier layout is

presented along with the AHL circuit. The bypassing
multiplier depends totally on the variable delay approach.
The Adaptive Hold Logic circuit may be adjusted by the
multiplier to reduce performance depletion because of the
increment in delay. Similar to the various types of instability
impact that causes transistor aging to increase, interconnect
additionally has aging problems, that is considered to be
electro-migration process. Also latency and performance
depletion may be remarkable if the aging consequences
because of the bias temperature instability effect and electro
migration are examined at the same time. The faults that have
happened because of timing contraventions are decremented
by using advanced dependable multiplier along with use of
adaptive hold logic.

The reliable multiplier is designed with adaptive hold

logic and razor flip flop circuit. The column and row
bypassing multiplier is efficiently executed with the help of
Xilinx ISE 14.7. By the help of razor flip flop circuit, the
latency of the circuit can be decreased hence guarantees

IJISRT22MAY1813 www.ijisrt.com 1578