VAR10 La-9781pp

A B C D E
1 COMPAL CONFIDENTIAL P5 17 1
MODEL NAME : VAR10

REV : 0.2 (X01)
PCB NO : LA-9781P
BOM P/N : 4319ME31L01 2013.01.17
GPIO MAP: GPIO map rev 3.0C @ : Nopop Component
CONN@ : Connector Component
PXDP@,JTAG@ : Total debug Component (pop them until ST)
2 2
3 3
4 4
DELL CONFIDENTIAL/PROPRIETARY
MB PCB
Part Compal Electronics, Inc.
Description PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
Number Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Cover Sheet
www.Vinafix.vn
DAA0006H000 PCB 0W2 LA-9781P REV0 M/B BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.2
LA-9781P
Date: Thursday, January 17, 2013 Sheet 1 of 68
A B C D E
A B C D E
EDP Panel DP(MXM)

Conn
P.32 Intel (DDRIII) Memory Bus DDRIII-DIMM X4
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7 P.13~16
PEG x16 Gen3 PEG Haswell 1.5V DDRIII 1333 /1600 /1866MHz (Overclocking)
LVDS Panel LVDS MUX rPGA CPU

Conn TS3DV20812R eDP to LVDS eDP
1 P.30 P.29 RTD2136S
eDP 947 Pins SATA Port 0 SATA 3.0 Repeater 1st HDD Conn. 1
P.35 DDID PS8520C P.37

P.37
DP 1.2 LVDS (MXM) DP_D P.6~12 SATA Port 5

DP Redriver LVDS 2nd HDD Conn.
Conn P.31 PS8330B P.37
P.31
DP (MXM) FDI x8 DMI x4 gen 2
DP_A SATA Port 1 ODD Conn.
CRT switch CRT (MXM) MXM Conn. SATA3.0
P.38
CRT Conn CRT
MAX14885 CRT TYPE B SATA 2.0 Repeater
P.33 P.33 SATA2.0 SATA Port 3 USB / eSATA Conn.
PS8513C P.41 P.41
DP_C
Docking RGB
P.17 USB Port 8
DP_B
USB2 Port 0
DDID USB 3.0 Conn
DP/HDMI
HDMI 1.4a DP MUX Right Side P.42
DP (MXM) USB 3.0 Repeater
Conn
P.36
DEMUX
PS8339 P.36 PS8331
P.47
Intel USB3 Port 1
PS8713B
CRT P.42
Docking DP Port1 Docking DP Port2
Lynx Point USB 3.0 Conn
USB3.0 USB3 Port 2 USB 3.0 Repeater Right Side
2 BGA PS8713B USB Charger
2
P.42 P.42
PCIE BUS
695 Pins USB2 Port 1
Port 8 Port 2 Port 1 Port 7 Port 6 Port 3 Port 5 USB2.0 USB3 Port 6 USB 3.0 Repeater USB 3.0 Conn
SATA Port 4 PS8713B
USB2 Port 2
Left Side
Intel Lewisville
Mini Card-4 Mini Card-3 Mini Card-2 Mini Card-1
WGI217LM Express Card USB3 Port 5 USB 3.0 Repeater USB 3.0 Conn
P.39 mSATA PP WLAN/WiGi WWAN PS8713B
P.45 P.45 P.44 P.44 P.18~26 HD Audio USB2 Port 9
Left Side
On I/O board P.49
USB Port 10 USB Port 4 USB Port 5
LAN switch On I/O board
USB2 Port 11 BT 4.0+LE
PI3L720ZHEX P.53
P.39 W25Q64FVSSIQ
P.21
SPI
Docking LAN 64M 4K sector USB2 Port 12 Digital Camera
P.30
W25Q32FVSSIQ USB2 Port 13

RJ45 Discrete TPM P.21 Touch screen
OZ777FJ2LN P.40 P.30
AT97SC3204 32M 4K sector
3 SD4.0/MMC P.43
3
LPC BUS
RFID
SMSC SIO BC BUS
ECE5048 TDA8034HN
SDXC USB Port 7 BRCM5882
P.50
On I/O board SMSC KBC TPM 1.2
MEC5075 Smart Card
P.51
FP_USB Fingerprint
Micro SIM Card
P.44 CONN
P.43
SATA Port 2 TP CONN KB CONN
P.53 On USH module
Free Fall Sensor USB2 Port 3
USB2 Port 6 On I/O board
LNG3DMTR
P.37 DAI Combo Jack
Audio Codec
RGB Array MIC Jack
Current Monitor ALC3226
4
EMC1701 LAN
E-Dock
4
P.28 Int. Speaker

USB3.0 Port 3 On I/O board
Thermal sensor LPC
EMC4021 DELL CONFIDENTIAL/PROPRIETARY
Docking DP
P.27 Compal Electronics, Inc.
www.Vinafix.vn
Title
Docking DP P.48 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Block Diagram
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
LA-9781P 0.2

A B C D E
5 4 3 2 1
POWER STATES
Signal SLP SLP SLP S4 SLP ALWAYS M SUS RUN CLOCKS USB PORT# DESTINATION
State S3# S4# S5# STATE# M# PLANE PLANE PLANE PLANE
0 JUSB1 (Ext Right Side)
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH HIGH ON ON ON ON ON
1 JUSB2 (Ext Right Side)
D
S3 (Suspend to RAM) / M1 LOW HIGH HIGH HIGH HIGH ON ON ON OFF OFF D
2 IO Board- JUSB1 (Ext Left Side)
S4 (Suspend to DISK) / M1 LOW LOW HIGH LOW HIGH ON ON OFF OFF OFF
3 Docking USB3.0
S5 (SOFT OFF) / M1 LOW LOW LOW LOW HIGH ON ON OFF OFF OFF
4 WLAN/WIMAX
S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH HIGH LOW ON OFF ON OFF OFF
5 WWAN/UWB
S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW LOW ON OFF OFF OFF OFF PCH
6 Docking USB 2.0
S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW LOW ON OFF OFF OFF OFF
7 USH
PM TABLE 8 ESATA
+PWR_SRC +3.3V_SUS +5V_RUN +3.3V_M +3.3V_M
+PWR_SRC_S +1.35V_MEM +3.3V_RUN +1.05V_M +1.05V_M 9 IO Board- JUSB2 (Ext Left Side)
C
+5V_ALW +1.5V_RUN (M-OFF) C
power
+3.3V_ALW +0.675V_DDR_VTT 10 Express Card
plane SATA DESTINATION
+3.3V_ALW_PCH +VCC_CORE
+3.3V_RTC_LDO +1.05V_RUN
SATA 0 HDD 1 11 BT 4.0
+3.3V_MXM
+5V_MXM 12 Carmera
State SATA 1 ODD
13 Touch Screen
SATA 2 Dock
S0 ON ON ON ON ON
SATA 3 ESATA
0 BIO
S3 ON ON OFF ON OFF
SATA 4 mSATA USH
1 NA
S5 S4/AC ON OFF OFF ON OFF
SATA 5 HDD 2
S5 S4/AC don't exist OFF OFF OFF OFF OFF
PCI EXPRESS DESTINATION
B B
Stack up Lane 1 MINI CARD-4 (NVRAM)
Lane 2 10/100/1G LOM
USB3.0 DESTINATION Lane 3 MINI CARD-2 (WLAN)
Port 1 JUSB1 (Ext Right Side) Lane 4 NA
Port 2 JUSB2 (Ext Right Side) Lane 5 MINI CARD-1 (WWAN)
Port 3 Dock Lane 6 MINI CARD-3 (PP)
Port 4 NA Lane 7 EXPRESS CARD
Port 5 IO Board- JUSB2 Lane 8 MMI(Card reader)

A A
Port 6 IO Board- JUSB1

Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
Index and Config.
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LA-9781P 0.2

5 4 3 2 1
5 4 3 2 1
PCH_ALW_ON TP0610K
+PWR_SRC_S
(PQ4)
EN_LCDPWR APL3512ABI
Docking EN_INVPWR
+EDPVDD
FDC654P (U33)
+BL_PWR_SRC
(Q21)
D MODC_EN TPS22965 Pop option D
+5V_MOD +5V_RUN
3.3V_RUN_GFX_ON
(U57)
ADAPTER SI4835DDY
+MXM_PWR_SRC
(Q186)
+PWR_SRC
BATTERY IMVP_VR_ON ISL95812
+VCC_CORE PWRSHARE_EN#
(PU500) +5V_USB_PWR2
TPS2560
(U45)
1.05V_0.8V_PWROK USB_SIDE_EN#
+5V_USB_PWR1
ESATA_USB_PWR_EN# TPS2560
+5V_ESATA_PWR
CHARGER (U48)
ALWON
+5V_ALW
C C
RT8205 3.3V_RUN_GFX_ON TPS22965

+5V_MXM
(PU101) (U35)
SIO_SLP_S4#
A_ON
RUN_ON Pop option

SIO_SLP_A#
TPS22966
SUS_ON
+5V_RUN +5V_HDD
(U37)
RUN_ON
SYN470D
TPS51212 +1.5V_RUN SIO_SLP_S3#
+3.3V_ALW
RT8207 (PU400)
(PU300)
(PU200)
+1.05V_M
MCARD_MISC_PWREN
3.3V_RUN_GFX_ON
PCH_ALW_ON
SIO_SLP_LAN#
NVRAM_PWR_EN
MCARD_WWAN_PWREN
RUN_ON
RUN_ON
LCD_VCC_TEST_EN
AUX_EN_WOWL
A_ON
SIO_SLP_WLAN#
SUS_ON
LCD_ENVDD_SW
MXM_ENVDD
ENVDD_PCH
+V_DDR_REF +0.675V_DDR_VTT +1.35V_MEM
B B
TPS22965
SI4164DY (U63) TPS22965 TPS22966 TPS22966
(Q63) (U34) (U36) (U40)
APL3512ABI
TPS22966 (U28)
TPS22965 TPS22965 TPS22965
(U37)
(U49) (U43) (U42)
+1.05V_RUN +3.3V_LAN
+3.3V_MXM +3.3V_RUN +3.3V_ALW_PCH +3.3V_SUS +3.3V_M
+LCDVDD
CCD_OFF
Pop option
+3.3V_PCIE_NVM +3.3V_PCIE_WWAN +3.3V_WLAN +3.3V_PCIE_FLASH
+3.3V_M
PMV65XP
(Q24)
A
+CAMERA_VDD A
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Power Rail
LA-9781P
5 4 3 2 1
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5 4 3 2 1
2.2K
SMBUS Address [0x9a]
+3.3V_ALW_PCH
2.2K
R10 MEM_SMBCLK 202
DMN66D0LDW SMBUS Address [A0h]
U11 MEM_SMBDATA 200 DIMM1 A0h --> 1010 0000
DMN66D0LDW
2.2K 202
SMBUS Address [A0h]
PCH 200 DIMM2 A0h --> 1010 0000
2.2K
+3.3V_LAN
202
D U8 LAN_SMBCLK 28 SMBUS Address [A4h] D
200 DIMM3 A4h --> 1010 0100
LAN_SMBDATA 31 LOM SMBUS Address [0xC8]
R7
N11 K6 202
SMBUS Address [A4h]
2.2K 200 DIMM4 A4h --> 1010 0100
SML1_SMBDATA
SML1_SMBCLK
+3.3V_ALW_PCH 53
2.2K
51 XDP1 SMBUS Address [TBD]
A5 B6 2.2K
1D 1D 53
2.2K +3.3V_ALW SMBUS Address 51 XDP2
SMBUS Address [TBD]
APR_EC: 0x48 SMBUS Address
B4 DOCK_SMB_CLK 127
1A SPR_EC: 0x70 SMB_ADM1032: 0x98
DOCK_SMB_DAT
129 DOCKING MSLICE_EC: 0x72 SMB_DIAG_DUMP: 0x04
1A A3 30
USB: 0x59 SMB_DIAG_DUMP2: 0x05
32 WWAN
AUDIO: 0x34 SMBUS Address [TBD] SMB_BLACKTOP: 0x60
SLICE_BATTERY: 0x17
2.2K
SLICE_CHARGER: 0x13
13
2.2K +3.3V_ALW RTD2136S
14 SMBUS Address [0xA8]
C
B5 LCD_SMBCLK C
1B 20 2.2K
A4 LCD_SMDATA eDP Panel SMBUS Address [TBD]
1B 21 +3.3V_RUN
2.2K
2.2K
4
6 LNG3DMTR
SMBUS Address [TBD]
KBC 2.2K
+3.3V_ALW
100 ohm 7
1C A56 PBAT_SMBCLK
100 ohm 6 BATTERY SMBUS Address [0x16]
1C B59 PBAT_SMBDAT CONN
2.2K
+3.3V_SUS
2.2K
A50 USH_SMBCLK 5
1E
B53 USH_SMBDAT 6 USH SMBUS Address [0xa4]
1E
2.2K
+3.3V_SUS
B
MEC 5075 2.2K
7 B
1F A49 CARD_SMBCLK
8 Express card SMBUS Address [TBD]
1F B52 CARD_SMBDAT
2.2K
+3.3V_ALW
2.2K
B50 CHARGER_SMBCLK 9
1G
A47 CHARGER_SMBDAT 8 Charger
1G SMBUS Address [0xFF]
@2.2K
+3.3V_MXM
@2.2K
A7 GPU_SMBCLK
1H 2N7002 70
A
B7 GPU_SMBDAT MXM SMBUS Address [TBD] A
1H 68
2N7002
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Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT SMBUS Bolck Diagram
LA-9781P 0.2

5 4 3 2 1
5 4 3 2 1
+VCOMP_OUT
PEG_COMP 2 1
24.9_0402_1% RC2 PEG_CRX_GTX_C_P[0..15]
PEG_CRX_GTX_C_P[0..15] <17>
PEG_CRX_GTX_C_N[0..15]
CAD Note: PEG_CRX_GTX_C_N[0..15] <17>
Trace width=12 mils ,Spacing=15mil
PEG_CTX_GRX_P[0..15]
D
Max length= 400 mils. PEG_CTX_GRX_P[0..15] <17>
D
PEG_CTX_GRX_N[0..15]
PEG_CTX_GRX_N[0..15] <17>
JCPU1A Haswell rPGA EDS
E23 PEG_COMP
PEG_RCOMP M29 PEG_CRX_GTX_N0 CC1 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N0
DMI_CRX_PTX_N0 D21 PEG_RXN_0 K28 PEG_CRX_GTX_N1 CC2 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N1
<19> DMI_CRX_PTX_N0 DMI_RXN_0 PEG_RXN_1
DMI_CRX_PTX_N1 C21 M31 PEG_CRX_GTX_N2 CC3 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N2
DMI_CRX_PTX_N2 B21 L30 PEG_CRX_GTX_N3 CC4 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N3
DMI_CRX_PTX_N3 A21 M33 PEG_CRX_GTX_N4 CC5 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N4
<19> DMI_CRX_PTX_N3 DMI_RXN_3 PEG_RXN_4 L32 PEG_CRX_GTX_N5 CC6 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N5
DMI_CRX_PTX_P0 D20 PEG_RXN_5 M35 PEG_CRX_GTX_N6 CC7 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N6
<19> DMI_CRX_PTX_P0 DMI_RXP_0 PEG_RXN_6
DMI_CRX_PTX_P1 C20 L34 PEG_CRX_GTX_N7 CC8 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N7
DMI_CRX_PTX_P2 B20 E29 PEG_CRX_GTX_N8 CC9 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N8
DMI_CRX_PTX_P3 A20 D28 PEG_CRX_GTX_N9 CC10 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N9
<19> DMI_CRX_PTX_P3
DMI
DMI_RXP_3 PEG_RXN_9 E31 PEG_CRX_GTX_N10 CC11 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N10
DMI_CTX_PRX_N0 D18 PEG_RXN_10 D30 PEG_CRX_GTX_N11 CC12 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N11
<19> DMI_CTX_PRX_N0 DMI_TXN_0 PEG_RXN_11
<19> DMI_CTX_PRX_N1 DMI_CTX_PRX_N1 C17 E35 PEG_CRX_GTX_N12 CC13 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N12
DMI_CTX_PRX_N2 B17 DMI_TXN_1 PEG_RXN_12 D34 PEG_CRX_GTX_N13 CC14 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N13
<19> DMI_CTX_PRX_N2 DMI_TXN_2 PEG_RXN_13
<19> DMI_CTX_PRX_N3 DMI_CTX_PRX_N3 A17 E33 PEG_CRX_GTX_N14 CC15 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N14
DMI_TXN_3 PEG_RXN_14 E32 PEG_CRX_GTX_N15 CC16 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_N15
DMI_CTX_PRX_P0 D17 PEG_RXN_15 L29 PEG_CRX_GTX_P0 CC17 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_P0
<19> DMI_CTX_PRX_P0 DMI_TXP_0 PEG_RXP_0
<19> DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 C18 L28 PEG_CRX_GTX_P1 CC18 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_P1
C
DMI_CTX_PRX_P2 B18 DMI_TXP_1 PEG_RXP_1 L31 PEG_CRX_GTX_P2 CC19 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_P2 C
<19> DMI_CTX_PRX_P2 DMI_TXP_2 PEG_RXP_2
<19> DMI_CTX_PRX_P3 DMI_CTX_PRX_P3 A18 K30 PEG_CRX_GTX_P3 CC20 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_P3
DMI_TXP_3 PEG_RXP_3 L33 PEG_CRX_GTX_P4 CC21 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_P4
PEG_RXP_4 K32 PEG_CRX_GTX_P5 CC22 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_P5
PEG_RXP_5 L35 PEG_CRX_GTX_P6 CC23 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_P6
PEG_RXP_6 K34 PEG_CRX_GTX_P7 CC24 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_P7
PEG_RXP_7 F29 PEG_CRX_GTX_P8 CC25 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_P8
H29 PEG_RXP_8 E28 2 1
PEG
PEG_CRX_GTX_P9 CC26 0.22U_0402_16V7K PEG_CRX_GTX_C_P9
<19> FDI_CSYNC
FDI
J29 FDI_CSYNC PEG_RXP_9 F31 PEG_CRX_GTX_P10 CC27 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_P10
<19> FDI_INT DISP_INT PEG_RXP_10 E30 2 1
PEG_CRX_GTX_P11 CC28 0.22U_0402_16V7K PEG_CRX_GTX_C_P11
PEG_RXP_12 E34 PEG_CRX_GTX_P13 CC30 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_P13
PEG_RXP_14 D32 PEG_CRX_GTX_P15 CC32 2 1 0.22U_0402_16V7K PEG_CRX_GTX_C_P15
PEG_RXP_15 H35 PEG_CTX_GRX_C_N0 CC44 2 1 0.22U_0402_16V7K PEG_CTX_GRX_N0
PEG_TXN_0 H34 PEG_CTX_GRX_C_N1 CC45 2 1 0.22U_0402_16V7K PEG_CTX_GRX_N1
PEG_TXN_1 J33 PEG_CTX_GRX_C_N2 CC53 2 1 0.22U_0402_16V7K PEG_CTX_GRX_N2
PEG_TXN_2 H32 PEG_CTX_GRX_C_N3 CC73 2 1 0.22U_0402_16V7K PEG_CTX_GRX_N3
PEG_TXN_3 J31 PEG_CTX_GRX_C_N4 CC46 2 1 0.22U_0402_16V7K PEG_CTX_GRX_N4
PEG_TXN_4 G30 PEG_CTX_GRX_C_N5 CC74 2 1 0.22U_0402_16V7K PEG_CTX_GRX_N5
PEG_TXN_5 C33 PEG_CTX_GRX_C_N6 CC47 2 1 0.22U_0402_16V7K PEG_CTX_GRX_N6
PEG_TXN_6 B32 PEG_CTX_GRX_C_N7 CC56 2 1 0.22U_0402_16V7K PEG_CTX_GRX_N7
PEG_TXN_8 A30 PEG_CTX_GRX_C_N9 CC48 2 1 0.22U_0402_16V7K PEG_CTX_GRX_N9
B B
PEG_TXN_15 J35 PEG_CTX_GRX_C_P0 CC67 2 1 0.22U_0402_16V7K PEG_CTX_GRX_P0
PEG_TXP_0 G34 PEG_CTX_GRX_C_P1 CC68 2 1 0.22U_0402_16V7K PEG_CTX_GRX_P1
PEG_TXP_1 H33 PEG_CTX_GRX_C_P2 CC51 2 1 0.22U_0402_16V7K PEG_CTX_GRX_P2
PEG_TXP_2 G32 PEG_CTX_GRX_C_P3 CC52 2 1 0.22U_0402_16V7K PEG_CTX_GRX_P3
PEG_TXP_5 B33 PEG_CTX_GRX_C_P6 CC55 2 1 0.22U_0402_16V7K PEG_CTX_GRX_P6
PEG_TXP_6 A32 PEG_CTX_GRX_C_P7 CC70 2 1 0.22U_0402_16V7K PEG_CTX_GRX_P7
PEG_TXP_7 C31 PEG_CTX_GRX_C_P8 CC57 2 1 0.22U_0402_16V7K PEG_CTX_GRX_P8
PEG_TXP_15
1 OF 9
A A
CONN@
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Haswell (1/7)
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LA-9781P 0.2

5 4 3 2 1
5 4 3 2 1
SM_DRAMPWROK with DDR Power Gating Topology +VCCIO_OUT

+PCH_VCCDSW3_3
0.1U_0402_25V6K
CXDP@ CC65
1U_0402_6.3V6K
D D
+1.35V_MEM
1 1
1 2 RUNPWROK_R +PCH_VCCDSW3_3
CC66
@ RC47 100K_0402_5%
1
1.8K_0402_1%
@ CC156
1 2 PM_DRAM_PWRGD_A 1 2 2 2
RC16
RC18 10K_0402_5%
0.1U_0402_25V6K
2 1 1.35V_SUS_PWRGD
2
5
UC2 @ RC46 6.8K_0402_5% +VCCIO_OUT
2 1 RUNPWROK_R 1
P
<50,51> RUNPWROK B 4 2 1PM_DRAM_PWRGD_CPU
@ RC88 0_0402_5% RUNPWROK_AND Place near JXDP1
2 1 PM_DRAM_PWRGD_A 2 O RC28 0_0402_5%
<19> PM_DRAM_PWRGD A
G
@ RC89 0_0402_5% JXDP1
+3.3V_ALW_PCH
3.3K_0402_1%
74AHC1G09GW_TSSOP5~D XDP_PREQ# 1 2 XDP_PRDY#
39_0402_5%
3
1 2
1
@ RC20
3 4
3 4
RC14
1 2 SYS_PWROK_XDP 5 6
CIS LINK OK @ RC124 1K_0402_1% 7 5 6 8
7 8 RC5 need to close to JCPU1
9 10 H_CPUPWRGD_XDP CXDP@ RC5 2 1 1K_0402_1% H_CPUPWRGD
CXDP@ RC6 1 2 0_0402_5% CFD_PWRBTN#_XDP 11 9 10 12 XDP_HOOK2 CXDP@ RC21 2 1 1K_0402_1%
<18,19> SIO_PWRBTN#_R CFG0 <10>
2
11 12
L2N7002WT1G_SC-70-3
@ RC9 1 2 0_0402_5% SYS_PWROK_XDP 13 14 CLK_XDP CXDP@ RH107 1 2 0_0402_5%
<19,50> SYS_PWROK CLK_CPU_ITP <20>
1 1
13 14
@ QC1
CXDP@ RH108 1 2 0_0402_5% CLK_XDP# 15 16
D <20> CLK_CPU_ITP# 15 16
CXDP@ RC8 1 2 1K_0402_1% XDP_RST#_R 17 18 XDP_DBRESET#
2 CPU_PLTRST#_R 19 17 18 20 XDP_TDO
<51,54> RUN_ON_ENABLE# 19 20 9/25
G XDP_TRST# 21 22 XDP_TDI
XDP_TMS 23 21 22 24
S
3
25 23 24 26 XDP_TCLK
25 26
27 28
29 GND GND 30
GND GND
ACES_50559-02601-001
@ QC2 CONN@
DMN65D8LW-7_SOT323-3
C C
RUNPWROK_AND 1 3 2 1 PM_DRAM_PWRGD_CPU
D
@ RC101 0_0402_5%
G
2
2 1 RUNPWROK_R
<13,15,21> DDR_HVREF_RST_PCH Haswell rPGA EDS
@ RC104 0_0402_5% Refer CRB 1.1 JCPU1B
2 1
<51,57> 1.35V_SUS_PWRGD MISC
RC103 0_0402_5% CPU_DETECT# AP32 AP3 SM_RCOMP0
DDR3L
+VCCST <50> CPU_DETECT# SKTOCC SM_RCOMP_0 AR3 SM_RCOMP1
H_CATERR# AN32 SM_RCOMP_1 AP2 SM_RCOMP2
CATERR SM_RCOMP_2
THERMAL
PECI_EC AR27 AN3 DDR3_DRAMRST#_CPU DDR3_DRAMRST#_CPU <13>
+1.05V_RUN <51> PECI_EC AK31 PECI SM_DRAMRST
RC57 1 2 56_0402_5% H_PROCHOT#_R AM30 FC_AK31 AR29 XDP_PRDY#_R CXDP@ RC62 1 2 0_0402_5% XDP_PRDY#
<51,60,61,62> H_PROCHOT# PROCHOT PRDY
@ RC129 1 2 0_0402_5% H_THERMTRIP#_R AM35 AT29 XDP_PREQ#_R CXDP@ RC81 1 2 0_0402_5% XDP_PREQ#
<51> H_THERMTRIP# THERMTRIP PREQ
place RC129 near CPU AM34 XDP_TCLK_R CXDP@ RC78 1 2 0_0402_5% XDP_TCLK
1 2 H_THERMTRIP# TCK AN33 XDP_TMS_R CXDP@ RC80 1 2 0_0402_5% XDP_TMS
@ RC126 100_0402_1% TMS AM33 XDP_TRST#_R CXDP@ RC56 1 2 0_0402_5% XDP_TRST#
H_PM_SYNC AT28 TRST AM31 XDP_TDI_R CXDP@ RC23 1 2 0_0402_5% XDP_TDI
JTAG
<19> H_PM_SYNC PM_SYNC TDI
PWR
1 2 VCCPWRGOOD_0_R AL34 AL33 XDP_TDO_R CXDP@ RC24 1 2 0_0402_5% XDP_TDO
<23> H_CPUPWRGD PWRGOOD TDO
RC25 0_0402_5% PM_DRAM_PWRGD_CPU AC10 AP33 XDP_DBRESET#_R @ RC26 2 1 0_0402_5% XDP_DBRESET# XDP_DBRESET# <18,19>
+VCCIO_OUT CPU_PLTRST#_R AT26 SM_DRAMPWROK DBR
PLTRSTIN AR30 XDP_OBS0_R PAD~D @ T167
BPM_N_0 AN31 XDP_OBS1_R PAD~D @ T168
@ RC51 2 1 0_0402_5% CPU_DPLL# G28 BPM_N_1 AN29 XDP_OBS2_R PAD~D @ T169
<20> CLK_CPU_DPLL# DPLL_REF_CLKN BPM_N_2
CLOCK
1 2 H_CATERR# @ RC52 2 1 0_0402_5% CPU_DPLL H28 AP31 XDP_OBS3_R PAD~D @ T170
<20> CLK_CPU_DPLL DPLL_REF_CLKP BPM_N_3
@ RC128 49.9_0402_1% @ RC43 2 1 0_0402_5% CPU_SSC_DPLL# F27 AP30 XDP_OBS4_R PAD~D @ T173
<20> CLK_CPU_SSC_DPLL# SSC_DPLL_REF_CLKN BPM_N_4
1 2 H_PROCHOT# @ RC22 2 1 0_0402_5% CPU_SSC_DPLL E27 AN28 XDP_OBS5_R PAD~D @ T174
<20> CLK_CPU_SSC_DPLL SSC_DPLL_REF_CLKP BPM_N_5
RC44 62_0402_5% @ RC15 2 1 0_0402_5% CPU_DMI# D26 AP29 XDP_OBS6_R PAD~D @ T171
<20> CLK_CPU_DMI# BCLKN BPM_N_6
@ RC13 2 1 0_0402_5% CPU_DMI E26 AP28 XDP_OBS7_R PAD~D @ T172
<20> CLK_CPU_DMI BCLKP BPM_N_7
2 OF 9 For ESD concern, please put near CPU
+1.05V_RUN +VCCST
CONN@
B 2 1 B
@ RC99 0_0603_5%
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1
@ @
PU/PD for JTAG signals
CC78
CC79
Refer CRB 1.0

2 2 +3.3V_RUN
XDP_DBRESET#_R RC19 2 1 1K_0402_1%
+1.05V_RUN
XDP_TMS_R @ RC27 2 1 51_0402_1%
VCCPWRGOOD_0_R XDP_TDI_R @ RC29 2 1 51_0402_1%
+3.3V_RUN
10K_0402_5%
XDP_PREQ#_R @ RC32 2 1 51_0402_1%
1
0.1U_0402_25V6K
RC130
XDP_TDO_R RC35 2 1 51_0402_1%
+1.05V_RUN DDR3 COMPENSATION SIGNALS
Buffered reset to CPU 1
@
CC140
2
1
1K_0402_1%
SM_RCOMP0 RC42 1 2 100_0402_1% XDP_TCLK_R RC40 2 1 51_0402_1%

2 @
RC17
SM_RCOMP1 RC55 1 2 75_0402_1% XDP_TRST#_R RC41 2 1 51_0402_1%
CAD Note: SM_RCOMP2 RC49 1 2 100_0402_1%

2
5
@ UC1
1 Avoid stub in the PWRGD path CAD Note:
P
NC 4 PCH_PLTRST#_BUF 1 2 @ RC54 2 1 0_0402_5% CPU_PLTRST#_R

2 Y @ RC10 43_0402_5%
while placing resistors RC25 & RC130 Trace width=12~15 mil, Spcing=20 mils
<18,19> PCH_PLTRST# A
G
A
RC53 2 1 0_0402_5% Max trace length= 500 mil A
<23> CPU_PLTRST#
3
20K_0402_5%
SN74LVC1G07DCKR_SC70-5~D
1
@
RC11
CIS LINK OK
2
CAD Note:
PLACE PULL-UP RESISTOR WITHIN 2 INCH OF THE CPU Compal Electronics, Inc.
Title
LA-9781P 0.2

5 4 3 2 1
www.Vinafix.vn
5 4 3 2 1
D D
Haswell rPGA EDS JCPU1C
Haswell rPGA EDS JCPU1D
<13,14> DDR_A_D[0..63] AR15 AC7 <15,16> DDR_B_D[0..63]
DDR_A_D0 @ T60 PAD~D
DDR_A_D1 AT14 SA_DQ_0 RSVD U4 M_CLK_DDR#0 DDR_B_D0 AR18 AG8 @ T64 PAD~D
AM14 SA_DQ_1 SA_CKN0 V4 M_CLK_DDR#0 <14> AT18 SB_DQ_0 RSVD Y4
DDR_A_D2 M_CLK_DDR0 DDR_B_D1 M_CLK_DDR#2
DDR_A_D3 AN14 SA_DQ_2 SA_CKP0 AD9 DDR_CKE0_DIMM2 M_CLK_DDR0 <14> DDR_B_D2 AM17 SB_DQ_1 SB_CKN0 AA4 M_CLK_DDR2 M_CLK_DDR#2 <16>
DDR_A_D4 AT15 SA_DQ_3 SA_CKE_0 U3 M_CLK_DDR#1 DDR_CKE0_DIMM2 <14> DDR_B_D3 AM18 SB_DQ_2 SB_CKP0 AF10 DDR_CKE2_DIMM4 M_CLK_DDR2 <16>
DDR_A_D5 AR14 SA_DQ_4 SA_CKN1 V3 M_CLK_DDR1 M_CLK_DDR#1 <14> DDR_B_D4 AR17 SB_DQ_3 SB_CKE_0 Y3 M_CLK_DDR#3 DDR_CKE2_DIMM4 <16>
AN15 SA_DQ_5 SA_CKP1 AC9 M_CLK_DDR1 <14> AT17 SB_DQ_4 SB_CKN1 AA3 M_CLK_DDR3 M_CLK_DDR#3 <16>
DDR_A_D6 DDR_CKE1_DIMM2 DDR_B_D5
DDR_A_D7 AM15 SA_DQ_6 SA_CKE_1 U2 M_CLK_DDR#4 DDR_CKE1_DIMM2 <14> DDR_B_D6 AN17 SB_DQ_5 SB_CKP1 AG10 DDR_CKE3_DIMM4 M_CLK_DDR3 <16>
DDR_A_D8 AM9 SA_DQ_7 SA_CKN2 V2 M_CLK_DDR4 M_CLK_DDR#4 <13> DDR_B_D7 AN18 SB_DQ_6 SB_CKE_1 Y2 M_CLK_DDR#6 DDR_CKE3_DIMM4 <16>
DDR_A_D9 AN9 SA_DQ_8 SA_CKP2 AD8 DDR_CKE4_DIMM1 M_CLK_DDR4 <13> DDR_B_D8 AT12 SB_DQ_7 SB_CKN2 AA2 M_CLK_DDR6 M_CLK_DDR#6 <15>
AM8 SA_DQ_9 SA_CKE_2 U1 DDR_CKE4_DIMM1 <13> AR12 SB_DQ_8 SB_CKP2 AG9 DDR_CKE6_DIMM3 M_CLK_DDR6 <15>
DDR_A_D10 M_CLK_DDR#5 DDR_B_D9
DDR_A_D11 AN8 SA_DQ_10 SA_CKN3 V1 M_CLK_DDR5 M_CLK_DDR#5 <13> DDR_B_D10 AN12 SB_DQ_9 SB_CKE_2 Y1 M_CLK_DDR#7 DDR_CKE6_DIMM3 <15>
AR9 SA_DQ_11 SA_CKP3 AC8 M_CLK_DDR5 <13> AM11 SB_DQ_10 SB_CKN3 AA1 M_CLK_DDR7 M_CLK_DDR#7 <15>
DDR_A_D12 DDR_CKE5_DIMM1 DDR_B_D11
DDR_A_D13 AT9 SA_DQ_12 SA_CKE_3 DDR_CKE5_DIMM1 <13> DDR_B_D12 AT11 SB_DQ_11 SB_CKP3 AF9 DDR_CKE7_DIMM3 M_CLK_DDR7 <15>
DDR_A_D14 AR8 SA_DQ_13 M7 DDR_CS0_DIMM2# DDR_B_D13 AR11 SB_DQ_12 SB_CKE_3 DDR_CKE7_DIMM3 <15>
DDR_A_D15 AT8 SA_DQ_14 SA_CS_N_0 L9 DDR_CS1_DIMM2# DDR_CS0_DIMM2# <14> DDR_B_D14 AM12 SB_DQ_13 P4 DDR_CS2_DIMM4#
DDR_A_D16 AJ9 SA_DQ_15 SA_CS_N_1 M9 DDR_CS4_DIMM1# DDR_CS1_DIMM2# <14> DDR_B_D15 AN11 SB_DQ_14 SB_CS_N_0 R2 DDR_CS3_DIMM4# DDR_CS2_DIMM4# <16>
AK9 SA_DQ_16 SA_CS_N_2 M10 DDR_CS4_DIMM1# <13> AR5 SB_DQ_15 SB_CS_N_1 P3 DDR_CS3_DIMM4# <16>
DDR_A_D17 DDR_CS5_DIMM1# DDR_B_D16 DDR_CS6_DIMM3#
DDR_A_D18 AJ6 SA_DQ_17 SA_CS_N_3 M8 M_ODT0 DDR_CS5_DIMM1# <13> DDR_B_D17 AR6 SB_DQ_16 SB_CS_N_2 P1 DDR_CS7_DIMM3# DDR_CS6_DIMM3# <15>
DDR_A_D19 AK6 SA_DQ_18 SA_ODT_0 L7 M_ODT1 M_ODT0 <14> DDR_B_D18 AM5 SB_DQ_17 SB_CS_N_3 DDR_CS7_DIMM3# <15>
DDR_A_D20 AJ10 SA_DQ_19 SA_ODT_1 L8 M_ODT4 M_ODT1 <14> DDR_B_D19 AM6 SB_DQ_18 R4 M_ODT2
DDR_A_D21 AK10 SA_DQ_20 SA_ODT_2 L10 M_ODT5 M_ODT4 <13> DDR_B_D20 AT5 SB_DQ_19 SB_ODT_0 R3 M_ODT3 M_ODT2 <16>
DDR_A_D22 AJ7 SA_DQ_21 SA_ODT_3 V5 DDR_A_BS0 M_ODT5 <13> DDR_B_D21 AT6 SB_DQ_20 SB_ODT_1 R1 M_ODT6 M_ODT3 <16>
DDR_A_D23 AK7 SA_DQ_22 SA_BS_0 U5 DDR_A_BS1 DDR_A_BS0 <13,14> DDR_B_D22 AN5 SB_DQ_21 SB_ODT_2 P2 M_ODT7 M_ODT6 <15>
DDR_A_D24 AF4 SA_DQ_23 SA_BS_1 AD1 DDR_A_BS2 DDR_A_BS1 <13,14> DDR_B_D23 AN6 SB_DQ_22 SB_ODT_3 R7 DDR_B_BS0 M_ODT7 <15>
DDR_A_D25 AF5 SA_DQ_24 SA_BS_2 DDR_A_BS2 <13,14> DDR_B_D24 AJ4 SB_DQ_23 SB_BS_0 P8 DDR_B_BS1 DDR_B_BS0 <15,16>
AF1 SA_DQ_25 V10 AK4 SB_DQ_24 SB_BS_1 AA9 DDR_B_BS1 <15,16>
DDR_A_D26 DDR_B_D25 DDR_B_BS2
DDR_A_D27 AF2 SA_DQ_26 VSS U6 DDR_A_RAS# DDR_B_D26 AJ1 SB_DQ_25 SB_BS_2 DDR_B_BS2 <15,16>
DDR_A_D28 AG4 SA_DQ_27 SA_RAS U7 DDR_A_WE# DDR_A_RAS# <13,14> DDR_B_D27 AJ2 SB_DQ_26 R10
C DDR_A_D29 AG5 SA_DQ_28 SA_WE U8 DDR_A_CAS# DDR_A_WE# <13,14> DDR_B_D28 AM1 SB_DQ_27 VSS R6 DDR_B_RAS# C
DDR_A_D30 AG1 SA_DQ_29 SA_CAS DDR_A_CAS# <13,14> DDR_B_D29 AN1 SB_DQ_28 SB_RAS P6 DDR_B_WE# DDR_B_RAS# <15,16>
DDR_A_D31 AG2 SA_DQ_30 V8 DDR_A_MA0 DDR_A_MA[0..15] <13,14> DDR_B_D30 AK2 SB_DQ_29 SB_WE P7 DDR_B_CAS# DDR_B_WE# <15,16>
DDR_A_D32 J1 SA_DQ_31 SA_MA_0 AC6 DDR_A_MA1 DDR_B_D31 AK1 SB_DQ_30 SB_CAS DDR_B_CAS# <15,16>
DDR_A_D33 J2 SA_DQ_32 SA_MA_1 V9 DDR_A_MA2 DDR_B_D32 L2 SB_DQ_31 R8 DDR_B_MA0 DDR_B_MA[0..15] <15,16>
DDR_A_D34 J5 SA_DQ_33 SA_MA_2 U9 DDR_A_MA3 DDR_B_D33 M2 SB_DQ_32 SB_MA_0 Y5 DDR_B_MA1
DDR_A_D35 H5 SA_DQ_34 SA_MA_3 AC5 DDR_A_MA4 DDR_B_D34 L4 SB_DQ_33 SB_MA_1 Y10 DDR_B_MA2
DDR_A_D36 H2 SA_DQ_35 SA_MA_4 AC4 DDR_A_MA5 DDR_B_D35 M4 SB_DQ_34 SB_MA_2 AA5 DDR_B_MA3
DDR_A_D37 H1 SA_DQ_36 SA_MA_5 AD6 DDR_A_MA6 DDR_B_D36 L1 SB_DQ_35 SB_MA_3 Y7 DDR_B_MA4
DDR_A_D38 J4 SA_DQ_37 SA_MA_6 AC3 DDR_A_MA7 DDR_B_D37 M1 SB_DQ_36 SB_MA_4 AA6 DDR_B_MA5
DDR_A_D39 H4 SA_DQ_38 SA_MA_7 AD5 DDR_A_MA8 DDR_B_D38 L5 SB_DQ_37 SB_MA_5 Y6 DDR_B_MA6
DDR_A_D40 F2 SA_DQ_39 SA_MA_8 AC2 DDR_A_MA9 DDR_B_D39 M5 SB_DQ_38 SB_MA_6 AA7 DDR_B_MA7
DDR_A_D41 F1 SA_DQ_40 SA_MA_9 V6 DDR_A_MA10 DDR_B_D40 G7 SB_DQ_39 SB_MA_7 Y8 DDR_B_MA8
DDR_A_D42 D2 SA_DQ_41 SA_MA_10 AC1 DDR_A_MA11 DDR_B_D41 J8 SB_DQ_40 SB_MA_8 AA10 DDR_B_MA9
DDR_A_D43 D3 SA_DQ_42 SA_MA_11 AD4 DDR_A_MA12 DDR_B_D42 G8 SB_DQ_41 SB_MA_9 R9 DDR_B_MA10
DDR_A_D44 D1 SA_DQ_43 SA_MA_12 V7 DDR_A_MA13 DDR_B_D43 G9 SB_DQ_42 SB_MA_10 Y9 DDR_B_MA11
DDR_A_D45 F3 SA_DQ_44 SA_MA_13 AD3 DDR_A_MA14 DDR_B_D44 J7 SB_DQ_43 SB_MA_11 AF7 DDR_B_MA12
DDR_A_D46 C3 SA_DQ_45 SA_MA_14 AD2 DDR_A_MA15 DDR_B_D45 J9 SB_DQ_44 SB_MA_12 P9 DDR_B_MA13
DDR_A_D47 B3 SA_DQ_46 SA_MA_15 DDR_B_D46 G10 SB_DQ_45 SB_MA_13 AA8 DDR_B_MA14
DDR_A_D48 B5 SA_DQ_47 DDR_B_D47 J10 SB_DQ_46 SB_MA_14 AG7 DDR_B_MA15
DDR_A_D49 E6 SA_DQ_48 AP15 DDR_A_DQS#0 DDR_A_DQS#[0..7] <13,14> DDR_B_D48 A8 SB_DQ_47 SB_MA_15
DDR_A_D50 A5 SA_DQ_49 SA_DQS_N_0 AP8 DDR_A_DQS#1 DDR_B_D49 B8 SB_DQ_48
DDR_A_D51 D6 SA_DQ_50 SA_DQS_N_1 AJ8 DDR_A_DQS#2 DDR_B_D50 A9 SB_DQ_49 AP18 DDR_B_DQS#0 DDR_B_DQS#[0..7] <15,16>
DDR_A_D52 D5 SA_DQ_51 SA_DQS_N_2 AF3 DDR_A_DQS#3 DDR_B_D51 B9 SB_DQ_50 SB_DQS_N_0 AP11 DDR_B_DQS#1
DDR_A_D53 E5 SA_DQ_52 SA_DQS_N_3 J3 DDR_A_DQS#4 DDR_B_D52 D8 SB_DQ_51 SB_DQS_N_1 AP5 DDR_B_DQS#2
DDR_A_D54 B6 SA_DQ_53 SA_DQS_N_4 E2 DDR_A_DQS#5 DDR_B_D53 E8 SB_DQ_52 SB_DQS_N_2 AJ3 DDR_B_DQS#3
DDR_A_D55 A6 SA_DQ_54 SA_DQS_N_5 C5 DDR_A_DQS#6 DDR_B_D54 D9 SB_DQ_53 SB_DQS_N_3 L3 DDR_B_DQS#4
DDR_A_D56 E12 SA_DQ_55 SA_DQS_N_6 C11 DDR_A_DQS#7 DDR_B_D55 E9 SB_DQ_54 SB_DQS_N_4 H9 DDR_B_DQS#5
DDR_A_D57 D12 SA_DQ_56 SA_DQS_N_7 AP14 DDR_A_DQS0 DDR_A_DQS[0..7] <13,14> DDR_B_D56 E15 SB_DQ_55 SB_DQS_N_5 C8 DDR_B_DQS#6
DDR_A_D58 B11 SA_DQ_57 SA_DQS_P_0 AP9 DDR_A_DQS1 DDR_B_D57 D15 SB_DQ_56 SB_DQS_N_6 C14 DDR_B_DQS#7
DDR_A_D59 A11 SA_DQ_58 SA_DQS_P_1 AK8 DDR_A_DQS2 DDR_B_D58 A15 SB_DQ_57 SB_DQS_N_7 AP17 DDR_B_DQS0 DDR_B_DQS[0..7] <15,16>
DDR_A_D60 E11 SA_DQ_59 SA_DQS_P_2 AG3 DDR_A_DQS3 DDR_B_D59 B15 SB_DQ_58 SB_DQS_P_0 AP12 DDR_B_DQS1
B DDR_A_D61 D11 SA_DQ_60 SA_DQS_P_3 H3 DDR_A_DQS4 DDR_B_D60 E14 SB_DQ_59 SB_DQS_P_1 AP6 DDR_B_DQS2 B
DDR_A_D62 B12 SA_DQ_61 SA_DQS_P_4 E3 DDR_A_DQS5 DDR_B_D61 D14 SB_DQ_60 SB_DQS_P_2 AK3 DDR_B_DQS3
DDR_A_D63 A12 SA_DQ_62 SA_DQS_P_5 C6 DDR_A_DQS6 DDR_B_D62 A14 SB_DQ_61 SB_DQS_P_3 M3 DDR_B_DQS4
AM3 SA_DQ_63 SA_DQS_P_6 C12 DDR_A_DQS7 DDR_B_D63 B14 SB_DQ_62 SB_DQS_P_4 H8 DDR_B_DQS5
+SM_VREF SM_VREF SA_DQS_P_7 SB_DQ_63 SB_DQS_P_5
F16 C9 DDR_B_DQS6
+SA_DIMM_VREFDQ SA_DIMM_VREFDQ SB_DQS_P_6
F13 C15 DDR_B_DQS7
+SB_DIMM_VREFDQ SB_DIMM_VREFDQ SB_DQS_P_7
4 OF 9
3 OF 9
CONN@
CONN@
A A
Title
Haswell (3/7)
www.Vinafix.vn
LA-9781P 0.2

5 4 3 2 1
5 4 3 2 1
JCPU1H Haswell rPGA EDS
T28 M27 EDP_CPU_AUX#

DDIB_TXN0 EDP_AUXN EDP_CPU_AUX# <35>
U28 N27 EDP_CPU_AUX
DDIB_TXP0 EDP_AUXP EDP_CPU_AUX <35>
T30 P27 EDP_HPD#
U30 DDIB_TXN1 EDP_HPD E24 EDP_COMP
U29 DDIB_TXP1 EDP_RCOMP R27
V29 DDIB_TXN2 EDP_DISP_UTIL PAD~D T69 @
U31 DDIB_TXP2
D V31 DDIB_TXN3 eDP D
DDIB_TXP3 P35 EDP_CPU_LANE_N0
T34 EDP_TXN_0 R35 EDP_CPU_LANE_P0 EDP_CPU_LANE_N0 <35>
U34 DDIC_TXN0 EDP_TXP_0 N34 EDP_CPU_LANE_N1 EDP_CPU_LANE_P0 <35>
U35 DDIC_TXP0 EDP_TXN_1 P34 EDP_CPU_LANE_P1 EDP_CPU_LANE_N1 <35>
V35 DDIC_TXN1 EDP_TXP_1 P33 FDI_CTX_PRX_N0 EDP_CPU_LANE_P1 <35>
DDIC_TXP1 DDI FDI_TXN_0 FDI_CTX_PRX_N0 <19>
U32 R33 FDI_CTX_PRX_P0
T32 DDIC_TXN2 FDI_TXP_0 N32 FDI_CTX_PRX_P0 <19>
FDI_CTX_PRX_N1
DDIC_TXP2 FDI_TXN_1 FDI_CTX_PRX_N1 <19>
U33 P32 FDI_CTX_PRX_P1
DDIC_TXN3 FDI_TXP_1 FDI_CTX_PRX_P1 <19>
V33
DDIC_TXP3
DPD_CPU_LANE_N0 P29
<47> DPD_CPU_LANE_N0 DPD_CPU_LANE_P0 R29 DDID_TXN0
<47> DPD_CPU_LANE_P0 DPD_CPU_LANE_N1 N28 DDID_TXP0
<47> DPD_CPU_LANE_N1 DPD_CPU_LANE_P1 P28 DDID_TXN1
<47> DPD_CPU_LANE_P1 DPD_CPU_LANE_N2 P31 DDID_TXP1
<47> DPD_CPU_LANE_N2 DPD_CPU_LANE_P2 R31 DDID_TXN2
<47> DPD_CPU_LANE_P2 DPD_CPU_LANE_N3 N30 DDID_TXP2
<47> DPD_CPU_LANE_N3 DPD_CPU_LANE_P3 P30 DDID_TXN3
<47> DPD_CPU_LANE_P3 DDID_TXP3
8 OF 9
+VCCIO_OUT
C C
CONN@
10K_0402_5%
2
RC65
HPD INVERSION FOR EDP
1
EDP_HPD#
COMPENSATION PU FOR eDP
QC6
1
D
+VCOMP_OUT 2
<35> CPU_EDP_HPD
G
S LBSS138LT1G_SOT-23-3
3
100K_0402_5%
EDP_COMP 2 1
1
24.9_0402_1% RC1
RC75
CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.
2
B B
A DELL CONFIDENTIAL/PROPRIETARY A

Title
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NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 0.2
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-9781P
5 4 3 2 1
5 4 3 2 1
CFG STRAPS for CPU

9/21
CFG2
1K_0402_1%
1
@
RC76
D D
2
PEG Static Lane Reversal - CFG2 is for the 16x
1:(Default) Normal Operation; Lane #
CFG2 definition matches socket pin map definition
0:Lane Reversed
JCPU1I Haswell rPGA EDS
CFG4
@ T70 PAD~D AT1
RSVD_TP
1K_0402_1%
@ T71 PAD~D AT2 C23 PAD~D T86 @
1
@ T72 PAD~D AD10 RSVD_TP RSVD_TP B23 PAD~D T78 @
RSVD RSVD_TP
RC77
D24 PAD~D T87 @
@ T73 PAD~D A34 RSVD_TP D23 PAD~D T88 @
@ T74 PAD~D A35 RSVD_TP RSVD_TP
RSVD_TP
2
@ T75 PAD~D W29
@ T76 PAD~D W28 RSVD_TP AT31 CFG_RCOMP PAD~D T136 @
H_CPU_RSVD G26 RSVD_TP CFG_RCOMP AR21 CFG16 PAD~D T137 @
W33 TESTLO_G26 CFG_16 AR23 CFG18 PAD~D T139 @
@ T79 PAD~D AL30 VSS CFG_18 AP21 CFG17 PAD~D T138 @
C @ T80 PAD~D AL29 RSVD CFG_17 AP23 CFG19 PAD~D T140 @ C
+VCC_CORE F25 RSVD CFG_19 Display Port Presence Strap

VCC
@ T82 PAD~D C35 AR33 PAD~D T91 @
@ T81 PAD~D B35 RSVD_TP RSVD G6 FC_G6 1 : Disabled; No Physical Display Port
RSVD_TP FC_G6 AM27 PAD~D T92 @
@ T85 PAD~D AL25 RSVD AM26 PAD~D T89 @ CFG4 attached to Embedded Display Port
RSVD_TP RSVD F5 PAD~D T93 @
@ T84 PAD~D W30 RSVD AM2 PAD~D T95 @ 0 : Enabled; An external Display Port device is
@ T83 PAD~D W31 RSVD_TP RSVD K6 PAD~D T94 @
H_CPU_TESTLO W34 RSVD_TP RSVD connected to the Embedded Display Port
TESTLO_W34 E18 PAD~D T96 @
CFG0 AT20 RSVD
<7> CFG0 CFG_0
@ T90 PAD~D CFG1 AR20 U10 PAD~D T98 @ CFG6
@ T103PAD~D CFG2 AP20 CFG_1 RSVD P10 PAD~D T97 @
@ T104PAD~D CFG3 AP22 CFG_2 RSVD CFG5
CFG_3
1K_0402_1%
@ T105PAD~D CFG4 AT22 B1
CFG_4 NC
1
1K_0402_1%
@ T107PAD~D CFG5 AN22 A2 PAD~D T100 @
CFG_5 RSVD
@ RC85
@ RC83
@ T106PAD~D CFG6 AT25 AR1 PAD~D T99 @
@ T108PAD~D CFG7 AN23 CFG_6 RSVD_TP
@ T109PAD~D CFG8 AR24 CFG_7 E21 PAD~D T102 @
@ T117PAD~D CFG9 AT23 CFG_8 RSVD_TP E20 PAD~D T101 @
2
@ T111PAD~D CFG10 AN20 CFG_9 RSVD_TP
@ T116PAD~D CFG11 AP24 CFG_10 AP27
@ T119PAD~D CFG12 AP26 CFG_11 VSS AR26
@ T128PAD~D CFG13 AN25 CFG_12 VSS
@ T127PAD~D CFG14 AN26 CFG_13 AL31
@ T135PAD~D CFG15 AP25 CFG_14 VSS AL32
CFG_15 VSS
PCIE Port Bifurcation Straps
9 OF 9
2 1 H_CPU_TESTLO Refer 1.2 CRB 11: (Default) x16 - Device 1 functions 1 and 2 disabled
B RC45 49.9_0402_1% B
2 1 CFG_RCOMP
CONN@ 10: x8, x8 - Device 1 function 1 enabled ; function 2
RC58 49.9_0402_1%
2 1 H_CPU_RSVD CFG[6:5] disabled
RC59 49.9_0402_1% 01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
Note: Reserve this circuit CFG7

for future compatibility
1
1K_0402_1%
@ RC86
RESET_OUT#
RESET_OUT# <18,19,51>
1
2
@ RC73
6.04K_0402_1%
2
FC_G6
PEG DEFER TRAINING
1
@ RC72 1: (Default) PEG Train immediately

2.67K_0402_1%
CFG7 following xxRESETB de assertion
0: PEG Wait for BIOS for training
2
A A
Title
LA-9781P 0.2
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5 4 3 2 1
5 4 3 2 1
+VCC_CORE
JCPU1E Haswell rPGA EDS
AA26
VCC AA28
@ T110
@T110 PAD~D K27 VCC AA34
@T77
@ T77 PAD~D L27 RSVD VCC AA30
@T112
@ T112 PAD~D T27 RSVD VCC AA32
@T113
@ T113 PAD~D V27 RSVD VCC AB26
RSVD VCC AB29
D D
+1.35V_MEM VCC AB25
VCC AB27
VCC AB28
AB11 VCC AB30
AB2 VDDQ VCC AB31
AB5 VDDQ VCC AB33
AB8 VDDQ VCC AB34
AE11 VDDQ VCC AB32
AE2 VDDQ VCC AC26
AE5 VDDQ VCC AB35
AE8 VDDQ VCC AC28
AH11 VDDQ VCC AD25
K11 VDDQ VCC AC30
N11 VDDQ VCC AD28
N8 VDDQ VCC AC32
T11 VDDQ VCC AD31
T2 VDDQ VCC AC34
T5 VDDQ VCC AD34
T8 VDDQ VCC AD26
W11 VDDQ VCC AD27
W2 VDDQ VCC AD29
W5 VDDQ VCC AD30
W8 VDDQ VCC AD32
VDDQ VCC AD33
@T115
@ T115 PAD~D N26 VCC AD35
+1.05V_RUN K26 RSVD VCC AE26
+VCC_CORE VCC VCC
AL27 AE32
@ T151
@T151 PAD~D AK27 RSVD VCC AE28
RSVD VCC
150_0402_1%
@T152
@ T152 PAD~D AE30
VCC
1
AG28
VCC
RC69
AG34
VCC AE34
+1.05V_RUN +VCCIO_OUT VCC AF25
+VCCIO_OUT VCC AF26
SVID ALERT
2
C
VCCSENSE_R AL35 VCC AF27 C
2 1 @T153
@ T153 PAD~D E17 VCC_SENSE VCC AF28
RSVD VCC
75_0402_1%
@RC4
@ RC4 0_0603_5% CPU_PWR_DEBUG +VCCIO_OUT AN35 AF29
VCCIO_OUT VCC
1
+VCCIO2PCH_R A23 AF30

FC_A23 VCC
RC60
10K_0402_5%
F22 AF31
CAD Note: Place the PU resistors close to CPU +VCOMP_OUT VCOMP_OUT VCC
1
W32 AF32
RC60 close to CPU 300 - 1500mils RSVD VCC
@
@ T160
@T160 PAD~D AL16 AF33
RSVD VCC
RC71
@T159
@ T159 PAD~D J27 AF34
2
AL13 RSVD VCC AF35

2 1 H_CPU_SVIDALRT# @T154
@ T154 PAD~D RSVD VCC AG26
<60> VIDALERT_N
2
43_0402_5% RC61 VCC AH26
RESISTOR STUFFING OPTIONS ARE VCC
H_CPU_SVIDALRT# AM28 AH29
PROVIDED FOR TESTING PURPOSES VIDSCLK AM29 VIDALERT VCC AG30
<60> VIDSCLK VIDSCLK VCC
VIDSOUT AL28 AG32
+VCCIO_OUT VIDSOUT VCC AH32
SVID DATA AP35
VSS
VCC
VCC
AH35
130_0402_1%
CPU_PWR_DEBUG H27 AH25

PWR_DEBUG VCC
1
AP34 AH27
CAD Note: Place the PU resistors close to CPU VSS VCC
RC63
AT35 AH28
RC63 close to CPU 300 - 1500mils @ T157
@T157 PAD~D AR35 RSVD_TP VCC AH30
@T158
@ T158 PAD~D IVR_ERROR AR32 RSVD_TP VCC AH31
+1.05V_RUN +VCCIO2PCH +VCCIO2PCH_R @T162
@ T162 PAD~D IST_TRIGGER AL26 RSVD_TP VCC AH33
2
@T163
@ T163 PAD~D AT34 RSVD_TP VCC AH34
VIDSOUT AL22 VSS VCC AJ25
<60> VIDSOUT VSS VCC
2 1 2 1 AT33 AJ26
VSS VCC
4.7U_0603_6.3V6K
@ RC105 0_0603_1% @RC106
@ RC106 0_0603_5% AM21 AJ27
AM25 VSS VCC AJ28
1 VSS VCC
CC137
AM22 AJ29
AM20 VSS VCC AJ30
AM24 VSS VCC AJ31
2 AL19 VSS VCC AJ32
+VCC_CORE @ AM23 VSS VCC AJ33
AT32 VSS VCC AJ34
VCC_SENSE VSS VCC
VCC
AJ35
100_0402_1%
B G25 B
VCC
1
H25
VCC
RC66
J25
VCC K25
+VCC_CORE VCC L25
VCC M25
CAD Note: RC67 SHOULD BE PLACED CLOSE TO CPU
2
+1.35V_MEM Y25 VCC N25

VDDQ DECOUPLING Y26 VCC VCC P25
VCCSENSE 2 1 VCCSENSE_R Y27 VCC VCC R25
<60> VCCSENSE VCC VCC
@RC67
@ RC67 0_0402_5% Y28 T25
Y29 VCC VCC
VCC
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
10U_0805_10V6K
330U_D2_2VM_R6M
330U_D2_2VM_R6M
Y30 U25
CAD Note: RC68 SHOULD BE PLACED CLOSE TO CPU @ @ @ @ @ @ @ @
1
@
1
Y31 VCC VCC U26
1 1 1 1 1 1 1 1 1 1 VCC VCC
CC167
CC172
+ + Y32 V25
VCC VCC
CC169
CC162
CC161
CC170
CC164
CC168
CC163
CC166
CC171
CC165
VSSSENSE 2 1 VSSSENSE_R Y33 V26
<60> VSSSENSE VSSSENSE_R <12> VCC VCC
@RC68
@ RC68 0_0402_5% Y34
2 2 2 2 2 2 2 2 2 2 2 2 Y35 VCC W26
VCC VCC
1
100_0402_1%
W27
5 OF 9 VCC
RC70
CONN@
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 @ 1 @ 1 1 @ 1 @ 1 @ 1 @ 1 @ 1 1 @ 1 @
CC33
CC34
CC35
CC36
CC37
CC38
CC39
CC40
CC41
CC42
CC43
2 2 2 2 2 2 2 2 2 2 2
A A
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Title
LA-9781P 0.2

5 4 3 2 1
5 4 3 2 1
JCPU1F Haswell rPGA EDS JCPU1G Haswell rPGA EDS
A10 AK34 B34 K10

A13 VSS VSS AK5 B4 VSS VSS K2
A16 VSS VSS AL1 B7 VSS VSS K29
A19 VSS VSS AL10 C1 VSS VSS K3
D
A3 VSS VSS AL17 C2 VSS VSS K5 D
A7 VSS VSS AL21 C28 VSS VSS L11
AA11 VSS VSS AL23 C30 VSS VSS L26
AA25 VSS VSS E22 C32 VSS VSS L6
AA27 VSS VSS AL3 C34 VSS VSS M11
AB1 VSS VSS AL6 D10 VSS VSS M30
AB10 VSS VSS AL7 D13 VSS VSS M32
AA33 VSS VSS AL8 D16 VSS VSS M34
AA35 VSS VSS AL9 D19 VSS VSS M6
AB3 VSS VSS AM10 D22 VSS VSS N1
AC25 VSS VSS AM13 D25 VSS VSS N10
AB6 VSS VSS E25 D31 VSS VSS N3
AD11 VSS VSS AN10 D7 VSS VSS N4
AC29 VSS VSS AN13 E1 VSS VSS N5
AD7 VSS VSS AN21 E4 VSS VSS P11
AE1 VSS VSS AN24 E7 VSS VSS P26
AE10 VSS VSS AN27 F10 VSS VSS P5
C C
AE25 VSS VSS AN30 F11 VSS VSS R11
AE35 VSS VSS AP1 F17 VSS VSS R32
AE7 VSS VSS AP16 F21 VSS VSS T1
AE9 VSS VSS AP19 F23 VSS VSS T10
AF11 VSS VSS AP4 F24 VSS VSS T29
AF6 VSS VSS AP7 F26 VSS VSS T3
AF8 VSS VSS W 25 F28 VSS VSS T31
AG11 VSS VSS AR10 F30 VSS VSS T33
AE31 VSS VSS AR16 F34 VSS VSS T4
AE33 VSS VSS AR2 F6 VSS VSS T7
AH1 VSS VSS AR25 F8 VSS VSS U11
AH10 VSS VSS AR28 F9 VSS VSS U27
AH2 VSS VSS AR31 G1 VSS VSS V11
AG27 VSS VSS AR34 G11 VSS VSS V28
AG29 VSS VSS AR4 G2 VSS VSS V30
AH3 VSS VSS AR7 G27 VSS VSS V32
AG33 VSS VSS AT10 G29 VSS VSS V34
AG35 VSS VSS AT13 G3 VSS VSS W1
AH4 VSS VSS AT16 G31 VSS VSS W 10
AH5 VSS VSS AT19 G33 VSS VSS W3
AH6 VSS VSS AT21 G35 VSS VSS W 35
B
AH7 VSS VSS AT24 G4 VSS VSS W4 B
AH8 VSS VSS AT27 G5 VSS VSS W6
AH9 VSS VSS AT3 H10 VSS VSS W7
AJ11 VSS VSS AT30 H26 VSS VSS W9
AJ5 VSS VSS AT4 H6 VSS VSS Y11
AK11 VSS VSS AT7 H7 VSS VSS H11
AK25 VSS VSS B10 J11 VSS VSS AL24
AK26 VSS VSS B13 J26 VSS VSS F19
AK28 VSS VSS B16 J28 VSS VSS T26
AK29 VSS VSS B19 J30 VSS VSS AK35
AK30 VSS VSS B2 J32 VSS VSS_SENSE AK33 VSSSENSE_R <11>
AK32 VSS VSS B22 J34 VSS RSVD PAD~D T114@
E19 VSS VSS J6 VSS
VSS K1 VSS
VSS
6 OF 9 7 OF 9
CONN@ CONN@
A A
PROPRIETARY NOTE:
Title
THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
www.Vinafix.vn
0.2
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD LA-9781P
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. Date: Thursday, January 17, 2013 Sheet 12 of 68
5 4 3 2 1
5 4 3 2 1
All VREF traces should

have 10 mil trace width
CPU JDIMM1 Top Side

Populate RD1, De-Populate RD2 for Intel DDR3 JDIMM3
VREFDQ multiple methods M1 JDIMM1 STD Type H=9.2
Populate RD2, De-Populate RD1 for Intel DDR3
PN change to SP07000NB10
JDIMM2 JDIMM4 Bottom Side
VREFDQ multiple methods M3
+DIMM1_VREF_DQ
1 2 +1.35V_MEM +1.35V_MEM
+SA_DIMM1_VREFDQ
@ RD1 0_0402_5%
JDIMM1 CONN@
1 2 1 2
D +V_DDR_REF VREF_DQ VSS1 D
@ RD2 0_0402_5% 3 4 DDR_A_D1
VSS2 DQ4
2.2U_0402_6.3V6M
0.1U_0402_16V4Z
DDR_A_D4 5 6 DDR_A_D5
DDR_A_D0 7 DQ0 DQ5 8
<14,8> DDR_A_DQS#[0..7] 9 DQ1 VSS3 10
1 1 DDR_A_DQS#0
VSS4 DQS#0
@ CD1
11 12 DDR_A_DQS0
<14,8> DDR_A_DQS[0..7] DM0 DQS0
CD6
13 14
DDR_A_D7 15 VSS5 VSS6 16 DDR_A_D2
<14,8> DDR_A_D[0..63] 2 2 17 DQ2 DQ6 18
DDR_A_D6 DDR_A_D3
19 DQ3 DQ7 20
<14,8> DDR_A_MA[0..15] 21 VSS7 VSS8 22
DDR_A_D8 DDR_A_D13
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D12
25 DQ9 DQ13 26
DDR_A_DQS#1 27 VSS9 VSS10 28 +1.35V_MEM
DDR_A_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#_R
DQS1 RESET#
1
1K_0402_1%
31 32
+1.35V_MEM DDR_A_D14 35 DQ10 DQ14 36 DDR_A_D10 +SA_DIMM_VREFDQ_Q
RD44
37 DQ11 DQ15 38 +SA_DIMM_VREFDQ
DDR_A_D21 39 VSS13 VSS14 40 DDR_A_D17 +SA_DIMM1_VREFDQ
2
DDR_A_D20 41 DQ16 DQ20 42 DDR_A_D16 QD6A
DQ17 DQ21
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
43 44 DMN66D0LDW-7_SOT363-6
DDR_A_DQS#2 45 VSS15 VSS16 46 1 6 RD41 1 2 2_0402_1%
1 1 1 1 DQS#2 DM2
DDR_A_DQS2 47 48
DQS2 VSS17
CD2
CD3
CD4
CD5
0.022U_0402_16V7K
49 50 DDR_A_D19
VSS18 DQ22
1K_0402_1%
2
DQ18 DQ23
1
2 2 2 2 DDR_A_D22 53 54
DQ19 VSS19 1
RD43
55 56 DDR_A_D25 DDR_HVREF_RST_PCH
VSS20 DQ28 <15,21,7> DDR_HVREF_RST_PCH
CD89
DDR_A_D28 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_A_DQS#3 2
2
63 VSS22 DQS#3 64 DDR_A_DQS3
65 DM3 DQS3 66
DQ27 DQ31
1
+1.35V_MEM
24.9_0402_1%
71 72
VSS25 VSS26
RC109
C C
10U_0603_6.3V6M
10U_0603_6.3V6M
73 74
<8> DDR_CKE4_DIMM1 DDR_CKE5_DIMM1 <8>
2
CKE0 CKE1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
75 76
VDD1 VDD2
330U_SX_2VY
1 77 78 DDR_A_MA15
NC1 A15
@ CD13
1 1 1 1 1 1 1 DDR_A_BS2 79 80 DDR_A_MA14
<14,8> DDR_A_BS2 BA2 A14 +1.35V_MEM
CD7
CD8
CD9
CD10
CD11
CD12
CD14
+ 81 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
A12/BC# A11
1
1K_0402_1%
DDR_A_MA9 85 86 DDR_A_MA7
2 2 2 2 2 2 2 2 87 A9 A7 88
DDR_A_MA8 89 VDD5 VDD6 90 DDR_A_MA6 +SM_VREF_Q
RD47
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4 +SM_VREF
93 A5 A4 94 QD7 +SM_VREF_DIMM
2
DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2 L2N7002WT1G_SC-70-3
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100 3 1 RD45 1 2 2_0402_1%
D
M_CLK_DDR4 101 VDD9 VDD10 102 M_CLK_DDR5
<8> M_CLK_DDR4 CK0 CK1 M_CLK_DDR5 <8>
0.022U_0402_16V7K
M_CLK_DDR#4 103 104 M_CLK_DDR#5
<8> M_CLK_DDR#4 CK0# CK1# M_CLK_DDR#5 <8>
1K_0402_1%
105 106
G
2
VDD11 VDD12
1
DDR_A_MA10 107 108 DDR_A_BS1 1
A10/AP BA1 DDR_A_BS1 <14,8>
RD46
DDR_A_BS0 109 110 DDR_A_RAS# DDR_HVREF_RST_PCH
Layout Note: <14,8> DDR_A_BS0 BA0 RAS# DDR_A_RAS# <14,8>
CD90
111 112
DDR_A_WE# 113 VDD13 VDD14 114
Place near JDIMM1.203,204 <14,8> DDR_A_WE#
DDR_A_CAS# 115 WE# S0# 116 M_ODT4
DDR_CS4_DIMM1# <8> 2
<14,8> DDR_A_CAS# M_ODT4 <8>
2
117 CAS# ODT0 118
DDR_A_MA13 119 VDD15 VDD16 120 M_ODT5 +DIMM1_VREF_CA
121 A13 ODT1 122 M_ODT5 <8>
<8> DDR_CS5_DIMM1# 123 S1# NC2 124
VDD17 VDD18
1
24.9_0402_1%
125 126 1 2 +SM_VREF_DIMM
NCTEST VREF_CA
RC110
127 128 @ RD7 0_0402_5%
VSS27 VSS28
2.2U_0402_6.3V6M
0.1U_0402_16V4Z
+0.675V_DDR_VTT DDR_A_D37 129 130 DDR_A_D33
DDR_A_D36 131 DQ32 DQ36 132 DDR_A_D32
DQ33 DQ37
@ CD15
133 134 1 1
2
VSS29 VSS30
CD16
DDR_A_DQS#4 135 136
DQS#4 DM4
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
DDR_A_DQS4 137 138

139 DQS4 VSS31 140 DDR_A_D38
1 1 1 1 VSS32 DQ38 2 2
DDR_A_D34 141 142 DDR_A_D39
DQ34 DQ39
CD17
CD18
CD19
CD20
B DDR_A_D35 143 144 B

145 DQ35 VSS33 146 DDR_A_D41
2 2 2 2 DDR_A_D45 147 VSS34 DQ44 148 DDR_A_D40
DDR_A_D44 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_A_DQS#5
155 DM5 DQS5 156 +1.35V_MEM
DDR_A_D46 159 DQ42 DQ46 160 DDR_A_D42 @ RD6
DQ43 DQ47
1
161 162 0_0402_5%
DDR_A_D48 163 VSS39 VSS40 164 DDR_A_D52 2 1 RD5
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53
DQ49 DQ53 1K_0402_5%
167 168
DDR_A_DQS#6 169 VSS41 VSS42 170 QD9
2
DDR_A_DQS6 171 DQS#6 DM6 172 L2N7002WT1G_SC-70-3
+3.3V_RUN 173 DQS6 VSS43 174 DDR_A_D54
175 VSS44 DQ54 176 3 1 1 2
D
DDR_A_D51 DDR_A_D50
DIMM Select DDR_A_D55 177

179
DQ50
DQ51
VSS46
DQ55
VSS45
DQ60
178
180 DDR_A_D60
<7> DDR3_DRAMRST#_CPU
RD51 1K_0402_1%
DDR3_DRAMRST#_R <14,15,16>
10K_0402_5%
DDR_A_D57 181 182 DDR_A_D61
G
2
DQ56 DQ61
2
1
DDR_A_D56 183 184
185 DQ57 VSS47 186 DDR_A_DQS#7 RD30 DDR_HVREF_RST_PCH
VSS48 DQS#7
RD8
187 188 DDR_A_DQS7 4.99K_0402_1% 1

189 DM7 DQS7 190
VSS49 VSS50 9/21
DDR_A_D63 191 192 DDR_A_D58 CD92
1
2
+3.3V_RUN DDR_A_D62 193 DQ58 DQ62 194 DDR_A_D59
DQ59 DQ63 0.047U_0402_16V4Z
DIMM1_SA0 195 196 2
DIMM1_SA1 DIMM1_SA0 197 VSS51 VSS52 198
199 SA0 EVENT# 200
SA0 SA1 DIMM1_SA1 201 VDDSPD SDA 202 DDR_XDP_WAN_SMBDAT <14,15,16,18,21,35,37>
SA1 SCL DDR_XDP_WAN_SMBCLK <14,15,16,18,21,35,37>
2
10K_0402_5%
0.1U_0402_16V4Z
2.2U_0402_6.3V6M
DIMM2 0 0 1 1 203 204

+0.675V_DDR_VTT VTT1 VTT2 +0.675V_DDR_VTT
RD13
@ CD22
CD21
DIMM4 0 1 205 206

G1 G2
2 2 TYCO_2-2013310-1~D
* DIMM1 1 0
1
DIMM3 1 1
A A
Check D15 de-pop
www.Vinafix.vn
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT DDRIII-SODIMM SLOT1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-9781P 0.2

5 4 3 2 1
5 4 3 2 1

JDIMM2 STD Type H=5.2
PN change to SP07000OF00
1 2 +DIMM2_VREF_DQ
+SA_DIMM1_VREFDQ
@ RD14 0_0402_5% +1.35V_MEM +1.35V_MEM CPU JDIMM1 Top Side
JDIMM2 CONN@
JDIMM3
+V_DDR_REF 1 2 1 2
<13,8> DDR_A_DQS#[0..7] VREF_DQ VSS1
@ RD15 0_0402_5% 3 4 DDR_A_D4
VSS2 DQ4 JDIMM2 JDIMM4 Bottom Side
2.2U_0402_6.3V6M
0.1U_0402_16V4Z
<13,8> DDR_A_DQS[0..7] DQ0 DQ5
1 1 DDR_A_D5 7 8
DQ1 VSS3
CD24
9 10 DDR_A_DQS#0
<13,8> DDR_A_D[0..63] VSS4 DQS#0
CD23
11 12 DDR_A_DQS0
13 DM0 DQS0 14
D D
<13,8> DDR_A_MA[0..15] 2 2 VSS5 VSS6
19 DQ3 DQ7 20
25 DQ9 DQ13 26
DDR_A_DQS#1 27 VSS9 VSS10 28
+1.35V_MEM DDR_A_DQS1 29 DQS#1 DM1 30
DQS1 RESET# DDR3_DRAMRST#_R <13,15,16>
31 32
DQ11 DQ15
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
37 38
1 1 1 1 DQ16 DQ20
DQ17 DQ21
CD25
CD26
CD27
CD28
43 44
2 2 2 2 DDR_A_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_A_D23
DDR_A_D19 51 VSS18 DQ22 52 DDR_A_D22
DDR_A_D18 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_A_D29
DDR_A_D24 59 DQ24 DQ29 60
+1.35V_MEM 65 DM3 DQS3 66
71 DQ27 DQ31 72
VSS25 VSS26
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
330U_SX_2VY
@CD35
@ 1
1 1 1 1 1 1 1 73 74
<8> DDR_CKE0_DIMM2 CKE0 CKE1 DDR_CKE1_DIMM2 <8>
CD29
CD30
CD31
CD32
CD33
CD34
CD35
CD36
+ 75 76
C
77 VDD1 VDD2 78 DDR_A_MA15 C
DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14
2 2 2 2 2 2 2 2 <13,8> DDR_A_BS2 BA2 A14
81 82
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88
93 A5 A4 94
99 A1 A0 100
Layout Note: <8> M_CLK_DDR0
M_CLK_DDR1 <8>
M_CLK_DDR#0 103 CK0 CK1 104 M_CLK_DDR#1
Place near JDIMM2.Pin 203,204 <8> M_CLK_DDR#0
105 CK0# CK1# 106
M_CLK_DDR#1 <8>
DDR_A_MA10 107 VDD11 VDD12 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 <13,8>
DDR_A_BS0 109 110 DDR_A_RAS#
<13,8> DDR_A_BS0 BA0 RAS# DDR_A_RAS# <13,8>
111 112
DDR_A_WE# 113 VDD13 VDD14 114
<13,8> DDR_A_WE# WE# S0# DDR_CS0_DIMM2# <8>
DDR_A_CAS# 115 116 M_ODT0
<13,8> DDR_A_CAS# CAS# ODT0 M_ODT0 <8>
117 118
DDR_A_MA13 119 VDD15 VDD16 120 M_ODT1 +DIMM2_VREF_CA
A13 ODT1 M_ODT1 <8>
+0.675V_DDR_VTT 121 122
<8> DDR_CS1_DIMM2# S1# NC2
123 124
125 VDD17 VDD18 126 1 2
NCTEST VREF_CA +SM_VREF_DIMM
127 128 @ RD16 0_0402_5%
VSS27 VSS28
2.2U_0402_6.3V6M
0.1U_0402_16V4Z
DDR_A_D33 129 130 DDR_A_D37
DQ32 DQ36
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
DDR_A_D32 131 132 DDR_A_D36

DQ33 DQ37
@
1 1 1 1 133 134 1 1
VSS29 VSS30
CD41
CD42
DDR_A_DQS#4 135 136
DQS#4 DM4
CD37
CD38
CD39
CD40
DDR_A_DQS4 137 138

139 DQS4 VSS31 140 DDR_A_D34
2 2 2 2 DDR_A_D38 141 VSS32 DQ38 142 DDR_A_D35 2 2
DDR_A_D39 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_A_D45
B B
DDR_A_D40 149 DQ40 DQ45 150
155 DM5 DQS5 156
DDR_A_D42 159 DQ42 DQ46 160 DDR_A_D46
161 DQ43 DQ47 162
DIMM Select DDR_A_D52
DDR_A_D53
163
165
167
VSS39
DQ48
DQ49
VSS40
DQ52
DQ53
164
166
168
DDR_A_D48
DDR_A_D49

DDR_A_DQS6 171 DQS#6 DM6 172
173 DQS6 VSS43 174 DDR_A_D51
DDR_A_D50 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_A_D57
DDR_A_D61 183 DQ56 DQ61 184
DIMM2_SA0 187 VSS48 DQS#7 188 DDR_A_DQS7
DM7 DQS7 9/21
SA0 SA1 189 190
DIMM2_SA1 DDR_A_D58 191 VSS49 VSS50 192 DDR_A_D63
+3.3V_RUN DQ58 DQ62
10K_0402_5%
DDR_A_D59 193 194 DDR_A_D62

* DIMM2 0 0 DQ59 DQ63
2
2
10K_0402_5%
195 196
VSS51 VSS52
RD19
RD20
DIMM2_SA0 197 198

DIMM4 0 1 199 SA0 EVENT# 200
VDDSPD SDA DDR_XDP_WAN_SMBDAT <13,15,16,18,21,35,37>
DIMM2_SA1 201 202
DIMM1 1 0 SA1 SCL DDR_XDP_WAN_SMBCLK <13,15,16,18,21,35,37>
0.1U_0402_16V4Z
2.2U_0402_6.3V6M
1 1 +0.675V_DDR_VTT 203 204 +0.675V_DDR_VTT

1
VTT1 VTT2
@
DIMM3 1 1
CD43
CD44
205 206
G1 G2
2 2 TYCO_2-2013289-1~D
A A
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Title

5 4 3 2 1
5 4 3 2 1

JDIMM3 STD Type H=5.2 CPU JDIMM1

JDIMM3 Top Side
<16,8> DDR_B_DQS#[0..7] PN change to SP07000OF00
1 2 +DIMM3_VREF_DQ
<16,8> DDR_B_DQS[0..7] +SB_DIMM2_VREFDQ
@RD23
@ RD23 0_0402_5% +1.35V_MEM +1.35V_MEM JDIMM2 JDIMM4 Bottom Side
JDIMM3 CONN@
<16,8> DDR_B_D[0..63]
+V_DDR_REF 1 2 1 2
@RD24
@ RD24 0_0402_5% 3 VREF_DQ VSS1 4 DDR_B_D4
<16,8> DDR_B_MA[0..15] VSS2 DQ4
2.2U_0402_6.3V6M
0.1U_0402_16V4Z
D DDR_B_D0 5 6 DDR_B_D5 D
DDR_B_D1 7 DQ0 DQ5 8
DQ1 VSS3
@CD49
@
1 1 9 10 DDR_B_DQS#0
VSS4 DQS#0
CD49
CD45
11 12 DDR_B_DQS0
13 DM0 DQS0 14
DDR_B_D7 15 VSS5 VSS6 16 DDR_B_D2
2 2 DDR_B_D6 17 DQ2 DQ6 18 DDR_B_D3
19 DQ3 DQ7 20
+1.35V_MEM DDR_B_D8 21 VSS7 VSS8 22 DDR_B_D13
DDR_B_D9 23 DQ8 DQ12 24 DDR_B_D12
25 DQ9 DQ13 26
DDR_B_DQS#1 27 VSS9 VSS10 28
DQS#1 DM1
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
DDR_B_DQS1 29 30 DDR3_DRAMRST#_R
DQS1 RESET# DDR3_DRAMRST#_R <13,14,16>
1 1 1 1 31 32
DQ10 DQ14
CD50
CD46
CD47
CD48
DDR_B_D15 35 36 DDR_B_D11
37 DQ11 DQ15 38
2 2 2 2 DDR_B_D21 39 VSS13 VSS14 40 DDR_B_D17
43 DQ17 DQ21 44
DDR_B_DQS#2 45 VSS15 VSS16 46 +1.35V_MEM
DDR_B_DQS2 47 DQS#2 DM2 48
DQS2 VSS17
1
1K_0402_1%
49 50 DDR_B_D19
DDR_B_D23 51 VSS18 DQ22 52 DDR_B_D18
DDR_B_D22 53 DQ18 DQ23 54 +SB_DIMM_VREFDQ_Q
RD50
+1.35V_MEM 55 DQ19 VSS19 56 DDR_B_D25 +SB_DIMM_VREFDQ
DDR_B_D29 57 VSS20 DQ28 58 DDR_B_D24 +SB_DIMM2_VREFDQ
2
DDR_B_D28 59 DQ24 DQ29 60 QD6B
61 DQ25 VSS21 62 DDR_B_DQS#3 DMN66D0LDW-7_SOT363-6
63 VSS22 DQS#3 64 DDR_B_DQS3 4 3 RD48 1 2 2_0402_1%
DM3 DQS3
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
65 66
VSS23 VSS24
330U_SX_2VY
0.022U_0402_16V7K
1 DDR_B_D31 67 68 DDR_B_D27
DQ26 DQ30
@CD57
@
1K_0402_1%
1 1 1 1 1 1 1 @ DDR_B_D30 69 70 DDR_B_D26
5
DQ27 DQ31
1
CD51
CD52
CD53
CD54
CD55
CD56
CD57
CD58
+ 71 72
VSS25 VSS26 1
RD49
DDR_HVREF_RST_PCH
C <13,21,7> DDR_HVREF_RST_PCH C
CD91
2 2 2 2 2 2 2 2
73 74 2
<8> DDR_CKE6_DIMM3 DDR_CKE7_DIMM3 <8>
2
75 CKE0 CKE1 76
77 VDD1 VDD2 78 DDR_B_MA15
DDR_B_BS2 79 NC1 A15 80 DDR_B_MA14
<16,8> DDR_B_BS2 BA2 A14
81 82
VDD3 VDD4
1
24.9_0402_1%
DDR_B_MA12 83 84 DDR_B_MA11
A12/BC# A11
RC111
DDR_B_MA9 85 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA8 89 VDD5 VDD6 90 DDR_B_MA6
Layout Note: DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
2
93 A5 A4 94
Place near JDIMM3.Pin 203,204 DDR_B_MA3 95 VDD7 VDD8 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
105 106
DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 <16,8>
DDR_B_BS0 109 110 DDR_B_RAS#
<16,8> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <16,8>
+0.675V_DDR_VTT 111 112
DDR_B_WE# 113 VDD13 VDD14 114
<16,8> DDR_B_WE# WE# S0# DDR_CS6_DIMM3# <8>
DDR_B_CAS# 115 116 M_ODT6
<16,8> DDR_B_CAS# CAS# ODT0 M_ODT6 <8>
117 118
DDR_B_MA13 119 VDD15 VDD16 120 M_ODT7
A13 ODT1 M_ODT7 <8> +DIMM3_VREF_CA
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
121 122
1 1 1 1 123 124
125 VDD17 VDD18 126 1 2
NCTEST VREF_CA +SM_VREF_DIMM
CD59
CD60
CD61
CD62
127 128 @RD25

@ RD25 0_0402_5%
VSS27 VSS28
2.2U_0402_6.3V6M
0.1U_0402_16V4Z
DDR_B_D32 129 130 DDR_B_D33
2 2 2 2 DDR_B_D36 131 DQ32 DQ36 132 DDR_B_D37
DQ33 DQ37
@CD63
@
133 134 1 1
VSS29 VSS30
CD63
CD64
DDR_B_DQS#4 135 136
B B
139 DQS4 VSS31 140 DDR_B_D35
DDR_B_D39 141 VSS32 DQ38 142 DDR_B_D34 2 2
DDR_B_D38 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_B_D41
DDR_B_D40 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#5
153 VSS36 DQS#5 154 DDR_B_DQS5
155 DM5 DQS5 156
+3.3V_RUN DDR_B_D46 157 VSS37 VSS38 158 DDR_B_D43
DDR_B_D47 159 DQ42 DQ46 160 DDR_B_D42
DIMM Select DDR_B_D48
161
163
DQ43
VSS39
DQ48
DQ47
VSS40
DQ52
162
164 DDR_B_D52
10K_0402_5%
10K_0402_5%
DDR_B_D49 165 166 DDR_B_D53

DQ49 DQ53
2
2
RD27
167 168
VSS41 VSS42
RD26
DDR_B_DQS#6 169 170

173 DQS6 VSS43 174 DDR_B_D51
1
DDR_B_D54 177 DQ50 DQ55 178

DIMM3_SA0 179 DQ51 VSS45 180 DDR_B_D60
SA0 SA1 DIMM3_SA1 DDR_B_D56 183 DQ56 DQ61 184
DIMM2 0 0 187 VSS48 DQS#7 188 DDR_B_DQS7
189 DM7 DQS7 190
DIMM4 0 1 191 VSS49 VSS50 192
+3.3V_RUN
DDR_B_D59
DQ58 DQ62
DDR_B_D63 9/21
DDR_B_D58 193 194 DDR_B_D62
DIMM1 1 0 195 DQ59 DQ63 196
DIMM3_SA0 197 VSS51 VSS52 198
* DIMM3 1 1 199 SA0 EVENT# 200
DIMM3_SA1 201 202
0.1U_0402_16V4Z
2.2U_0402_6.3V6M
+0.675V_DDR_VTT 203 204 +0.675V_DDR_VTT

VTT1 VTT2
A 1 1 A
@ CD66
205 206
G1 G2
CD65
TYCO_2-2013289-1~D
2 2
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Title

5 4 3 2 1
5 4 3 2 1

<15,8> DDR_B_DQS#[0..7]
JDIMM4 REV Type H=5.2 CPU JDIMM1
JDIMM3 Top Side
<15,8> DDR_B_DQS[0..7] PN change to SP07000PF00
1 2 +DIMM4_VREF_DQ JDIMM2 JDIMM4 Bottom Side
<15,8> DDR_B_D[0..63] +SB_DIMM2_VREFDQ +1.35V_MEM +1.35V_MEM
@ RD32 0_0402_5%
JDIMM4 CONN@
<15,8> DDR_B_MA[0..15]
+V_DDR_REF 1 2 1 2
@ RD33 0_0402_5% 3 VREF_DQ VSS1 4 DDR_B_D0
VSS2 DQ4
2.2U_0402_6.3V6M
0.1U_0402_16V4Z
D DDR_B_D4 5 6 DDR_B_D1 D
DDR_B_D5 7 DQ0 DQ5 8
DQ1 VSS3
@
1 1 9 10 DDR_B_DQS#0
VSS4 DQS#0
CD67
CD68
11 12 DDR_B_DQS0
+1.35V_MEM 13 DM0 DQS0 14
2 2 DDR_B_D3 17 DQ2 DQ6 18 DDR_B_D6
19 DQ3 DQ7 20
VSS7 VSS8
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1 DQ9 DQ13
25 26
VSS9 VSS10
CD70
CD71
CD72
CD69
DDR_B_DQS#1 27 28
DDR_B_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#_R
2 2 2 2 DQS1 RESET# DDR3_DRAMRST#_R <13,14,15>
31 32
37 DQ11 DQ15 38
43 DQ17 DQ21 44
DDR_B_DQS#2 45 VSS15 VSS16 46
+1.35V_MEM DDR_B_DQS2 47 DQS#2 DM2 48
49 DQS2 VSS17 50 DDR_B_D23
DDR_B_D18 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_B_D29
VSS20 DQ28
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
DQ24 DQ29
330U_SX_2VY
1 DDR_B_D24 59 60
DQ25 VSS21
@CD79
@
1 1 1 1 1 1 1 61 62 DDR_B_DQS#3
VSS22 DQS#3
CD73
CD74
CD75
CD76
CD77
CD78
CD79
CD80
+ 63 64 DDR_B_DQS3
65 DM3 DQS3 66
2 2 2 2 2 2 2 2 DDR_B_D26 69 DQ26 DQ30 70 DDR_B_D30
71 DQ27 DQ31 72
VSS25 VSS26
C C
73 74
<8> DDR_CKE2_DIMM4 CKE0 CKE1 DDR_CKE3_DIMM4 <8>
75 76
77 VDD1 VDD2 78 DDR_B_MA15
DDR_B_BS2 79 NC1 A15 80 DDR_B_MA14
<15,8> DDR_B_BS2 BA2 A14
81 82
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
Layout Note: 87 A9 A7 88
Place near JDIMM4.Pin 203,204 DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
105 106
+0.675V_DDR_VTT DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 <15,8>
DDR_B_BS0 109 110 DDR_B_RAS#
<15,8> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <15,8>
111 112
DDR_B_WE# 113 VDD13 VDD14 114
<15,8> DDR_B_WE# WE# S0# DDR_CS2_DIMM4# <8>
DDR_B_CAS# 115 116 M_ODT2
<15,8> DDR_B_CAS# CAS# ODT0 M_ODT2 <8>
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
117 118
DDR_B_MA13 119 VDD15 VDD16 120 M_ODT3
1 1 1 1 A13 ODT1 M_ODT3 <8>
121 122 +DIMM4_VREF_CA
CD81
CD82
CD83
CD84
123 124
125 VDD17 VDD18 126 1 2
2 2 2 2 NCTEST VREF_CA +SM_VREF_DIMM
127 128 @ RD34 0_0402_5%
VSS27 VSS28
2.2U_0402_6.3V6M
0.1U_0402_16V4Z
DDR_B_D33 129 130 DDR_B_D32
DDR_B_D37 131 DQ32 DQ36 132 DDR_B_D36
DQ33 DQ37
@
133 134 1 1
VSS29 VSS30
CD85
CD86
DDR_B_DQS#4 135 136
B B
139 DQS4 VSS31 140 DDR_B_D39
DDR_B_D35 141 VSS32 DQ38 142 DDR_B_D38 2 2
DDR_B_D34 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_B_D45
DDR_B_D44 149 DQ40 DQ45 150
153 VSS36 DQS#5 154 DDR_B_DQS5
155 DM5 DQS5 156
+3.3V_RUN DDR_B_D43 157 VSS37 VSS38 158 DDR_B_D46
DDR_B_D42 159 DQ42 DQ46 160 DDR_B_D47
DIMM Select DDR_B_D52
161
163
DQ43
VSS39
DQ48
DQ47
VSS40
DQ52
162
164 DDR_B_D48
2
10K_0402_5%
DDR_B_D53 165 166 DDR_B_D49

167 DQ49 DQ53 168
VSS41 VSS42
RD36
DDR_B_DQS#6 169 170

173 DQS6 VSS43 174 DDR_B_D55
1

DDR_B_D50 177 DQ50 DQ55 178
DIMM4_SA0 179 DQ51 VSS45 180 DDR_B_D57
SA0 SA1 DIMM4_SA1 DDR_B_D61 183 DQ56 DQ61 184
DIMM2 0 0 VSS48 DQS#7
2
10K_0402_5%
187 188 DDR_B_DQS7

189 DM7 DQS7 190
* DIMM4 0 1 191 VSS49 VSS50 192
+3.3V_RUN
DDR_B_D63
DQ58 DQ62
DDR_B_D59 9/21
RD37
DDR_B_D62 193 194 DDR_B_D58

DIMM1 1 0 195 DQ59 DQ63 196
1
DIMM4_SA0 197 VSS51 VSS52 198

DIMM3 1 1 199 SA0 EVENT# 200 DIMM4_SMBDAT
DIMM4_SA1 201 202 DIMM4_SMBCLK
0.1U_0402_16V4Z
2.2U_0402_6.3V6M
+0.675V_DDR_VTT 203 204 +0.675V_DDR_VTT

VTT1 VTT2
A 1 1 A
@
205 206
G1 G2
CD87
CD88
TYCO_2-2013290-1
2 2
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Title
5 4 3 2 1
5 4 3 2 1
+3.3V_MXM
+3.3V_MXM
+3.3V_MXM
4.7K_0402_5%
4.7K_0402_5%
1
1
+3.3V_MXM
10K_0402_5%
@
PEG_CRX_GTX_C_P[0..15]
<6> PEG_CRX_GTX_C_P[0..15]
R1
R2
1 2 MXM_CRT_DDC_DAT
1
PEG_CRX_GTX_C_N[0..15] @ R3 4.3K_0402_5%
<6> PEG_CRX_GTX_C_N[0..15]
2
R4
1 2 MXM_CRT_DDC_CLK
2
PEG_CTX_GRX_P[0..15] @ R5 4.3K_0402_5%
<6> PEG_CTX_GRX_P[0..15] 1 2 DGPU_PWROK GPU_SMBDAT_R 1 6
10/5 <28> GPU_SMBDAT_R GPU_SMBDAT <51>
2
G
PEG_CTX_GRX_N[0..15] R1977 10K_0402_5%
<6> PEG_CTX_GRX_N[0..15]
2
1 2 MXM_CLK_REQ# Q295A
5
R1978 10K_0402_5% MXM_ALERT# 3 1 DGPU_ALERT# <50> DMN66D0LDW-7_SOT363-6
1 2 MXM_RSVD1
D
@ R6 0_0402_5% <28> GPU_SMBCLK_R GPU_SMBCLK_R 4 3
GPU_SMBCLK <51>
1 2 MXM_RSVD2
@ R1979 0_0402_5% Q5 Q295B
D DMN65D8LW-7_SOT323-3 DMN66D0LDW-7_SOT363-6 D
+MXM_PWR_SRC +MXM_PWR_SRC
JMXM1A CONN@ 400mil(10A) JMXM1B CONN@
1 2 163 162
3 PWR_SRC PWR_SRC 4 PEG_CRX_GTX_C_N2 165 GND GND 164 PEG_CTX_GRX_N2
PWR_SRC PWR_SRC PEX_RX2# PEX_TX2#
10U_0805_25V6K
680P_0603_50V7K
68P_0402_50V8J
0.1U_0603_25V7K
5 6 PEG_CRX_GTX_C_P2 167 166 PEG_CTX_GRX_P2
7 PWR_SRC PWR_SRC 8 169 PEX_RX2 PEX_TX2 168
PWR_SRC PWR_SRC 1 1 1 1 GND GND
9 10 PEG_CRX_GTX_C_N1 171 170 PEG_CTX_GRX_N1
PWR_SRC E1 E2 PWR_SRC PEX_RX1# PEX_TX1#
C2
C3
C4
C1
11 12 PEG_CRX_GTX_C_P1 173 172 PEG_CTX_GRX_P1
13 PWR_SRC PWR_SRC 14 175 PEX_RX1 PEX_TX1 174
15 PWR_SRC PWR_SRC 16 2 2 2 2 PEG_CRX_GTX_C_N0 177 GND GND 176 PEG_CTX_GRX_N0
17 PWR_SRC PWR_SRC 18 PEG_CRX_GTX_C_P0 179 PEX_RX0# PEX_TX0# 178 PEG_CTX_GRX_P0
PWR_SRC PWR_SRC 181 PEX_RX0 PEX_TX0 180
+5V_MXM CLK_PCIE_VGA# 183 GND GND 182 MXM_CLK_REQ#
<20> CLK_PCIE_VGA# PEX_REFCLK# PEX_CLK_REQ#
19 20 CLK_PCIE_VGA 185 184 DGPU_PEX_RST#
GND GND <20> CLK_PCIE_VGA PEX_REFCLK PEX_RST#
21 22 187 186 MXM_CRT_DDC_DAT <33>
23 GND GND 24 189 GND VGA_DDC_DAT 188
GND GND RSVD VGA_DDC_CLK MXM_CRT_DDC_CLK <33> CRT
0.1U_0402_16V4Z
10U_0603_6.3V6M
25 26 191 190 MXM_CRT_VSYNC MXM_CRT_VSYNC <33>

27 GND GND 28 193 RSVD VGA_VSYNC 192 MXM_CRT_HSYNC
1 1 GND GND RSVD VGA_HSYNC MXM_CRT_HSYNC <33> OK
C328
29 E3 E4 30 195 194
GND GND RSVD GND
C7
31 32 197 196 MXM_CRT_RED MXM_CRT_RED <33>

+5V_MXM 33 GND GND 34 MXM_LVDS_BCLK- 199 RSVD VGA_RED 198 MXM_CRT_GRN
2 2 GND GND <29> MXM_LVDS_BCLK- LVDS_UCLK# VGA_GREEN MXM_CRT_GRN <33>
35 36 <29> MXM_LVDS_BCLK+ MXM_LVDS_BCLK+ 201 200 MXM_CRT_BLU MXM_CRT_BLU <33>
37 GND GND 38 203 LVDS_UCLK VGA_BLUE 202
5V PRSNT_R# MXM_PRESENTR# <23> GND GND
39 40 @ R1972 1 2 0_0402_5% 205 204 MXM_LVDS_ACLK- MXM_LVDS_ACLK- <29>
5V WAKE# PCIE_WAKE# <44,45,49,51> LVDS_UTX3# LVDS_LCLK#
41 42 DGPU_PWROK 10/5 207 206 MXM_LVDS_ACLK+ MXM_LVDS_ACLK+ <29>
43 5V PWR_GOOD 44 209 LVDS_UTX3 LVDS_LCLK 208
5V PWR_EN DGPU_PWR_EN <19,50> GND GND
45 46 <29> MXM_LVDS_B2- MXM_LVDS_B2- 211 210
47 5V RSVD 48 MXM_LVDS_B2+ 213 LVDS_UTX2# LVDS_LTX3# 212
100mil(2.5A, 5VIA) 49 GND RSVD 50 LVDS <29> MXM_LVDS_B2+
215 LVDS_UTX2 LVDS_LTX3 214
51 GND RSVD 52 MXM_LVDS_B1- 217 GND GND 216 MXM_LVDS_A2- LVDS
53 GND RSVD 54 MXM_PWR_LEVEL (Upper/even) <29> MXM_LVDS_B1-
MXM_LVDS_B1+ 219 LVDS_UTX1# LVDS_LTX2# 218 MXM_LVDS_A2+
MXM_LVDS_A2- <29>
@ R1970 1 2 0_0402_5% 55 GND PWR_LEVEL 56 MXM_OVERT#
<29> MXM_LVDS_B1+
221 LVDS_UTX1 LVDS_LTX2 220
MXM_LVDS_A2+ <29> (Lower/odd)
@ R1971 1 2 0_0402_5% 57 PEX_STD_SW# TH_OVERT# 58 MXM_ALERT# OK MXM_LVDS_B0- 223 GND GND 222 MXM_LVDS_A1-
<30> MXM_ENVDD 59 VGA_DISABLE# TH_ALERT# 60
<29>
<29>
MXM_LVDS_B0-
MXM_LVDS_B0+ MXM_LVDS_B0+ 225 LVDS_UTX0# LVDS_LTX1# 224 MXM_LVDS_A1+
MXM_LVDS_A1-
MXM_LVDS_A1+
<29>
<29>
OK
61 PNL_PWR_EN TH_PWM 62 227 LVDS_UTX0 LVDS_LTX1 226
<30> MXM_PANEL_BKEN PNL_BL_EN GPIO0 GND GND
<30> MXM_BIA_PWM 63 64 <47> MXM_DPC_N0 MXM_DPC_N0 229 228 MXM_LVDS_A0- MXM_LVDS_A0- <29>
65 PNL_BL_PWM GPIO1 66 MXM_DPC_P0 231 DP_C_L0# LVDS_LTX0# 230 MXM_LVDS_A0+
C HDMI_CEC GPIO2 <47> MXM_DPC_P0 DP_C_L0 LVDS_LTX0 MXM_LVDS_A0+ <29> C
67 68 GPU_SMBDAT_R 233 232
69 DVI_HPD SMB_DAT 70 GPU_SMBCLK_R MXM_DPC_N1 235 GND GND 234 MXM_EDP_TX0-
<29> MXM_LVDS_DDC_DAT LVDS_DDC_DAT SMB_CLK <47> MXM_DPC_N1 DP_C_L1# DP_D_L0# MXM_EDP_TX0- <32>
71 72 SYSTEM <47> MXM_DPC_P1 MXM_DPC_P1 237 236 MXM_EDP_TX0+ MXM_EDP_TX0+ <32>
<29> MXM_LVDS_DDC_CLK LVDS_DDC_CLK GND DP_C_L1 DP_D_L0
73 74 239 238
75 GND OEM 76 MXM_DPC_N2 241 GND GND 240 MXM_EDP_TX1-
OEM OEM <47> MXM_DPC_N2 DP_C_L2# DP_D_L1# MXM_EDP_TX1- <32>
77 78 PAD~D @ T175 MXM_DPC_P2 243 242 MXM_EDP_TX1+
T176 @ PAD~D 79 OEM OEM 80 MXM_PIN80 <44>
HDMI/Docking DP <47> MXM_DPC_P2
245 DP_C_L2 DP_D_L1 244
MXM_EDP_TX1+ <32>
81 OEM OEM 82 MXM_DPC_N3 247 GND GND 246 MXM_EDP_TX2-
83 OEM GND 84 PEG_CTX_GRX_N15 MUX <47> MXM_DPC_N3
MXM_DPC_P3 249 DP_C_L3# DP_D_L2# 248 MXM_EDP_TX2+
MXM_EDP_TX2- <32>
PEG_CRX_GTX_C_N15 85 GND PEX_TX15# 86 PEG_CTX_GRX_P15
<47> MXM_DPC_P3
251 DP_C_L3 DP_D_L2 250
MXM_EDP_TX2+ <32> eDP
PEG_CRX_GTX_C_P15 87 PEX_RX15# PEX_TX15 88 OK MXM_DPC_AUX# 253 GND GND 252 MXM_EDP_TX3-
89 PEX_RX15 GND 90 PEG_CTX_GRX_N14
<47>
<47>
MXM_DPC_AUX#
MXM_DPC_AUX MXM_DPC_AUX 255 DP_C_AUX# DP_D_L3# 254 MXM_EDP_TX3+
MXM_EDP_TX3-
MXM_EDP_TX3+
<32>
<32>
OK
PEG_CRX_GTX_C_N14 91 GND PEX_TX14# 92 PEG_CTX_GRX_P14 257 DP_C_AUX DP_D_L3 256
PEG_CRX_GTX_C_P14 93 PEX_RX14# PEX_TX14 94 259 RSVD GND 258 MXM_EDP_AUX-
PEX_RX14 GND RSVD DP_D_AUX# MXM_EDP_AUX- <32>
95 96 PEG_CTX_GRX_N13 261 260 MXM_EDP_AUX+ MXM_EDP_AUX+ <32>
PEG_CRX_GTX_C_N13 97 GND PEX_TX13# 98 PEG_CTX_GRX_P13 263 RSVD DP_D_AUX 262 MXM_DPC_HPD_GATE
PEG_CRX_GTX_C_P13 99 PEX_RX13# PEX_TX13 100 265 RSVD DP_C_HPD 264 MXM_EDP_HPD
PEX_RX13 GND RSVD DP_D_HPD MXM_EDP_HPD <32>
101 102 PEG_CTX_GRX_N12 267 266
PEG_CRX_GTX_C_N12 103 GND PEX_TX12# 104 PEG_CTX_GRX_P12 269 RSVD RSVD 268 MXM_RSVD1
PEG_CRX_GTX_C_P12 105 PEX_RX12# PEX_TX12 106 271 RSVD RSVD 270 MXM_RSVD2
107 PEX_RX12 GND 108 PEG_CTX_GRX_N11 273 RSVD RSVD 272
PEG_CRX_GTX_C_N11 109 GND PEX_TX11# 110 PEG_CTX_GRX_P11 275 RSVD GND 274 MXM_DPB_N0
PEX_RX11# PEX_TX11 RSVD DP_B_L0# MXM_DPB_N0 <48>
PEG_CRX_GTX_C_P11 111 112 277 276 MXM_DPB_P0 MXM_DPB_P0 <48>
113 PEX_RX11 GND 114 PEG_CTX_GRX_N10 279 RSVD DP_B_L0 278
PEG_CRX_GTX_C_N10 115 GND PEX_TX10# 116 PEG_CTX_GRX_P10 281 RSVD GND 280 MXM_DPB_N1
PEX_RX10# PEX_TX10 GND DP_B_L1# MXM_DPB_N1 <48>
PEG_CRX_GTX_C_P10 117 118 <31> MXM_MB_DP_N0 MXM_MB_DP_N0 283 282 MXM_DPB_P1 MXM_DPB_P1 <48>
119 PEX_RX10 GND 120 PEG_CTX_GRX_N9 MXM_MB_DP_P0 285 DP_A_L0# DP_B_L1 284
GND PEX_TX9# <31> MXM_MB_DP_P0 DP_A_L0 GND
PEG_CRX_GTX_C_N9 121 122 PEG_CTX_GRX_P9 287 286 MXM_DPB_N2 MXM_DPB_N2 <48>
PEG_CRX_GTX_C_P9 123 PEX_RX9# PEX_TX9 124 MXM_MB_DP_N1 289 GND DP_B_L2# 288 MXM_DPB_P2
<31>
<31>
MXM_MB_DP_N1
MXM_MB_DP_P1 MXM_MB_DP_P1 291 DP_A_L1# DP_B_L2 290
MXM_DPB_P2 <48> Docking DP port 2
PEG_CRX_GTX_C_N8 127 GND PEX_TX8# 128 PEG_CTX_GRX_P8 293 DP_A_L1 GND 292 MXM_DPB_N3
PEX_RX8# PEX_TX8 GND DP_B_L3# MXM_DPB_N3 <48>
PEG_CRX_GTX_C_P8 129 130 MXM_MB_DP_N2 295 294 MXM_DPB_P3
<31> MXM_MB_DP_N2
MXM_MB_DP_P2 297 DP_A_L2# DP_B_L3 296
MXM_DPB_P3 <48> OK
PEG_CRX_GTX_C_N7 133 GND PEX_TX7# 134 PEG_CTX_GRX_P7 MB DP <31> MXM_MB_DP_P2
299 DP_A_L2 GND 298 MXM_DPB_AUX# MXM_DPB_AUX# <34>
PEG_CRX_GTX_C_P7 135 PEX_RX7# PEX_TX7 136 MXM_MB_DP_N3 301 GND DP_B_AUX# 300 MXM_DPB_AUX
137 PEX_RX7 GND 138 PEG_CTX_GRX_N6 OK <31>
<31>
MXM_MB_DP_N3
MXM_MB_DP_P3 MXM_MB_DP_P3 303 DP_A_L3# DP_B_AUX 302 MXM_DPB_HPD_GATE
MXM_DPB_AUX <34>
PEG_CRX_GTX_C_N6 139 GND PEX_TX6# 140 PEG_CTX_GRX_P6 305 DP_A_L3 DP_B_HPD 304 MXM_MB_DP_HPD_GATE
PEG_CRX_GTX_C_P6 141 PEX_RX6# PEX_TX6 142 MXM_MB_DP_AUX# 307 GND DP_A_HPD 306
PEX_RX6 GND <31> MXM_MB_DP_AUX# DP_A_AUX# 3V3 +3.3V_MXM
143 144 PEG_CTX_GRX_N5 <31> MXM_MB_DP_AUX MXM_MB_DP_AUX 309 308
PEG_CRX_GTX_C_N5 145 GND PEX_TX5# 146 PEG_CTX_GRX_P5 MXM_PRESENTL# 310 DP_A_AUX 3V3
PEG_CRX_GTX_C_P5 147 PEX_RX5# PEX_TX5 148
<23> MXM_PRESENTL# PRSNT_L# 40mil(1A)
149 PEX_RX5 GND 150 PEG_CTX_GRX_N4 311 312 +3.3V_MXM
PEG_CRX_GTX_C_N4 151 GND PEX_TX4# 152 PEG_CTX_GRX_P4 GND GND
PEG_CRX_GTX_C_P4 153 PEX_RX4# PEX_TX4 154 JAE_MM70-314-310B1-1-R300
B B
GND PEX_TX3# LInk CIS
10U_0603_6.3V6M
0.1U_0402_16V4Z
PEG_CRX_GTX_C_N3 157 158 PEG_CTX_GRX_P3
PEG_CRX_GTX_C_P3 159 PEX_RX3# PEX_TX3 160
PEX_RX3 GND 1 1
161
GND
C332
C8
JAE_MM70-314-310B1-1-R300 2 2
LInk CIS
PCB Footprint: JAE_MM70-314-310B1-1-R3_310P-S
+3.3V_MXM
+3.3V_MXM +3.3V_MXM
+3.3V_MXM +3.3V_ALW @ C96 @ C95 @ C94
1 2 1 2 1 2
750_0402_1%
@ C90 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K

1
5
1 2
R38
1 DGPU_PWROK 1 DGPU_PWROK 1 DGPU_PWROK

P
P
0.1U_0402_10V7K MXM_DPB_HPD_GATE 4 IN1 MXM_DPC_HPD_GATE 4 IN1 MXM_MB_DP_HPD_GATE 4 IN1
O 2 O 2 O 2
IN2 MXM_DPB_HPD <48> IN2 MXM_DPC_HPD <47> IN2 MXM_MB_DP_HPD <31>
G
G
100K_0402_5%
100K_0402_5%
100K_0402_5%
2
1
@ R758
@ R519
U14 U25 U27

3
3
@ R60
1 DGPU_HOLD_RST# <19> SN74AHC1G08DCKR_SC70-5 SN74AHC1G08DCKR_SC70-5 SN74AHC1G08DCKR_SC70-5
P
DGPU_PEX_RST# 4 B
O 2
A PLTRST_GPU# <19>
G
Meet high level for DGPU_PEX_RST#

2
2
1
100K_0402_5%
U16 10/15
3
74AHC1G09GW_TSSOP5~D
on N14P
R51
2
1 2 +3.3V_MXM +3.3V_ALW
@ R19 0_0402_5% +3.3V_ALW
DGPU_PEX_RST#
+3.3V_MXM
@ C92
1
100K_0402_5%
10K_0402_5%
1 2 <23,50> DGPU_PWROK
1
10K_0402_5%
1
100K_0402_5%
0.1U_0402_10V7K
1
R37
R10
R11
D7
MXM_DPC_HPD 2 1
MXM_DP_HDMI_HPD <50>
2
R135
2
2
A A
G
RB751VM-40TE-17_SOD323-2 1 ACAV_IN <27,51,61,62>
P
2
MXM_PWR_LEVEL 4 B
2
D8 O 2 MXM_OVERT# 3 1
A GPU_PWR_LEVEL <50> DGPU_THERMTRIP# <51>
G
MXM_MB_DP_HPD 2 1
D
@ D19 U17
3
RB751VM-40TE-17_SOD323-2 1 2 74AHC1G09GW_TSSOP5~D
<28,50> DYN_TURB_GPU_PWR_ALRT# Q4
D18 RB751VM-40TE-17_SOD323-2 DMN65D8LW-7_SOT323-3
MXM_DPB_HPD 2 1
RB751VM-40TE-17_SOD323-2
www.Vinafix.vn
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
MXM
LA-9781P
5 4 3 2 1
5 4 3 2 1
+RTC_CELL
PCH XDP
USB_OC0#_R PXDP@ RH3 1 2 0_0402_5% XDP_FN0 +3.3V_ALW_PCH JXDP2
<22> USB_OC0#_R
330K_0402_1%
USB_OC1#_R PXDP@ RH4 1 2 0_0402_5% XDP_FN1 1 2
<22> USB_OC1#_R GND0 GND1
1
USB_OC2# PXDP@ RH6 1 2 0_0402_5% XDP_FN2 +3.3V_ALW_PCH 3 4 XDP_FN16
<22> USB_OC2# OBSFN_A0 OBSFN_C0
RH5
USB_OC3# PXDP@ RH7 1 2 0_0402_5% XDP_FN3 5 6 XDP_FN17
<22> USB_OC3# OBSFN_A1 OBSFN_C1
0.1U_0402_25V6K
USB_OC4#_R PXDP@ RH8 1 2 0_0402_5% XDP_FN4 7 8
<22> USB_OC4#_R USB_OC5# PXDP@ RH9 1 2 0_0402_5% XDP_FN5 XDP_FN0 9 GND2 GND3 10 XDP_FN8
<22> USB_OC5# 1 OBSDATA_A0 OBSDATA_C0
PXDP@
USB_OC6# PXDP@ RH17 1 2 0_0402_5% XDP_FN6 XDP_FN1 11 12 XDP_FN9
2
<22> USB_OC6# OBSDATA_A1 OBSDATA_C1
CH2
SIO_EXT_SMI# PXDP@ RH10 1 2 0_0402_5% XDP_FN7 13 14
<22,51> SIO_EXT_SMI# HDD1_DET# PXDP@ RH11 1 2 0_0402_5% XDP_FN8 XDP_FN2 15 GND4 GND5 16 XDP_FN10
D PCH_INTVRMEN <18,37> HDD1_DET# BBS_BIT0_R PXDP@ RH13 1 2 0_0402_5% XDP_FN9 2 XDP_FN3 17 OBSDATA_A2 OBSDATA_C2 18 XDP_FN11 D
PCH_GPIO36 PXDP@ RH12 1 2 0_0402_5% XDP_FN10 19 OBSDATA_A3 OBSDATA_C3 20
<23> PCH_GPIO36 GND6 GND7
330K_0402_1%
PCH_GPIO37 PXDP@ RH14 1 2 0_0402_5% XDP_FN11 21 22
<23> PCH_GPIO37 OBSFN_B0 OBSFN_D0
1
mCARD_PCIE_SATA# PXDP@ RH16 1 2 0_0402_5% XDP_FN12 23 24

<23,50> mCARD_PCIE_SATA# OBSFN_B1 OBSFN_D1
@ RH18
HDD2_DET# PXDP@ RH19 1 2 0_0402_5% XDP_FN13 25 26

<23,37> HDD2_DET# 1 2 27 GND8 GND9 28
LANCLK_REQ# PXDP@ RH20 0_0402_5% XDP_FN14 XDP_FN4 XDP_FN12
<20,39> LANCLK_REQ# 1 2 29 OBSDATA_B0 OBSDATA_D0 30
CARDCLK_REQ# PXDP@ RH22 0_0402_5% XDP_FN15 XDP_FN5 XDP_FN13
<20,49> CARDCLK_REQ# SIO_EXT_WAKE# PXDP@ RH24 1 2 0_0402_5% XDP_FN16 31 OBSDATA_B1 OBSDATA_D1 32
2
<23,50> SIO_EXT_WAKE# PCH_GPIO35 PXDP@ RH25 1 2 0_0402_5% XDP_FN17 XDP_FN6 33 GND10 GND11 34 XDP_FN14
<23> PCH_GPIO35 PCH_RSMRST#_Q PXDP@ RH26 1 2 1K_0402_1% RSMRST#_XDP XDP_FN7 35 OBSDATA_B2 OBSDATA_D2 36 XDP_FN15
<19,53> PCH_RSMRST#_Q 1 2 37 OBSDATA_B3 OBSDATA_D3 38
RESET_OUT# PXDP@ RH27 1K_0402_1% RESET_OUT#_R
<10,19,51> RESET_OUT# 39 GND12 GND13 40
RSMRST#_XDP +1.05V_RUN
1 2 PCH_PWRBTN#_XDP 41 PWRGOOD/HOOK0 ITPCLK/HOOK4 42
INTVRMEN - INTEGRATED SUS 1.05V VRM <19,7> SIO_PWRBTN#_R
PXDP@ RH28 0_0402_5% 43 HOOK1 ITPCLK#/HOOK5 44
VCC_OBS_AB VCC_OBS_CD +3.3V_ALW_PCH
ENABLE 45 46 RESET_OUT#_R
47 HOOK2 RESET#/HOOK6 48 XDP_DBRESET#
High - Enable Internal VRs PXDP@ RH30 0_0402_5% 49 HOOK3 DBR#/HOOK7 50 XDP_DBRESET# <19,7>
Low - Enable External VRs 1 2 DDR_XDP_WAN_SMBDAT_R2 51 GND14 GND15 52 PCH_JTAG_TDO
<13,14,15,16,21,35,37> DDR_XDP_WAN_SMBDAT 1 2 53 SDA TD0 54 1 2
DDR_XDP_WAN_SMBCLK_R2 PCH_JTAG_RST_R PCH_JTAG_RST
<13,14,15,16,21,35,37> DDR_XDP_WAN_SMBCLK 55 SCL TRST# 56
PXDP@ RH31 0_0402_5% PCH_JTAG_TDI @ RH32 0_0402_5%
PCH_JTAG_TCK 57 TCK1 TDI 58 PCH_JTAG_TMS
+3.3V_RUN +3.3V_ALW_PCH 59 TCK0 TMS 60
GND16 GND17
SAMTE_BSH-030-01-L-D-A CONN@
1 2 SPKR 1 2 PCH_AZ_SDOUT
@ RH34 10K_0402_5% @ RH35 1K_0402_1%
+3.3V_RUN
NO REBOOT STRAP FLASH DESCRIPTOR SECURITY OVERRIDE HDD1_DET# 1 2
DISABLED WHEN LOW (DEFAULT) LOW = DESABLED (DEFAULT) 10K_0402_5% RH36
BBS_BIT0_R 1 2
ENABLED WHEN HIGH HIGH = ENABLED CH4 10K_0402_5% RH37
1 2 PCH_RTCX1_R 1 2 PCH_RTCX1
RH38 0_0402_5%
C C
18P_0402_50V8J Change PN from SA00005NE2L to SA00006P30L
1
+3.3V_ALW_PCH
LPT_PCH_M_EDS
YH1 RH39 UH1A
+3.3V_RUN 32.768KHZ_12.5PF_Q13FC1350000 10M_0402_5%
1 2 PCH_AZ_SYNC BC8
PSATA_PRX_DTX_N0_C <37>
2
1 2 PCH_GPIO33 @ RH41 1K_0402_1% B5 SATA_RXN_0 BE8
PSATA_PRX_DTX_P0_C <37>
2
RH40 10K_0402_5% CH5 RTCX1 SATA_RXP_0
1 2 PCH_GPIO13 1 2 PCH_RTCX2 B4 AW8 HDD1
RH60 10K_0402_5% RTCX2 SATA_TXN_0 AY8 PSATA_PTX_DRX_N0_C <37>
RTC
RH42 1 2 20K_0402_5% 18P_0402_50V8J SRTCRST# B9 SATA_TXP_0 PSATA_PTX_DRX_P0_C <37>
+RTC_CELL SRTCRST# BC10
SATA_RXN_1 SATA_ODD_PRX_DTX_N1_C <38>
RH43 1 2 1M_0402_5% INTRUDER# A8 BE10
INTRUDER# SATA_RXP_1 SATA_ODD_PRX_DTX_P1_C <38>
PCH_INTVRMEN G10 AV10 ODD
INTVRMEN SATA_TXN_1 AW10 SATA_ODD_PTX_DRX_N1_C <38>
RH44 1 2 20K_0402_5% PCH_RTCRST# D9 SATA_TXP_1 SATA_ODD_PTX_DRX_P1_C <38>
RTCRST# BB9
SATA_RXN_2 BD9 SATA_PRX_DKTX_N2_C <48>
<43> PCH_RTCRST# SATA_RXP_2 SATA_PRX_DKTX_P2_C <48>
CMOS_CLR1 CMOS setting PCH_AZ_BITCLK B25
HDA_BCLK AY13 DOCK
1 2 1 2 PCH_AZ_SYNC A22 SATA_TXN_2 AW13 SATA_PTX_DKRX_N2_C <48>
Shunt Clear CMOS 1 2 1 2 HDA_SYNC SATA_TXP_2 SATA_PTX_DKRX_P2_C <48>
SPKR AL10 BC12
Open Keep CMOS <49> SPKR SPKR SATA_RXN_3 BE12 ESATA_PRX_DTX_N3_C <41>
C24 SATA_RXP_3 ESATA_PRX_DTX_P3_C <41>
@ @ PCH_AZ_RST#
ME_CLR1 TPM setting ME1 SHORT PADS~D CMOS1 SHORT PADS~D HDA_RST# AR13 E-SATA
1 2 1 2 L22 SATA_TXN_3 AT13 ESATA_PTX_DRX_N3_C <41>
AZALIA
PCH_AZ_CODEC_SDIN0
SATA
1U_0402_6.3V6K <49> PCH_AZ_CODEC_SDIN0 HDA_SDI0 SATA_TXP_3 ESATA_PTX_DRX_P3_C <41>
Shunt Clear ME RTC Registers CH6 1U_0402_6.3V6K CH7
K22
CMOS place near DIMM HDA_SDI1 BD13
Open Keep ME RTC Registers G22 SATA_RXN4/PERN1 BB13 mSATA_PRX_DTX_N4_C <45>
HDA_SDI2 SATA_RXP4/PERP1 mSATA_PRX_DTX_P4_C <45>
F22 AV15 mSATA
HDA_SDI3 SATA_TXN4/PETN1 AW15 mSATA_PTX_DRX_N4_C <45>
1 2 PCH_AZ_SDOUT A24 SATA_TXP4/PETP1 mSATA_PTX_DRX_P4_C <45>
B <50> ME_FWP B
RH45 1K_0402_1% HDA_SDO BC14
B17 SATA_RXN5/PERN2 BE14 SATA_PRX_DTX_N5_C <37>
PCH_GPIO33
DOCKEN#/GPIO33 SATA_RXP5/PERP2 SATA_PRX_DTX_P5_C <37>
+3.3V_ALW_PCH PCH_GPIO13 C22 AP15 HDD2
HDA_DOCK_RST#/GPIO13 SATA_TXN5/PETN2 AR15 SATA_PTX_DRX_N5_C <37>
SATA_TXP5/PETP2 SATA_PTX_DRX_P5_C <37>
1
0_0603_5%
RH46
AY5 SATA_COMP
SATA_RCOMP
AP3 SATA_ACT#
SATALED# SATA_ACT# <52>
2
RH47 2 1 51_0402_1% PCH_JTAG_TCK AB3 AT1 HDD1_DET#

JTAG_TCK SATA0GP/GPIO21 HDD1_DET# <18,37>
+3.3V_ALW_PCH_JTAG RH48 1 2 210_0402_1% PCH_JTAG_TMS AD1 AU2 BBS_BIT0_R 1 3
S
JTAG_TMS SATA1GP/GPIO19 PCH_SATA_MOD_EN# <51>
RH50 1 2 210_0402_1% PCH_JTAG_TDI AE2 BD4 SATA_IREF 2 1 QH5
JTAG
JTAG_TDI SATA_IREF +1.5V_RUN
0_0402_5% @ RH51 BSS138_NL_SOT23-3
G
2
RH52 1 2 210_0402_1% PCH_JTAG_TDO AD3 BA2
JTAG_TDO TP9 PCH_PLTRST# <19,7>
PAD~D T57 @
1 2 PCH_TP25 F8 BB2
TP25 TP8
100_0402_1%
100_0402_1%
100_0402_1%
RH53 @ 0_0402_5% PAD~D T58 @

1
C26
TP22
RH54
RH55
RH56
@ T59 PAD~D
PCH_JTAG_RST AB6
TP20
SATA Impedance Compensation
2
1 OF 11
HDA for Codec SATA_COMP 1 2

+1.5V_RUN
7.5K_0402_1% RH57
1 2 PCH_AZ_SDOUT
<49> PCH_AZ_CODEC_SDOUT
RH59 33_0402_5% CAD note:
1 2 PCH_AZ_SYNC
A <49> PCH_AZ_CODEC_SYNC
RH61 33_0402_5%
Place the resistor within 500 mils of the PCH. Avoid A
1 2 PCH_AZ_RST# routing next to clock pins.
<49> PCH_AZ_CODEC_RST#
RH63 33_0402_5%
1 2 PCH_AZ_BITCLK
<49> PCH_AZ_CODEC_BITCLK
EMC@ RH65 33_0402_5%
27P_0402_50V8J
@ CH9
PROPRIETARY NOTE:
2 Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT PCH (1/9)
0.2
5 4 3 2 1
www.Vinafix.vn
5 4 3 2 1
+3.3V_RUN
RH66 1 2 0_0402_5%
+3.3V_RUN +RTC_CELL RPH1

+PCH_VCCDSW3_3 @ CH10 PCI_PIRQB# 1 8
330K_0402_1%
1 2 PCI_PIRQD# 2 7
2
1 2 SIO_SLP_LAN# PCI_PIRQA# 3 6
RH67
@ RH80 10K_0402_5% 0.1U_0402_25V6K PCI_PIRQC# 4 5
1 2 PCH_PCIE_WAKE# 1
P
<18,7> XDP_DBRESET# B
RH78 10K_0402_5% 4 SYS_RESET# 8.2K_8P4R_5%
2 1 ME_RESET# 2 O SYS_RESET# <43> DGPU_HOLD_RST# 2 1
1
A
G
@ RH70 8.2K_0402_5% @ UC3 +3.3V_ALW2 8.2K_0402_5% RH148
+3.3V_ALW_PCH CIS LINK OK 74AHC1G09GW_TSSOP5~D @ CH11 LCD_CBL_DET# 2 1
3
1 2 PCH_GPIO55 10K_0402_5% RH77
CIS LINK OK DSWODVREN
5
D UH2 0.1U_0402_25V6K D
1
330K_0402_1%
1K_0402_1%
1 2 PCH_PCIE_WAKE# PCH_GPIO3 2 1
VCC
@ RH81
@ RH76
@ RH88 10K_0402_5% SIO_SLP_A# 1 10K_0402_5% RH83
IN B
2
1 2 SUS_STAT#/LPCPD# PCH_DPWROK 1 2 PCH_RSMRST#_R 4PM_APWROK_R CAM_MIC_CBL_DET# 2 1
@ RH73 10K_0402_5% @ RH79 0_0402_5% PM_APWROK 2 OUT Y 10K_0402_5% RH86
GND
<51> PM_APWROK IN A
1 2 ME_SUS_PWR_ACK
2
RH75 10K_0402_5%
@@
1 2 PCH_RI# NL17SZ08DFT2G_SC70-5 PCH_CRT_DDC_CLK R97 1 2 2.2K_0402_5%
1
RH84 10K_0402_5% RESET_OUT# 1 2 SYS_PWROK PCH_CRT_DDC_DAT R1251 2 2.2K_0402_5%
@ RH85 0_0402_5% PCH_DDPD_CTRLCLK R1261 2 2.2K_0402_5%
1 2 PCH_DDPD_CTRLDATA R1281 2 2.2K_0402_5%
+3.3V_RUN @ RH87 0_0402_5%
1 2 CLKRUN# ME_SUS_PWR_ACK_R 1 2 SUSACK#_R DSWODVREN - ON DIE DSW VR ENABLE A16 SWAP OVERRIDE STRAP
RH90 8.2K_0402_5% @ RH91 0_0402_5%
1 2 ME_RESET#
@ RH93 8.2K_0402_5%
HIGH = ENABLED (DEFAULT)
LOW = DISABLED STP_A16OVR LOW = A16 SWAP OVERRIDE
HIGH = DEFAULT
LPT_PCH_M_EDS
UH1B
DMI_CTX_PRX_N0 AW22
<6> DMI_CTX_PRX_N0 AR20 DMI_RXN_0
DMI_CTX_PRX_N1
<6> DMI_CTX_PRX_N1 DMI_RXN_1 AJ35 FDI_CTX_PRX_N0
FDI_RXN_0 FDI_CTX_PRX_N0 <9>
DMI_CTX_PRX_N2 AP17
<6> DMI_CTX_PRX_N2 DMI_RXN_2
DMI_CTX_PRX_N3 AV20 AL35 FDI_CTX_PRX_N1
<6> DMI_CTX_PRX_N3 DMI_RXN_3 FDI_RXN_1 FDI_CTX_PRX_N1 <9>
DMI_CTX_PRX_P0 AY22 AJ36 FDI_CTX_PRX_P0 UH1E LPT_PCH_M_EDS
<6> DMI_CTX_PRX_P0 DMI_RXP_0 FDI_RXP_0 FDI_CTX_PRX_P0 <9>
DMI_CTX_PRX_P1 AP20
<6> DMI_CTX_PRX_P1 DMI_RXP_1 AL36 FDI_CTX_PRX_P1 PCH_CRT_BLU T45 R40
FDI_RXP_1 FDI_CTX_PRX_P1 <9> <33> PCH_CRT_BLU VGA_BLUE DDPB_CTRLCLK
DMI_CTX_PRX_P2 AR17
<6> DMI_CTX_PRX_P2 DMI_RXP_2
DMI_CTX_PRX_P3 AW20 AV43 PAD~D T132 @ PCH_CRT_GRN U44 R39
C <6> DMI_CTX_PRX_P3 DMI_RXP_3 TP16 <33> PCH_CRT_GRN VGA_GREEN DDPB_CTRLDATA C
DMI_CRX_PTX_N0 BD21 AY45 PAD~D T133 @ PCH_CRT_RED V45 R35

<6> DMI_CRX_PTX_N0 DMI_TXN_0 TP5 <33> PCH_CRT_RED VGA_RED DDPC_CTRLCLK
DMI_CRX_PTX_N1 BE20
<6> DMI_CRX_PTX_N1 DMI_TXN_1 DMI FDI AV45 PAD~D T130 @ PCH_CRT_DDC_CLK M43 R36
TP15 <33> PCH_CRT_DDC_CLK VGA_DDC_CLK DDPC_CTRLDATA
DMI_CRX_PTX_N2 BD17
<6> DMI_CRX_PTX_N2 DMI_TXN_2
DMI_CRX_PTX_N3 BE18 AW44 PAD~D T131 @ PCH_CRT_DDC_DAT M45 N40 PCH_DDPD_CTRLCLK
CRT
<6> DMI_CRX_PTX_N3 DMI_TXN_3 TP10 <33> PCH_CRT_DDC_DAT VGA_DDC_DATA DDPD_CTRLCLK PCH_DDPD_CTRLCLK <47>
DMI_CRX_PTX_P0 BB21 AL39 FDI_CSYNC 1 2 HSYNC N42 N38 PCH_DDPD_CTRLDATA
<6> DMI_CRX_PTX_P0 DMI_TXP_0 FDI_CSYNC FDI_CSYNC <6> <33> PCH_CRT_HSYNC VGA_HSYNC DDPD_CTRLDATA PCH_DDPD_CTRLDATA <47>
DMI_CRX_PTX_P1 BC20 RH94 20_0402_1%
<6> DMI_CRX_PTX_P1 DMI_TXP_1 AL40 FDI_INT 1 2 VSYNC N44
FDI_INT FDI_INT <6> <33> PCH_CRT_VSYNC VGA_VSYNC
DMI_CRX_PTX_P2 BB17 RH95 20_0402_1% H45
<6> DMI_CRX_PTX_P2 BC18 DMI_TXP_2 AT45 2 1 1 2 CRT_IREF U40 DDPB_AUXN
DMI_CRX_PTX_P3 FDI_IREF
DISPLAY
<6> DMI_CRX_PTX_P3 DMI_TXP_3 FDI_IREF +1.5V_RUN DAC_IREF
@ RH96 0_0402_5% RH97 649_0402_1% K43
2 1 DMI_IREF BE16 AU42 PAD~D T134 @ U39 DDPC_AUXN
+1.5V_RUN DMI_IREF TP17 VGA_IRTN
@ RH98 0_0402_5% J42 PCH_DDPD_AUX#
DDPD_AUXN PCH_DDPD_AUX# <47>
AW17 AU44 PAD~D T66 @
@ T65 PAD~D TP12 TP13 BIA_PWM_PCH N36 H43
<35> BIA_PWM_PCH EDP_BKLTCTL DDPB_AUXP
AV17 AR44 FDI_RCOMP 2 1
LVDS
TP7 FDI_RCOMP +1.5V_RUN
@ T67 PAD~D 7.5K_0402_1% RH99 PANEL_BKEN_PCH K36 K45
<30> PANEL_BKEN_PCH EDP_BKLTEN DDPC_AUXP
+1.5V_RUN 1 2 DMI_RCOMP AY17
RH100 7.5K_0402_1% DMI_RCOMP ENVDD_PCH G36 J44 PCH_DDPD_AUX
<30,50> ENVDD_PCH EDP_VDDEN DDPD_AUXP PCH_DDPD_AUX <47>
K40
1 2 SUSACK#_R R6 C8 DSWODVREN PCI_PIRQA# H20 DDPB_HPD
<50> SUSACK# SUSACK# DSWVRMEN PIRQA#
RH101 0_0402_5% K38
SYS_RESET# AM1 L13 PCH_DPWROK PCI_PIRQB# L20 DDPC_HPD
SYS_RESET# DPWROK PCH_DPWROK <50> PIRQB# H39 DPD_PCH_HPD
DDPD_HPD DPD_PCH_HPD <47>
1 2 SYS_PWROK_R AD7 K3 PCH_PCIE_WAKE# PCI_PIRQC# K17
<50,7> SYS_PWROK SYS_PWROK WAKE# PCH_PCIE_WAKE# <51> PIRQC#
RH102 0_0402_5%
1 2 PCH_PWROK F10 AN7 CLKRUN# PCI_PIRQD# M20
<10,18,51> RESET_OUT# PWROK CLKRUN# CLKRUN# <43,50,51> PIRQD#
RH103 0_0402_5% System Power G17 LCD_CBL_DET#
AB7 Management U7 A12 PIRQE#/GPIO2 LCD_CBL_DET# <30>
PM_APWROK_R SUS_STAT#/LPCPD# DGPU_HOLD_RST#
APWROK SUS_STAT#/GPIO61 SUS_STAT#/LPCPD# <43> <17> DGPU_HOLD_RST# GPIO50 F17 PCH_GPIO3
1 2 PM_DRAM_PWRGD_R H3 Y6 SUSCLK T68 PAD~D@ CPPE# B13 PCI PIRQF#/GPIO3
<7> PM_DRAM_PWRGD DRAMPWROK SUSCLK/GPIO62 <44> CPPE# GPIO52
B RH104 0_0402_5% T146 PAD~D@ L15 CAM_MIC_CBL_DET# B
PIRQG#/GPIO4 CAM_MIC_CBL_DET# <30>
1
PCH_RSMRST#_Q 2 PCH_RSMRST#_R J2 Y7 SIO_SLP_S5# DGPU_PWR_EN# C12
<18,53> PCH_RSMRST#_Q RSMRST# SLP_S5#/GPIO63 SIO_SLP_S5# <43,51> GPIO54
RH105 0_0402_5% M15 FFS_PCH_INT 2 1
T118 PAD~D @ PIRQH#/GPIO5 HDD_FALL_INT <37>
1 2 ME_SUS_PWR_ACK_R J4 C6 SIO_SLP_S4# BBS_BIT1 C10 @ RH106 0_0402_5%
<51> ME_SUS_PWR_ACK SUSWARN#/SUSPWRNACK/GPIO30 SLP_S4# SIO_SLP_S4# <43,50,54,57> GPIO51
RH258 0_0402_5% AD10 @ T141 PAD~D
<18,7> SIO_PWRBTN#_R PME#
1 2 SIO_PWRBTN#_R K1 H1 SIO_SLP_S3# USB_MCARD1_DET# A10
<51> SIO_PWRBTN# PWRBTN# SLP_S3# SIO_SLP_S3# <43,49,50,54,59> <44> USB_MCARD1_DET# GPIO53
@ RH259 0_0402_5% Y11 PCH_PLTRST# 0_0402_5% 2 1 RH109
PLTRST# PLTRST_USH# <43>
AC_PRESENT E6 F3 SIO_SLP_A# PCH_GPIO55 AL6 0_0402_5% 2 1 RH110
<51> AC_PRESENT ACPRESENT/GPIO31 SLP_A# SIO_SLP_A# <43,50,54,58> GPIO55 PLTRST_MMI# <49>
0_0402_5% 2 1 RH111
T145 PAD~D @ PLTRST_LAN# <39>
+PCH_VCCDSW3_3
1 2 PCH_BATLOW# K7 F1 SIO_SLP_SUS# 5 OF 11
RH112 8.2K_0402_5% BATLOW#/GPIO72 SLP_SUS# SIO_SLP_SUS# <50> 0_0402_5% 2 1 RH114
T129 PAD~D @ PLTRST_GPU# <17>
PCH_RI# N4 AY3 H_PM_SYNC
RI# PMSYNCH H_PM_SYNC <7>
@ T144 PAD~D AB10 G5 SIO_SLP_LAN# +3.3V_RUN
TP21 SLP_LAN# SIO_SLP_LAN# <39,50> CH12
SIO_SLP_WLAN# D2 1 2
<46> SIO_SLP_WLAN# SLP_WLAN#/GPIO29
4 OF 11 0.1U_0402_25V6K
9/25
1 2 PCH_CRT_BLU
5
RH115 150_0402_1%
1 2PCH_RSMRST#_Q 1 2 PCH_CRT_GRN PCH_PLTRST# 1
P
<18,7> PCH_PLTRST# B 4
RH89 10K_0402_5% RH116 150_0402_1% PCH_PLTRST#_EC
O PCH_PLTRST#_EC <43,44,45,49,50,51>
1 2 PCH_CRT_RED 2
Boot BIOS Strap A
G
+3.3V_MXM RH117 150_0402_1% UH3
10/8 P5 only. 1 2 ENVDD_PCH TC7SH08FU_SSOP5~D
3
100K_0402_5%
SATA_SLPD RH118 100K_0402_5%

1
+3.3V_RUN @
BBS_BIT1 (BBS_BIT0) Boot BIOS Location
RH113
BBS_BIT1
1K_0402_1%
8.2K_0402_5%
0 0 LPC
1
@ RH328
2
@ RH119
0 1 Reserved (NAND) DGPU_PWR_EN

A DGPU_PWR_EN <17,50> A
2
100K_0402_5%
1 0 PCI
1
D
RH132
DGPU_PWR_EN# 2
@ QC5
* 1 1 SPI G
S
3
GPIO51 has internal pull up.

2
10/5 for EC inital value.

PROPRIETARY NOTE:
Title
0.2
5 4 3 2 1
www.Vinafix.vn
5 4 3 2 1
+3.3V_ALW_PCH
2
10K_0402_5%
RH128
D D
1
GFX_CLK_REQ#
L2N7002WT1G_SC-70-3
1
D
QH3
2
LPT_PCH_M_EDS <50,54> 3.3V_RUN_GFX_ON
UH1C G
S
3
@ RH307 2 1 0_0402_5% PCIE_MINI1# Y43 AB35 CLK_PCIE_VGA#
<44> CLK_PCIE_MINI1# CLKOUT_PCIE_N_0 CLKOUT_PEG_A CLK_PCIE_VGA# <17>
WWAN (Mini Card 1)---> @ RH308 2 1 0_0402_5% PCIE_MINI1 Y45 AB36 CLK_PCIE_VGA
<44> CLK_PCIE_MINI1 RH123 2 1 10K_0402_5% CLKOUT_PCIE_P_0 CLKOUT_PEG_A_P CLK_PCIE_VGA <17>
+3.3V_ALW_PCH
MINI1CLK_REQ# AB1 AF6 GFX_CLK_REQ#
<44> MINI1CLK_REQ# PCIECLKRQ0#/GPIO73 PEGA_CLKRQ#/GPIO47
@ RH82 2 1 0_0402_5% PCIE_LAN# AA44 Y39
<39> CLK_PCIE_LAN# @ RH92 2 1 0_0402_5% PCIE_LAN AA42 CLKOUT_PCIE_N_1 CLKOUT_PEG_B if can place closed or not suggest use 8P4R
<39> CLK_PCIE_LAN 2 1 10K_0402_5% CLKOUT_PCIE_P_1 Y38
10/100/1G LAN ---> +3.3V_RUN RH145
CLKOUT_PEG_B_P
RPH3
LANCLK_REQ# AF1 CLK_BUF_DMI 1 8
<18,39> LANCLK_REQ# PCIECLKRQ1#/GPIO18 U4 PEG_B_CLKRQ# 2 1 CLK_BUF_DMI# 2 7
PEGB_CLKRQ#/GPIO56 +3.3V_ALW_PCH
@ RH121 2 1 0_0402_5% PCIE_CARD# AB43 10K_0402_5% RH130 CLK_BUF_BCLK 3 6
<49> CLK_PCIE_CARD# CLKOUT_PCIE_N_2 AF39 CLK_CPU_DMI# CLK_BUF_BCLK# 4 5
@ RH122 2 1 0_0402_5% PCIE_CARD AB45 CLKOUT_DMI CLK_CPU_DMI# <7>
MMI ---> <49> CLK_PCIE_CARD CLKOUT_PCIE_P_2
+3.3V_RUN RH120 1 2 10K_0402_5% AF40 CLK_CPU_DMI 10K_8P4R_5%
CARDCLK_REQ# AF3 CLKOUT_DMI_P CLK_CPU_DMI <7>
<18,49> CARDCLK_REQ# PCIECLKRQ2#/GPIO20/SMI# AJ40 CLK_CPU_SSC_DPLL#
@ RH133 2 1 0_0402_5% PCIE_MINI3# AD43 CLKOUT_DP AJ39 CLK_CPU_SSC_DPLL CLK_CPU_SSC_DPLL# <7> CLK_BUF_DOT96# RH1501 2 10K_0402_5%
<45> CLK_PCIE_MINI3# CLKOUT_PCIE_N_3 CLKOUT_DP_P CLK_CPU_SSC_DPLL <7>
PP (Mini Card 3)---> @ RH135 2 1 0_0402_5% PCIE_MINI3 AD45 CLK_BUF_DOT96 RH1511 2 10K_0402_5%
C <45> CLK_PCIE_MINI3 CLKOUT_PCIE_P_3 C
+3.3V_ALW_PCH RH254 2 1 10K_0402_5% MINI3CLK_REQ# T3 AF35 CLK_CPU_DPLL# CLK_BUF_CKSSCD# RH1671 2 10K_0402_5%
PCIECLKRQ3#/GPIO25 CLKOUT_DPNS AF36 CLK_CPU_DPLL CLK_CPU_DPLL# <7> CLK_BUF_CKSSCD RH1691 2 10K_0402_5%
<45> MINI3CLK_REQ# CLKOUT_DPNS_P CLK_CPU_DPLL <7>
@ RH137 2 1 0_0402_5% PCIE_EXP# AF43
<49> CLK_PCIE_EXP# CLKOUT_PCIE_N_4
@ RH139 2 1 0_0402_5% PCIE_EXP AF45 AY24 CLK_BUF_DMI#
<49> CLK_PCIE_EXP CLKOUT_PCIE_P_4 CLKIN_DMI
Express card---> +3.3V_ALW_PCH RH125 2 1 10K_0402_5% EXPCLK_REQ# V3 AW24 CLK_BUF_DMI
PCIECLKRQ4#/GPIO26 CLOCK SIGNAL CLKIN_DMI_P CLK_PCH_14M RH1461 2 10K_0402_5%
<49> EXPCLK_REQ# AE44 AR24 CLK_BUF_BCLK#
AE42 CLKOUT_PCIE_N5 CLKIN_GND AT24 CLK_BUF_BCLK
RH147 2 1 10K_0402_5% AA2 CLKOUT_PCIE_P_5 CLKIN_GND_P
+3.3V_ALW_PCH PCIECLKRQ5#/GPIO44 H33 CLK_BUF_DOT96#
@ RH127 2 1 0_0402_5% PCIE_MINI2# AB40 CLKIN_DOT96N G33 CLK_BUF_DOT96
WLAN (Mini Card 2)--->
<44> CLK_PCIE_MINI2#
@ RH126 2 1 0_0402_5% PCIE_MINI2 AB39 CLKOUT_PCIE_N_6 CLKIN_DOT96P CLOCK TERMINATION for FCIM and need close to PCH
<44> CLK_PCIE_MINI2 CLKOUT_PCIE_P_6
+3.3V_ALW_PCH RH124 2 1 10K_0402_5% MINI2CLK_REQ# AE4 BE6 CLK_BUF_CKSSCD#
PCIECLKRQ6#/GPIO45 CLKIN_SATA BC6 CLK_BUF_CKSSCD
<44> MINI2CLK_REQ# CLKIN_SATA_P
@ RH144 2 1 0_0402_5% PCIE_NVR# AJ44
<45> CLK_PCIE_NVR# CLKOUT_PCIE_N_7 F45 CLK_PCH_14M
@ RH142 2 1 0_0402_5% PCIE_NVR AJ42 REFCLK14IN D17 CLK_PCI_LOOPBACK
NVRAM (Mini Card 4)---> <45> CLK_PCIE_NVR CLKOUT_PCIE_P_7 CLKIN_33MHZLOOPBACK
RH140 2 1 10K_0402_5% EMBCLK_REQ# Y3 AM43 XTAL25_IN 2 1
+3.3V_ALW_PCH PCIECLKRQ7#/GPIO46 XTAL25_IN AL44 XTAL25_OUT RH152 1 2 0_0402_5%
<45> EMBCLK_REQ# XTAL25_OUT
@ RH154 2 1 0_0402_5% CLK_BCLK_ITP# AH43 EMC@ 9/21 RH153 1M_0402_5%
XTAL25_IN_R
<7> CLK_CPU_ITP# CLKOUT_ITPXDP C40 PCI_TPM_TCM RH155 2 1 22_0402_5%
CLKOUTFLEX0/GPIO64 CLK_PCI_TPM <43>
@ RH156 2 1 0_0402_5% CLK_BCLK_ITP AH45
<7> CLK_CPU_ITP CLKOUT_ITPXDP_P F38 2 1 22_0402_5%
SIO_14MEMC@
EMC@RH157
RH157
2 1 22_0402_5% PCI_5048 D44 CLKOUTFLEX1/GPIO65 CLK_SIO_14M <50>
EMC@RH158
EMC@ RH158
<50> CLK_PCI_5048 CLKOUT_33MHZ0 F36 CLK_80HEMC@ 2 1 22_0402_5%
EMC@RH159
RH159 YH2
2 1 22_0402_5% E44 CLKOUTFLEX2/GPIO66 PCLK_80H <45>
EMC@RH160
EMC@ RH160 PCI_MEC 25MHZ_10PF_Q22FA2380049900
<51> CLK_PCI_MEC CLKOUT_33MHZ1 F39 2 1 22_0402_5% 3 1
JETWAY_14M@
@RH161
RH161
2 1 22_0402_5% PCI_DOCK B42 CLKOUTFLEX3/GPIO67 JETWAY_CLK14M <43> OUT IN
EMC@RH162
EMC@ RH162
<48> CLK_PCI_DOCK CLKOUT_33MHZ2
12P_0402_50V8J
12P_0402_50V8J
AM45 ICLK_IREF 0_0402_5% 1 2 @ RH163 4 2
ICLK_IREF +1.5V_RUN GND GND
F41 2 2
CLKOUT_33MHZ3
CH14
AD39
CH13
B CLK_PCI_LOOPBACK EMC@
EMC@RH164
RH164 2 1 22_0402_5% PCI_LOOPBACKOUT A40 TP19 AD38 PAD~D T148 @ B
CLKOUT_33MHZ4 TP18 PAD~D T147 @
AN44 PCH_CLK_BIASREF 1 2 1 1
DIFFCLK_BIASREF +1.5V_RUN
7.5K_0402_1% RH165
2 OF 11
PCIECLK REQ Pull UP Power Rail: CLK_PCI_5048 CLK_PCI_MEC CLK_PCI_DOCK CLK_PCI_LOOPBACK PCI_TPM_TCM CLK_SIO_14M JETWAY_CLK14M
SUS Rail : 0 3 4 5 6 7
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
1 1 1 1 1 1 1
@
@
Core Rail: 1 2
@ CH16
@ CH77
CH15
CH76
CH78
CH79
CH80
2 2 2 2 2 2 2
A A
PROPRIETARY NOTE:
Title
PCH (3/9)
www.Vinafix.vn
0.2
5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
2
MEM_SMBCLK 6 1
DDR_XDP_WAN_SMBCLK <13,14,15,16,18,35,37>
QH4A
5
DMN66D0LDW-7_SOT363-6
D +3.3V_ALW_PCH D
MEM_SMBDATA 3 4
DDR_XDP_WAN_SMBDAT <13,14,15,16,18,35,37> PCH_SMB_ALERT# 2 1
QH4B 10K_0402_5% RH166
+3.3V_RUN DMN66D0LDW-7_SOT363-6 DDR_HVREF_RST_PCH 2 1
1K_0402_1% RH170
1 2 IRQ_SERIRQ TEMP_ALERT# 2 1
RH168 10K_0402_5% 10K_0402_5% RH171
RPH5
LPT_PCH_M_EDS
UH1D SML1_SMBCLK 1 8
SML1_SMBDATA 2 7
MEM_SMBCLK 3 6
MEM_SMBDATA 4 5
N7 PCH_SMB_ALERT#
LPC_LAD0 A20 SMBALERT#/GPIO11
<43,45,50,51> LPC_LAD0 LAD_0 R10 MEM_SMBCLK
SMBus
SMBCLK 2.2K_0804_8P4R_5%
LPC_LAD1 C20
<43,45,50,51> LPC_LAD1 LAD_1 U11 MEM_SMBDATA
LPC_LAD2 A18 SMBDATA
LPC
<43,45,50,51> LPC_LAD2 LAD_2 N8 +3.3V_LAN
DDR_HVREF_RST_PCH
LPC_LAD3 C18 SML0ALERT#/GPIO60 DDR_HVREF_RST_PCH <13,15,7>
<43,45,50,51> LPC_LAD3 LAD_3 U8 LAN_SMBCLK LAN_SMBCLK 2 1
LPC_LFRAME# B21 SML0CLK LAN_SMBCLK <39> 2.2K_0402_5% RH174
<43,45,50,51> LPC_LFRAME# LFRAME# R7 LAN_SMBDATA LAN_SMBDATA 2 1
9/26 SML0DATA LAN_SMBDATA <39>
D21 2.2K_0402_5% RH175
LDRQ0# H6 TEMP_ALERT#
LPC_LDRQ1# G20 SML1ALERT#/PCHHOT#/GPIO74 TEMP_ALERT# <50>
<50> LPC_LDRQ1# LDRQ1#/GPIO23 K6 SML1_SMBCLK
AL11 SML1CLK/GPIO58 SML1_SMBCLK <51>
IRQ_SERIRQ
<43,50,51> IRQ_SERIRQ SERIRQ N11 SML1_SMBDATA
SML1DATA/GPIO75 SML1_SMBDATA <51>
C C
AF11 PCH_CL_CLK1
PCH_SPI_CLK AJ11 CL_CLK PCH_CL_CLK1 <44>
SPI_CLK AF10 PCH_CL_DATA1
PCH_SPI_CS0# AJ7 C-Link CL_DATA PCH_CL_DATA1 <44>
SPI_CS0# AF7 PCH_CL_RST1#
PCH_SPI_CS1# AL7 CL_RST# PCH_CL_RST1# <44>
SPI_CS1#
AJ10
SPI_CS2#
SPI
BA45 PAD~D T149 @
PCH_SPI_DO AH1 TP1
SPI_MOSI BC45 PAD~D T150 @
PCH_SPI_DIN AH3 Thermal TP2 SPI_CLK32 SPI_CLK64
SPI_MISO BE43 PAD~D T120 @
TP4
1
PCH_SPI_DO2 AJ4
SPI_IO2 BE44 PAD~D T121 @ @ @
PCH_SPI_DO3 AJ2 TP3 RE2 RE1
SPI_IO3 AY43 PCH_TD_IREF 1 2 33_0402_5% 33_0402_5%
TD_IREF RH176 8.2K_0402_1%
2
1 1
3 OF 11 @ @
CE2 CE1
27P_0402_50V8J 27P_0402_50V8J
+3.3V_SPI 2 2
1 2 SPI_PCH_DO2_64 +3.3V_SPI
R3664 1K_0402_5%
1 2 SPI_PCH_DO3_64 C746
R3668 1K_0402_5% 200 MIL SO8 1 2
B 64Mb Flash ROM 0.1U_0402_25V6K B
JSPI1
U52 2 1 SPI_PCH_CS1# 1
SPI_PCH_CS0# R7 1 2 47_0402_5% SPI_PCH_CS0#_R 1 8 0_0402_5% RH177 PCH_SPI_CS1# 2 1
SPI_PCH_DIN R8 1 2 33_0402_5% SPI_DIN64 2 /CS VCC 7 SPI_PCH_DO3_64 R3669 1 2 33_0402_5% SPI_PCH_DO3 2 1 SPI_PCH_DO 3 2
SPI_PCH_DO2 R9 1 2 33_0402_5% SPI_PCH_DO2_64 3 DO(IO1) /HOLD(IO3) 6 SPI_CLK64 EMC@ R899 1
EMC@R899 2 33_0402_5% SPI_PCH_CLK 0_0402_5% RH178 PCH_SPI_DO 4 3
4 /WP(IO2) CLK 5 SPI_DO64 R901 1 2 33_0402_5% SPI_PCH_DO 2 1 SPI_PCH_DIN 5 4
SPI_WP#_SEL 2 1 GND DI(IO0) 0_0402_5% RH179 PCH_SPI_DIN 6 5
<50> SPI_WP#_SEL 2 1 7 6
@ RH180 0_0402_5% W25Q64FVSSIQ_SO8 SPI_PCH_CLK
0_0402_5% RH181 PCH_SPI_CLK 8 7
2 1 SPI_PCH_CS0# 9 8
CIS LINK OK 9
0_0402_5% RH182 PCH_SPI_CS0# 10
U52 change PN to SA000039A30 IC FL 64M W25Q64FVSSIQ SOIC 8P SPI ROM 2 1 SPI_PCH_DO2 11 10
+3.3V_SPI 0_0402_5% RH183 PCH_SPI_DO2 12 11
2 1 SPI_PCH_DO3 13 12
0_0402_5% RH184 PCH_SPI_DO3 14 13
1 2 SPI_PCH_DO2_32 15 14
+3.3V_SPI 15
R3665 1K_0402_5% 16
+3.3V_M 16
1 2 SPI_PCH_DO3_32 +3.3V_SPI 17
R3666 1K_0402_5% 2 1 18 17
C1216 RH185 0_0402_5% 19 18
200 MIL SO8 1 2 20 19
20
32Mb Flash ROM 0.1U_0402_25V6K 21
U53 22 GND1
SPI_PCH_CS1# R936 1 2 47_0402_5% SPI_PCH_CS1#_R 1 8 GND2
SPI_PCH_DIN R895 1 2 33_0402_5% SPI_DIN32 2 /CS VCC 7 SPI_PCH_DO3_32 R3670 1 2 33_0402_5% SPI_PCH_DO3 TYCO_2-2041070-0
SPI_PCH_DO2 R3667 1 2 33_0402_5% SPI_PCH_DO2_32 3 DO/IO1 /HOLD/IO3 6 SPI_CLK32 EMC@ R897 1
EMC@R897 2 33_0402_5% SPI_PCH_CLK CONN@
4 /WP/IO2 CLK 5 SPI_DO32 R900 1 2 33_0402_5% SPI_PCH_DO
SPI_WP#_SEL 2 1 GND DI/IO0
@RH186
@ RH186 0_0402_5% W25Q32FVSSIQ_SO8
A A
CIS LINK OK
U53 change PN to SA00003K820 IC FL 32M W25Q32FVSSIQ SOIC 8P SPI ROM
PROPRIETARY NOTE:
Title
PCH (4/9)
www.Vinafix.vn
0.2
5 4 3 2 1
5 4 3 2 1
D D
UH1I LPT_PCH_M_EDS
USB3RN3 AW31 B37 USBP0-

<48> USB3RN3 PERN1/USB3RN3 USB2N0 USBP0- <42>
<48> USB3RP3
USB3RP3 AY31
PERP1/USB3RP3 USB2P0
D37 USBP0+
USBP0+ <42>
----->Right Side Top
A38 USBP1-
Dock -----> USB3TN3 BE32 USB2N1 C38 USBP1+
USBP1- <42>
----->Right Side Bottom
<48> USB3TN3 USB3TP3 BC32 PETN1/USB3TN3 USB2P1 A36 USBP2- USBP1+ <42>
<48> USB3TP3 PETP1/USB3TP3 USB2N2 USBP2- <49>
USB2P2
C36 USBP2+
USBP2+ <49>
----->Left Side TOP
PCIE_PRX_GLANTX_N2 AT31 A34 USBP3-
<39> PCIE_PRX_GLANTX_N2 PERN2/USB3RN4 USB2N3 USBP3- <48>
<39> PCIE_PRX_GLANTX_P2
PCIE_PRX_GLANTX_P2 AR31
PERP2/USB3RP4 USB2P3
C34 USBP3+
USBP3+ <48>
----->MLK DOCK
10/100/1G LAN ---> B33 USBP4-
PCIE_PTX_GLANRX_N2 BD33 USB2N4 D33 USBP4+ USBP4- <44> ----->WLAN/WIMAX
<39> PCIE_PTX_GLANRX_N2 PCIE_PTX_GLANRX_P2 BB33 PETN2/USB3TN4 USB2P4 F31 USBP5- USBP4+ <44>
<39> PCIE_PTX_GLANRX_P2 PETP2/USB3TP4 USB2N5 G31 USBP5+ USBP5- <44> ----->WWAN/UWB
USB2P5 K31 USBP6- USBP5+ <44>
PCIE_PRX_WLANTX_N3 AW33 USB2N6 L31 USBP6+ USBP6- <48> ----->DOCK
<44> PCIE_PRX_WLANTX_N3 PERN_3 USB2P6 USBP6+ <48>
PCIE_PRX_WLANTX_P3 AY33 G29 USBP7-
WLAN (Mini Card 2) --->
<44> PCIE_PRX_WLANTX_P3 PERP_3 USB2N7 H29 USBP7+ USBP7- <43> ----->USH
PCIE_PTX_WLANRX_N3 BE34 USB2P7 A32 USBP8- USBP7+ <43>
<44> PCIE_PTX_WLANRX_N3 PCIE_PTX_WLANRX_P3 BC34 PETN_3 USB2N8 C32 USBP8+
USBP8- <41> ----->TOP side E-SATA
<44> PCIE_PTX_WLANRX_P3 PETP_3 USB2P8 A30 USBP9- USBP8+ <41>
AT33 USB2N9 C30 USBP9+ USBP9- <49> ----->Left Side Bottom USBRBIAS
C AR33 PERN_4 USB2P9 B29 USBP10- USBP9+ <49> C
PERP_4 USB2N10 USBP10- <49>
----->Express Card
22.6_0402_1%
D29 USBP10+
USB2P10 USBP10+ <49>
1
BE36 A28 USBP11-
PETN_4 USB2N11 USBP11- <53>
----->BT
RH187
BC36 C28 USBP11+
PETP_4 USB2P11 G26 USBP12- USBP11+ <53>
USB2N12 USBP12- <30>
----->Camera
PCIe
PCIE_PRX_WANTX_N5 AW36 F26 USBP12+
USB
<44> PCIE_PRX_WANTX_N5 AV36 PERN_5 USB2P12 F24 USBP12+ <30>
PCIE_PRX_WANTX_P5 USBP13-
<44> PCIE_PRX_WANTX_P5 USBP13- <30>
2
PERP_5 USB2N13 G24 USBP13+ ----->LCD Touch
WWAN (Mini Card 1) ---> USB2P13 USBP13+ <30>
PCIE_PTX_WANRX_N5 BD37
<44> PCIE_PTX_WANRX_N5 PCIE_PTX_WANRX_P5 BB37 PETN_5
<44> PCIE_PTX_WANRX_P5 PETP_5 AR26 USB3RN1
AY38 USB3RN1 AP26 USB3RN1 <42>
PCIE_PRX_WPANTX_N6 USB3RP1 CAD NOTE:
<45> PCIE_PRX_WPANTX_N6 PERN_6 USB3RP1 USB3RP1 <42>
<45> PCIE_PRX_WPANTX_P6
PCIE_PRX_WPANTX_P6 AW38
PERP_6 USB3TN1
BE24 USB3TN1
USB3TN1 <42>
----->Right Side Top Route single-end 50-ohms and max 500-mils length.
BD23 USB3TP1
PCIE_PTX_WPANRX_N6 BC38 USB3TP1 AW26 USB3RN2 USB3TP1 <42> Avoid routing next to clock pins or under stitching capacitors.
PP (Mini Card 3)---> <45> PCIE_PTX_WPANRX_N6 PETN_6 USB3RN2 USB3RN2 <42>
PCIE_PTX_WPANRX_P6 BE38 AV26 USB3RP2 Recommended minimum spacing to other signal traces is 15 mils.
<45> PCIE_PTX_WPANRX_P6 PETP_6 USB3RP2 BD25 USB3RP2 <42>
USB3TN2
PCIE_PRX_EXPTX_N7 AT40 USB3TN2 BC24 USB3TP2
USB3TN2 <42> ----->Right Side Bottom
<49> PCIE_PRX_EXPTX_N7 AT39 PERN_7 USB3TP2 AW29 USB3TP2 <42>
PCIE_PRX_EXPTX_P7 USB3RN5
<49> PCIE_PRX_EXPTX_P7 PERP_7 USB3RN5 AV29 USB3RP5 USB3RN5 <49>
EXPRESS Card---> USB3RP5 USB3RP5 <49>
PCIE_PTX_EXPRX_N7 BE40 BE26 USB3TN5
<49> PCIE_PTX_EXPRX_N7 PCIE_PTX_EXPRX_P7 BC40 PETN_7 USB3TN5 BC26 USB3TP5
USB3TN5 <49> ----->Left Side Bottom
<49> PCIE_PTX_EXPRX_P7 PETP_7 USB3TP5 AR29 USB3RN6 USB3TP5 <49>
AN38 USB3RN6 AP29 USB3RN6 <49>
PCIE_PRX_MMITX_N8 USB3RP6
<49> PCIE_PRX_MMITX_N8 PCIE_PRX_MMITX_P8 AN39 PERN_8 USB3RP6 BD27 USB3TN6 USB3RP6 <49>
<49> PCIE_PRX_MMITX_P8 PERP_8 USB3TN6 BE28 USB3TP6 USB3TN6 <49> ----->Left Side TOP
BD42 USB3TP6 USB3TP6 <49>
MMI ---> PCIE_PTX_MMIRX_N8
<49> PCIE_PTX_MMIRX_N8 PCIE_PTX_MMIRX_P8 BD41 PETN_8 K24 USBRBIAS
<49> PCIE_PTX_MMIRX_P8 PETP_8 USBRBIAS# K26
USBRBIAS
1 2 PCH_PCIE_IREF BE30 M33 PAD~D T122 @
+1.5V_RUN PCIE_IREF TP24
@ RH188 0_0402_5% L33 PAD~D T123 @
B TP23 +3.3V_ALW_PCH B
@ T124 PAD~D BC30 P3 USB_OC0#_R @ RH189 1 2 0_0402_5%
TP11 OC0#/GPIO59 V1 USB_OC1#_R 1 2 0_0402_5% USB_OC0# <42>
@ RH190 RPH6 PN change to SD30910020L
OC1#/GPIO40 U2 USB_OC2# USB_OC1# <49> USB_OC1#_R 1 8
BB29 OC2#/GPIO41 P1 USB_OC3# USB_OC2# <18> 2 7
@ T125 PAD~D USB_OC2#
TP6 OC3#/GPIO42 M3 USB_OC4#_R 1 2 0_0402_5% USB_OC3# <18> USB_OC5# 3 6
@ RH191
OC4#/GPIO43 T1 USB_OC5# USB_OC4# <41,49> USB_OC0#_R 4 5
1 2 PCH_PCIE_RCOMP BD29 OC5#/GPIO9 N2 USB_OC6# USB_OC5# <18>
+1.5V_RUN PCIE_RCOMP OC6#/GPIO10 USB_OC6# <18>
RH192 7.5K_0402_1% M1 SIO_EXT_SMI# 10K_8P4R_5%
OC7#/GPIO14 SIO_EXT_SMI# <18,51>
9 OF 11 RPH7 PN change to SD30910020L
USB_OC0#_R <18> 1 8
USB_OC3#
USB_OC1#_R <18> USB_OC6# 2 7
USB_OC4#_R <18> SIO_EXT_SMI# 3 6
USB_OC4#_R 4 5
10K_8P4R_5%
A A
PROPRIETARY NOTE:
Title
PCH (5/9)
www.Vinafix.vn
0.2
5 4 3 2 1
5 4 3 2 1
+PCH_VCCDSW3_3 Support Deep S3 mode
2 1 EC_WAKE#
RH216 10K_0402_5%
2 1 PM_LANPHY_ENABLE
RH217 10K_0402_5%
+3.3V_RUN UH1F LPT_PCH_M_EDS
2 1 PCH_GPIO35 1 2 AT8
<51> SIO_EXT_SCI# BMBUSY#/GPIO0
RH208 10K_0402_5% @RH195
@ RH195 0_0402_5%
2 1 PCH_TPM_EN USH_DET# F13
<43> USH_DET# TACH1/GPIO1
@RH214
@ RH214 10K_0402_5%
2 1 SIO_A20GATE PCH_GPIO06 A14
RH215 10K_0402_5% TACH2/GPIO6
D D
1 2 G15 CPU/Misc
TPM_ID1 MXM_PRESENTL#
<17> MXM_PRESENTL# TACH3/GPIO7
RH200 20K_0402_5%
SIO_EXT_WAKE# Y1
<18,50> SIO_EXT_WAKE# GPIO8
RPH8
1 8 PCH_GPIO06 PM_LANPHY_ENABLE K13
<39> PM_LANPHY_ENABLE LAN_PHY_PWR_CTRL/GPIO12
2 7 CONTACTLESS_DET# AN10 SIO_A20GATE
TP14 SIO_A20GATE <51>
3 6 MXM_PRESENTL# PCH_GPIO15 AB11
4 5 PCH_GPIO69 GPIO15 AY1 PAD~D T126 @
10/9 PECI
mCARD_PCIE_SATA# AN2
<18,50> mCARD_PCIE_SATA# SATA4GP/GPIO16
10K_8P4R_5% AT6 SIO_RCIN#
GPIO RCIN# SIO_RCIN# <51>
RPH9 C14
<17,50> DGPU_PWROK TACH0/GPIO17
1 8 AV3 H_CPUPWRGD +1.05V_RUN
PROCPWRGD H_CPUPWRGD <7>
2 7 MXM_PRESENTR# PCH_TPM_EN BB4
<43> PCH_TPM_EN SCLOCK/GPIO22
3 6 USH_DET# AV1 PCH_THRMTRIP#_R 2 1
4 5 PCH_GPIO71 PCH_GPIO24 Y10 THRMTRIP# RH206 56_0402_5%
GPIO24
0.1U_0402_25V6K
AU4 CPU_PLTRST#
PLTRST_PROC# CPU_PLTRST# <7>
10K_8P4R_5% R11 1
<51> EC_WAKE# GPIO27
RPH10 N10
VSS
CH17
1 8 TPM_ID0 SLP_ME_CSW_DEV# AD11 @?? check with E5
<50> SLP_ME_CSW_DEV# GPIO28
2 7 SIO_RCIN#
3 6 SIO_EXT_SCI# PCH_GPIO34 AN6 2
4 5 PCH_GPIO34 GPIO34
PCH_GPIO35 AP1
<18> PCH_GPIO35 GPIO35/NMI#
10K_8P4R_5%
PCH_GPIO36 AT3
+3.3V_ALW_PCH <18> PCH_GPIO36 SATA2GP/GPIO36
PCH_GPIO37 AK1
<18> PCH_GPIO37 SATA3GP/GPIO37
2 1 SIO_EXT_WAKE#
RH210 10K_0402_5% TPM_ID0 AT7
2 1 PCH_GPIO15 SLOAD/GPIO38
RH211 10K_0402_5% TPM_ID1 AM3 A2
2 1 KB_DET# SDATAOUT0/GPIO39 VSS A41
RH212 10K_0402_5% FFS_INT2 AN4 VSS A43
<37> FFS_INT2 SDATAOUT1/GPIO48 VSS
2 1 PCH_GPIO24 A44
C
RH213 10K_0402_5% HDD2_DET# AK3 VSS B1 C
<18,37> HDD2_DET# SATA5GP/GPIO49 VSS B2
KB_DET# U12 VSS B44
<53> KB_DET# GPIO57 VSS
2 1 PCH_TPM_EN B45
RH218 100K_0402_5% CONTACTLESS_DET# C16 VSS BA1
<43> CONTACTLESS_DET# TACH4/GPIO68 VSS BC1
PCH_GPIO69 D13 VSS BD1
TACH5/GPIO69 VSS BD2
MXM_PRESENTR# G13 VSS BD44
<17> MXM_PRESENTR# TACH6/GPIO70 VSS BD45
PCH_GPIO71 H15 VSS BE2
+3.3V_ALW_PCH TACH7/GPIO71 VSS BE3
VSS D1
BE41 VSS E1
VSS VSS
2
NCTF
4.7K_0402_5%
1 2 TP_VSS_NCTF BE5 E45

@RH219
@ RH219 0_0402_5% C45 VSS VSS A4
VSS VSS
RH222
A5
VSS
6 OF 11
1
SLP_ME_CSW_DEV#
1
@RH223
10K_0402_5% +3.3V_RUN Confirm with DELL
1 2 mCARD_PCIE_SATA#
2
RH224 10K_0402_5%
2 1 HDD2_DET#
RH225 10K_0402_5%
2 1 mCARD_PCIE_SATA#
PLL ON DIE VR ENABLE @RH226
@ RH226 10K_0402_5%
B
ENABLED - HIGH(DEFAULT) 2 1 HDD2_DET# B
@RH227
@ RH227 10K_0402_5%
DISABLED - LOW
+3.3V_RUN
2 1 PCH_GPIO36
@RH228
@ RH228 1K_0402_1%
2 1 PCH_GPIO37
RH229 1K_0402_1%
2 1 PCH_GPIO36
RH230 10K_0402_5%
2 1 PCH_GPIO37
@RH231
@ RH231 10K_0402_5%
Note: GPIO strap option is only GPIO16 GPIO49 00b or 01b: Assign muxed signal to desired port
available for SATA/PCIE muxed 10b: Reserved
signals to support 0: PCIE1 0: PCIE2
11b: Assign desired port based on GPIO
mSATA/mini PCIE port switching
1: SATA4 1: SATA5 SATA2GP/GPIO36 , SATA3GP/GPIO37 SAMPLED AT RISING EDGE OF PWROK.
WEAK INTERNAL PULL-DOWN.(WEAK INTERNAL PULL-DOWN IS DISABLED AFTER
PLRST_N DE-ASSERTS).
Muxed Muxed NOTE: THIS SIGNAL SHOLD NOT BE PULLED HIGH WHEN STRAP IS SAMPLED.
Fixed Signals Signals Fixed Signals Signals Fixed Signals
USB3 USB3 USB3 USB3 PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE SATA SATA SATA SATA SATA SATA
1 2 5 6 1 2 3 4 5 6 7 8 4 5 0 1 2 3
A (00) (00) (00) (00) A
USB3 USB3 PCIE PCIE

3 4 1 2
(01) (01) (01) (01) DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: Compal Electronics, Inc.
www.Vinafix.vn
Title
0.2
5 4 3 2 1
5 4 3 2 1
LH1
+VCCADAC 2 1
+1.5V_RUN
BLM18PG181SN1_0603
0.01U_0402_16V7K
0.1U_0402_10V7K
10U_0603_6.3V6M
D D
1 1 1
CH18
CH19
CH20
2 2 2
PCH Power Rail Table

UH1G LPT_PCH_M_EDS
+1.05V_RUN P45 Voltage Rail Voltage S0 Iccmax Current (A)

VCCADAC1_5 +1.5V_RUN
AA24 P43
VCC CRT DAC VSS
330U_SX_2VY
1 AA26 VCC 1.05V 1.29 A
VCC
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
1 1 1 1 @ AD20 M31
VCC VCCADACBG3_3 +3.3V_RUN +1.05V_RUN
CH60
+ AD22
VCC
CH21
CH22
CH23
CH24
AD24 1 VCCIO 1.05V 3.629 A
VCC
1U_0402_6.3V6K
@ CH26
AD26 BB44
2 2 2 2 2 AD28 VCC VCCVRM
VCC FDI 1
AE18 AN34 VCCADAC1_5 1.5V 0.070 A
VCC VCCIO +3.3V_RUN 2
CH25
AE20
AE22 VCC AN35
AE24 VCC VCCIO 2
VCC VCCADAC3_3 3.3V 0.0133 A
AE26 R30
VCC HVCMOS VCC3_3_R30
0.1U_0402_10V7K
AG18 R32
AG20 VCC VCC3_3_R32
VCC 1 VCCCLK 1.05V 0.306 A
AG22 Y12 +PCH_USB_DCPSUS1 +3.3V_ALW_PCH
VCC DCPSUS1
CH27
AG24
Y26 VCC AJ30
VCC VCCSUS3_3 2
VCCCLK3_3 3.3V 0.055 A
Core
AJ32
VCCSUS3_3
+1.05V_M AJ26 +PCH_USB_DCPSUS3 +1.5V_RUN VCCVRM 1.5V 0.179 A
C +PCH_VCCDSW U14 USB3 DCPSUS3 AJ28 C
AA18 DCPSUSBYP DCPSUS3 AK20
VCCASW VCCIO +1.05V_RUN
U18 AK26 VCC3_3 3.3V 0.133 A
VCCASW VCCVRM +1.5V_RUN
22U_0805_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
U20 AK28 1
VCCASW VCCVRM
@ CH31
1 1 1 U22
U24 VCCASW BE22
VCCASW VCCVRM VCCASW 1.05V 0.67 A
CH28
CH29
CH30
V18 PCIe/DMI
VCCASW +1.5V_RUN 2
10U_0603_6.3V6M
V20 AK18 1
2 2 2 VCCASW VCCIO +1.05V_RUN
@ CH32
V22 VCCSUSHDA 3.3V 0.01 A
V24 VCCASW AN11
VCCASW VCCVRM
10U_0603_6.3V6M
Y18
Y20 VCCASW SATA AK22 2
VCCASW VCCIO 1 VCCSPI 3.3V 0.022 A
@ CH33
Y22 +1.05V_RUN
VCCASW AM18
VCCIO AM20
VCCIO 2
VCCSUS3_3 3.3V 0.261 A
AM22
VCCMPHY VCCIO AP22
VCCIO
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
10U_0603_6.3V6M
AR22 1 1 1 1 1 VCCDSW3_3 3.3V 0.015 A
VCCIO AT22
VCCIO
CH34
CH35
CH36
CH37
CH38
7 OF 11 V_PROC_IO 1.05V 0.004 A
2 2 2 2 2
1 2 +PCH_VCCDSW
RH232 5.11_0402_1% +1.05V_M
+PCH_VCCDSW_R
+PCH_USB_DCPSUS1 2 1
0_0402_5% RH234 @
1U_0402_6.3V6K
B B
@CH39
@
1U_0402_6.3V6K
CH39
2
1
CH40
+1.05V_M
2
+PCH_USB_DCPSUS3 1 2
0_0603_5% RH236 @
10U_0603_6.3V6M
1U_0402_6.3V6K
1 1
@ CH41
@ CH42
2 2
A A
PROPRIETARY NOTE:
Title
PCH (7/9)
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0.2
5 4 3 2 1
5 4 3 2 1
Support DEEP SX: populated RH238/RH246, de-populated RH237/RH240
+3.3V_ALW_PCH
+PCH_VCCDSW3_3
0.1U_0402_10V7K
2 1 +3.3V_ALW_PCH
LPT_PCH_M_EDS
UH1H 0_0603_5% @ RH237
0.1U_0402_10V7K
1 2 1 +3.3V_ALW
+3.3V_ALW_PCH
CH43
0_0603_5% RH238
1
CH44
R24 R20
R26 VCCSUS3_3 VCCSUS3_3 R22 2
D D
VCCSUS3_3 VCCSUS3_3
0.1U_0402_10V7K
R28
+1.05V_RUN U26 VCCSUS3_3 GPIO/LPC 2
1 VCCSUS3_3 A16 +PCH_VCCDSW3_3
CH45 M24 VCCDSW3_3 +3.3V_RUN PCH Power Rail Table
VSS AA14 +PCH_VCCSST 1 2
2 +3.3V_RUN DCPSST
0.1U_0402_10V7K
U35 CH46 0.1U_0402_10V7K
VCCUSBPLL AE14
1 Voltage Rail Voltage S0 Iccmax Current (A)
USB
L24 VCC3_3 AF12
VCC3_3 VCC3_3
CH47
0.1U_0402_10V7K
AG14
VCC3_3 +3.3V_ALW_PCH
0.1U_0402_10V7K
U30 1 VCC 1.05V 1.29 A
2 +1.05V_RUN V28 VCCIO
1 VCCIO
CH48
CH49
V30 U36 +1.05V_RUN
Y30 VCCIO VCCIO
VCCIO 2
VCCIO 1.05V 3.629 A
2
0.1U_0402_10V7K
+1.5V_RUN +PCH_USB_DCPSUS2 Y35 Azalia
DCPSUS2
1U_0402_6.3V6K
1 A26 1 VCCADAC1_5 1.5V 0.070 A
AF34 VCCSUSHDA
VCCVRM
CH50
CH51
+RTC_CELL
10U_0603_6.3V6M
1 +PCH_VCC AP45 K8 +3.3V_VCCPRTCSUS VCCADAC3_3 3.3V 0.0133 A
2 VCC VCCSUS3_3 2
CH52
+PCH_VCCCLK Y32 A6
VCCCLK VCCRTC
2 RTC
VCCCLK 1.05V 0.306 A
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
+PCH_VCCCLK3_3 M29 P14 +PCH_DCPRTC CH54
+1.05V_M VCCCLK3_3 DCPRTC P16 1 2
DCPRTC 1 1 1
L29 VCCCLK3_3 3.3V 0.055 A
VCCCLK3_3
CH55
CH56
CH57
1 2 +PCH_USB_DCPSUS2 0.1U_0402_10V7K
@ RH239 0_0402_5% L26 AJ12 +VCCIO2PCH
VCCCLK3_3 V_PROC_IO +3.3V_M 2 2 2
1U_0402_6.3V6K
M26 CPU AJ14 VCCVRM 1.5V 0.179 A

VCCCLK3_3 V_PROC_IO
1
@ CH58
U32
VCCCLK3_3
1U_0402_6.3V6K
V32
ICC
AD12 VCC3_3 3.3V 0.133 A
VCCCLK3_3 SPI VCCSPI
2 AD34
+PCH_VCCCLK VCCCLK 1
P18 +PCH_VCCCFUSE VCCASW 1.05V 0.67 A
C VCC C
CH59
AA30 P20
AA32 VCCCLK VCC
VCCCLK L17 2
VCCASW +1.05V_M VCCSUSHDA 3.3V 0.01 A
AD35
VCCCLK R18
AG30 VCCASW +VCCIO2PCH
VCCCLK VCCSPI 3.3V 0.022 A
AG32
VCCCLK AW40
VCCVRM +1.5V_RUN
AD36 VCCSUS3_3 3.3V 0.261 A
+1.05V_RUN +1.05V_RUN_VCC VCCCLK +3.3V_RUN
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
AK30
AE30 VCC3_3
Thermal 1 1 1
LH2 AE32 VCCCLK AK32
VCCCLK VCC3_3 VCCDSW3_3 3.3V 0.015 A
0.1U_0402_10V7K
CH83
CH82
CH81
1 2 1 2 +PCH_VCC
RH241 0_0603_5% 4.7UH_LQM18FN4R7M00D_20% 1 2 2 2
10U_0603_6.3V6M
1U_0402_6.3V6K
8 OF 11 V_PROC_IO 1.05V 0.004 A
CH65
1 1
CH63
CH64
2 2
Place near pin AP45
+PCH_VCCCFUSE 2 1 +3.3V_RUN
+1.05V_RUN +PCH_VCCCLK 0_0805_5% RH242
1U_0402_6.3V6K
2 1 +1.05V_RUN
1 2 1 0_0805_5% RH243 @
RH244 0_0805_5%
1U_0402_6.3V6K
1U_0402_6.3V6K
CH66
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
2
1 1 1 1 1
CH67
CH68
CH69
CH70
CH71
B B
2 2 2 2 2
Place near pin Y32,AA30,AA32 Place near pin AD34 Place near pin AD35,AD36
Place near pin AG30,AG32,AE30,AE32
+3.3V_VCCPRTCSUS 2 1 +3.3V_ALW_PCH
0_0603_5% @ RH240
2 1
+3.3V_RUN +3.3V_ALW
1U_0402_6.3V6K
+PCH_VCCCLK3_3 1 0_0603_5% RH246
CH53
1 2
RH245 0_0805_5% 2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1
CH72
CH73
CH74
CH75
2 2 2 2
Place near pin M29 Place near pin L29 Place near pin L26,M26 Place near pin U32,V32
A A
PROPRIETARY NOTE: Compal Electronics, Inc.
Title
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0.2
5 4 3 2 1
5 4 3 2 1
D D
UH1J LPT_PCH_M_EDS
AL34 K39 UH1K LPT_PCH_M_EDS

AL38 VSS VSS L2
AL8 VSS VSS L44 AA16 B19
AM14 VSS VSS M17 AA20 VSS VSS B23
AM24 VSS VSS M22 AA22 VSS VSS B27
AM26 VSS VSS N12 AA28 VSS VSS B31
AM28 VSS VSS N35 AA4 VSS VSS B35
AM30 VSS VSS N39 AB12 VSS VSS B39
AM32 VSS VSS N6 AB34 VSS VSS B7
AM16 VSS VSS P22 AB38 VSS VSS BA40
AN36 VSS VSS P24 AB8 VSS VSS BD11
AN40 VSS VSS P26 AC2 VSS VSS BD15
AN42 VSS VSS P28 AC44 VSS VSS BD19
AN8 VSS VSS P30 AD14 VSS VSS AY36
AP13 VSS VSS P32 AD16 VSS VSS AT43
C AP24 VSS VSS R12 AD18 VSS VSS BD31 C
AP31 VSS VSS R14 AD30 VSS VSS BD35
AP43 VSS VSS R16 AD32 VSS VSS BD39
AR2 VSS VSS R2 AD40 VSS VSS BD7
AK16 VSS VSS R34 AD6 VSS VSS D25
AT10 VSS VSS R38 AD8 VSS VSS AV7
AT15 VSS VSS R44 AE16 VSS VSS F15
AT17 VSS VSS R8 AE28 VSS VSS F20
AT20 VSS VSS T43 AF38 VSS VSS F29
AT26 VSS VSS U10 AF8 VSS VSS F33
AT29 VSS VSS U16 AG16 VSS VSS BC16
AT36 VSS VSS U28 AG2 VSS VSS D4
AT38 VSS VSS U34 AG26 VSS VSS G2
D42 VSS VSS U38 AG28 VSS VSS G38
AV13 VSS VSS U42 AG44 VSS VSS G44
AV22 VSS VSS U6 AJ16 VSS VSS G8
AV24 VSS VSS V14 AJ18 VSS VSS H10
BB25 VSS VSS V43 AJ24 VSS VSS H22
AV40 VSS VSS W2 AJ34 VSS VSS H24
AV6 VSS VSS W44 AJ38 VSS VSS H26
AW2 VSS VSS Y14 AJ6 VSS VSS H31
F43 VSS VSS Y16 AJ8 VSS VSS H36
AY10 VSS VSS Y24 AK14 VSS VSS H40
AY15 VSS VSS Y28 AK24 VSS VSS H7
AY20 VSS VSS Y34 AK43 VSS VSS K10
AY26 VSS VSS Y36 AK45 VSS VSS K15
AY29 VSS VSS Y40 AL12 VSS VSS K20
AY7 VSS VSS Y8 AL2 VSS VSS K29
B11 VSS VSS BC22 VSS VSS K33
B15 VSS BB42 VSS VSS BC28
B VSS VSS VSS B
10 OF 11 11 OF 11
A A
PROPRIETARY NOTE:
Title
PCH (9/9)
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0.2
5 4 3 2 1
5 4 3 2 1
CPU FAN JFAN1 CONN@

+3.3V_RUN
1 FAN2_PWM_D 2 1
FAN1_PWM 2 1 10K_0402_5% R403
<51> FAN1_PWM 2
<51> FAN1_TACH_FB FAN1_TACH_FB 3 FAN1_PWM 2 1
4 3 +RTC_CELL 10K_0402_5% R407
+5V_RUN 4 C287 FAN2_PWM 2 1
10U_0805_10V6K
0.1U_0402_25V6K
5 1 2 10K_0402_5% @ R409
6 GND1 FAN2_TACH_FB 2 1
D Place Q16 under MXM(TOP side) 1 1 GND2 D
C329
C364
0.1U_0402_25V6K 10K_0402_5% R405
5
ACES_50271-0040N-001 FAN1_TACH_FB 2 1
Place C273 close to the Q16 1 10K_0402_5% R408
P
2 2 B DOCK_PWR_SW# <51>
REM_DIODE1_P_4021 POWER_SW# 4
Link CIS OK O
100P_0402_50V8J
2 POWER_SW_IN# <51>
A
G
1 1
@ C273
C U10
3
2 TC7SH08FU_SSOP5~D +3.3V_ALW
B
2 E
3
Q16 EMC4021_BC_INT# 2 1
PMST3904_SOT323-3 REM_DIODE1_N_4021
MXM FAN @ R386 10K_0402_5%
DP2/DN2 for MXM on Q27(BOT side), @ R213 2 1 0_0603_5% +3.3V_M

JFAN2 CONN@
place Q27 close to Butterfly CHB and C291 close to Q27 D90 1
REM_DIODE2_P_4021 FAN2_PWM 1 2 FAN2_PWM_D 2 1 EMC4021_BC_INT# 2 1
2
100P_0402_50V8J
FAN2_TACH_FB 3 R385 10K_0402_5%

RB751S40T1_SOD523-2 4 3
+5V_RUN 4
@ C291
1
1
10U_0805_10V6K
0.1U_0402_25V6K
C 5
2 6 GND1
1 1 GND2
C330
C370
B
2 E ACES_50271-0040N-001
3
Q27
PMST3904_SOT323-3 2 2
C
REM_DIODE2_N_4021 Link CIS OK C
CIS LINK OK
U29
9/26
2
+3.3V_M 3 VDD_H
6 VDD_H 17 2 1
VDD_L THERMTRIP2# +3.3V_M
1 2 VDD_PWRGD 13 R130 10K_0402_5%
R389 10K_0402_5% VDD_PWRGD 18
N/C
1 2 REM_DIODE1_N_4021 23
C270 2200P_0402_50V7K REM_DIODE1_P_4021 24 DN1/THERM 19
DP1/VREF_T SYS_SHDN# THERM_STP# <56>
SMSC review in 6/22
2 1 REM_DIODE2_N_4021 26 20 POWER_SW# 1 2 +RTC_CELL
2 1 VCP_4021 C294 2200P_0402_50V7K REM_DIODE2_P_4021 27 DN2/DP4 POWER_SW# @ R390 47K_0402_1%
R431 10K_0402_5% DP2/DN4
30 21 ACAV_IN <17,51,61,62>
29 N/C ACAVAIL_CLR 9 EMC4021_BC_INT#
N/C ATF_INT#/BC_IRQ# EMC4021_BC_INT# <51>
1 2 VCP2 31
R131 100K_0402_5% VCP_4021 25 VCP
VIN 5
VSET_4021 28 FAN_OUT 4
VSET FAN_OUT
B B
SMSC request
VSET_4021 8
SMCLK/BC_CLK EMC4021_BC_CLK <51>
0.1U_0402_25V6K
FAN2_TACH_FB 10 7
TACH/GPIO1 SMDATA/BC_DATA EMC4021_BC_DAT <51>
+3.3V_M @ R411 2 1 10K_0402_5%
1
1.33K_0402_1%
1 R406 2 1 10K_0402_5% 11
TEST3
R424
C319
FAN2_PWM 15
GPIO3/PWM/THERMTRIP_SIO +3.3V_M
2
2
1
1 2 3V_PWROK# 12 R388
Rest=1.33k, Tp=93degree <51> PCH_PWRGD#
R391 1K_0402_1% 3V_PWROK#
22_0402_5%
1 +VCC_4021
2
VDD 32 +ADDR_XEN 1 2
ADDR_MODE/XEN +VCC_4021
0.1U_0402_25V6K
1U_0402_6.3V6K
4.7K_0402_5% R393 1 1
14
TEST1
C277
C1179
22
16 TEST2 33
+RTC_CELL RTC_PWR3V VSS 2 2
1
1U_0402_6.3V6K
1 EMC4021-1-EZK-TR_QFN32_5X5~D R404
10K_0402_5%
C274
SMSC request
2
2
A A
Title
FAN control
5 4 3 2 1
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5 4 3 2 1
Monitor PWR_SRC_MXM
+3.3V_MXM
2
@ R2185
RESISTOR (5%) SMBUS ADDRESS
10K_0402_5%
0 1001_100(r/w)
1
+MXM_PWR_SRC_A0
100 1001_101(r/w)
D 180 1001_110(r/w) D
2
@ R2187
300 1001_111(r/w)
+MXM_PWR_R 1 2 10K_0402_5%
@ R2180
430 1001_000(r/w)
0_0402_5% For +MXM_PWR_SRC
560 1001_001(r/w)
1
slave address : 100XXXX
750 1001_010(r/w)
please placemnet near R-sense
@U60
@ U60 1270 1001_011(r/w)
1 8 +MXM_PWR_SRC_A1 +3.3V_MXM
+MXM_PWR_SRC_R1 2 2 VIN+ A1 7 +MXM_PWR_SRC_A0
@ R2181 3 VIN- A0 6 MXM_CURI2C_DATA 0_0402_5% 2 1 @ R2183
1600 0101_000(r/w)
0_0402_5% GND SDA GPU_SMBDAT_R <17>
2
4 5 MXM_CURI2C_CLK 0_0402_5% 2 1 @ R2182
+3.3V_MXM VS SCL GPU_SMBCLK_R <17> @ R2184
2000 0101_001(r/w)
INA219AIDCNRG4_SOT23-8 10K_0402_5%
2700 0101_010(r/w)
3600 0101_011(r/w)
1
+MXM_PWR_SRC_A1 5600 0101_100(r/w)
9100 0101_100(r/w)
2
@ R2186 20000 0101_101(r/w)
10K_0402_5%
Open 0011_000(r/w)
1
C C
Monitor PWR_SRC_MXM for DELL request

+MXM_PWR
@ U59
1 2 +MXM_PWR_R 4 3
IN+ V+ +3.3V_MXM
10_0402_1% 5 2
100P_0402_50V8J
+MXM_PWR_SRC_R
IN- GND
4
2
@ PR14
0.1U_0402_25V6K
@
PC17
P C17
0.002_1206_1%
1
2
@
@ PR25
PC6
6 1
1
Out REF
1
INA199A2DCKR_SC70-6~D
1 2
0.01U_0402_25V7K
+5V_ALW
10_0402_1%
100P_0402_50V8J
@ PR24
221K_0402_1%
PC18
PC21
DYN_TURB_GPU_PWR_ALRT# <17,50>
2
+MXM_PWR_SRC
PR31
0_0402_5%
@ @
2
@
PR30
+3.3V_ALW2 +5V_ALW @ PR29
50K_0402_1%
B 1.8M_0402_1% B
1
1 2 @
1
1
PR27
@ PR28
8
@ 20K_0402_1% @ PU2A
1 2 3
P
2
+ 1
O
1
1.6V 2 D
-
G
220P_0402_50V8J
2 @ PQ323
LM393DR_SO8~D G DMN65D8LW-7_SOT323-3
4
1
PC19
3
100P_0402_50V8J
1
@
2
1
PC20
@PR26
@ PR26
76.8K_0402_1% @
2
2
MAX130W Protection Circuit

A A
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Current Sensor
www.Vinafix.vn

5 4 3 2 1
5 4 3 2 1
D D
+3.3V_RUN +3.3V_RUN
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 @ 1
C1146
C1145
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Channel A Channel B 1 @ 1
C1159
C1149
2 2
U11 U13
2 2
31 31
<17> MXM_LVDS_ACLK+ 30 D0_A+ <17> MXM_LVDS_BCLK+ 30 D0_A+
<17> MXM_LVDS_ACLK- 26 D0_A- 35 <17> MXM_LVDS_BCLK- 26 D0_A- 35
<17> MXM_LVDS_A2+ 25 D1_A+ VDD <17> MXM_LVDS_B2+ 25 D1_A+ VDD
From MXM
<17> MXM_LVDS_A2-
<17> MXM_LVDS_A1+
<17> MXM_LVDS_A1-
22
21
D1_A-
D2_A+
D2_A-
From MXM <17> MXM_LVDS_B2-
<17> MXM_LVDS_B1+
<17> MXM_LVDS_B1-
22
21
D1_A-
D2_A+
D2_A-
18 36 SW_LVDS_ACLK+ 18 36 SW_LVDS_BCLK+
<17> MXM_LVDS_A0+ D3_A+ D0+ SW_LVDS_ACLK+ <30> <17> MXM_LVDS_B0+ D3_A+ D0+ SW_LVDS_BCLK+ <30>
17 1 SW_LVDS_ACLK- 17 1 SW_LVDS_BCLK-
C <17> MXM_LVDS_A0- D3_A- D0- SW_LVDS_ACLK- <30> <17> MXM_LVDS_B0- D3_A- D0- SW_LVDS_BCLK- <30> C
5 2 SW_LVDS_A2+ 5 2 SW_LVDS_B2+
<17> MXM_LVDS_DDC_CLK 13 1A_A D1+ 3 SW_LVDS_A2- SW_LVDS_A2+ <30> 13 1A_A D1+ 3 SW_LVDS_B2- SW_LVDS_B2+ <30>
<17> MXM_LVDS_DDC_DAT 33 2A_A D1- 7 SW_LVDS_A1+ SW_LVDS_A2- <30> 33 2A_A D1- 7 SW_LVDS_B1+ SW_LVDS_B2- <30>
3A_A D2+ 8 SW_LVDS_A1- SW_LVDS_A1+ <30> 3A_A D2+ 8 SW_LVDS_B1- SW_LVDS_B1+ <30>
D2- 9 SW_LVDS_A0+ SW_LVDS_A1- <30> D2- 9 SW_LVDS_B0+ SW_LVDS_B1- <30>
D3+ 10 SW_LVDS_A0- SW_LVDS_A0+ <30> D3+ 10 SW_LVDS_B0- SW_LVDS_B0+ <30>
29 D3- 4 LDDC_CLK_SW SW_LVDS_A0- <30> 29 D3- 4 SW_LVDS_B0- <30>
<35> LVDS_ACLK+ 28 D0_B+ 1A 12 LDDC_CLK_SW <30> <35> LVDS_BCLK+ 28 D0_B+ 1A 12
LDDC_DATA_SW
<35> LVDS_ACLK- 24 D0_B- 2A 34 LDDC_DATA_SW <30> <35> LVDS_BCLK- 24 D0_B- 2A 34
<35> LVDS_A2+ 23 D1_B+ 3A <35> LVDS_B2+ 23 D1_B+ 3A
From RTD2136S <35> LVDS_A2-

<35> LVDS_A1+
<35> LVDS_A1-
20
19
D1_B-
D2_B+
D2_B-
From RTD2136S <35> LVDS_B2-
<35> LVDS_B1+
<35> LVDS_B1-
20
19
D1_B-
D2_B+
D2_B-
16 16
(eDP to LVDS) <35> LVDS_A0+
<35> LVDS_A0-
<35> LCD_EDID_CLK
LCD_EDID_CLK
15
6
D3_B+
D3_B- 27 DGPU_SELECT#
DGPU_SELECT# <30,33,50>
<35> LVDS_B0+
<35> LVDS_B0-
15
6
D3_B+
D3_B- 27 DGPU_SELECT#
LCD_EDID_DATA 14 1A_B SEL 14 1A_B SEL
<35> LCD_EDID_DATA 32 2A_B 32 2A_B
3A_B 3A_B
37 37
TPAD 11 TPAD 11
GND GND
TS3DV20812RHHR_VQFN36_6X6~D
SEL Channel Source TS3DV20812RHHR_VQFN36_6X6~D SEL Channel Source
CIS LINK OK 0 DO=A MXM CIS LINK OK
0 DO=A MXM
1 DO=B CPU
1 DO=B CPU
+3.3V_MXM
B 1 2 MXM_LVDS_DDC_CLK B
@ R1122 2.2K_0402_5%
1 2 MXM_LVDS_DDC_DAT
@ R1121 2.2K_0402_5%
MXM already internal pull up.
+3.3V_RUN
1 2 LCD_EDID_CLK
R1124 4.7K_0402_5%
1 2 LCD_EDID_DATA
R1123 4.7K_0402_5%
A A
Title
LVDS SW
www.Vinafix.vn
LA-9781P 0.2

5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
@C726
@ C726
+3.3V_RUN 1 2
1 2 LDDC_CLK_SW U54 0.1U_0402_25V6K +LCDVDD

R159 2.2K_0402_5% TC7SH08FU_SSOP5~D 1 2 LCD Power
5
1 2 LDDC_DATA_SW R1139 100K_0402_5% +3.3V_ALW @ C540 +3.3V_ALW
R160 2.2K_0402_5% 1 10U_0603_6.3V6M U28
P
1 2 4 B PANEL_BKEN_SW <35> 2 1 1
@ C727
O 2 2 1 VOUT 5
A PANEL_BKEN_PCH <19> VIN
G
D65 @ U55
RB751V40_SC76-2 0.1U_0402_25V6K TC7SH08FU_SSOP5~D 2
3
GND
5
D53 4
1 RB751VM-40TE-17_SOD323-2 SS
P
<35> LCD_ENVDD_SW B 4 2 1 3
2 O EN
<19,50> ENVDD_PCH A
G
D
11/22 pin swap for ME request APL3512ABI-TRG_SOT23-5
D
100K_0402_5%
1
JLVDS1 CONN@ D64
R1140
1 DISP_ON 1 2
1 2 LCD_CBL_DET# <19> <32> DISP_ON MXM_PANEL_BKEN <17> 1 2
DISP_ON
2 3
100K_0402_5%
1 2 BIA_PWM_LVDS RB751VM-40TE-17_SOD323-2 R433 0_0402_5%
3 4
1
EMC@ R207 0_0603_5%
2
4 5
R1138
D69
5 6 EMI request 1 2
6 7 PANEL_BKEN_EC <50> 2
7 8 +BL_PWR_SRC <50> LCD_VCC_TEST_EN
RB751VM-40TE-17_SOD323-2 1
2
8 9 EN_LCDPWR <32>
9 10 3
10 11 <17> MXM_ENVDD
11 12
12 13 LCD_TST <32,50>
D6
13 14 BAT54CW_SOT323-3
14 15
15 16 +LCDVDD
16 17 +3.3V_RUN
17 18
18 19 5P_0402_50V8C LDDC_CLK_SW <29>
19 20 @ C1188 LDDC_DATA_SW <29>
20 21 1
21 22 SW_LVDS_A0+ <29>
22 23 SW_LVDS_A0- <29>
23 24 SW_LVDS_A1+ <29> 2
24 25 SW_LVDS_A1- <29>
25 26 SW_LVDS_A2+ <29>
26 27 SW_LVDS_A2- <29>
27 28
28 29 SW_LVDS_ACLK+ <29>
29 30 SW_LVDS_ACLK- <29>
5P_0402_50V8C
5P_0402_50V8C
30 31
@ C1183
@ C1184
31 32 SW_LVDS_B0+ <29> 1 1
D66
32 33 SW_LVDS_B0- <29> 1 2
33 34 SW_LVDS_B1+ <29> BIA_PWM_SW <35>
34 35 SW_LVDS_B1- <29> 2 2 RB751VM-40TE-17_SOD323-2
41 35 36 SW_LVDS_B2+ <29>
42 G1 36 37 SW_LVDS_B2- <29>
C C
43 G2 37 38 +3.3V_RUN
44 G3
G4
38 39
39 40
SW_LVDS_BCLK+
SW_LVDS_BCLK-
<29>
<29>
C248 40mil
5P_0402_50V8C
5P_0402_50V8C
45 1 2 Q21
G5 40
@ C1186
@ C1185
+PWR_SRC FDC654P-G_SSOT-6 +BL_PWR_SRC

1 1 <29,33,50> DGPU_SELECT#
ACES_50398-04071-001 0.1U_0402_10V7K
6
40mil
D
4 5
S
Link CIS OK
5
2 2
0.47U_1206_50V7-K
2
100K_0402_5%
D68 1
OE#
0.1U_0603_50V7K
1 2 4 2 1
<32> BIA_PWM_LVDS Y A MXM_BIA_PWM <17>
1
C297
1
3
G
R422
RB751VM-40TE-17_SOD323-2 U3
10K_0402_5%
C296
TC7SH125FU_SSOP5
3
1
+BL_PWR_SRC +LCDVDD +3.3V_RUN 2
2
R1137
9/21
2
0.1U_0603_50V7K
0.1U_0402_25V6K
PWR_SRC_ON
0.1U_0402_25V6K
D71
2
1 2 Q22
2 1 1 BIA_PWM_EC <51>
C298
C243
C249
RB751VM-40TE-17_SOD323-2
1 2 1 3
S
1 2 2 R423 47K_0402_5%
Panel backlight power control by EC
G
2
<51> EN_INVPWR FDC654P: P CHANNAL
Close to JLVDS1
LInk CIS
4 3 USBP13_D-
B <22> USBP13- 4 3 B
<22> USBP13+ 1
1
2
2 USBP13_D+ Touch Screen & CAM +3.3V_ALW
@ L11 DLW21SN121SQ2L_4P TOUCH_SCREEN_PD# 2 1

1 2 @R426
@ R426 100K_0402_5%
EMC@ R429 0_0402_5%
Webcam PWR CTRL 1 2 JCAM1 CONN@
EMC@ R430 0_0402_5% USBP13_D- 1 2
+3.3V_RUN +CAMERA_VDD 1 2 +3.3V_RUN
Q24 USBP13_D+ 3 4
DMG2301U-7_SOT23-3 5 3 4 6
5 6 +5V_RUN
TOUCH_SCREEN_PD# 7 8
<50> TOUCH_SCREEN_PD# 7 8
S
3 1 9 10
11 9 10 12
<49> DMIC_CLK 11 12
0.1U_0402_25V6K
10U_0805_10V6K
0.1U_0402_25V6K
13 14
<49> DMIC0 15 13 14 16
G
2
17 15 16 18 CAM_MIC_CBL_DET# <19>
1 @ 1 1 USBP12_D-
17 18
C301
C300
C299
USBP12_D+ 19 20
EMC request change main source 19 20 +CAMERA_VDD
21 22
2 2 2 to SM070001N00 GND GND
CCD_OFF <50>
ACES_50238-0207N-002
L10 DLW21SN121SQ2L_4P
4 3 USBP12_D- +3.3V_RUN +5V_RUN
<22> USBP12- 4 3
LInk CIS
0.1U_0402_25V6K
0.1U_0402_25V6K
1 2 USBP12_D+
<22> USBP12+ 1
EMC@ 2
1 1
C310
C311
1 2
@R427
@ R427 0_0402_5%
2 2
1 2
@R428
@ R428 0_0402_5%
Close to JCAM1
A
ESD request change main source A
to SCA00001L00
Title
www.Vinafix.vn
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT LVDS& CAM& TS
LA-9781P 0.2

5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
+3.3V_RUN +3.3V_RUN
DP_RP_PEQ 2 1
@
DP_RP_CFG0 2 1 DP_RP_CFG1 2 1 4.7K_0402_5% R80
@
4.7K_0402_5% R76 4.7K_0402_5% R78
DP_RP_PEQ 1 2
@
DP_RP_CFG0 1 2 DP_RP_CFG1 1 2 4.7K_0402_5% R81
@
4.7K_0402_5% R77 4.7K_0402_5% R79
D D
Configuration pin for automatic EQ and AUX interception; Internal pull down at ~150kΩ, 3.3V I/O. Configuration pin for auto test and input offset cancellation, 3.3V IO, internal pull up at ~150K Programmable input equalization levels; Internal pull down at ~150kΩ, 3.3V I/O.
L: default, automatic EQ enable & AUX interception enable H: default, auto test disable & input offset cancellation enable L: default, LEQ, compensate channel loss up to 12dB @ HBR2
H: automatic EQ disable & AUX interception enable L: auto test enable & input offset cancellation enable H: HEQ, compensate channel loss up to 15dB @ HBR2
M: automatic EQ disable & AUX interception disable, no pre-emphasis, 600mVpp swing M: auto test disable & input offset cancellation disable M: LLEQ, compensate channel loss up to 5dB @ HBR2
+3.3V_RUN
0.1U_0402_16V4Z
0.01U_0402_16V7K
DP_RP_REXT DP_RP_CEXT 1 1
C496
C497
4.99K_0402_1%
2.2U_0402_6.3V6M
2
1 2 2
R75
C87
2
12
25
32
36
1
6
U22
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
C285 1 2 0.1U_0402_10V6K MXM_MB_DP_P0_C 38 23 MB_DP_RP_C_P0 0.1U_0402_10V6K 2 1 C307 MB_DP_RP_P0
<17> MXM_MB_DP_P0 1 2 MXM_MB_DP_N0_C 39 IN0p OUT0p 22 MB_DP_RP_C_N0 2 1
C284 0.1U_0402_10V6K 0.1U_0402_10V6K C304 MB_DP_RP_N0
<17> MXM_MB_DP_N0 1 2 41 IN0n OUT0n 20 2 1
C280 0.1U_0402_10V6K MXM_MB_DP_P1_C MB_DP_RP_C_P1 0.1U_0402_10V6K C295 MB_DP_RP_P1
<17> MXM_MB_DP_N1 1 2 MXM_MB_DP_P2_C 44 IN1n OUT1n 17 MB_DP_RP_C_P2 2 1
C281 0.1U_0402_10V6K 0.1U_0402_10V6K C306 MB_DP_RP_P2
C <17> MXM_MB_DP_P2 1 2 MXM_MB_DP_N2_C 45 IN2p OUT2p 16 MB_DP_RP_C_N2 2 1 C
<17> MXM_MB_DP_N2 1 2 MXM_MB_DP_P3_C 47 IN2n OUT2n 14 MB_DP_RP_C_P3 2 1
C279 0.1U_0402_10V6K 0.1U_0402_10V6K C303 MB_DP_RP_P3
C282 0.1U_0402_10V6K 0.1U_0402_10V6K C302 MB_DP_RP_N3 +3.3V_RUN
<17> MXM_MB_DP_N3 IN3n OUT3n
3 40 DP_RP_CFG1
I2C_ADDR CFG1
1
DP_RP_PEQ 4 46 +3.3V_RUN
DP_RP_CFG0 5 SCL_CTL/PEQ NC U30
VIN
SDA_CTL/CFG0 35 MB_DP_RST#
RST# APL3517AI-TRG_SOT23-3
10K_0402_5%
26 10 MB_DP_CA_DET
PD# CAD_SNK
R415
DP_RP_REXT 7 11 MB_DP_HPD
REXT HPD_SINK
VOUT
GND
8
CAD_SRC
2
MXM_MB_DP_HPD 9 28 MB_DP_RP_AUX +DP_VCC
<17> MXM_MB_DP_HPD
3
HPD_SRC AUX_SNKP 27 MB_DP_RP_AUX#
AUX_SNKN MB_DP_RST#
2.2U_0402_6.3V6M
33
34 SCL_DDC
SDA_DDC 1
0.01U_0402_16V7K
10U_0805_10V6K
2 DP_RP_CEXT
CEXT
C88
15
1 2 0.1U_0402_10V6K MXM_MB_DP_AUX_C 30 NC2 21 1 1
C397
C313
C482
<17> MXM_MB_DP_AUX AUX_SRCP NC3 2
C398 1 2 0.1U_0402_10V6K MXM_MB_DP_AUX#_C 29 37
<17> MXM_MB_DP_AUX# AUX_SRCN NC4 43
NC5 2 2
+3.3V_RUN
GND1
GND2
GND3
EPAD
MXM DP_A Dongle DDC JDP1CONN@
2.2K_0402_5%
B PS8330BQFN48GTR2-A0_QFN48_7X7 20 B
18
24
31
49
DP_PWR
1
+5V_RUN +3.3V_RUN 19
RTN
R2191
MB_DP_HPD 18
MB_DP_RP_AUX# 17 HP_DET
AUX_CH-
100K_0402_5%
MB_DP_RP_AUX# 2 1 16
100K_0402_5% R56 MB_DP_RP_AUX 15 GND
2
AUX_CH+
1
+5V_RUN DP_MB_P14 14
GND
R2193
MB_DP_RP_AUX 2 1 MB_DP_CA_DET 13
According to new EIA rule and change package to GTR2 CA_DET
6
100K_0402_5% R59 MB_DP_RP_N3 12 21

LANE3- GND
100K_0402_5%
MB_DP_CA_DET 2 1 11 22
LANE3_shield GND
Q340A
1M_0402_5% R62 MB_DP_RP_P3 10 23

2
LANE3+ GND
1
DP_A_MXM_AUX_Q2 DP_MB_P14 2 1 MB_DP_RP_N2 9 24

LANE2- GND
R2192
5.1M_0603_1% R801 8
LANE2_shield
3
MB_DP_RP_P2 7
1
MB_DP_RP_N1 6 LANE2+
LANE1-
Q339B
5
2
5 MB_DP_RP_P1 4 LANE1_shield
MB_DP_RP_N0 3 LANE1+
2 LANE0-
4
MB_DP_RP_P0 1 LANE0_shield
LANE0+
6
MXM_MB_DP_AUX
+3.3V_RUN FOX_3V11211-NBYD7-7H
Q339A
LInk CIS
2.2K_0402_5%
MB_DP_CA_DET 2
1
Vendor change MPN to 3V11211-NBYD7-7H

R2190
1
0.01U_0402_16V7K
1
but no modift PCB footprint
C1341
2
3
A A
Q340B
5
For debug issue that (DF543750)DP->HDMI/DP->S-DVI dongle
4
no function on NV units Compal Electronics, Inc.

Add TMDS DDC pull up schematic on DP port Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL DP CONN
www.Vinafix.vn
MXM_MB_DP_AUX# BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD LA-9781P 0.2
5 4 3 2 1
5 4 3 2 1
D D
EDP power
+EDPVDD +5V_ALW
change eDP pin defined same as LVDS
C396
10U_0603_6.3V6M U33 +3.3V_RUN
2 1 1 JEDP1
VOUT 5 1
VIN MXM_EDP_AUX-_C 2 1 <50> eDP_DET# 2 1
<30> DISP_ON 2
2 100K_0402_5% R339 1 2 3
GND <30> BIA_PWM_LVDS 3
4 RGB_PNL_DET# 2 1 EMC@ R208 0_0603_5% 4
SS 100K_0402_5% R340 5 4
5
2200P_0402_50V7K
EN_LCDPWR 3 6
<30,32> EN_LCDPWR EN 6
+BL_PWR_SRC 7
APL3512ABI-TRG_SOT23-5 8 7
1 8
MXM_EDP_HPD 2 1 9
9
C729
100K_0402_5% R222 10
MXM_EDP_AUX+_C 2 1 11 10
2 100K_0402_5% R336 12 11
<30,50> LCD_TST 12
13
14 13
15 14
16 15
+EDPVDD 16
17
RGB_PNL_DET# 18 17
19 18
20 19
<51> LCD_SMBCLK 20
21
<51> LCD_SMBDAT 21
<17> MXM_EDP_HPD 22
C
23 22 C
EN_LCDPWR 24 23
<30,32> EN_LCDPWR 24
25
C372 1 2 0.1U_0402_10V6K MXM_EDP_TX3+_C 26 25
<17> MXM_EDP_TX3+ 26
C374 1 2 0.1U_0402_10V6K MXM_EDP_TX3-_C 27
<17> MXM_EDP_TX3- 27
28
C375 1 2 0.1U_0402_10V6K MXM_EDP_TX2+_C 29 28
C376 1 2 0.1U_0402_10V6K MXM_EDP_TX2-_C 30
31
C377 1 2 0.1U_0402_10V6K MXM_EDP_TX1+_C 32 31
C378 1 2 0.1U_0402_10V6K MXM_EDP_TX1-_C 33
34
C379 1 2 0.1U_0402_10V6K MXM_EDP_TX0+_C 35 34
C380 1 2 0.1U_0402_10V6K MXM_EDP_TX0-_C 36 41
<17> MXM_EDP_TX0- 36 G1 42
37
C371 1 2 0.1U_0402_10V6K MXM_EDP_AUX+_C 38 37 G2 43
<17> MXM_EDP_AUX+ 38 G3 44
C373 1 2 0.1U_0402_10V6K MXM_EDP_AUX-_C 39
<17> MXM_EDP_AUX- 39 G4 45
40
40 G5
ACES_50398-04071-001
LinkCONN@
CIS OK
+3.3V_RUN +EDPVDD +BL_PWR_SRC
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0603_50V4Z
+3.3V_RUN
1 1 1
+3.3V_RUN
0.1U_0402_10V7K
C244
C305
C250
1 2 2 2
B @ B
1
100K_0402_5%
C93
2
R341
5
Close to JEDP1
2
eDP_DET# 1
4 3D_ON 3D_ON <44>
RGB_PNL_DET 2
U627
3
1
D SN74AHC1G02DCKR_SC70-5~D
RGB_PNL_DET# 2 Q88
G DMN65D8LW-7_SOT323-3
S
3
EDP_DET# RGB_DET# 3D_ON

RGB panel 0 1 0
3D panel 0 0 1
A A
LVDS panel 1 0 0
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BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, EDP CONN
LA-9781P 0.2

5 4 3 2 1
5 4 3 2 1
+5V_RUN +3.3V_RUN
1U_0402_6.3V6K
U19 1 1
MAX14885E
C1181
7 29 C1182
<17> MXM_CRT_RED 17 REDA VCC 1U_0603_10V7K
<19> PCH_CRT_RED REDB 21 2 2
8 VCC
<17> MXM_CRT_GRN 18 GRNA 11
<19> PCH_CRT_GRN GRNB VL
9
<17> MXM_CRT_BLU 19 BLUA
<19> PCH_CRT_BLU BLUB 33 RED_CRT
5 RED1 24
<17> MXM_CRT_DDC_CLK 15 SCLA RED2 RED_DOCK <48>
D <19> PCH_CRT_DDC_CLK SCLB 32 D
GREEN_CRT
Channel A --> MXM <17> MXM_CRT_DDC_DAT
<19> PCH_CRT_DDC_DAT
6
16 SDAA
SDAB
GRN1
GRN2
23
GREEN_DOCK <48>
Port 1 --> MB board CRT
31 BLUE_CRT
1 2 CRT_EN 2 BLU1 22
+3.3V_RUN EN BLU2 BLUE_DOCK <48>
R421 100K_0402_5%
3 35 CLK_DDC2_CRT
<17> MXM_CRT_HSYNC 13 SHA SCL1 26
<19> PCH_CRT_HSYNC SHB SCL2 CLK_DDC2_DOCK <48>
4 34 DAT_DDC2_CRT
Channel B --> PCH <17> MXM_CRT_VSYNC
<19> PCH_CRT_VSYNC
14 SVA
SVB
SDA1
SDA2
25
DAT_DDC2_DOCK <48> Port 2 --> Docking Port RGB
1 37 HSYNC_BUF
<50> EDID_SELECT# CRT_SWITCH 40 S00 SH1 28
<50> CRT_SWITCH 39 S01 SH2 HSYNC_DOCK <48>
<29,30,50> DGPU_SELECT# 38 S10 36
CRT_SWITCH VSYNC_BUF
S11 SV1 27
SV2 VSYNC_DOCK <48>
30
20 GND 12
10 GND NC
GND
41
GPAD
CRT_SWITCH DGPU_SELECT# EDID_SELECT# Output MAX14885EETL+T_TQFN40_5X5~D
SDAA to SDA1
SCLA to SCL1
REDA to RED1
DSC mode output to MB VGA 0 0 0 GRNA to GRN1
BLUA to BLU1
SHA to SH1
SVA to SV1
SDAA to SDA2
SCLA to SCL2
C REDA to RED2 C
DSC mode output to docking VGA 1 0 0 GRNA to GRN2
BLUA to BLU2
SHA to SH2
SVA to SV2
SDAB to SDA1
SCLB to SCL1
REDB to RED1
UMA mode output to MB VGA 0 1 1 GRNB to GRN1
BLUB to BLU1
SHB to SH1
SVB to SV1
SDAB to SDA2
SCLB to SCL2
REDB to RED2
UMA mode output to docking VGA 1 1 1 GRNB to GRN2
BLUB to BLU2
SHB to SH2
+5V_RUN +CRT_VCC
SVB to SV2
1U_0402_6.3V6K
1
C14
IN
AP2330W-7_SC59-3
2
RED_CRT EMC@ L1 1 2 BLM15BB470SN1D_2P RED_CRT_L
U6
GREEN_CRT EMC@ L2 1 2 BLM15BB470SN1D_2P GREEN_CRT_L
GND
OUT
B B
BLUE_CRT EMC@ L3 1 2 BLM15BB470SN1D_2P BLUE_CRT_L
3
@ T61
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
1
1
150_0402_1%
150_0402_1%
150_0402_1%
10P_0402_50V8J
10P_0402_50V8J
10P_0402_50V8J
PAD~D
1 1 1
1 1 1
R53
R54
R55
C20
C23
C22
C21
C12
C13
CRT_11
2 2 2
2
2 2 2
9/21 JCRT1
6
11
1
+CRT_VCC 7
DAT_DDC2_CRT 12
2
8 16
G
2.2K_0402_5%
2.2K_0402_5%
1K_0402_5%
1K_0402_5%
13 17
G
1
1
@
3 18
G
R47
R48
@ R50
@ R52
+CRT_VCC 9 19
14 G
M_ID2# 4
10
2
CLK_DDC2_CRT 15
5
DAT_DDC2_CRT
SUYIN_070449HR015M221ZR
CLK_DDC2_CRT
LInk CIS
CONN@
0.1U_0402_16V4Z
1
L4
C15
HSYNC_BUF EMC@1 2 HSYNC_L
BLM15AG121SN1D_L0402_2P
L5 2
VSYNC_BUF EMC@1 2 VSYNC_L
BLM15AG121SN1D_L0402_2P
A A
22P_0402_50V8J
22P_0402_50V8J
1 @ 1 @
C18
C19
2 2
www.Vinafix.vn
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, VGA CONN

5 4 3 2 1
5 4 3 2 1
AUX/DDC GPU for DPC to E-DOCK +3.3V_RUN
1 2
C359
D 0.1U_0402_25V6K D
CIS LINK OK
U20
1 14
2 1 DPC_DOCK_AUX 2 BE0 VCC 13
<17> MXM_DPB_AUX A0 BE3
0.1U_0402_10V6K C387
3 12 MXM_DPB_AUX
<48> DPC_DOCK_SW_AUX B0 A3
DPC_CA_DET 4 11
2 1 DPC_DOCK_AUX# 5 BE1 B3 10 DPC_CA_DET#
<17> MXM_DPB_AUX# C388 A1 BE2
0.1U_0402_10V6K
6 9 MXM_DPB_AUX#
<48> DPC_DOCK_SW_AUX# B1 A2
7 8
GND B2
PI3C3125LEX_TSSOP14~D
CA_DET Output
A2=B2
HDMI/DVI 1 A3=B3
A0=B0
DP 0 A1=B1
C C
+3.3V_RUN
2.2K_0402_5%
DOCK DPB(PORT2) DDC
1
+5V_RUN
R1539
100K_0402_5%
2
1
+5V_RUN
R1537
6
100K_0402_5%
Q113A
2
1
2
R1532
1
Q110B
2
DPC_CA_DET# 5
B B
4
6
DPC_DOCK_SW_AUX
+3.3V_RUN
Q110A
2.2K_0402_5%
DPC_CA_DET 2
<48> DPC_CA_DET
1
R1530
1
0.01U_0402_16V7K
1
C1174
2
3
Q113B
5
4
DPC_DOCK_SW_AUX#
A A
DP DDC SW
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5 4 3 2 1
5 4 3 2 1
Power Consumption:
Pin5 (DPV33) < 20mA
Pin 11 (DPV12) < 100mA
D
Pin 15 (SWR_VCCK) < 100mA (layout trace > 60 mil) D
+3.3V_RUN +3.3V_RUN
Pin 17 (SWR_LX) < 600mA (layout trace > 60 mil)
Pin 18 (SWR_VDD) < 200mA (layout trace > 40 mil)
2
2
R1990 @ R1992 Pin 22 (PVCC) < 50 mA
4.7K_0402_5% 4.7K_0402_5%
Pin 43 (VCCK) < 50mA
1
1
MIIC_SCL0 MIIC_SDA0
PN change to SA000067100
2
2
@ R1991 R1993 U23
4.7K_0402_5% 4.7K_0402_5%
RTD2136S
1
1
35
+3.3V_RUN 22 TXOC+ 36 LVDS_ACLK+ <29>
PVCC TXOC- LVDS_ACLK- <29>
L60 2 1 +DVCC33 40 mils 18 41
FBMA-L11-201209-221LMA30T_0805 SW R_VDD TXO0+ 42 LVDS_A0+ <29>
TXO0- LVDS_A0- <29>
PWR
L61 2 1 +AVCC33 5
FBMA-L11-201209-221LMA30T_0805 DP_V33 39
C
+SWR_V12 L62 1 2 +SW_LX 40 mils 17 TXO1+ 40 LVDS_A1+ <29> C
4.7UH_PG031B-4R7MS_1.1A_20% SW R_LX TXO1- LVDS_A1- <29>

1 2 40 mils 15 37
@ R550 0_0805_5% SW R_VCCK TXO2+ 38 LVDS_A2+ <29>
43 TXO2- LVDS_A2- <29>
VCCK 33
+AVCC33 11 TXO3+ 34
Close to 5 pin DP_V12 TXO3-
10U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z 25
1 1 1 TXEC+ LVDS_BCLK+ <29>
C100 2 1 0.1U_0402_10V7K EDP_CPU_LANE_P0_C 7 26
LVDS
<9> EDP_CPU_LANE_P0 LANE0P TXEC- LVDS_BCLK- <29>
C106
C107
C108
C101 2 1 0.1U_0402_10V7K EDP_CPU_LANE_N0_C 8
<9> EDP_CPU_LANE_N0 LANE0N 31
2 2 2 C103 2 1 0.1U_0402_10V7K EDP_CPU_LANE_P1_C 9 TXE0+ 32 LVDS_B0+ <29>
<9> EDP_CPU_LANE_P1 LANE1P TXE0- LVDS_B0- <29>
C118 2 1 0.1U_0402_10V7K EDP_CPU_LANE_N1_C 10
<9> EDP_CPU_LANE_N1 LANE1N
DP
29
R2198 1 2 10_0402_1% EDP_CPU_AUX_R C104 2 1 0.1U_0402_10V7K EDP_CPU_AUX_C 4 TXE1+ 30 LVDS_B1+ <29>
<9> EDP_CPU_AUX AUX-CH_P TXE1- LVDS_B1- <29>
R2199 1 2 10_0402_1% EDP_CPU_AUX#_R C105 2 1 0.1U_0402_10V7K EDP_CPU_AUX#_c 3
<9> EDP_CPU_AUX# AUX-CH_N 27
CPU_EDP_HPD 1 TXE2+ 28 LVDS_B2+ <29>
<9> CPU_EDP_HPD DP_HPD TXE2- LVDS_B2- <29>
23
1 2 TXE3+ 24
60 mils TXE3-
R127 100K_0402_5%
B +SWR_V12 1 2 BIA_PWM_PCH_R 21 B
<19> BIA_PWM_PCH 1 2 2 PW MIN 46 LCD_EDID_CLK
10/11 R1996 0_0402_5%
TESTMODE MIICSCL1 LCD_EDID_CLK <29>
22U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
@ R100 1 2 0_0402_5% 12 45 LCD_EDID_DATA

DP_REXT MIICSDA1 LCD_EDID_DATA <29>
OTHERS
1 1 1 1 R101 12K_0402_1%
20 LCD_ENVDD_SW
+3.3V_RUN PANEL_VCC LCD_ENVDD_SW <30>
C109
C110
C111
C112
19 BIA_PWM_SW
MIIC_SCL0 48 PW MOUT 44 PANEL_BKEN_SW BIA_PWM_SW <30>
2 2 2 2 MIIC_SDA0 47 MIICSCL0 BL_EN PANEL_BKEN_SW <30>
MIICSDA0
1
R1994 DDR_XDP_WAN_SMBCLK 13 6
<13,14,15,16,18,21,37> DDR_XDP_WAN_SMBCLK 14 CIICSCL1 DP_GND
100K_0402_5% Close to 11 pin Close to 43 pin DDR_XDP_WAN_SMBDAT
<13,14,15,16,18,21,37> DDR_XDP_WAN_SMBDAT CIICSDA1 16 +UTLGND 1 2
GND
2
GND @ R1989 0_0402_5%

EDP_CPU_AUX# 49
@ EDP_CPU_AUX PAD
+DVCC33
RTD2136S-VE-CG_QFN48_6X6
1
10U_0603_6.3V6M
0.1U_0402_16V4Z
22U_0603_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 1 1 1
R1995
C113
C114
C115
C116
C117
100K_0402_5%
2
2 2 2 2 2
A A
@
AUX termination DELL CONFIDENTIAL/PROPRIETARY
Close to 18 pin Close to 22 pin
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, eDP to LVDS
LA-9781P
5 4 3 2 1
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5 4 3 2 1
+3.3V_RUN
Meet AMD HDMI 297 MHz EA setting

+3.3V_RUN TMDS_RT 2 1
4.7K_0402_5% R71
DP_CFG0 2 1
4.7K_0402_5% R64 @
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
TMDS_DDCBUF 2 1
1 1 1 1 @ 1
Choice DDC active buffer mode 4.7K_0402_5% R68
C410
C405
C437
C402
PEQ 2 1
C766
4.7K_0402_5% R70 @
CIS LINK OK DP_CFG1 2 1
2 2 2 2 2 4.7K_0402_5% R72 @
MODE 2 1
U9 4.7K_0402_5% R58
14 40 DPD_GPU_LANE_P0 TMDS_PRE 2 1
28 VDD33 DP_D0p 39 DPD_GPU_LANE_N0 DPD_GPU_LANE_P0 <48> 4.7K_0402_5% R65
D 41 VDD33 DP_D0n DPD_GPU_LANE_N0 <48> D
56 VDD33 37 DPD_GPU_LANE_P1 Meet AMD HDMI 297 MHz EA setting
VDD33 DP_D1p 36 DPD_GPU_LANE_N1 DPD_GPU_LANE_P1 <48> TMDS_RT 2 1
DP_CFG0 44 DP_D1n DPD_GPU_LANE_N1 <48> 4.7K_0402_5% R57 @
DOCKED# 45 DP_CFG0/SCL_CTL 34 DPD_GPU_LANE_P2 DP_CFG0 2 1
38 SW/SDA_CTL DP_D2p 33 DPD_GPU_LANE_N2 DPD_GPU_LANE_P2 <48> 4.7K_0402_5% R61 @
I2C_CTL_EN DP_D2n DPD_GPU_LANE_N2 <48> For Docking DP port D TMDS_DDCBUF 2 1
MUX_D0 C505 1 2 0.1U_0402_10V6K MUX_D0_C 3 31 DPD_GPU_LANE_P3 4.7K_0402_5% R66 @
<47> MUX_D0 IN_D0p DP_D3p DPD_GPU_LANE_P3 <48>
MUX_D0# C506 1 2 0.1U_0402_10V6K MUX_D0#_C 4 30 DPD_GPU_LANE_N3 PEQ 2 1
<47> MUX_D0# IN_D0n DP_D3n DPD_GPU_LANE_N3 <48> 4.7K_0402_5% R69 @
MUX_D1 C507 1 2 0.1U_0402_10V6K MUX_D1_C 6 55 DPD_DOCK_AUX DP_CFG1 2 1
<47> MUX_D1 IN_D1p DP_AUXp_SCL DPD_DOCK_AUX <48>
MUX_D1# C508 1 2 0.1U_0402_10V6K MUX_D1#_C 7 54 DPD_DOCK_AUX# 4.7K_0402_5% R73 @
<47> MUX_D1# IN_D1n DP_AUXn_SDA DPD_DOCK_AUX# <48>
32 DPD_GPU_HPD MODE 2 1
DP_HPD DPD_GPU_HPD <48>
MUX_D2 C509 1 2 0.1U_0402_10V6K MUX_D2_C 9 4.7K_0402_5% R63
<47> MUX_D2 IN_D2p
MUX_D2# C510 1 2 0.1U_0402_10V6K MUX_D2#_C 10 TMDS_PRE 2 1
<47> MUX_D2# IN_D2n 42 DPD_CA_DET
DPD_CA_DET <48>
Meet AMD HDMI 297 MHz EA setting 4.7K_0402_5% R67
MUX_D3 C511 1 2 0.1U_0402_10V6K MUX_D3_C 12 DP_CA_DET DPD_CA_DET 2 1
<47> MUX_D3 IN_D3p
MUX_D3# C512 1 2 0.1U_0402_10V6K MUX_D3#_C 13 29 DP_CFG1 1M_0402_5% R491
<47> MUX_D3# IN_D3n DP_CFG1
MUX_AUX 52 19 TMDSE_RP_P0
<47> MUX_AUX IN_AUXp TMDS_CH0p
MUX_AUX# 51 18 TMDSE_RP_N0
<47> MUX_AUX# IN_AUXn TMDS_CH0n
50 22 TMDSE_RP_P1
49 IN_DDC_SCL TMDS_CH1p 21 TMDSE_RP_N1
IN_DDC_SDA TMDS_CH1n
MUX_CA_DET 11 25 TMDSE_RP_P2
<47> MUX_CA_DET IN_CA_DET TMDS_CH2p 24 TMDSE_RP_N2
<47> MUX_HPD
MUX_HPD 5
IN_HPD
TMDS_CH2n For HDMI
16 TMDSE_RP_CLK
TMDS_CLKp 15 TMDSE_RP_CLK#
MODE = L: Control Switching Mode, HDMI ID disable
Change from 100k to 10kohm TMDS_CLKn = H: Automatic Switching Mode, HDMI ID disable
CEXT 1 48 HDMI_SCL_SINK
to meet the input high-level voltage. CEXT TMDS_SCL 47 HDMI_SDA_SINK
= M: Automatic Switching Mode, HDMI ID enable
+3.3V_RUN TMDS_DDCBUF 2 TMDS_SDA
TMDS_DDCBUF 17 HDMI_HPD_SINK
TMDS_HPD TMDS_PRE = L: no pre-emphasis
10K_0402_5%
PEQ 8
1
PEQ 23 TMDS_RT = H: 1.5dB pre-emphasis

TMDS_RT
R518
MUX_CA_DET REXT3 CEXT REXT3 27 20 TMDS_PRE

REXT TMDS_PRE = M: 3.0dB pre-emphasis
46 26
PD GND
1M_0402_5%
4.99K_0402_1%
35
2
GND
2.2U_0402_6.3V6M
MODE 53 43
MODE GND TMDS_RT = L: Standard open drain driver
R493
C 57 C
1 Thermal/GND = H: Open drain driver with termination resistors
R74
C86
DOCKED#
PS8339BQFN56GTR2-A0_QFN56_7X7
1
2
TMDS_DDCBUF = L: DDC pass through
1
D
DMN65D8LW -7_SOT323-3
= H: DDC active buffer
2
<39,50> DOCKED
G Q326 = M: DDC pass through with 40 kohm pull up resistor
S
3
+3.3V_RUN +3.3V_RUN PEQ = L: default, LEQ, compensate channel loss up to 12dB @ HBR2
DOCK DPA(PORT1) DDC Reserve = H: HEQ, compensate channel loss up to 15dB @ HBR2
= M: LLEQ, compensate channel loss up to 5dB @ HBR2
2.2K_0402_5%
2.2K_0402_5%
9/21
1
1
+5V_RUN
R2151
R2154
DP_CFG1 = L: default, auto test disable & input offset cancellation enable
= H: auto test enable & input offset cancellation enable
100K_0402_5%
For Control Switching:

= M: auto test disable & input offset cancellation disable
2
2
1
SW = L: DP output is selected +3.3V_RUN

R2153
SW = H: TMDS output is selected
6
6
DP_CFG0 = L: default, automatic EQ enable & AUX interception enable
100K_0402_5%
= H: automatic EQ disable & AUX interception enable

Q335A
Q337A
2
1
DPD_DOCK_AUX_Q 2 DPD_DOCK_AUX_Q 2
= M: automatic EQ disable & AUX interception disable, no pre-emphasis, 800mVpp swing
R2152
1 2
1
1
@ R451 0_0402_5%
Q336B
2
5
EMC@ L19
TMDSE_RP_CLK 4 3 TMDSE_CON_CLK
4
4 3
6
MUX_AUX DPD_DOCK_AUX
TMDSE_RP_CLK# 1 2 TMDSE_CON_CLK# +3.3V_RUN +3.3V_RUN
1 2
Q336A
2.2K_0402_5%
2.2K_0402_5%
DLW 21SN900HQ2L_0805_4P DPD_CA_DET 2 9/21
1
1
+5V_RUN
R2157
R2159
1
0.01U_0402_16V7K
1 2 1
@ R452 0_0402_5% +VDISPLAY_VCC
C1332
B B
2
1
1 2 2
AP2330W-7_SC59-3
U5
0.1U_0402_10V7K
10U_0805_10V6K
@ R453 0_0402_5%
IN
3
3
1 1
Q335B
Q337B
C47
EMC@ L23
C46
TMDSE_RP_P0 4 3 TMDSE_CON_P0 5 5
4 3 For debug issue that (DF528281)SUT detect DVI device
and no sound output when attached HDMI monitor 2 2
GND
OUT
4
TMDSE_RP_N0 1 2 TMDSE_CON_N0
1 2 Change TMDS DDC pull up control pin from IN_CA_DET to DP_CA_DET
DLW 21SN900HQ2L_0805_4P
3
1 2
@ R454 0_0402_5% MUX_AUX# DPD_DOCK_AUX#
1 2
@ R455 0_0402_5% EMI request reserve C(3.3pF) for HDMI signals. 10/11 CIS LINK OK
9/21
TMDSE_CON_CLK TMDSE_CON_P0 JHDMI1
EMC@ L24 HDMI_HPD_SINK 1 2 HDMI_HPD_SINK_R 19
TMDSE_RP_P1 4 3 TMDSE_CON_P1 +VDISPLAY_VCC 10K_0402_5% R1164 18 HP_DET
4 3 TMDSE_CON_CLK# TMDSE_CON_N0 17 +5V
DDC/CEC_GND
3.3P_0402_50V8C
3.3P_0402_50V8C
3.3P_0402_50V8C
3.3P_0402_50V8C
HDMI_SDA_SINK 16
TMDSE_RP_N1 1 2 TMDSE_CON_N1 HDMI_SCL_SINK 15 SDA
1 2 @ @ @ @ 14 SCL
1 1 1 1 Reserved
C1334
C1333
C1335
C1336
DLW 21SN900HQ2L_0805_4P HDMI_CEC 13

TMDSE_CON_CLK# 12 CEC
11 CK-
1 2 2 2 2 2 TMDSE_CON_CLK 10 CK_shield
@ R456 0_0402_5% TMDSE_CON_N0 9 CK+
8 D0-
TMDSE_CON_P0 7 D0_shield
1 2 TMDSE_CON_N1 6 D0+
@ R459 0_0402_5% R460 1 2 1.5K_0402_5% HDMI_SDA_SINK 5 D1-
R461 1 2 1.5K_0402_5% HDMI_SCL_SINK TMDSE_CON_P1 4 D1_shield 20
TMDSE_CON_N2 3 D1+ GND 21
EMC@ L25 TMDSE_CON_P1 TMDSE_CON_P2 2 D2- GND 22
A TMDSE_RP_P2 4 3 TMDSE_CON_P2 TMDSE_CON_P2 1 D2_shield GND 23 A
4 3 D2+ GND
TMDSE_CON_N1 TMDSE_CON_N2 +3.3V_RUN CONCR_099AAAC19BBLCNF
3.3P_0402_50V8C
3.3P_0402_50V8C
3.3P_0402_50V8C
3.3P_0402_50V8C
TMDSE_RP_N2 1 2 TMDSE_CON_N2
1 2
CONN@
DLW 21SN900HQ2L_0805_4P 1 @ 1 @ 1 @ 1 @ HDMI_CEC 1 2
C1337
C1338
C1339
C1340
10K_0402_5% R1165
HDMI_HPD_SINK 1 2 HDMI
1 2 100K_0402_5% @ R1128
2 2 2 2 Part Number Description
@ R458 0_0402_5%
RO0000002HM HDMI W/Logo:RO0000002HM DELL CONFIDENTIAL/PROPRIETARY
EMI request non-pop R451~R456,R458,R459 and Compal Electronics, Inc.
pop L19,L23~25 and HDMI EA have verify it.
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TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT HDMI CONN

5 4 3 2 1
5 4 3 2 1
+3.3V_RUN +3.3V_RUN
R501
1 2 DDR_XDP_WAN_SMBDAT
10K_0402_5%
Free Fall Sensor
10U_0603_6.3V6M
0.1U_0402_25V6K
1 2 DDR_XDP_WAN_SMBCLK
R502 10K_0402_5%
1 2 HDD_FALL_INT 1 1
R503 100K_0402_5% U88
C392
C391
1 2 FFS_INT2 LNG3DM
R504 100K_0402_5%
2 2 1 RES
10
13
HDD PWR
14 VDD_IO RES 15
VDD RES 16
HDD_FALL_INT 11 RES +5V_HDD +5V_RUN
<19> HDD_FALL_INT FFS_INT2 9 INT 1 5 PJP3
INT 2 GND 12 1 2
D GND 1 2 D
7
6 SDO/SA0 JUMP_43X79
<13,14,15,16,18,21,35> DDR_XDP_WAN_SMBDAT 4 SDA / SDI / SDO
<13,14,15,16,18,21,35> DDR_XDP_WAN_SMBCLK SCL/SPC 2
NC SHORT DEFAULT
8 3
CS NC
LNG3DMTR_LGA16_3X3~D
CIS LINK OK
+3.3V_RUN
HDD Repeater
CIS LINK OK
A_PRE0
4.7K_0402_5%
A_PRE1
2
2
1
1
R42 @
+3.3V_RUN Pre-emphasis level setting for Channel A,
4.7K_0402_5% R40 @
U26 B_PRE0 2 1 3.3V tolerant. Internally pulled down at ~150KΩ
@ C24 1 2 1U_0402_6.3V6K SATA_repeater_EN 7 10 4.7K_0402_5% R46 @ [A_PRE1, A_PRE0] ==
EN VDD 20 B_PRE1 2 1
VDD 00: 0dB, no pre-emphasis
0.01U_0402_16V7K
0.1U_0402_16V4Z
PSATA_PTX_DRX_P0_C @ C423 2 1 0.01U_0402_16V7K PSATA_PTX_DRX_P0 1 4.7K_0402_5% R39 @
<18> PSATA_PTX_DRX_P0_C
PSATA_PTX_DRX_N0_C @ C422 2 1 0.01U_0402_16V7K PSATA_PTX_DRX_N0 2 A_INp 6 DEW2 TEST 2 1 01: 1.5dB pre-emphasis is selected
<18> PSATA_PTX_DRX_N0_C A_INn NC 1 1
NC
16 DEW1 4.7K_0402_5% R41 @ 10: 2.5dB pre-emphasis is selected
C420
C419
PSATA_PRX_DTX_P0_C @ C421 2 1 0.01U_0402_16V7K PSATA_PRX_DTX_P0 5 DEW2 2 1 11: 3.5dB pre-emphasis is selected
<18> PSATA_PRX_DTX_P0_C PSATA_PRX_DTX_N0_C @ C418 2 1 0.01U_0402_16V7K PSATA_PRX_DTX_N0 4 B_OUTp 9 A_PRE0 4.7K_0402_5% R83 @
<18> PSATA_PRX_DTX_N0_C B_OUTn A_PRE0 8 B_PRE0 2 2 DEW1 2 1
B_PRE1 19 B_PRE0 4.7K_0402_5% R84 @
A_PRE1 17 A_PRE1 15 PSATA_PTX_DRX_P0_RP
B_PRE1 A_OUTp Pre-emphasis level setting for Channel B,
14 PSATA_PTX_DRX_N0_RP DEW2 2 1
TEST 18 A_OUTn 4.7K_0402_5% R85 @
3.3V tolerant. Internally pulled down at ~150KΩ
3 TEST 11 PSATA_PRX_DTX_P0_RP DEW1 2 1 [B_PRE1, B_PRE0] ==
13 GND B_INp 12 PSATA_PRX_DTX_N0_RP 4.7K_0402_5% R90 @
C GND B_INn 00: 0dB, no pre-emphasis C
21 A_PRE0 1 2
EPAD 0_0402_5% R88 @ 01: 1.5dB pre-emphasis is selected
PS8520CTQFN20GTR2-A_TQFN20_4X4 A_PRE1 1 2 10: 2.5dB pre-emphasis is selected
0_0402_5% R89 @ 11: 3.5dB pre-emphasis is selected
B_PRE0 1 2
0_0402_5% R87 @
PSATA_PTX_DRX_P0_C 1 2 PSATA_PTX_DRX_P0_BP C390 2 1 0.01U_0402_16V7K SATA_PTX_DRX_P0 B_PRE1 1 2
PSATA_PTX_DRX_N0_C 1
R1643 20_0402_5% PSATA_PTX_DRX_N0_BP C389 2 1 0.01U_0402_16V7K SATA_PTX_DRX_N0 0_0402_5% R82 @
R1644 0_0402_5% TEST 1 2
PSATA_PRX_DTX_P0_C 1 2 PSATA_PRX_DTX_P0_BP C393 2 1 0.01U_0402_16V7K SATA_PRX_DTX_P0 0_0402_5% R86 @
PSATA_PRX_DTX_N0_C 1
R1645 20_0402_5% PSATA_PRX_DTX_N0_BP C394 2 1 0.01U_0402_16V7K SATA_PRX_DTX_N0
R1646 0_0402_5%
C423.2 close to R1623.1 C390.1 close to C383.1

C422.2 close to R1644.1 Reserve bypass HDD Repeater C389.1 close to C384.1
HDD2 CONN
HDD1 CONN C413 2 1 0.01U_0402_16V7K SATA_PTX_DRX_P5
1
2
JSATA2
GND
<18> SATA_PTX_DRX_P5_C 2 1 0.01U_0402_16V7K 3 RX+
JSATA1 C411 SATA_PTX_DRX_N5
+5V_HDD 1 <18> SATA_PTX_DRX_N5_C 4 RX-
PSATA_PTX_DRX_P0_RP @ C383 2 1 0.01U_0402_16V7K SATA_PTX_DRX_P0 2 GND C414 2 1 0.01U_0402_16V7K SATA_PRX_DTX_N5 5 GND
B RX+ <18> SATA_PRX_DTX_N5_C TX- B
100K_0402_5%
PSATA_PTX_DRX_N0_RP @ C384 2 1 0.01U_0402_16V7K SATA_PTX_DRX_N0 3 C412 2 1 0.01U_0402_16V7K SATA_PRX_DTX_P5 6

RX- <18> SATA_PRX_DTX_P5_C TX+
1
4 7
GND GND
@ R506
PSATA_PRX_DTX_N0_RP @ C385 2 1 0.01U_0402_16V7K SATA_PRX_DTX_N0 5

+3.3V_RUN PSATA_PRX_DTX_P0_RP @ C386 2 1 0.01U_0402_16V7K SATA_PRX_DTX_P0 6 TX- 8
TX+ +3.3V_RUN 3.3V
7 9
GND 3.3V
100K_0402_5%
10
2
3.3V
1
8 11
+3.3V_RUN 3.3V GND
R513
9 HDD2_DET# 12
FFS_INT2_Q 10 3.3V <18,23> HDD2_DET# 13 GND
11 3.3V 14 GND
GND +5V_HDD 5V
HDD1_DET# 12 15
Add 22u for DELL request
2
<18> HDD1_DET# GND 5V

3
13 16
14 GND 17 5V
9/21 +5V_HDD 5V GND
Q29B
15 +3.3V_RUN +5V_HDD FFS_INT2_Q 18 23

5 16 5V 19 Reserved GND1 24
17 5V 20 GND GND2
GND 12V
0.1U_0402_25V6K
0.1U_0402_25V6K
22U_0805_6.3V6M
1000P_0402_50V7K
0.1U_0402_25V6K
+3.3V_RUN +5V_HDD FFS_INT2_Q 18 23 21
4
Reserved GND1 12V

6
19 24 22
20 GND GND2 12V
12V 1 1 1 1 1
Q29A
0.1U_0402_25V6K
0.1U_0402_25V6K
1000P_0402_50V7K
0.1U_0402_25V6K
21 OCTEK_SAT-22PDAB
12V
10U_0805_25V6K
C408
C407
C498
C409
C415
2 22
<23> FFS_INT2
1 1 1 1 1
12V
2 2 2 2 2
LInk CIS
CONN@
OCTEK_SAT-22PDAB
Main SATA +5V Default
1
C404
C403
C395
C406
C5
2 2 2 2 2
LInk CIS
CONN@
Main SATA +5V Default
Pleace near HDD2 CONN Pleace near HDD2 CONN
Pleace near HDD1 CONN Pleace near HDD1 CONN
A A
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BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, HDD CONN

5 4 3 2 1
5 4 3 2 1
D D
+5VMOD Source
+5V_ALW +5V_MOD
U57
MODC_EN 3
<50> MODC_EN ON
1 7
VIN VOUT
100K_0402_5%
10U_0603_6.3V6M
2 8
VIN VOUT
R514
1
C767
4
2
VBIAS 5 2
6 GND 9
C CT GND C
470P_0402_50V7K
1
C544
TPS22965DSGR_SON8_2X2~D
+3.3V_ALW_PCH
ODD CONN
JODD1
2 1 SATA_ODD_PTX_DRX_P1 1
1 2 ZODD_WAKE# <18> SATA_ODD_PTX_DRX_P1_C 2 GND
C433 0.01U_0402_16V7K
R796 10K_0402_5% 2 1 SATA_ODD_PTX_DRX_N1 3 RX+
1 2 <18> SATA_ODD_PTX_DRX_N1_C 4 RX-
MOD_MD C434 0.01U_0402_16V7K
R520 10K_0402_5% 2 1 SATA_ODD_PRX_DTX_N1 5 GND
<18> SATA_ODD_PRX_DTX_N1_C C432 0.01U_0402_16V7K 6 TX-
2 1 SATA_ODD_PRX_DTX_P1 7 TX+
<18> SATA_ODD_PRX_DTX_P1_C C430 0.01U_0402_16V7K GND
B 8 B
<51> DEVICE_DET# 9 DP
+5V_MOD +5V
10
MOD_MD 11 +5V
10/11 MD
12 14
Q81A 13 GND GND1 15
DMN66D0LDW-7_SOT363-6 GND GND2
MOD_MD 1 6 ZODD_WAKE# OCTEK_SLS-13SZAB
ZODD_WAKE# <50>
+5V_MOD LInk CIS
CONN@
2
MODC_EN#
1000P_0402_50V7K
0.1U_0402_16V4Z
10/11
1 1
+3.3V_ALW
C428
C429
2 2
100K_0402_5%
1
R515
Pleace near ODD CONN

2
MODC_EN#
3
MODC_EN 5 DMN66D0LDW-7_SOT363-6
A Q81B A
4
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT ODD CONN
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5 4 3 2 1
5 4 3 2 1
+3.3V_LAN
1 2 TP_LAN_JTAG_TMS
@ R545 10K_0402_5% PN change to SA00005OO3L
1 2 TP_LAN_JTAG_TCK
@ R546 10K_0402_5% U31
+3.3V_LAN 48 13 LAN_TX0+
<18,20> LANCLK_REQ# 36 CLK_REQ_N MDI_PLUS0 14 LAN_TX0-
<19> PLTRST_LAN# PE_RST_N MDI_MINUS0
2 1 LAN_WAKE#_R CLK_PCIE_LAN 44 17 LAN_TX1+ +0.9V_LAN
<20> CLK_PCIE_LAN 45 PE_CLKP MDI_PLUS1 18
D @ R559 4.7K_0402_5% CLK_PCIE_LAN# LAN_TX1- D
<20> CLK_PCIE_LAN#
PCIE
PE_CLKN MDI_MINUS1
MDI
2 1 PCIE_PRX_GLANTX_P2_C L29
<22> PCIE_PRX_GLANTX_P2
C458 0.1U_0402_10V7K 38 20 LAN_TX2+ REGCTL_PNP10 1 2
2 1 PCIE_PRX_GLANTX_N2_C 39 PETp MDI_PLUS2 21 LAN_TX2- 4.7UH_CBC2012T4R7M_20%
<22> PCIE_PRX_GLANTX_N2 PETn MDI_MINUS2
10U_0603_6.3V6M
0.1U_0402_10V7K
C459 0.1U_0402_10V7K Idc max=330mA
1 2 PCIE_PTX_GLANRX_P2_C 41 23 LAN_TX3+ 1 1
+3.3V_LAN <22> PCIE_PTX_GLANRX_P2 PERp MDI_PLUS3
C462
C463
C460 0.1U_0402_10V7K 42 24 LAN_TX3-
1 2 PCIE_PTX_GLANRX_N2_C PERn MDI_MINUS3 @ R558 1 2 0_0402_5%
<22> PCIE_PTX_GLANRX_N2
C461 0.1U_0402_10V7K
2 2
10K_0402_5%
28 6 VCT_LAN_R1 @ R553 2 1 4.7K_0402_5% +3.3V_LAN
<21> LAN_SMBCLK
SMBUS
SMB_CLK SVR_EN_N
1
@ 31
<21> LAN_SMBDATA SMB_DATA
R549
SMBus Device Address 0xC8 1 +RSVD_VCC3P3_2 R554 2 1 4.7K_0402_5%
RSVD_VCC3P3_1
R556 1 2 0_0402_5% LAN_WAKE#_R 2 5
<51> LAN_WAKE# LAN_DISABLE#_R 3 LANWAKE_N VDD3P3_IN
2
<50> LAN_DISABLE#_R LAN_DISABLE_N 4 +3.3V_LAN_OUT @ R209 1 2 0_0603_1%
VDD3P3_4 +3.3V_LAN
1U_0603_10V7K
@ R555 1 2 0_0402_5% LAN_DISABLE#_R 15 1 Place R548, C462, C463 and L29 close to U31
<23> PM_LANPHY_ENABLE VDD3P3_15
LOM_ACTLED_YEL# 26 19
LED0 VDD3P3_19
C464
LOM_SPD100LED_ORG# 27 29
LED
10K_0402_5% LOM_SPD10LED_GRN# 25 LED1 VDD3P3_29
LED2
1
@ R557 2
47 +0.9V_LAN
VDD0P9_47 46
TP_LAN_JTAG_TDI 32 VDD0P9_46 37 +0.9V_LAN +3.3V_LAN
@ T142 PAD~D TP_LAN_JTAG_TDO 34 JTAG_TDI VDD0P9_37
2
JTAG
@ T143 PAD~D TP_LAN_JTAG_TMS 33 JTAG_TDO 43
TP_LAN_JTAG_TCK 35 JTAG_TMS VDD0P9_43
JTAG_TCK
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
22U_0805_6.3V6M
22U_0805_6.3V6M
11
VDD0P9_11
1 1 1 1 1
C1177
XTALO 9 40 1
XTAL_OUT VDD0P9_40
C466
C467
C468
C469
C1178
XTALI 10 22
XTAL_IN VDD0P9_22 16
VDD0P9_16 8 2 2 2 2 2
LAN_TEST_EN 30 VDD0P9_8 2
XTALO_R 1 2 XTALO TEST_EN
R1144 0_0402_5% RES_BIAS 12 7 REGCTL_PNP10
RBIAS CTRL0P9
C C
1K_0402_1%
3.01K_0402_1%
XTALI 49
VSS_EPAD
1
R561
R562
Crystal EA. WGI217LM-QPN9-A2_QFN48_6X6~D Note: +1.0V_LAN will work at 0.95V to 1.15V Place C1178 close to pin5
Y3
25MHZ_18PF_X3G025000DI1H-H
2
1 3
IN OUT +1.0V_LAN POWER OPTIONS
22P_0402_50V8J
27P_0402_50V8J
2 4 Shared with PCH

GND GND
1 1 * Internal SRV
1.05V SVR
C470
C471
2 2 STUFF: R548 STUFF: L29

NO STUFF: L29 NO STUFF: R548
+3.3V_ALW +3.3V_LAN
U63
+3.3V_LAN LAN ANALOG SWITCH <19,50> SIO_SLP_LAN#

SIO_SLP_LAN# 3
1
ON
7
VIN VOUT
10U_0603_6.3V6M
2 8
VIN VOUT
1
0.1U_0402_25V6K
0.1U_0402_25V6K
0.1U_0402_25V6K
C770
1 1 1
+5V_ALW 4
VBIAS 2
C472
C473
C474
5
6 GND 9
Layout Notice : Place bead as 2 2 2 CT GND
close PI3L720 as possible
470P_0402_50V7K
B 1 B
C547
39
30
21
14
8
4
1
U32
+3.3V_LAN
VDD
VDD
VDD
VDD
VDD
VDD
VDD
38 SW_LAN_TX3- 2 @ C478
B0+ 37 SW_LAN_TX3- <40> 1 2
SW_LAN_TX3+
B0- SW_LAN_TX3+ <40>
LAN_TX3- 1 2 LAN_TX3-R 2
L63 12NH_0603CS-120EJTS_5% A0+ 34 SW_LAN_TX2- 0.1U_0402_10V7K
B1+ SW_LAN_TX2- <40>
5
LAN_TX3+ 1 2 LAN_TX3+R 3 33 SW_LAN_TX2+
L64 12NH_0603CS-120EJTS_5% A0- B1- SW_LAN_TX2+ <40> LOM_SPD100LED_ORG# 1
P
29 SW_LAN_TX1- B 4
B2+ SW_LAN_TX1- <40> O WLAN_LAN_DISB# <50>
LAN_TX2- 1 2 LAN_TX2-R 6 28 SW_LAN_TX1+ LOM_SPD10LED_GRN# 2
A1+ B2- SW_LAN_TX1+ <40> A
G
L65 12NH_0603CS-120EJTS_5% U15
LAN_TX2+ 1 2 LAN_TX2+R 7 25 SW_LAN_TX0- TC7SH08FU_SSOP5~D
SW_LAN_TX0- <40>
3
L66 12NH_0603CS-120EJTS_5% A1- B3+ 24 SW_LAN_TX0+
B3- SW_LAN_TX0+ <40>
LAN_TX1- 1 2 LAN_TX1-R 9 17 LAN_ACTLED_YEL#
L67 12NH_0603CS-120EJTS_5% A2+ LEDB0 18 LED_100_ORG#
LAN_TX1+ 1 2 LAN_TX1+R 10 LEDB1 41 LED_10_GRN#
L68 12NH_0603CS-120EJTS_5% A2- LEDB2 Q327
36 DOCK_LOM_TRD3- Q325A L2N7002WT1G_SC-70-3
C0+ DOCK_LOM_TRD3- <48>
LAN_TX0- 1 2 LAN_TX0-R 11 35 DOCK_LOM_TRD3+ DMN66D0LDW-7_SOT363-6
A3+ C0- DOCK_LOM_TRD3+ <48>
D
L69 12NH_0603CS-120EJTS_5% LAN_ACTLED_YEL# 1 6 LED_10_GRN# 3 1
LAN_ACTLED_YEL#_Q <40> LED_10_GRN#_Q <40>
LAN_TX0+ 1 2 LAN_TX0+R 12 32 DOCK_LOM_TRD2-
L70 12NH_0603CS-120EJTS_5% A3- C1+ 31 DOCK_LOM_TRD2+ DOCK_LOM_TRD2- <48>
C1- DOCK_LOM_TRD2+ <48>
G
2
2
13 27 DOCK_LOM_TRD1-
<36,50> DOCKED SEL C2+ DOCK_LOM_TRD1- <48>
26 DOCK_LOM_TRD1+ TO DOCK SYS_LED_MASK#
C2- DOCK_LOM_TRD1+ <48> SYS_LED_MASK# <49,50,52>
SYS_LED_MASK#
LOM_ACTLED_YEL# 15 23 DOCK_LOM_TRD0-
16 LEDA0 C3+ 22 DOCK_LOM_TRD0- <48>
LOM_SPD100LED_ORG# DOCK_LOM_TRD0+
LEDA1 C3- DOCK_LOM_TRD0+ <48>
LOM_SPD10LED_GRN# 42
LEDA2 19 DOCK_LOM_ACTLED_YEL# Q325B
LEDC0 DOCK_LOM_ACTLED_YEL# <48>
5 20 DOCK_LOM_SPD100LED_ORG# DMN66D0LDW-7_SOT363-6
PD LEDC1 DOCK_LOM_SPD100LED_ORG# <48>
40 DOCK_LOM_SPD10LED_GRN# LED_100_ORG# 4 3
LEDC2 DOCK_LOM_SPD10LED_GRN# <48> LED_100_ORG#_Q <40>
43
PAD_GND
A 1: TO DOCK A
5
FROM NIC DOCKED SYS_LED_MASK#
0: TO RJ45
PI3L720ZHEX_TQFN42_9X3P5~D
CIS LINK OK
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, LAN/LAN SW
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5 4 3 2 1
5 4 3 2 1
+3.3V_LAN/+3.3V_LAN_LOM:20mils
+3.3V_LAN
D D
For IEEE EA request

NB_LAN_TX0+ 1 2 NB_LAN_TX0+_R
@ R575 0_0402_5% JLOM1 CONN@
NB_LAN_TX0- 1 2 NB_LAN_TX0-_R 1 2 13
<39> LAN_ACTLED_YEL#_Q Yellow_LED-
@ R576 0_0402_5% R1171 150_0402_5%
NB_LAN_TX1+ 1 2 NB_LAN_TX1+_R 12
@ R577 0_0402_5% Yellow_LED+
NB_LAN_TX1- 1 2 NB_LAN_TX1-_R NB_LAN_TX3- 8
@ R578 0_0402_5% PR4-
change TAIMAG to be main source NB_LAN_TX3+ 7
PR4+
T156 Placement close to T156 NB_LAN_TX1-_R 6
PR2-
NB_LAN_TX2- 5
SW_LAN_TX0+ 1 1:1 24 NB_LAN_TX0+ PR3-
<39> SW_LAN_TX0+ TD1+ TX1+ 4
NB_LAN_TX2+
PR3+
NB_LAN_TX1+_R 3
SW_LAN_TX0- 2 PR2+
<39> SW_LAN_TX0- TD1- 23 NB_LAN_TX0- NB_LAN_TX0-_R 2 15
TX1- PR1- SHLD2
C C
NB_LAN_TX0+_R 1 14
+TRM_CT1 3 22 Z2805 PR1+ SHLD1
TDCT1 TXCT1 1 2 10
<39> LED_10_GRN#_Q Green_LED-
R1170 150_0402_5%
+TRM_CT2 4 21 Z2807 9
SW_LAN_TX1+ 5 TDCT2 TXCT2 20 NB_LAN_TX1+ LED+
<39> SW_LAN_TX1+ TD2+ 1:1 TX2+
0.47U_0603_10V7K
0.47U_0603_10V7K
1 2 11
<39> LED_100_ORG#_Q ORANGE_LED-
R1167 150_0402_5%
1 1 SANTA_130454-H
C479
C480
SW_LAN_TX1- 6 19 NB_LAN_TX1- LInk CIS

<39> SW_LAN_TX1- TD2- TX2- +3.3V_LAN
2 2
1U_0603_10V6K
0.1U_0402_10V7K
470P_0402_50V7K
SW_LAN_TX2+ 7 1:1 18 NB_LAN_TX2+ 1 1 1
<39> SW_LAN_TX2+ TD3+ TX3+
C481
C483
C1167
SW_LAN_TX2- 8 2 2 2
<39> SW_LAN_TX2- TD3- 17 NB_LAN_TX2-
TX3-
B +TRM_CT3 9 16 Z2806 B
TDCT3 TXCT3
+TRM_CT4 10 15 Z2808
TDCT4 TXCT4
0.47U_0603_10V7K
75_0402_1%
75_0402_1%
75_0402_1%
75_0402_1%
SW_LAN_TX3+ 11 1:1 14 NB_LAN_TX3+
<39> SW_LAN_TX3+ TD4+ TX4+
0.47U_0603_10V7K
1 1
Close to JLOM1
C484
C486
SW_LAN_TX3- 12 13 NB_LAN_TX3-
2 2 <39> SW_LAN_TX3- TD4- TX4-
1
350uH_IH-115-F
R571 2
R572 2
R573 2
R574 2
1 2 GND_CHASSIS
EMC@ C485 150P_1808_3KV8J
A A
GND CHASSIS DELL CONFIDENTIAL/PROPRIETARY

RJ45

5 4 3 2 1
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5 4 3 2 1
D D
EMC request change main source

+5V_ESATA_PWR
to SM070001N00
+5V_ALW +5V_ALW_ESATA U48
PJP31 1 10
EMC@L51
EMC@ L51 EMC@D73
EMC@ D73
DLW21SN900SQ2L_0805_4P 2 1 +5V_ALW_ESATA 2 GND FAULT1# 9
2 1 IN OUT1
10U_0805_10V4Z
1 2 USBP8_D+ USBP8_D- 2 3 8
<22> USBP8+ 1 2 IN OUT2
0.1U_0402_16V4Z
1 JUMP_43X79 4 7
USBP8_D+ 3 5 EN1# ILIM 6
1 1 <50> ESATA_USB_PWR_EN# EN2# FAULT#2 USB_OC4# <22,49>
4 3 USBP8_D- 11
<22> USBP8- 4 3 T-PAD
C676
C675
24.9K_0402_1%
L30ESDL5V0C3-2_SOT23-3
1
TPS2560DRCR-PG1.1_SON10_3X3~D
2 2
R783
1 2 ESD request change main source
@ R736 0_0402_5%
1 2 to SCA00001L00
2
@ R742 0_0402_5%
+3.3V_RUN
C +3.3V_RUN +3.3V_RUN_PS8513 C
PJP9
PAD-OPEN1x1m ESATA_PE1 2 1
1 2 4.7K_0402_5% @ R44
ESATA_PE2 2 1
0.01U_0402_16V7K
0.1U_0402_25V6K
4.7K_0402_5% @ R43
1 1 CD 1 2
ESATA Repeater PS
0_0402_5%
1 2
@ R853
C661
C662
0_0402_5% @ R852
2 2
9/27
+5V_ESATA_PWR
CD 1 2
0_0402_5% R840
150U_D2_6.3VY_R15M
+3.3V_RUN_PS8513 @ C25 1 2 1U_0402_6.3V6K PS 1 2
0.1U_0402_16V4Z
U44 0_0402_5% R851
7 6 ESATA_PE1 2 1 1
EN VDD 16 4.7K_0402_5% @ R49
VDD 1
C667
C668
ESATA_PTX_DRX_P3_C 2 1 ESATA_PTX_DRX_P3 1 ESATA_PE2 2 1 +
<18> ESATA_PTX_DRX_P3_C A_INp
<18> ESATA_PTX_DRX_N3_C
ESATA_PTX_DRX_N3_C @ C663 2 1 0.01U_0402_16V7K ESATA_PTX_DRX_N3 2 10 4.7K_0402_5% @ R45
@ C664 0.01U_0402_16V7K A_INn NC/GND/VDD 17
NC/GND/VDD JESA1
ESATA_PRX_DTX_P3_C 2 1 ESATA_PRX_DTX_P3 5 18 CD 2 2
<18> ESATA_PRX_DTX_P3_C ESATA_PRX_DTX_N3_C @ C666 2 1 0.01U_0402_16V7K ESATA_PRX_DTX_N3 4 B_OUTpNC/GND/VDD 19 PS 1 USB
<18> ESATA_PRX_DTX_N3_C @ C665 0.01U_0402_16V7K B_OUTnNC/GND/VDD 20 USBP8_D- 2 USB_V
ESATA_PE1 9 NC/GND/VDD USBP8_D+ 3 USB_D-
ESATA_PE2 8 A_PRE 15 ESATA_PTX_DRX_P3_RP 4 USB_D+
B_PRE A_OUTp 14 ESATA_PTX_DRX_N3_RP USB_GND
3 A_OUTn 5
13 GND 11 ESATA_PRX_DTX_P3_RP ESATA_PTX_DRX_P3_RP @ C671 1 2 0.01U_0402_16V7K SATA_PTX_DRX_P3 6 GND
21 GND B_INp 12 ESATA_PRX_DTX_N3_RP ESATA_PTX_DRX_N3_RP @ C672 1 2 0.01U_0402_16V7K SATA_PTX_DRX_N3 7 A+ ESATA
EPAD B_INn 8 A- 12
PS8513CTQFN20GTR2-A_TQFN20_4X4 ESATA_PRX_DTX_N3_RP @ C673 1 2 0.01U_0402_16V7K SATA_PRX_DTX_N3 9 GND GND 13
B ESATA_PRX_DTX_P3_RP @ C674 1 2 0.01U_0402_16V7K SATA_PRX_DTX_P3 10 B- GND 14 B
CIS LINK OK B+ GND
11 15
GND GND
TAIWI_EU093-117CRL-TW
LInk CIS
CONN@
R827 1 2 0_0402_5% ESATA_PTX_DRX_P3_BP C679 1 2 0.01U_0402_16V7K

R828 1 2 0_0402_5% ESATA_PTX_DRX_N3_BP C678 1 2 0.01U_0402_16V7K
R842 1 2 0_0402_5% ESATA_PRX_DTX_N3_BP C680 1 2 0.01U_0402_16V7K
R844 1 2 0_0402_5% ESATA_PRX_DTX_P3_BP C677 1 2 0.01U_0402_16V7K

C665.2 close to R842.1 Reserve bypass ESATA Repeater C680.2 close to C673.2
A A
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL ESATA
www.Vinafix.vn
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD LA-9781P 0.2
5 4 3 2 1
5 4 3 2 1
@ R94 1 2 0_0402_5%
Change power net to meet USB1 repeater VDD @ Q90 +3.3V_ALW EMC request change main source
DMG2301U-7_SOT23-3
+USB1_repeater_VDD +3.3V_RUN to SM070001N00
PJP34 +USB1_repeater_VDD 1 3 EMC@ L39
S
PAD-OPEN1x1m 3 4 USBP0_D-
<22> USBP0- 3 4
1 2 USB1_A_EQ1 2 1
@ R22 4.7K_0402_5% Reserve for USB3 reconnect issue from S3 to S0
G
2
0.01U_0402_16V7K
0.1U_0402_16V4Z
1 2 USB1_A_DE0 SHORT DEFAULT 2 1 USBP0_D+
<22> USBP0+ 2 1
@ R23 4.7K_0402_5% USB_SIDE_EN#
1 2 USB1_A_EQ0
1 1
DLW21SN900SQ2L_0805_4P For ESD request
+5V_USB_PWR1
C453
C450
@ R24 4.7K_0402_5%
1 2 USB1_A_DE1 1 2 EMC@ D14 JUSB1
@ R25 4.7K_0402_5% 2 2 @ R749 0_0402_5% USB3_TX1_P_D+ 9 1 USB3_TX1_P_D+ 1
1 2 USB1_TEST 1 2 USBP0_D- 2 VBUS
D @ R12 4.7K_0402_5% LInk CIS ok @ R748 0_0402_5% USB3_TX1_N_D- 8 2 USB3_TX1_N_D- USBP0_D+ 3 D-
D
1 2 USB1_B_EQ1 U625 4 D+
@ R15 4.7K_0402_5% 1 USB3_RX1_P_D+ 7 4 USB3_RX1_P_D+ USB3_RX1_N_D- 5 GND
1 2 USB1_B_DE0 13 VDD USB3_RX1_P_D+ 6 SSRX- 10
@ R16 4.7K_0402_5% VDD EMC@ L42 USB3_RX1_N_D- 6 5 USB3_RX1_N_D- 7 SSRX+ GND 11
1 2 USB1_B_EQ0 USB3TN1_RP 3 4 USB3_TX1_N_D- USB3_TX1_N_D- 8 GND GND 12
@ R18 4.7K_0402_5% USB1_A_EQ1 15 4 USB1_B_EQ1 3 4 USB3_TX1_P_D+ 9 SSTX- GND 13
1 2 USB1_B_DE1 USB1_A_DE0 16 A_EQ1/SDA_CTL B_EQ1/I2C_ADDR1 3 USB1_B_DE0 SSTX+ GND
@ R21 4.7K_0402_5% USB1_A_EQ0 17 A_DE0/SCL_CTL B_DE0/I2C_ADDR0 2 USB1_B_EQ0 USB3TP1_RP 2 1 USB3_TX1_P_D+ 3 LOTES_AUSB0041-P002A
USB1_A_DE1 18 A_EQ0/NC B_EQ0/NC 6 USB1_B_DE1 2 1
A_DE1/NC B_DE1/NC DLW21SN900HQ2L_0805_4P TVWDF1004AD0_DFN9 LInk CIS ok
CONN@
2
C454 2 1 0.1U_0402_10V7K USB3TP1_C 19 12 USB3TP1_RP_C C489 2 1 0.1U_0402_10V7K USB3TP1_RP
<22> USB3TP1 A_INp A_OUTp
EMC@ D15
C452 2 1 0.1U_0402_10V7K USB3TN1_C 20 11 USB3TN1_RP_C C488 2 1 0.1U_0402_10V7K USB3TN1_RP 1 2
<22> USB3TN1 A_INn A_OUTn @ R743 0_0402_5%
1 2
USB3RP1_RP R831 1 2 0_0402_5% USB3RP1_RP_R 9 22 USB3RP1_C C465 2 1 0.1U_0402_10V7K
USB3RP1 <22> @ R744 0_0402_5% ESD request change main source
USB3RN1_RP R830 1 2 0_0402_5% USB3RN1_RP_R 8 B_INp B_OUTp 23 USB3RN1_C C487 2 1 0.1U_0402_10V7K +5V_USB_PWR1
1 2 USB1_B_DE1 B_INn B_OUTn USB3RN1 <22> to SC300002800
@ R773 0_0402_5%
1 2 USB1_A_DE1 5 EMC@ L40
1
PD#
220U_6.3V_M
10U_0603_6.3V6M
@ R809 0_0402_5% 7 10 USB3RN1_RP 3 4 USB3_RX1_N_D- 1
1 2 USB1_B_DE0 USB1_TEST 14 REXT GND 21 3 4
TEST GND 1
4.99K_0402_1%
C324
C793
@ R103 4.7K_0402_5% 24 25 +
I2C_EN GPAD
2
2K_0402_5%
0_0402_5%
1 2 USB1_A_DE0 @ @ USB3RP1_RP 2 1 USB3_RX1_P_D+
2 1 ESD request change main source
R2201
R2200
@ R104 4.7K_0402_5% PS8713BTQFN24GTR2_TQFN24_4X4
2 2
R1207
1 2 USB1_B_EQ0 DLW21SN900HQ2L_0805_4P
@ R105 4.7K_0402_5% to SCA00001L00
1 2 USB1_A_EQ0 For Parade USB3 xHCI controller issue and 1 2
1
@ R106 4.7K_0402_5% @ R746 0_0402_5%
1 2 USB1_B_EQ1 change repeater to 8713 1 2
@ R107 4.7K_0402_5% @ R745 0_0402_5%
1 2 USB1_A_EQ1 CIS not link ready
@ R108 4.7K_0402_5% +5V_ALW
Close to JUSB1
100K_0402_5%
2
+5V_USB_PWR2 +5V_USB_PWR1
<50> USB_PWR_SHR_EN#
<50> USB_PWR_SHR_VBUS_EN
R816
C C
1
0_0402_5%
@ R1626
+5V_ALW +5V_ALW_FUSE U45
PJP30 1 10
Power share SW
1
2 1 2 GND FAULT1# 9
2 1 3 IN OUT1 8
IN OUT2 7
10U_0805_10V4Z
0.1U_0402_16V4Z
JUMP_43X79 PWRSHARE_EN# 4 PWRSHARE_EN#

change SILEGO to be main source
2
USB_SIDE_EN# 5 EN1# ILIM 6
1 1 <49,50> USB_SIDE_EN# EN2# FAULT#2 11 USB_OC0# <22>
C669
C670
T-PAD
1
D
24.9K_0402_1%
U2
Q55
TPS2560DRCR_SON10_3X3~D SB# 8 1 2
2 2 7 CB CEN 2 USBP1_D- G
R747
LInk CIS ok <22> USBP1-
<22> USBP1+
6 TDM DM 3 USBP1_D+ S
3
5 TDP DP 4 SEL
+5V_ALW VDD SELCDP 9
2
Thermal Pad +5V_ALW
SLGC55584AVTR_TDFN8_2X2
10K_0402_5%
Change power net to meet USB2 repeater VDD
2
0.1U_0402_25V6K
1
R1614
PN change to SA00006L600,
C715
+USB2_repeater_VDD
2 wait symbol release.
1
1 2 USB2_A_EQ1
@ R31 4.7K_0402_5% @ R95 1 2 0_0402_5%
1 2 USB2_A_DE0
Reserve for USB3 reconnect issue from S3 to S0
1
@ R32 4.7K_0402_5% @ Q91 +3.3V_ALW D
@
1 2 USB2_A_EQ0 DMG2301U-7_SOT23-3 R1613 2 SB#
@ R33 4.7K_0402_5% +3.3V_RUN 10K_0402_5% G @ Q338
1 2 USB2_A_DE1 PJP35 +USB2_repeater_VDD 1 3 DMN65D8LW-7_SOT323-3
D
3
@ R34 4.7K_0402_5% PAD-OPEN1x1m
1
1 2 USB2_TEST 2 1
@ R26 4.7K_0402_5% EMC request change main source
G
2
0.01U_0402_16V7K
0.1U_0402_16V4Z
1 2 USB2_B_EQ1
@ R27 4.7K_0402_5% SHORT DEFAULT 1 1 PWRSHARE_EN# to SM070001N00 Reserve for samsung mobile issue
1 2 USB2_B_DE0
For SILEGO power share SW EA Samsung mobile can’t recognize on USB during S0
C455
C451
@ R28 4.7K_0402_5%
1 2 USB2_B_EQ0 OCE2012120YZF_4P
B
@ R29 4.7K_0402_5% 2 2 USBP1_D- 3 4 USBP1_R_D- Add MOSFET to control charger mode to fix on SDP during S0 for Pericom & Maxim B
1 2 USB2_B_DE1 LInk CIS ok

@ R30 4.7K_0402_5%
U626 USBP1_D+ 2 1 USBP1_R_D+ +5V_USB_PWR2
1 JUSB2
13 VDD EMC@ L41 1
1 2 USB2_B_DE1 VDD USBP1_R_D- 2 VBUS
@ R813 0_0402_5% 1 2 USBP1_R_D+ 3 D-
1 2 USB2_A_DE1 USB2_A_EQ1 15 4 USB2_B_EQ1 @ R754 0_0402_5% 4 D+
@ R826 0_0402_5% USB2_A_DE0 16 A_EQ1/SDA_CTL B_EQ1/I2C_ADDR1 3 USB2_B_DE0 1 2 USB3_RX2_N_D- 5 GND
1 2 USB2_B_DE0 USB2_A_EQ0 17 A_DE0/SCL_CTL B_DE0/I2C_ADDR0 2 USB2_B_EQ0 @ R764 0_0402_5% USB3_RX2_P_D+ 6 SSRX- 10
@ R112 4.7K_0402_5% USB2_A_DE1 18 A_EQ0/NC B_EQ0/NC 6 USB2_B_DE1 7 SSRX+ GND 11
1 2 USB2_A_DE0 A_DE1/NC B_DE1/NC USB3_TX2_N_D- 8 GND GND 12
@ R113 4.7K_0402_5% C457 2 1 0.1U_0402_10V7K USB3TP2_C 19 12 USB3TP2_RP_C C493 2 1 0.1U_0402_10V7K USB3TP2_RP USB3_TX2_P_D+ 9 SSTX- GND 13
<22> USB3TP2 A_INp A_OUTp DLW21SN900HQ2L_0805_4P SSTX+ GND
1 2 USB2_B_EQ0 C456 2 1 0.1U_0402_10V7K USB3TN2_C 20 11 USB3TN2_RP_C C492 2 1 0.1U_0402_10V7K USB3TN2_RP
@ R110 4.7K_0402_5%
<22> USB3TN2 A_INn A_OUTn USB3TN2_RP 2 1 USB3_TX2_N_D- For ESD request LOTES_AUSB0041-P002A
1 2 USB2_A_EQ0 2 1
@ R114 4.7K_0402_5% USB3RP2_RP R833 1 2 0_0402_5% USB3RP2_RP_R 9 22 USB3RP2_C C490 2 1 0.1U_0402_10V7K
USB3RP2 <22> EMC@ D16 LInk CIS ok
CONN@
1 2 USB2_B_EQ1 USB3RN2_RP R832 1 2 0_0402_5% USB3RN2_RP_R 8 B_INp B_OUTp 23 USB3RN2_C C491 2 1 0.1U_0402_10V7K USB3TP2_RP 3 4 USB3_TX2_P_D+ USB3_TX2_P_D+ 9 1 USB3_TX2_P_D+
USB3RN2 <22>
2
B_INn B_OUTn 3 4
@ R109 4.7K_0402_5%
EMC@ L44
EMC@ D17
1 2 USB2_A_EQ1 USB3_TX2_N_D- 8 2 USB3_TX2_N_D-
@ R111 4.7K_0402_5% 5 +5V_USB_PWR2
7 PD# 10 1 2 USB3_RX2_P_D+ 7 4 USB3_RX2_P_D+
USB2_TEST 14 REXT GND 21 @ R750 0_0402_5%
TEST GND
4.99K_0402_1%
24 25 1 2 USB3_RX2_N_D- 6 5 USB3_RX2_N_D-
I2C_EN GPAD
2
2
2K_0402_5%
0_0402_5%
220U_6.3V_M
10U_0603_6.3V6M
@ @ @ R751 0_0402_5% 1
R2203
R2202
PS8713BTQFN24GTR2_TQFN24_4X4 1
R1191
C323
C794
+
For Parade USB3 xHCI controller issue and
1
3
change repeater to 8713
1
DLW21SN900HQ2L_0805_4P TVWDF1004AD0_DFN9 2 2
USB3RN2_RP 2 1 USB3_RX2_N_D-
Parade_PS8713B CIS not link ready 2 1
@ R857 1 2 0_0402_5% USB3TP2_BP @ C535 2 1 0.1U_0402_10V7K ESD request change main source
@ R856 1 2 0_0402_5% USB3TN2_BP @ C537 2 1 0.1U_0402_10V7K USB3RP2_RP 3 4 USB3_RX2_P_D+ ESD request change main source
3 4 to SCA00001L00
A EMC@ L43 to SC300002800 A
A_EQ0 A_EQ1 B_EQ0 B_EQ1 Recommended EQ @ R855 1 2 0_0402_5% USB3RP2_BP @ R863 1 2 0_0402_5%
@ R854 1 2 0_0402_5% USB3RN2_BP @ R862 1 2 0_0402_5% 1 2 Close to JUSB2
@ R752 0_0402_5%
0 0 0 0 loss up to 9.5dB 1 2
R857.1 close to C457.2 C535.1 close to C493.1 @ R753 0_0402_5%
R856.1 close to C456.2 Reserve bypass USB3.0 Repeater C537.1 close to C492.1
0 1 0 1 loss up to 4.5dB R855.1 close to R833.1 R863.2 close to C490.1
R854.1 close to R832.1 R863.2 close to C491.1 DELL CONFIDENTIAL/PROPRIETARY
1 0 1 0 loss up to 13dB Compal Electronics, Inc.
Title
1 1 1 1 loss up to 7.5dB PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
USB3.0
Both A_EQ&B_EQ have internal pull-down 150k NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD LA-9781P 0.2
5 4 3 2 1
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5 4 3 2 1
+3.3V_RUN +3.3V_RUN_TPM
PJP77
1 2
PAD-OPEN1x1m
SHORT DEFAULT +3.3V_SUS
D USH_SMBCLK 2 1 D
2.2K_0402_5% R589
USH_SMBDAT 2 1
2.2K_0402_5% R585
JUSH1 CONN@
+3.3V_RUN_TPM +3.3V_RUN_TPM 1
2 1
<22> USBP7-
3 2 2
ATMEL TPM for E4 +3.3V_SUS <22> USBP7+
4 3
5 4 4
0.1U_0402_25V6K
4700P_0402_25V7K
<51> USH_SMBCLK
6 5
2200P_0402_50V7K
2200P_0402_50V7K
2200P_0402_50V7K
0.1U_0402_25V6K
<51> USH_SMBDAT
1 1 7 6 6
<50> BCM5882_ALERT# 8 7
0.1U_0402_25V6K
U39 1 1 1 1
9 8 8
C48
C45
C553
@
10 9
C550
C551
C552
10 1
2 2 VCC_0 11 10 10
C55
1 2 5 19 @ R221 1 2 0_0402_5%
<23> PCH_TPM_EN SB3V VCC_1 <53> BT_COEX_STATUS2
@ R2195 0_0402_5% 24 2 2 2 2 12 11
VCC_2 <53> BT_PRI_STATUS 13 12 12
1 2 2 14 13
<19> SUS_STAT#/LPCPD#
@ R2194 0_0402_5% 15 14 14
<19> PLTRST_USH# 16 15
1 2 SP_TPM_LPC_EN_R 28 12 <50> USH_PWR_STATE# 17 16 16
<50> SP_TPM_LPC_EN LPCPD# V_BAT <23> CONTACTLESS_DET#
R2188 0_0402_5% 13 +3.3V_RUN 18 17
NBO_13 JETWAY_CLK14M <20>
LPC_LAD0 26 14 19 18 18
<21,45,50,51> LPC_LAD0 LAD0 NBO_14
LPC_LAD1 23 +5V_RUN 20 19
<21,45,50,51> LPC_LAD1 LAD1 <23> USH_DET# 20 20
0.1U_0402_25V6K
LPC_LAD2 20
<21,45,50,51> LPC_LAD2 LAD2
LPC_LAD3 17 21
<21,45,50,51> LPC_LAD3 LAD3 G1
0.1U_0402_25V6K
6 1 22
GPIO6 G2
C51
23
CLK_PCI_TPM 21 9 1 2 G3 24
<20> CLK_PCI_TPM LCLK TESTBI 1 G4
C54
LPC_LFRAME# 22 8 R657 4.7K_0402_5%
<21,45,50,51> LPC_LFRAME# LFRAME# TESTI 2
PCH_PLTRST#_EC 16 E-T_6700K-Y20N-00L
<19,44,45,49,50,51> PCH_PLTRST#_EC LRESET#
IRQ_SERIRQ 27
<21,50,51> IRQ_SERIRQ SERIRQ 2
CLKRUN# 15 CIS LINK OK
C <19,50,51> CLKRUN# CLKRUN# C
7
NC_7
CLK_PCI_TPM 1 4
2 ATEST_1 GND_4 11
3 ATEST_2 GND_11 18
ATEST_3 GND_18
33_0402_5%
25
GND_25
1
@RE5
@
AT97SC3204-X2A18-AB_TSSOP28
RE5
Change U39 TPM solution to SA00004WQ40

2
AT97SC3204-DX4A12-ABF
27P_0402_50V8J
1
@ CE3
Check ME about wire to board PN

JAPS1
+3.3V_ALW_PCH 1
2 1
<19,49,50,54,59> SIO_SLP_S3# 2
+PCH_VCCDSW3_3 3
4 3
B B
<19,51> SIO_SLP_S5# 4
5
<19,50,54,57> SIO_SLP_S4# 5
6
<19,50,54,58> SIO_SLP_A# 6
+3.3V_ALW 7
8 7
9 8
<18> PCH_RTCRST# 9
10
11 10
<49,51> POWER_SW#_MB 11
12
13 12
<19> SYS_RESET# 13
14
15 14
16 15
16
17
18 GND
GND
TYCO_1-2041070-6~D
CONN@
A A
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BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, TPM
LA-9781P 0.2

5 4 3 2 1
5 4 3 2 1
Mini WWAN/GPS/LTE H= 4 mm
+3.3V_PCIE_WWAN +3.3V_PCIE_WWAN
JMINI1 CONN@
PCIE_WAKE# 1 2
3 1 2 4
5 3 4 6
D
MINI1CLK_REQ# 7 5 6 8 D
<20> MINI1CLK_REQ# 7 8 +SIM_PWR
9 10 UIM_DATA
CLK_PCIE_MINI1# 11 9 10 12 UIM_CLK
<20> CLK_PCIE_MINI1# CLK_PCIE_MINI1 13 11 12 14 UIM_RESET
<20> CLK_PCIE_MINI1 15 13 14 16 +UIM_VPP
17
19
21
15
17
19
16
18
20
18
20
22
WWAN_RADIO_DIS# <50>
SIM Card Push-Push type
PCIE_PRX_WANTX_N5 23 21 22 24 PCH_PLTRST#_EC <19,43,45,49,50,51>
<22> PCIE_PRX_WANTX_N5 PCIE_PRX_WANTX_P5 25 23 24 26 +SIM_PWR
<22> PCIE_PRX_WANTX_P5 27 25 26 28
C597 0.1U_0402_10V7K 29 27 28 30 JSIM1 CONN@
PCIE_PTX_WANRX_N5 1 2 PCIE_PTX_WANRX_N5_C 31 29 30 32 1
<22> PCIE_PTX_WANRX_N5 1 2 PCIE_PTX_WANRX_P5_C 33 31 32 34 2 VCC 11
PCIE_PTX_WANRX_P5 UIM_RESET
<22> PCIE_PTX_WANRX_P5 33 34 RST GND_2
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
C599 0.1U_0402_10V7K 35 36 USBP5- UIM_CLK 3 12
35 36 USBP5- <22> CLK GND_3
EMC@ C616
MXM_PIN80_R 37 38 USBP5+ +3.3V_PCIE_WWAN 4 13
37 38 USBP5+ <22> D+ GND_4
39 40 1 1 1 5 14
39 40 GND_1 GND_5
@ C645
@ C643
41 42 LED_WWAN_OUT# +UIM_VPP 6 15
43 41 42 44 UIM_DATA 7 VPP GND_6 16
45 43 44 46 8 I/O GND_7 17
45 46 2 2 2 D- GND_8
100K_0402_5%
33P_0402_50V8J
33P_0402_50V8J
33P_0402_50V8J
33P_0402_50V8J
47 48 9 18
47 48 DET GND_9
2
49 50 1 1 1 1 10
49 50 COM
R719
@ C629
@ C628
@ C630
@ C631
51 52
<50> HW_GPS_DISABLE2# 51 52
53 54 T-SOL_159-1000302602
GND1 GND2
2
2 2 2 2
G
1
LCN_DAN08-52526-0100
LED_WWAN_OUT# 3 1 LInk CIS
LInk CIS WIRELESS_LED# <50,52>
D
<32> 3D_ON
Q77
2
G
3 1 MXM_PIN80_R
<17> MXM_PIN80
S
Q85 +3.3V_PCIE_WWAN
1 DMN65D8LW-7_SOT323-3
2
0_0402_5% R1161 @
Primary Power Aux Power

0.047U_0402_16V4Z
0.047U_0402_16V4Z
33P_0402_50V8J
22U_0805_6.3V6M
33P_0402_50V8J
220U_6.3V_M
330U_D2E_6.3VM_R25
PWR Voltage
EMC@ C610
EMC@ C611
EMC@ C612
EMC@ C613
EMC@ C614
EMC@ C615
1 1 Rail Tolerance
1 1 1 1 1 Peak Normal Normal
@ C1176
+ +
2 2 2 2 2 2 2
+3.3V +-9% 1000 750
C 250 (Wake enable) C
+3.3Vaux +-9% 330 250 5 (Not wake enable)
+1.5V +-5% 500 375 NA
+3.3V_WLAN
1 2 2 1 WLAN_RADIO_DIS#_R
@ R697 0_0402_5% R728 100K_0402_5%
2 1 WIGIG60GHZ_DIS#_R
1 2 WLAN_RADIO_DIS#_R R725 100K_0402_5%
Mini WLAN/WIMAX/WiGig H=5.2 <50> WLAN_RADIO_DIS#
D31
1
@ R695
2
0_0402_5%
RB751V40_SC76-2
R727
2 1 BT_RADIO_DIS#_R
100K_0402_5%
+3.3V_WLAN +3.3V_WLAN 1 2 WIGIG60GHZ_DIS#_R

<50> WIGIG60GHZ_DIS#
D35 RB751V40_SC76-2
1 2 +3.3V_RUN
JMINI2 CONN@ @ R696 0_0402_5%
1 2
<17,45,49,51> PCIE_WAKE# 3 1 2 4 1 2 BT_RADIO_DIS#_R 2 1 CPPE#
<53> COEX2_WLAN_ACTIVE 3 4 <50,53> BT_RADIO_DIS#
5 6 D36 RB751V40_SC76-2 R823 10K_0402_5%
<53> COEX1_BT_ACTIVE 7 5 6 8 2 1 USB_MCARD1_DET#
<20> MINI2CLK_REQ# 9 7 8 10 R824 10K_0402_5%
11 9 10 12
<20> CLK_PCIE_MINI2# 13 11 12 14 MSDATA
<20> CLK_PCIE_MINI2 15 13 14 16
17 15 16 18 HOST_DEBUG_TX <51>
B <50,51> EC5048_TX 19 17 18 20 WLAN_RADIO_DIS#_R
B
<51> MSCLK 21 19 20 22 PCH_PLTRST#_EC
23 21 22 24
<22> PCIE_PRX_WLANTX_N3 25 23 24 26
<22> PCIE_PRX_WLANTX_P3 27 25 26 28
C596 0.1U_0402_10V7K 29 27 28 30 +3.3V_WLAN
1 2 PCIE_PTX_WLANRX_N3_C 31 29 30 32 WIGIG60GHZ_DIS#_R
<22> PCIE_PTX_WLANRX_N3 1 2 PCIE_PTX_WLANRX_P3_C 33 31 32 34 Add WiGig card function
<22> PCIE_PTX_WLANRX_P3 35 33 34 36
C598 0.1U_0402_10V7K USBP4-
35 36 USBP4- <22>
100K_0402_5%
100K_0402_5%
100K_0402_5%
CPPE# 37 38 USBP4+
<19> CPPE# 37 38 USBP4+ <22>
2
39 40 USB_MCARD1_DET#
39 40 USB_MCARD1_DET# <19>
R726
R718
R705
41 42 WIGIG_LED#
43 41 42 44 WLAN_LED#
45 43 44 46 BT_LED#
<21> PCH_CL_CLK1 45 46
5
47 48
<21> PCH_CL_DATA1
1
1 2 49 47 48 50 1 2 MSDATA
<21> PCH_CL_RST1# 51 49 50 52 MSDATA <51> 4 3
@ R709 0_0402_5% @ R706 0_0402_5% WIGIG_LED# WIRELESS_LED#
BT_RADIO_DIS#_R 51 52
53 54 Q124B
GND1 GND2
2
Add WiGig card function LCN_DAN08-52526-0100
WLAN_LED# 1 6
LInk CIS
Q124A
2
G
BT_LED# 3 1
BT_LED#_R <52>
D
COEX2_WLAN_ACTIVE +3.3V_WLAN HOST_DEBUG_TX
Q89
4700P_0402_25V7K
33P_0402_50V8J
0.047U_0402_16V4Z
0.047U_0402_16V4Z
0.1U_0402_25V6K
0.1U_0402_25V6K
4.7U_0603_6.3V6K
0.1U_0402_25V6K
1
1
@ C601
C595
1 1 1 2 2 1
@ C603
2
C604
C605
C606
C607
C608
2
2 2 2 1 1 2
A A
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Mini Card-1/2

5 4 3 2 1
5 4 3 2 1
Pink Pather H=5.2

+3.3V_PCIE_FLASH +3.3V_PCIE_FLASH
JMINI3
1 2
<17,44,49,51> PCIE_WAKE# 3 1 2 4
5 3 4 6
MINI3CLK_REQ# 7 5 6 8
<20> MINI3CLK_REQ# 9 7 8 10
D
CLK_PCIE_MINI3# 11 9 10 12 D
<20> CLK_PCIE_MINI3# 13 11 12 14
CLK_PCIE_MINI3
<20> CLK_PCIE_MINI3 15 13 14 16
17 15 16 18
19 17 18 20
21 19 20 22
23 21 22 24 PCH_PLTRST#_EC <19,43,44,45,49,50,51>
PCIE_PRX_WPANTX_N6
<22> PCIE_PRX_WPANTX_N6 PCIE_PRX_WPANTX_P6 25 23 24 26
<22> PCIE_PRX_WPANTX_P6 27 25 26 28
29 27 28 30
@ C636 1 2 0.1U_0402_10V7K PCIE_PTX_WPANRX_N6_C 31 29 30 32
<22> PCIE_PTX_WPANRX_N6 31 32
@ C626 1 2 0.1U_0402_10V7K PCIE_PTX_WPANRX_P6_C 33 34
<22> PCIE_PTX_WPANRX_P6 35 33 34 36
37 35 36 38
39 37 38 40
41 39 40 42
43 41 42 44
45 43 44 46
47 45 46 48
49 47 48 50
51 49 50 52
51 52
53 54
GND1 GND2
LCN_DAN08-52526-0100
LInk
CONN@
CIS
+3.3V_PCIE_FLASH
0.047U_0402_16V4Z
0.047U_0402_16V4Z
0.1U_0402_25V6K
0.1U_0402_25V6K
4.7U_0603_6.3V6K
0.1U_0402_25V6K
1 @ 1 1 2 @ 2 @ 1 @
@ @
C639
C634
C624
C637
C638
C633
C 2 2 2 1 1 2 C
mSATA H=5.2
+3.3V_PCIE_NVM +3.3V_PCIE_NVM
JMINI4
1 2
3 1 2 4
5 3 4 6
EMBCLK_REQ# 7 5 6 8 LPC_LFRAME#
<20> EMBCLK_REQ# 9 7 8 10 LPC_LFRAME# <21,43,50,51>
LPC_LAD3
11 9 10 12 LPC_LAD3 <21,43,50,51>
CLK_PCIE_NVR# LPC_LAD2
<20> CLK_PCIE_NVR# CLK_PCIE_NVR 13 11 12 14 LPC_LAD1 LPC_LAD2 <21,43,50,51>
B <20> CLK_PCIE_NVR 15 13 14 16 LPC_LAD1 <21,43,50,51> B
LPC_LAD0
17 15 16 18 LPC_LAD0 <21,43,50,51>
PCH_PLTRST#_EC
PCLK_80H 19 17 18 20
<20> PCLK_80H 21 19 20 22
1 2 C447 mSATA_PRX_DTX_P4 23 21 22 24 PCH_PLTRST#_EC <19,43,44,45,49,50,51>
0.01U_0402_16V7K
<18> mSATA_PRX_DTX_P4_C 0.01U_0402_16V7K 1 2 C448 mSATA_PRX_DTX_N4 25 23 24 26
<18> mSATA_PRX_DTX_N4_C 27 25 26 28
29 27 28 30
0.01U_0402_16V7K 1 2 C445 mSATA_PTX_DRX_N4 31 29 30 32
<18> mSATA_PTX_DRX_N4_C 1 2 C446 mSATA_PTX_DRX_P4 33 31 32 34
0.01U_0402_16V7K
<18> mSATA_PTX_DRX_P4_C 35 33 34 36
37 35 36 38
39 37 38 40
41 39 40 42
43 41 42 44
45 43 44 46
47 45 46 48
49 47 48 50
MSATA_PCIE_PIN51 51 49 50 52
<50> MSATA_PCIE_PIN51 51 52
53 54
GND1 GND2
"LOW"=SATA; "HIGH"=PCIe LCN_DAN08-52526-0100
Check Samsung SSD card LInk

CONN@
CIS
Insert card, pin51=low +3.3V_PCIE_NVM
Pull out card, pin51=high
0.047U_0402_16V4Z
0.047U_0402_16V4Z
330U_V_6.3VM
33P_0402_50V8J
22U_0805_6.3VAM
33P_0402_50V8J
1
@
1 1 1 1 1
C619
+
C623
C621
C618
C622
C617
2 2 2 2 2 2
A A
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BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Mini Card-2/2

5 4 3 2 1
5 4 3 2 1
D D
Power Control for Mini card1

+3.3V_ALW +3.3V_PCIE_WWAN
+3.3V_ALW U42 +3.3V_WLAN
U43
1 2 AUX_EN_WOWL_R 3
<50> AUX_EN_WOWL ON
R839 0_0402_5% MCARD_WWAN_PWREN 3
<50> MCARD_WWAN_PWREN ON
1
100K_0402_5%
1 7
VIN VOUT
1
100K_0402_5%
10U_0603_6.3V6M
1 2 1 7
<19> SIO_SLP_WLAN# VIN VOUT
R720
@R815
@ R815 0_0402_5% 2 8 1
R717 VIN VOUT
C536
10U_0603_6.3V6M
2 8
VIN VOUT
1
2
2
C762
+5V_ALW 4
VBIAS 5 4
GND +5V_ALW VBIAS 2
6 9 5
CT GND 6 GND 9
CT GND
470P_0402_50V7K
2
470P_0402_50V7K
TPS22965DSGR_SON8_2X2~D 1
C538
C541
1
2
C C
+3.3V_ALW +3.3V_PCIE_NVM
U49
NVRAM_PWR_EN 3
<50> NVRAM_PWR_EN ON
B B
1 7
VIN VOUT
100K_0402_5%
1
10U_0603_6.3V6M
2 8
VIN VOUT
R739
1
C764
+5V_ALW 4
2
VBIAS 5 2
6 GND 9
CT GND
470P_0402_50V7K
1
C542
A A
www.Vinafix.vn
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Mini Card PWR
LA-9781P 0.2

5 4 3 2 1
5 4 3 2 1
+3.3V_RUN
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 1 1 1
C495
C499
C504
C494
C783
2 2 2 2 2
+3.3V_RUN
D
U629 CIS LINK OK D
21
26 VDD33
35 VDD33
49 VDD33 32 MUX_AUX
60 VDD33 OUT_AUXp_SCL 31 MUX_AUX# MUX_AUX <36>
VDD33 OUT_AUXn_SDA MUX_AUX# <36>
IN2_PEQ 51 MUX_PC0 @ R98 1 24.7K_0402_5%
IN1_PEQ 52 IN2_PEQ/SCL_CTL 53 MUX_PC1 @ R99 1 24.7K_0402_5%
IN1_AEQ# 59 IN1_PEQ/SDA_CTL I2C_CTL_EN IN1_AEQ# @ R117 1 24.7K_0402_5%
IN2_AEQ# 58 IN1_AEQ# IN2_AEQ# @ R118 1 24.7K_0402_5%
IN2_AEQ# 56 MUX_PI0 IN1_PEQ @ R119 1 24.7K_0402_5%
PI0 38 MUX_PC0 IN2_PEQ @ R120 1 24.7K_0402_5%
MXM_DPC_P0 C523 1 2 0.1U_0402_10V6K MXM_DPC_P0_C 1 PC0 55 MUX_PC1 MUX_PI0 @ R124 1 24.7K_0402_5%
<17> MXM_DPC_P0 IN1_D0p PC1
MXM_DPC_N0 C525 1 2 0.1U_0402_10V6K MXM_DPC_N0_C 2
From MXM <17>
<17>
MXM_DPC_N0
MXM_DPC_P1
MXM_DPC_P1 C524 1 2 0.1U_0402_10V6K MXM_DPC_P1_C 4 IN1_D0n
IN1_D1p
MXM_DPC_N1 C527 1 2 0.1U_0402_10V6K MXM_DPC_N1_C 5
<17> MXM_DPC_N1 IN1_D1n
MXM_DPC_P2 C526 1 2 0.1U_0402_10V6K MXM_DPC_P2_C 6 48 MUX_CA_DET
<17> MXM_DPC_P2 IN1_D2p CA_DET MUX_CA_DET <36>
MXM_DPC_N2 C529 1 2 0.1U_0402_10V6K MXM_DPC_N2_C 7 CEXT_8331 C97 2 1 2.2U_0402_6.3V6M
<17> MXM_DPC_N2 IN1_D2n
MXM_DPC_P3 C530 1 2 0.1U_0402_10V6K MXM_DPC_P3_C 9
<17> MXM_DPC_P3 IN1_D3p
MXM_DPC_N3 C528 1 2 0.1U_0402_10V6K MXM_DPC_N3_C 10 46 MUX_D0
<17> MXM_DPC_N3 IN1_D3n OUT_D0p MUX_D0 <36>
45 MUX_D0# MUX_PI0 @ R123 1 24.7K_0402_5%
MXM_DPC_AUX C532 1 2 0.1U_0402_10V6K MXM_DPC_AUX_C 28 OUT_D0n 43 MUX_D1 MUX_D0# <36> MUX_PC0 @ R115 1 24.7K_0402_5%
<17> MXM_DPC_AUX IN1_AUXp OUT_D1p MUX_D1 <36>
MXM_DPC_AUX# C531 1 2 0.1U_0402_10V6K MXM_DPC_AUX#_C 27 42 MUX_D1# MUX_PC1 @ R116 1 24.7K_0402_5%
<17> MXM_DPC_AUX#
23 IN1_AUXn
IN1_SCL
OUT_D1n
OUT2_D2p
40 MUX_D2 MUX_D1#
MUX_D2
<36>
<36>
To DEMUX IN1_PEQ @ R121 1 24.7K_0402_5%
22 39 MUX_D2# IN2_PEQ @ R122 1 24.7K_0402_5%
IN1_SDA OUT2_D2n 37 MUX_D3 MUX_D2# <36>
OUT_D3p 36 MUX_D3# MUX_D3 <36>
DPD_CPU_LANE_P0 C516 1 2 0.1U_0402_10V6K DPD_CPU_LANE_P0_C 11 OUT_D3n MUX_D3# <36>
<9> DPD_CPU_LANE_P0 IN2_D0p
DPD_CPU_LANE_N0 C515 1 2 0.1U_0402_10V6K DPD_CPU_LANE_N0_C 12
<9> DPD_CPU_LANE_N0 IN2_D0n
DPD_CPU_LANE_P1 C518 1 2 0.1U_0402_10V6K DPD_CPU_LANE_P1_C 14 54 PBA_GPU_SEL#
<9> DPD_CPU_LANE_P1 IN2_D1p SW PBA_GPU_SEL# <50>
<9> DPD_CPU_LANE_N1 IN2_D1n
DPD_CPU_LANE_P2 C520 1 2 0.1U_0402_10V6K DPD_CPU_LANE_P2_C 16 44 MUX_HPD
C
From CPU <9>
<9>
DPD_CPU_LANE_P2
DPD_CPU_LANE_N2
DPD_CPU_LANE_N2 C519 1 2 0.1U_0402_10V6K DPD_CPU_LANE_N2_C 17 IN2_D2p
IN2_D2n
OUT_HPD MUX_HPD <36>
C
DPD_CPU_LANE_P3 C521 1 2 0.1U_0402_10V6K DPD_CPU_LANE_P3_C 19
<9> DPD_CPU_LANE_P3 IN2_D3p
<9> DPD_CPU_LANE_N3 IN2_D3n 34 REXT
PCH_DDPD_AUX C533 1 2 0.1U_0402_10V6K PCH_DDPD_AUX_C 30 REXT 47 CEXT_8331
<19> PCH_DDPD_AUX IN2_AUXp CEXT
2
PCH_DDPD_AUX# C534 1 2 0.1U_0402_10V6K PCH_DDPD_AUX#_C 29
<19> PCH_DDPD_AUX# IN2_AUXn
PCH_DDPD_CTRLCLK 25 R96
<19> PCH_DDPD_CTRLCLK IN2_SCL
PCH_DDPD_CTRLDATA 24 8 4.99K_0402_1%
<19> PCH_DDPD_CTRLDATA IN2_SDA GND 18
GND 33
1
MXM_DPC_HPD 3 GND 41
<17> MXM_DPC_HPD DPD_PCH_HPD 13 IN1_HPD GND 57
<19> DPD_PCH_HPD IN2_HPD GND 61
Epad 50
PD
PS8331BQFN60GTR-A0_QFN60_5X9
DOCK DPA(PORT1) DDC-before PS8331
+3.3V_RUN
9/21
B B
+5V_RUN +3.3V_RUN
3
6
1
Q343B
Q343A
100K_0402_5%
100K_0402_5%
5 2
R721
R722
4
2
3
Q347B
1 2 MXM_DPC_AUX 5
R129 4.7K_0402_5%
4
1 2 MXM_DPC_AUX#
Q347A
R132 4.7K_0402_5%
2 MUX_CA_DET
1
A A
www.Vinafix.vn
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, MXM/CPU MUX(PS8331)
LA-9781P 0.2

5 4 3 2 1
5 4 3 2 1
EMI request add 33ohm for DOCK DVI signals.

1 2 DPC_CA_DET
R492 1M_0402_5%
JDOCK1 CONN@
DOCK_DET_1 1 2
3 1 2 4 DOCK_AC_OFF <62>
<39> DOCK_LOM_SPD10LED_GRN# 5 3 4 6 DOCK_LOM_SPD100LED_ORG# <39>
<36> DPD_CA_DET 7 5 6 8 DPC_CA_DET <34>
C366 2 1 0.1U_0402_10V7K DPD_DOCK_LANE_P0 EMC@ R2164 1 2 33_0402_5% DPD_DOCK_LANE_P0_R 9 7 8 10 DPC_DOCK_LANE_P0_R EMC@ R2172 1 2 33_0402_5% DPC_DOCK_LANE_C_P0 0.1U_0402_10V7K 1 2 C431
<36> DPD_GPU_LANE_P0 9 10 MXM_DPB_P0 <17>
C367 2 1 0.1U_0402_10V7K DPD_DOCK_LANE_N0 EMC@ R2165 1 2 33_0402_5% DPD_DOCK_LANE_N0_R 11 12 DPC_DOCK_LANE_N0_R EMC@ R2173 1 2 33_0402_5% DPC_DOCK_LANE_C_N0 0.1U_0402_10V7K 1 2 C438
<36> DPD_GPU_LANE_N0 11 12 MXM_DPB_N0 <17>
D 13 14 D
19 20
25 26
31 32
DPD_DOCK_AUX 33 31 32 34 DPC_DOCK_SW_AUX
<36> DPD_DOCK_AUX 33 34 DPC_DOCK_SW_AUX <34>
DPD_DOCK_AUX# 35 36 DPC_DOCK_SW_AUX#
<36> DPD_DOCK_AUX# 35 36 DPC_DOCK_SW_AUX# <34>
37 38
DPD_GPU_HPD 39 37 38 40 MXM_DPB_HPD
<36> DPD_GPU_HPD 39 40 MXM_DPB_HPD <17>
0.033U_0402_16V7K
+NBDOCK_DC_IN_SS 41 42
41 42 ACAV_DOCK_SRC# <62>
0.033U_0402_16V7K
1 43 44
43 44
@ C695
@ C696
BLUE_DOCK 45 46 1
<33> BLUE_DOCK 45 46 DAT_DDC2_DOCK <33>
47 48
47 48 CLK_DDC2_DOCK <33>
49 50
2 51 49 50 52
RED_DOCK 53 51 52 54 SATA_PRX_DKTX_P2 C697 2 1 0.01U_0402_16V7K 2
<33> RED_DOCK 53 54 SATA_PRX_DKTX_P2_C <18>
55 56 SATA_PRX_DKTX_N2 C698 2 1 0.01U_0402_16V7K
Close to DOCK 57 55 56 58
SATA_PRX_DKTX_N2_C <18>
GREEN_DOCK 59 57 58 60 SATA_PTX_DKRX_P2 C699 1 2 0.01U_0402_16V7K Close to DOCK
Its for Enhance ESD on dock issue. <33> GREEN_DOCK
61 59 60 62 SATA_PTX_DKRX_N2 C700 1 2 0.01U_0402_16V7K SATA_PTX_DKRX_P2_C <18>
63 61 62 64 SATA_PTX_DKRX_N2_C <18> Its for Enhance ESD on dock issue.
65 63 64 66
<33> HSYNC_DOCK 65 66 USBP6+ <22>
67 68
<33> VSYNC_DOCK 67 68 USBP6- <22>
69 70
DPD_GPU_HPD 71 69 70 72
<51> CLK_MSE 71 72 USBP3+ <22>
73 74
<51> DAT_MSE 73 74 USBP3- <22>
75 76 MXM_DPB_HPD
75 76
100K_0402_5%
77 78
<49> DAI_BCLK# 77 78 CLK_KBD <51>
1
79 80
<49> DAI_LRCK# 79 80 DAT_KBD <51>
R757
100K_0402_5%
81 82
81 82
1
C C
83 84
<49> DAI_DI 83 84 USB3RN3 <22>
R2160
85 86
<49> DAI_DO# 85 86 USB3RP3 <22>
87 88
2
89 87 88 90
<49> DAI_12MHZ# 89 90 USB3TN3 <22>
91 92
USB3TP3 <22>
2
93 91 92 94
95 93 94 96
97 95 96 98
<50> D_LAD0 97 98 BREATH_LED# <50,52>
99 100
<50> D_LAD1 99 100 DOCK_LOM_ACTLED_YEL# <39>
101 102
<50> D_LAD2
103
105
101
103
102
104
104
106 DOCK_LOM_TRD0+ <39> audio not transfer to DP display if
<50> D_LAD3 105 106 DOCK_LOM_TRD0- <39>
<50> D_LFRAME#
107
109 107
109
108
110
108
110
DOCK_LOM_TRD1+ <39>
play movie when attached external DP display
111 112 +LOM_VCT
<50> D_CLKRUN# 111 112 DOCK_LOM_TRD1- <39>
1U_0402_6.3V6K
113 114
115 113 114 116
<50> D_SERIRQ 115 116 1
+3.3V_ALW
@C701
@
117 118 +LOM_VCT
<50> D_DLDRQ1# 117 118
C701
119 120
121 119 120 122
<20> CLK_PCI_DOCK 121 122 DOCK_LOM_TRD2+ <39> 2
123 124 DOCK_DET# 2 1
123 124 DOCK_LOM_TRD2- <39>
125 126 10K_0402_5% R755
127 125 126 128
<51> DOCK_SMB_CLK 127 128 DOCK_LOM_TRD3+ <39>
129 130
<51> DOCK_SMB_DAT
131 129 130 132
DOCK_LOM_TRD3- <39> System hangs after hot dock (DF531758)
133 131 132 134
<50,55> DOCK_SMB_ALERT# 133 134 DOCK_DCIN_IS+ <61>
135 136
<55> DOCK_PSID 135 136 DOCK_DCIN_IS- <61>
137 138
139 137 138 140 D32
<51> DOCK_PWR_BTN# 139 140 DOCK_POR_RST# <51>
141 142 RB751S40T1_SOD523-2
143 141 142 144 DOCK_DET_R# 1 2
<50,55,62> SLICE_BAT_PRES# 143 144 DOCK_DET# <50>
145 149 +DOCK_PWR_BAR
146 GND1 PWR2 150
+DOCK_PWR_BAR PWR1 PWR2
L30ESD24VC3-2_SOT23-3
0.1U_0603_50V7K
B 147 151 B
PWR1 PWR2
3
2
0.1U_0603_50V7K
@D33
@
148 152
PWR1 GND2
4.7U_0805_25V6-K
D33
C703
1 @ 1 153 159
Shield_G Shield_G
C702
154 160
Shield_G Shield_G
CE6
155 161
156 Shield_G Shield_G 162 2
2 2 157 Shield_G Shield_G 163
158 Shield_G Shield_G 164
Shield_G Shield_G
1
JAE_WD2F144WB5R400
ESD request reserve it. CIS LINK OK

ESD request change main source
to SCA00001G00
DAI_12MHZ# DAI_BCLK# CLK_PCI_DOCK
1
EMC@
@ RE11 @ RE12
@RE12 R756
10_0402_1% 10_0402_1% 33_0402_5%
2
1 1 1
EMC@
@CE8
@CE8 @CE9
@CE9 C704
4.7P_0402_50V8C 4.7P_0402_50V8C 12P_0402_50V8J
2 2 2
A A
www.Vinafix.vn
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Docking
LA-9781P 0.2

5 4 3 2 1
5 4 3 2 1
D D
JIO1 CONN@
1 2 +3.3V_ALW
3 1 2 4
<22> USB3RN6 3 4
5 6
Left Side JUSB1----->
<22> USB3RP6
7
9
5
7
6
8
8
10
WireLess ON/OFF CONN
<22> USB3TN6 9 10 PLTRST_MMI# <19>
11 12 JWL1
<22> USB3TP6 11 12
13 14 1
13 14 PCIE_PRX_MMITX_P8 <22> 1
15 16 2
<22> USB3RN5 15 16 PCIE_PRX_MMITX_N8 <22> 2
17 18 3
<22> USB3RP5 17 18 <50> WIRELESS_ON#/OFF 3
19 20
Left Side JUSB2-----> 21 19 20 22 PCIE_PTX_MMIRX_P8 <22> 4
<22> USB3TN5 21 22 PCIE_PTX_MMIRX_N8 <22> GND
23 24 5
<22> USB3TP5 23 24 GND
25 26
25 26 CLK_PCIE_CARD# <20>
27 28 ACES_50228-0034N-001
<50> AUD_NB_MUTE# 27 28 CLK_PCIE_CARD <20>
29 30
<51> BEEP 29 30
31 32
<18> SPKR
33 31 32 34
CARDCLK_REQ# <18,20> LInk CIS
CONN@
33 34 SIO_SLP_S3# <19,43,50,54,59>
35 36 RUN_ON <50,54,59>
<22> USB_OC1# 35 36
37 38 PCH_PLTRST#_EC <19,43,44,45,50,51>
<22,41> USB_OC4# 37 38
39 40
41 39 40 42
<22> USBP2- 41 42 USBP10- <22>
Left Side JUSB1-----> <22> USBP2+
43
43 44
44
USBP10+ <22> <-----Express Card
45 46
47 45 46 48
<22> USBP9- 47 48 CARD_SMBCLK <51>
49 50
Left Side JUSB2-----> <22> USBP9+
51 49 50 52
CARD_SMBDAT <51>
53 51 52 54 PCIE_WAKE# <17,44,45,51>
<18> PCH_AZ_CODEC_BITCLK 53 54 EXPCLK_REQ# <20>
55 56
<18> PCH_AZ_CODEC_SDIN0 57 55 56 58
<18> PCH_AZ_CODEC_SDOUT 57 58 CLK_PCIE_EXP# <20>
59 60
<18> PCH_AZ_CODEC_SYNC 59 60 CLK_PCIE_EXP <20>
61 62
<18> PCH_AZ_CODEC_RST# 61 62
63 64 PCIE_PRX_EXPTX_N7 <22>
<48> DAI_12MHZ# 65 63 64 66
C <50> DOCK_HP_DET 65 66 PCIE_PRX_EXPTX_P7 <22> C
67 68
<50> DOCK_MIC_DET 67 68
69 70
<50> AUD_HP_NB_SENSE 69 70 PCIE_PTX_EXPRX_N7 <22>
71 72
<50> AUDIO_BACKLITE# 71 72 PCIE_PTX_EXPRX_P7 <22>
73 74
<48> DAI_DI 75 73 74 76
<48> DAI_DO# 75 76 +1.5V_RUN
77 78
<48> DAI_BCLK# 79 77 78 80
<48> DAI_LRCK# 81 79 80 82
<50> EN_I2S_NB_CODEC# 81 82
83 84 +3.3V_SUS
<30> DMIC_CLK 85 83 84 86
<30> DMIC0 85 86
87 88
87 88 SATA_SIDE_LED <52>
89 90
<42,50> USB_SIDE_EN# 89 90 NUM_LED <52>
91 92
<50,52> LID_CL# 91 92 BT_LED <52>
93 94
<51> VOL_UP 93 94 WLAN_LED <52>
95 96
<51> VOL_DOWN 95 96 SATA_LED <52>
97 98
<51> VOL_MUTE 97 98 BREATH_LED#_Q <52>
+5V_ALW 99 100
99 100 SYS_LED_MASK# <39,50,52>
101 102
103
105
101
103
102
104
104
106
BAT2_LED# <50>
BAT1_LED# <50> Power Button CONN
105 106 MASK_BASE_LEDS# <52>
107 108 JPB1 CONN@
107 108 DAT_TP_SIO <51>
109 110 POWER_SW#_MB 1
109 110 CLK_TP_SIO <51> 1
111 112 +5V_ALW 2
113 111 112 114 3 2
113 114 PS2_DAT_TS <53> 3
115 116 4
115 116 PS2_CLK_TS <53> <52> BREATH_WHITE_LED 4
117 118 5
119 117 118 120 6 5
119 120 +3.3V_RUN 6
121 122
123 121 122 124 7
125 123 124 126 8 GND
127 125 126 128 GND
129 127 128 130 ACES_50228-0067N-001
+5V_RUN 129 130
131 132
B
133
135
131
133
132
134
134
136
Link CIS OK B
137
139
135
137
136
138
138
140
+RTC_CELL
PCB footprint pin define swap need to use cable
139 140
141
GND GND
142 to meet new connector
FOX_QTSA1401-7011-9H
Power Switch for debug
LInk CIS
+5V_RUN +5V_ALW +3.3V_RUN +3.3V_ALW +1.5V_RUN +3.3V_SUS
1 2
<43,51> POWER_SW#_MB 1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
100P_0402_50V8J
1 1 1 1 1 1 1
@ C759
C763
C721
C722
C723
C724
C725
@ PWRSW1
2 2 2 2 2 2 2 @SHORT PADS~D
Place on Bottom
SW1
POWER_SW#_MB 2 1
4 3
SKRBAAE010_4P
A A
Title
I/O board
www.Vinafix.vn
LA-9781P 0.2

5 4 3 2 1
5 4 3 2 1
+3.3V_ALW
RP1
1 8 ESATA_USB_PWR_EN# +3.3V_ALW_U46 +3.3V_ALW
2 7 USB_PWR_SHR_VBUS_EN PJP29
3 6 PROCHOT_GATE PAD-OPEN1x1m
4 5 WWAN_RADIO_DIS# 2 1
0.1U_0402_25V6K
0.1U_0402_25V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
100K_0804_8P4R_5% SHORT DEFAULT
RP2 1 1
1 8 CPU_DETECT# 1 1 1 1
C710
C709
C708
C717
C718
C719
2 7 USB_PWR_SHR_EN#
3 6 WIRELESS_ON#/OFF RP4
4 5 eDP_DET# 2 2 CPU_VTT_ON 1 8
D
2 2 2 2 RUN_ON 2 7 D
100K_0804_8P4R_5% 0.75V_DDR_VTT_ON 3 6
SUS_ON 4 5
1 2 USB_SIDE_EN#
A17
B30
A43
A54
R768 10K_0402_5% CIS LINK OK 100K_0804_8P4R_5%
B5
U46
1 2 DOCK_SMB_ALERT# RP8
VCC1
VCC1
VCC1
VCC1
VCC1
R763 10K_0402_5% A23 AUX_MOD_EN 1 8
GPIOI0 PAD~D @ T166
1 2 HW_GPS_DISABLE2# <33> CRT_SWITCH CRT_SWITCH B52 B63 SIO_SLP_A# LCD_TST 2 7
GPIOA0 GPIOI1 SIO_SLP_A# <19,43,54,58>
R779 100K_0402_5% <57> DDR_1.35V_CNTRL0 DDR_1.35V_CNTRL0 A49 A60 0.75V_DDR_VTT_ON SLICE_BAT_ON 3 6
1 2 SLICE_BAT_PRES# MCARD_MISC_PWREN B53 GPIOA1 GPIOI2/TACH0 A61 SIO_SLP_S4# 0.75V_DDR_VTT_ON <57> 4 5
<54> MCARD_MISC_PWREN GPIOA2 GPIOI3 SIO_SLP_S4# <19,43,54,57>
R2158 100K_0402_5% <61> PROCHOT_GATE PROCHOT_GATE A50 B65 SIO_SLP_S3#
GPIOA3 GPIOI4 SIO_SLP_S3# <19,43,49,54,59>
LID_CL_SIO# B54 A62 IMVP_PWRGD 100K_0804_8P4R_5%
GPIOA4 GPIOI5 IMVP_PWRGD <60>
DOCK_SMB_ALERT# A51 B66
<48,55> DOCK_SMB_ALERT# GPIOA5 GPIOI6 IMVP_VR_ON <60>
TOUCH_SCREEN_PD# B55 A63
<30> TOUCH_SCREEN_PD# GPU_PWR_LEVEL A52 GPIOA6 GPIOI7 DOCK_AC_OFF_EC <62> SYS_LED_MASK# 2 1
<17> GPU_PWR_LEVEL GPIOA7 B67 AUX_EN_WOWL 10K_0402_5% R775
USB_SIDE_EN# A33 GPIOJ0 A64 WLAN_LAN_DISB# AUX_EN_WOWL <46> MXM_DP_HDMI_HPD 2 1
<42,49> USB_SIDE_EN# GPIOB0 GPIOJ1/TACH1 WLAN_LAN_DISB# <39>
EN_I2S_NB_CODEC# B36 A5 SIO_SLP_LAN# 100K_0402_5% R17
<49> EN_I2S_NB_CODEC# GPIOB1 GPIOJ2/TACH2 SIO_SLP_LAN# <19,39>
USH_PWR_STATE# A34 B6 SIO_SLP_SUS# USH_PWR_STATE# 2 1
<43> USH_PWR_STATE# GPOC2 GPIOJ3 SIO_SLP_SUS# <19>
<62> EN_DOCK_PWR_BAR EN_DOCK_PWR_BAR B37 A6 GPIO_PSID_SELECT 1M_0402_5% R102
+3.3V_RUN PANEL_BKEN_EC A35 GPOC3 GPIOJ4 B7 MODC_EN GPIO_PSID_SELECT <55>
<30> PANEL_BKEN_EC GPOC4 GPIOJ5 MODC_EN <38>
ENVDD_PCH B38 A7 DOCK_HP_DET
<19,30> ENVDD_PCH GPOC5 GPIOJ6 DOCK_HP_DET <49>
LCD_TST A36 B8 DOCK_MIC_DET
<30,32> LCD_TST GPOC6/TACH4 GPIOJ7 DOCK_MIC_DET <49>
1 2 SP_TPM_LPC_EN PSID_DISABLE# A37
@ R772 10K_0402_5% <55> PSID_DISABLE# PBAT_PRES# B40 GPIOC7 A8 ME_FWP
<55,62> PBAT_PRES# GPIOD0 GPIOK0 ME_FWP <18>
RP3 DOCKED A38 B9 MASK_SATA_LED#
<36,39> DOCKED GPIOC1 GPIOK1/TACH3 MASK_SATA_LED# <52>
1 8 D_CLKRUN# DOCK_DET# B41 B10 USB_PWR_SHR_EN#
<48> DOCK_DET# GPIOC0 GPIOK2 USB_PWR_SHR_EN# <42>
2 7 D_SERIRQ AUD_NB_MUTE# A39 A10 LED_SATA_DIAG_OUT#
<49> AUD_NB_MUTE# GPIOB7 GPIOK3 LED_SATA_DIAG_OUT# <52>
3 6 D_DLDRQ1# MCARD_WWAN_PWREN B42 B11 TEMP_ALERT#_R 1 2
<46> MCARD_WWAN_PWREN GPIOB6 GPIOK4 TEMP_ALERT# <21>
4 5 DGPU_ALERT# LCD_VCC_TEST_EN A40 A11 RUN_ON R741 0_0402_5%
<30> LCD_VCC_TEST_EN GPIOB5 GPIOK5 RUN_ON <49,54,59>
CCD_OFF B43 B12 AC_DIS
<30> CCD_OFF GPIOB4 GPIOK6 AC_DIS <55,62>
100K_0804_8P4R_5% AUD_HP_NB_SENSE A41 A12
<49> AUD_HP_NB_SENSE GPIOB3 GPIOK7 SPI_WP#_SEL <21>
ESATA_USB_PWR_EN# B44
<41> ESATA_USB_PWR_EN# GPIOB2
2 1 GPU_PWR_LEVEL B60 SUS_ON 10/9
C GPIOL0/PWM7 SUS_ON <54,57> C
R782 100K_0402_5% A57 MSATA_PCIE_PIN51
GPIOL1/PWM8 MSATA_PCIE_PIN51 <45>
NVRAM_PWR_EN B32 B64 BAT1_LED#
<46> NVRAM_PWR_EN GPIOD1 GPIOL2/PWM0 BAT1_LED# <49> trace width 20 mils
<62> SLICE_BAT_ON SLICE_BAT_ON A31 B68 AUDIO_BACKLITE#
GPIOD2 GPIOL3/PWM1 AUDIO_BACKLITE# <49>
SLICE_BAT_PRES# B33 A9 BAT2_LED#
<48,55,62> SLICE_BAT_PRES# GPIOD3 GPIOL4/PWM3 BAT2_LED# <49> trace width 20 mils
<61> BST_CHG_MODE# BST_CHG_MODE# B15 B1
GPIOD4 GPIOL5/PWM2 PAD~D @ T165
PBA_GPU_SEL# A15 A18 USH_PWR_ON
<47> PBA_GPU_SEL# GPIOD5 GPIOL6 USH_PWR_ON <54>
SLICE_BST_CHG_EN B16 A44
<62> SLICE_BST_CHG_EN GPIOD6 GPIOL7/PWM5 PAD~D @ T164
SLICE_BAT_ON 1 2 SLICE_BST_CHG_EN DDR_1.35V_CNTRL1 A16
<57> DDR_1.35V_CNTRL1 GPIOD7
@ R765 0_0402_5% B34 HW_GPS_DISABLE2#
GPIOM1 HW_GPS_DISABLE2# <44>
B39 BREATH_LED#
GPIOM3/PWM4 BREATH_LED# <48,52>
WIGIG60GHZ_DIS# A1 B51 DIS_BAT_PROCHOT#
<44> WIGIG60GHZ_DIS# GPIOE0/RXD GPIOM4/PWM6 DIS_BAT_PROCHOT# <62>
EC5048_TX B2
10/9<44,51> EC5048_TX
<52> NUM_LED#
NUM_LED# A2 GPIOE1/TXD
GPIOE2/RTS#
1 2 mCARD_PCIE_SATA#_R B3 A27 LPC_LAD0
<18,23> mCARD_PCIE_SATA# GPIOE3/DSR# LAD0 LPC_LAD0 <21,43,45,51>
R761 0_0402_5% CPU_DETECT# A3 A26 LPC_LAD1
<7> CPU_DETECT# GPIOE4/CTS# LAD1 LPC_LAD1 <21,43,45,51>
DGPU_PWR_EN B45 B26 LPC_LAD2
<17,19> DGPU_PWR_EN GPIOE5/DTR# LAD2 LPC_LAD2 <21,43,45,51>
DGPU_ALERT# A42 B25 LPC_LAD3
<17> DGPU_ALERT# GPIOE6/RI# LAD3 LPC_LAD3 <21,43,45,51>
MXM_DP_HDMI_HPD B4 A21 LPC_LFRAME#
<17> MXM_DP_HDMI_HPD GPIOE7/DCD# LFRAME# LPC_LFRAME# <21,43,45,51>
+3.3V_ALW B22 PCH_PLTRST#_EC
LRESET# PCH_PLTRST#_EC <19,43,44,45,49,51>
A28 CLK_PCI_5048
PCICLK CLK_PCI_5048 <20>
ZODD_WAKE# A59 B20 CLKRUN#
<38> ZODD_WAKE# GPIOF0 CLKRUN# CLKRUN# <19,43,51>
1 2 DYN_TURB_GPU_PWR_ALRT# BCM5882_ALERT# B62
<43> BCM5882_ALERT# GPIOF1
R14 10K_0402_5% SUSACK# A58 A22 LPC_LDRQ1#
<19> SUSACK# GPIOF2 LDRQ1# LPC_LDRQ1# <21>
EDID_SELECT# B61 B21 IRQ_SERIRQ
<33> EDID_SELECT# GPIOF3/TACH8 SER_IRQ IRQ_SERIRQ <21,43,51>
DGPU_PWROK A56 A32 CLK_SIO_14M
<17,23> DGPU_PWROK GPIOF4/TACH7 14.318MHZ/GPIOM0 CLK_SIO_14M <20>
VGA_ID B59 B35 EC_32KHZ_ECE5048 EC_32KHZ_ECE5048 <51>
3.3V_RUN_GFX_ON A55 GPIOF5 CLK32/GPIOM2
<20,54> 3.3V_RUN_GFX_ON GPIOF6
SLP_ME_CSW_DEV# B58
<23> SLP_ME_CSW_DEV# GPIOF7 B29 D_LAD0
DLAD0 B28 D_LAD1 D_LAD0 <48>
LAN_DISABLE#_R B47 DLAD1 A25 D_LAD2 D_LAD1 <48>
<39> LAN_DISABLE#_R GPIOG0/TACH5 DLAD2 D_LAD2 <48>
AUX_MOD_EN A45 A24 D_LAD3
SYS_LED_MASK# B48 GPIOG1 DLAD3 B23 D_LFRAME# D_LAD3 <48>
<39,49,52> SYS_LED_MASK# GPIOG2 DLFRAME# D_LFRAME# <48>
<17,28> DYN_TURB_GPU_PWR_ALRT# DYN_TURB_GPU_PWR_ALRT# A46 A19 D_CLKRUN#
GPIOG3 DCLKRUN# D_CLKRUN# <48>
B <18,23> SIO_EXT_WAKE# R797 1 2 0_0402_5% B49 B24 D_DLDRQ1# B
GPIOG4 DLDRQ1# D_DLDRQ1# <48>
WIRELESS_LED# A47 A20 D_SERIRQ
<44,52> WIRELESS_LED# GPIOG5 DSER_IRQ D_SERIRQ <48>
USB_PWR_SHR_VBUS_EN B50
+3.3V_ALW <42> USB_PWR_SHR_VBUS_EN WLAN_RADIO_DIS# A48 GPIOG6
<44> WLAN_RADIO_DIS# GPIOG7/TACH6 A29 BC_INT#_ECE5048
BC_INT# BC_INT#_ECE5048 <51>
B31 BC_DAT_ECE5048
BC_DAT BC_DAT_ECE5048 <51>
100K_0402_5%
WIRELESS_ON#/OFF B13 A30 BC_CLK_ECE5048

<49> WIRELESS_ON#/OFF GPIOH0 BC_CLK BC_CLK_ECE5048 <51>
1
BT_RADIO_DIS# A13
<44,53> BT_RADIO_DIS# GPIOH1
@R800
@
WWAN_RADIO_DIS# A53
<44> WWAN_RADIO_DIS# SYSOPT1/GPIOH2
R800
SYS_PWROK B57 A4 RUNPWROK

<19,7> SYS_PWROK SYSOPT0/GPIOH3 PWRGD RUNPWROK <51,7>
DGPU_SELECT# B14
<29,30,33> DGPU_SELECT# GPIOH4
eDP_DET# A14 B56 SP_TPM_LPC_EN
<32> eDP_DET# SP_TPM_LPC_EN <43>
2
CPU_VTT_ON B17 GPIOH5 OUT65

1 2 B18 GPIOH6
<19> PCH_DPWROK GPIOH7
VGA_ID R802 0_0402_5% B19 1 2
TEST_PIN R804 1K_0402_1%
100K_0402_5%
B46 +CAP_LDO
CAP_LDO
1
100K_0402_5%
4.7U_0603_6.3V6K
1
R808
B27
VGA_ID0 VSS 1
R803
C1
EP
C714
Discrete 0 DB Version 0.4
2
ECE5048-LZY_DQFN132_11X11~D 2
UMA 1
2
+3.3V_ALW
+CAP_LDO trace width 20 mils
100K_0402_5%
CLK_SIO_14M CLK_PCI_5048
1
ME_FWP PCH has internal 20K PD.

R805
1
(suspend power rail)

10_0402_1%
10_0402_1%
@R794
@
@R795
@
R794
R795
ME_FWP
2
A A
2
2
1
1K_0402_1%
LID_CL_SIO# 2 1
LID_CL# <49,52>
@R793
@
R807 10_0402_1%
R793
0.047U_0402_16V4Z
4.7P_0402_50V8C
4.7P_0402_50V8C
1
C716
1 1
2
@ C712
@ C713
2 Compal Electronics, Inc.
www.Vinafix.vn
2 2 Title
SIO
Size Document Number Rev
LA-9781P 0.2

5 4 3 2 1
5 4 3 2 1
+RTC_CELL +RTC_CELL
100K_0402_5%
100K_0402_5%
1
1
+3.3V_ALW
R810
R819
@ C1354 @ C733
@ C720 1 2 1 2
1 2
1U_0402_6.3V6K 1U_0402_6.3V6K
2
0.1U_0402_25V6K
5
+RTC_CELL POWER_SW_IN# 1 2 DOCK_PWR_SW# 1 2
1 <27> POWER_SW_IN# POWER_SW#_MB <43,49> <27> DOCK_PWR_SW# DOCK_PWR_BTN# <48>
R811 10K_0402_5% R825 10K_0402_5%
P
<59> 1.5V_RUN_PWRGD B
1U_0402_6.3V6K
1U_0402_6.3V6K
4 1 2 +RTC_CELL_VBAT 1 1
2 O 1.05V_0.8V_PWROK <60>
RUNPWROK R1985 0_0402_5%
A
0.1U_0402_25V6K
C1352
C734
@ U50
TC7SH08FU_SSOP5~D
3
2 2
1
C1353
+1.05V_RUN
10K_0402_5%
1 2
1
@ R1179
CIS LINK OK R1180 0_0402_5%
D D
EC_WAKE# 1 2 LAN_WAKE# U51
R846 0_0402_5% +3.3V_ALW 1 2 +3.3V_VTR
R834 0_0402_5% B64 A10 SYSTEM_ID
+3.3V_ALW VBAT GPIO021/RC_ID1 H_PROCHOT# <60,61,62,7>
0.1U_0402_25V6K
1U_0402_6.3V4Z
1 2 B10 BOARD_ID
+3.3V_M
2
@ R837 0_0402_5% GPIO020/RC_ID2 B8 R1984 1 2 1K_0402_5%
1 1 GPIO014/GPTP-IN7/RC_ID3 VOL_UP <49>
1
1 2 A22 B27 LAN_WAKE# D
H_VTR GPIO025/UART_CLK LAN_WAKE# <39>
C739
C1349
R845 0_0402_5% B44 HOST_DEBUG_TX PROCHOT#_EC 2 @ Q47
GPIO120/UART_TX HOST_DEBUG_TX <44,51>
0.1U_0402_25V6K
1U_0402_6.3V4Z
+3.3V_ALW B46 HOST_DEBUG_RX G DMN65D8LW-7_SOT323-3
2 2 +VTR_ADC A58 GPIO124/GPTP-OUT5/UART_RX B26 RUNPWROK
1 1 S
3
VTR_ADC VCC_PWRGD RUNPWROK <50,7>
100K_0402_5%
A25 EN_INVPWR
GPIO060/KBRST/BCM_B_INT# EN_INVPWR <30>
C736
2
C757
1 2 PCIE_WAKE# B36 PCH_SATA_MOD_EN#
GPIO101/ECGP_SCLK/GANG_DATA5 PCH_SATA_MOD_EN# <18>
@ R812
R759 10K_0402_5% B3 B37
2 2 VTR GPIO103/ECGP_MISO/GANG_DATA7 PAD~D @ T161
1 2 HOST_DEBUG_RX A11 B38 PCIE_WAKE#
A26 VTR GPIO105/ECGP_MOSI A34 PCIE_WAKE# <17,44,45,49>
R760 10K_0402_5% EMC4021_BC_INT#
1 2 +3.3V_ALW +3.3V_ALW_U51 B35 VTR GPIO102/BCM_C_INT#/GANG_DATA6 A35 EMC4021_BC_INT# <27>
BC_DAT_ECE5048
1
R814 100K_0402_5% PJP65 A41 VTR GPIO104 A36 CPU1.5V_S3_GATE DYN_TUR_CURRNT_SET# <61>
1 2 BC_DAT_ECE1117 1 2 A52 VTR GPIO106 A40 MSDATA +RTC_CELL
VTR GPIO116/MSDATA/V2P_COUT_LO/TAP_SEL_STRAP B43 MSDATA <44>
R817 100K_0402_5% MSCLK
GPIO117/MSCLK/V2P_COUT_HI MSCLK <44>
10U_0603_6.3V6M
0.1U_0402_25V6K
0.1U_0402_25V6K
0.1U_0402_25V6K
0.1U_0402_25V6K
0.1U_0402_25V6K
0.1U_0402_25V6K
RP5 PN change to SD309220180 PAD-OPEN1x1m A45 SIO_A20GATE
1 8 GPIO127/A20M B65 SIO_A20GATE <23>
PBAT_SMBDAT SHORT DEFAULT 1 1 1 1 1 1 1 NFWP
FWP#
2 7 PBAT_SMBCLK SML1_SMBDATA A5 LAT_ON_SW# 2 1
<21> SML1_SMBDATA GPIO007/I2C1D_DATA/PS2_CLK0B/I2C3A_DATA/GANG_BUSY
C781
C1345
C1348
C1355
C777
C780
C782
3 6 CHARGER_SMBDAT SML1_SMBCLK B6 100K_0402_5% R870
4 5 <21> SML1_SMBCLK A37 GPIO010/I2C1D_CLK/PS2_DAT0B/I2C3A_CLK/GANG_ERROR B57
CHARGER_SMBCLK CLK_TP_SIO VOL_DOWN_R R887 1 2 1K_0402_5% VCI_IN3# 2 1
2 2 2 2 2 2 2 <49> CLK_TP_SIO DAT_TP_SIO B40 GPIO110/PS2_CLK2/GPTP-IN6 GPIO156/LED0 B1 DEVICE_DET# VOL_DOWN <49>
100K_0402_5% R880
<49> DAT_TP_SIO GPIO111/PS2_DAT2/GPTP-OUT6 GPIO157/LED1 DEVICE_DET# <38>
2.2K_8P4R_5% CLK_KBD A38 A55 PS_ID
<48> CLK_KBD GPIO112/PS2_CLK1A GPIO153/LED2 PS_ID <55>
DAT_KBD B41 A1 ALW_PWRGD_3V_5V
<48> DAT_KBD A39 GPIO113/PS2_DAT1A GPIO027/GPTP-OUT1 B28 ALW_PWRGD_3V_5V <56>
CLK_MSE 1.05V_A_PWRGD
<48> CLK_MSE B42 GPIO114/PS2_CLK0A GPIO026/GPTP-IN1 B2 1 2 1.05V_A_PWRGD <58>
+5V_RUN DAT_MSE +PCH_VCCDSW3_3
<48> DAT_MSE PBAT_SMBDAT B59 GPIO115/PS2_DAT0A GPIO001/ECSPI_CS1 A8 VOL_MUTE <49>
R884 1K_0402_5%
<55> PBAT_SMBDAT A56 GPIO154/I2C1C_DATA/PS2_CLK1B GPIO015/GPTP-OUT7/GANG_DATA3 B9 ME_SUS_PWR_ACK <19> 2 1
PBAT_SMBCLK 1.35V_SUS_PWRGD AC_PRESENT
PN change to SD309470180 <55> PBAT_SMBCLK GPIO155/I2C1C_CLK/PS2_DAT1B GPIO016/GPTP-IN8/GANG_DATA4 A9 1.35V_SUS_PWRGD <57,7>
RP6 PM_APWROK 10K_0402_5% R835
GPIO017/GPTP-OUT8 PM_APWROK <19>
1 8 DAT_KBD JTAG_TDI A51 B39 RESET_OUT#
GPIO145/I2C1K_DATA/JTAG_TDI GPIO107/NRESET_OUT RESET_OUT# <10,18,19>
2 7 DAT_MSE JTAG_TDO B55 A44 PCH_PCIE_WAKE#
3 6 CLK_KBD JTAG_CLK B56 GPIO146/I2C1K_CLK/JTAG_TDO GPIO125/GPTP-IN5 B47 PCH_RSMRST# PCH_PCIE_WAKE# <19>
4 5 A53 GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK GPIO126 A54 PCH_RSMRST# <53>
CLK_MSE JTAG_TMS AC_PRESENT +3.3V_ALW
A57 GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS GPIO151/GPTP-IN4 B58 AC_PRESENT <19>
JTAG_RST# SIO_PWRBTN#
JTAG_RST# GPIO152/GPTP-OUT4 SIO_PWRBTN# <19> 2 1
4.7K_0804_8P4R_5% LCD_SMBCLK
DOCK_POR_RST# <27> FAN1_TACH_FB FAN1_TACH_FB B22 A3 DOCK_SMB_DAT 2.2K_0402_5% R418 @
+3.3V_RUN DOCK_POR_RST# A21 GPIO050/FAN_TACH1/GTACH GPIO003/I2C1A_DATA/GANG_MODE B4 DOCK_SMB_CLK DOCK_SMB_DAT <48> LCD_SMBDAT 2 1
<48> DOCK_POR_RST# B23 GPIO051/FAN_TACH2 GPIO004/I2C1A_CLK/GANG_START A4 DOCK_SMB_CLK <48>
10/5 EC_WAKE# LCD_SMBDAT 2.2K_0402_5% R420 @
1 2 <23> EC_WAKE# B24 GPIO052/FAN_TACH3 GPIO005/I2C1B_DATA/BCM_B_DAT/GANG_STROBE B5 LCD_SMBDAT <32> 2 1
VOL_MUTE LCD_SMBCLK DOCK_SMB_DAT
<54,58> A_ON GPIO053/PWM0 GPIO006/I2C1B_CLK/BCM_B_CLK/GANG_FULL LCD_SMBCLK <32>
0.1U_0402_25V6K
@ R1986 100K_0402_5% PCH_ALW_ON A23 B7 GPU_SMBDAT 2.2K_0402_5% R838
1 2 <54,55> PCH_ALW_ON B25 GPIO054/PWM1 GPIO012/I2C1H_DATA/I2C2D_DATA/GANG_DATA1 A7 GPU_SMBDAT <17> 2 1
VOL_DOWN 1 <30> BIA_PWM_EC BIA_PWM_EC GPU_SMBCLK DOCK_SMB_CLK
C737 FAN1_PWM A24 GPIO055/PWM2 GPIO013/I2C1H_CLK/I2C2D_CLK/GANG_DATA2 B48 EMC4021_BC_DAT GPU_SMBCLK <17>
@ R1197 100K_0402_5% 2.2K_0402_5% R841
<27> FAN1_PWM GPIO056/PWM3/GPWM GPIO130/I2C2A_DATA/BCM_C_DAT EMC4021_BC_DAT <27>
1 2 VOL_UP B49 EMC4021_BC_CLK
GPIO131/I2C2A_CLK/BCM_C_CLK EMC4021_BC_CLK <27>
@ R1118 100K_0402_5% A47 CHARGER_SMBDAT
1 2 2 GPIO132/I2C1G_DATA B50 CHARGER_SMBDAT <61> 2 1
GPU_SMBDAT CHARGER_SMBCLK EMC4021_BC_DAT
A43 GPIO140/I2C1G_CLK B52 CHARGER_SMBCLK <61>
R829 2.2K_0402_5% BC_CLK_ECE5048 CARD_SMBDAT 100K_0402_5% R1126
1 2 GPU_SMBCLK <50> BC_CLK_ECE5048 BC_DAT_ECE5048 B45 GPIO123/BCM_A_CLK GPIO141/I2C1F_DATA/I2C2B_DATA A49 CARD_SMBCLK CARD_SMBDAT <49> DYN_TUR_CURRNT_SET# 2 1
<50> BC_DAT_ECE5048 A42 GPIO122/BCM_A_DAT GPIO142/I2C1F_CLK/I2C2B_CLK B53 CARD_SMBCLK <49>
C R822 2.2K_0402_5% BC_INT#_ECE5048 USH_SMBDAT 100K_0402_5% R1980 C
<50> BC_INT#_ECE5048 B20 GPIO121/BCM_A_INT# GPIO143/I2C1E_DATA A50 USH_SMBDAT <43> 2 1
ACAV_IN_NB USH_SMBCLK DEVICE_DET#
<61,62> ACAV_IN_NB GPIO032/BCM_E_CLK GPIO144/I2C1E_CLK USH_SMBCLK <43>
1 2 MSDATA SIO_SLP_S5# A18 100K_0402_5% R1125
R869 10K_0402_5%
Place close pin A21 <19,43> SIO_SLP_S5#
BEEP B19 GPIO031/GPTP-OUT2/BCM_E_DAT A59 SYSPWR_PRES 1 2
<49> BEEP GPIO030/GPTP-IN2/BCM_E_INT# SYSPWR_PRES +3.3V_ALW2 +3.3V_ALW
100K_0402_5%
RP7 BC_CLK_ECE1117 A20 R874 1K_0402_5%
<53> BC_CLK_ECE1117 GPIO047/LSBCM_D_CLK
1
1 8 DOCK_POR_RST# <53> BC_DAT_ECE1117 BC_DAT_ECE1117 B21 A64 ACAV_IN
2 7 A19 GPIO046/LSBCM_D_DAT VCI_OVRD_IN A60 ACAV_IN <17,27,61,62>
PCH_ALW_ON BC_INT#_ECE1117 ALWON
<53> BC_INT#_ECE1117 GPIO045/LSBCM_D_INT# VCI_OUT ALWON <56>
1
8.2K_0402_5%
3 6 EN_INVPWR B67 POWER_SW_IN#
VCI_IN0#
R876
R396
4 5 1.05V_0.8V_PWROK SIO_EXT_SMI# A6 A63 DOCK_PWR_SW#
<18,22> SIO_EXT_SMI# A27 GPIO011/nSMI/GANG_DATA0 VCI_IN1# B63
SIO_RCIN# LAT_ON_SW#
2
100K_0804_8P4R_5% <23> SIO_RCIN# IRQ_SERIRQ A28 GPIO061/LPCPD# VCI_IN2# B68 VCI_IN3#
<21,43,50> IRQ_SERIRQ PCH_PLTRST#_EC B30 SER_IRQ VCI_IN3#
<19,43,44,45,49,50> PCH_PLTRST#_EC R866 close to U51 at least 250mils
2
1 2 RESET_OUT# CLK_PCI_MEC A29 LRESET# B51 +PECI_VREF 1 2
<20> CLK_PCI_MEC PCI_CLK VREF_PECI +1.05V_RUN
@ R843 8.2K_0402_5% LPC_LFRAME# B31 A48 PECI_EC_R 1 2 @ R866 0_0402_5%
<21,43,45,50> LPC_LFRAME# LFRAME# PECI_DAT PECI_EC <7>
0.1U_0402_25V6K
1 2 CPU1.5V_S3_GATE LPC_LAD0 A30 R952 43_0402_5% 1
<21,43,45,50> LPC_LAD0 B32 LAD0
R889 100K_0402_5% LPC_LAD1 THERMATRIP2#
<21,43,45,50> LPC_LAD1 LAD1
C740
1 2 PCH_RSMRST# LPC_LAD2 A31 B13 REM_DIODE1_N C1343 1 2 2200P_0402_50V7K
<21,43,45,50> LPC_LAD2 LAD2 DN1-THERM +VCCIO_OUT
PMST3904_SOT323-3
0.1U_0402_25V6K
R892 10K_0402_5% LPC_LAD3 B33 A13 REM_DIODE1_P 1
<21,43,45,50> LPC_LAD3 LAD3 DP1-VREF_T 2
C327
1 2 A_ON CLKRUN# A32 B14 REM_DIODE2_N C1350 1 2 2200P_0402_50V7K
<19,43,50> CLKRUN# CLKRUN# DN2
1
R432 47K_0402_5% SIO_EXT_SCI# A33 A14 REM_DIODE2_P C
<23> SIO_EXT_SCI# GPIO100/NEC_SCI DP2
Q28
A15 REM_DIODE3_N C1351 1 2 2200P_0402_50V7K 1 R399 2 2
MEC_XTAL1 A61 DN3 B16 REM_DIODE3_P 2.2K_0402_5% B 2
MEC_XTAL2 2 1 MEC_XTAL2_R A62 XTAL1 DP3 A16 REM_DIODE4_N C1346 1 2 2200P_0402_50V7K E
3
R1068 0_0402_5% B62 XTAL2 DN4 B17 REM_DIODE4_P
<50> EC_32KHZ_ECE5048 GPIO160/32KHZ_OUT DP4 B15
+3.3V_ALW PAD~D @ T155 C1343, C1350, C1351, C1346 Place near U51
VIN A17 VSET_5075
VSET A12 ADP_I_R 2 1 ADP_I
VCP ADP_I <61>
B34 THERMATRIP2# R134 4.7K_0402_5%
THERMTRIP2#
100K_0402_5%
A2 THERMATRIP3# <7> H_THERMTRIP#

GPIO002/THERMTRIP3#
1
R1981
B29 THSEL_STRAP
VSS_ADC
GPIO024/THSEL_STRAP
VSS_RO
VR_CAP
A46 PROCHOT#_EC
32 KHz Clock
H_VSS
PROCHOT_IN#/PROCHOT_IO#
AGND
CLK_PCI_MEC B61 BST_CHG_IMON BST_CHG_IMON <61>
VSS
V_ISYS
EP
1
+3.3V_ALW
10_0402_1%
2
@ R885
MEC5075-LZY_DQFN132_11X11~D
B66
B11
B60
+VR_CAP B12
B54
B18
C1
+3.3V_MXM
8.2K_0402_5%
JTAG_RST# MEC_XTAL1 1 2 MEC_XTAL2
15mil
2
1
4.7P_0402_50V8C
27P_0402_50V8J
33P_0402_50V8J
Y6 C290 Place near U51.A48

1
10K_0402_5%
2.2K_0402_5%
R397
1 32.768KHZ_12.5PF_Q13FC1350000 1 THSEL_STRAP 1 2
1
1U_0402_6.3V6K
4.7U_0603_6.3V6K
1 R1069 1K_0402_5% PECI_EC_R 1 2
1
1
JTAG1 CONN@
@SHORT PADS~D
100_0402_1%
C743
C741
R401
@
1 1 @ C292 47P_0402_50V8J
@ C747
R400
@
2
2 2
C735
R836
C779
2 THERMATRIP3#
2
2 2
PMST3904_SOT323-3
0.1U_0402_25V6
1: Channel 1 will provide Thermistor Readings 1
2
1
2
C343
C
Place close pin A29 ESR <2ohms 0: Channel 1 will provide Diode Readings
Q115
THERMB3 2
2
B 2
B B
E
3
+3.3V_ALW
R875 C744 REV
<17> DGPU_THERMTRIP#
240K 4700p X00
10K_0402_5%
49.9_0402_1%
10K_0402_5%
10K_0402_5%
10K_0402_5%
* 130K 4700p X01

1
+3.3V_ALW
R864
R858
R859
R860
R861
VSET_5075 JDEG2 CONN@

12 33K 4700p X02
0.1U_0402_25V6K
GND 11
GND 4.3K 4700p *** Place Q26 under CPU DP3/DN3 for SODIMM(TOP) on Q14,
1
1
1.33K_0402_1%
10K_0402_5%
10K_0402_5%
10K_0402_5%
100K_0402_5%
1
2
2
R425
@ R850
2K 4700p *** Place C339 close to the Q26 place Q14 close to SODIMM(TOP) and C272 close to Q14
C320
R847
R848
R849
10
10 9 JTAG_TDI REM_DIODE1_P REM_DIODE3_P
2 9 1K 4700p A00 100P_0402_50V8J
100P_0402_50V8J
8 JTAG_TMS
2
1
7 JTAG_CLK 2 C 1
7
1
@ C339
@ C272
6 JTAG_TDO 2 C
6 5 MSCLK B 2
5 4 MSDATA E B
Rest=1.33k, Tp=93degree
3
4 3 HOST_DEBUG_TX 1 Q26 2 E
HOST_DEBUG_TX <44,51>
3
3 2 EC5048_TX PMST3904_SOT323-3 Q14
2 EC5048_TX <44,50>
1 REM_DIODE1_N PMST3904_SOT323-3 REM_DIODE3_N
1
ACES_87152-10071 BOARD_ID rise time is measured from 5%~68%. DP2/DN2 for SODIMM(BOT) on Q17, DP4/DN4 for Skin on Q15,
place Q17 close to SODIMM(BOT) and C340 close to Q17 place Q15 close to Vcore VR choke and C288 close to Q15
REM_DIODE2_P REM_DIODE4_P
100P_0402_50V8J
100P_0402_50V8J
1
1
@ C340
@ C288
C 1
1
+3.3V_M +3.3V_ALW 2 C
+3.3V_ALW B 2
+3.3V_RUN 2 Channel Location
100K_0402_5%
+3.3V_ALW E B
3
1
2
10K_0402_5%
Q17 E
3
1
1K_0402_5%
R893
10K_0402_5%
PMST3904_SOT323-3 REM_DIODE2_N Q15

DP1/DN1 CPU(TOP)
1
1
R872
130K_0402_5%
PMST3904_SOT323-3
1
R871
R799
REM_DIODE4_N
R875
DP2/DN2 DIMM(TOP)
2
PCH_PWRGD# <27>
2
2
FWP#
DP3/DN3 DIMM(BOT)
2
1
D
4700P_0402_25V7K
SYSTEM_ID RUNPWROK
RESET_OUT# 2 Q52 BOARD_ID
2
10K_0402_5%
G
1 DMN65D8LW-7_SOT323-3
DP4/DN4 V.R(BOT)
1
D
4700P_0402_25V7K
S
3
C742
@ R879
A 2 Q45 1 A
<54,7> RUN_ON_ENABLE#
2
C744
S
1
CHIPSET_ID for BID function
www.Vinafix.vn
PROPRIETARY NOTE:
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT MEC5075
0.2
5 4 3 2 1
5 4 3 2 1
HDD LED
NUM LED
+3.3V_ALW +5V_RUN
10K_0402_5%
+5V_ALW
1
R932
3
Q93
3
2
D
Q74B Q74A 3 1 2
<50> NUM_LED#
DMN66D0LDW-7_SOT363-6 D59 DMN66D0LDW-7_SOT363-6
4 3 1 2 1 6 2
<18> SATA_ACT# PDTA114EU_SC70-3
G
2
RB751S40T1_SOD523-2 Q80
D PDTA114EU_SC70-3 D
1
Q75 MASK_BASE_LEDS#
1
<50> MASK_SATA_LED#
1 2
MASK_BASE_LEDS# R942 1.2K_0402_1% NUM_LED <49>
1 2
D62 R934 910_0402_1% SATA_LED <49>
1 2 For PT2 regression
<50> LED_SATA_DIAG_OUT#
RB751S40T1_SOD523-2 For PT2 regression
+5V_ALW
3
Q321
Breath LED
D
3 1 2
PDTA114EU_SC70-3
G
For PT2 regression BREATH_LED TOP view.
2
Q86 Q84A
1
1 6 1 2 BREATH_WHITE_LED BREATH_WHITE_LED <49>
<48,50> BREATH_LED#
R956 475_0402_1%
SYS_LED_MASK#
1 2
2
R943 220_0402_5% SATA_SIDE_LED <49>
MASK_BASE_LEDS#
For PT2 regression Q84B
4 3 1 2 BREATH_LED#_Q <49>
WWAN/WLAN LED R955 220_0402_5%
BREATH_LED side view.

For PT2 regression
5
C SYS_LED_MASK# C
+3.3V_ALW
+5V_ALW
1
+3.3V_ALW
R937
100K_0402_5% @C778
@ C778
3
Q78 1 2
2
0.1U_0402_25V6K
5
3 1 2
S
<44,50> WIRELESS_LED# 1
SYS_LED_MASK#
P
<39,49,50> SYS_LED_MASK# B 4 MASK_BASE_LEDS#
PDTA114EU_SC70-3 LID_CL# 2 O MASK_BASE_LEDS# <49>
G
2
<49,50> LID_CL# A
G
Q79 U58
TC7SH08FU_SSOP5~D
1
3
MASK_BASE_LEDS#
1 2
R939 1.2K_0402_1% WLAN_LED <49>
For PT2 regression
BT LED
+3.3V_ALW
BT LED will be light when system is in S3/S4/S5
that change PU from RUN to ALW rail
100K_0402_5%
MASK_BASE_LEDS#
1
B B
R938
For PT2 regression

2
For WiGig combo card

2
1 6 1 2
<44> BT_LED#_R BT_LED <49>
R941 1K_0402_1%
Q318A
3
Q318B
5
<53> BT_ACTIVE
4
LED Circuit Control Table

SYS_LED_MASK# LID_CL#
Mask All LEDs (Sniffer Function) 0 X

Mask Base MB LEDs (Lid Closed) 1 0
Fiducial Mark Do not Mask LEDs (Lid Opened) 1 1
@FD1
@ FD1
A 1 A
FIDUCIAL MARK~D @ H1
@H1 @ H2 @ H3 @ H4
@H4 @H5
@ H5 @ H6 @ H7
@H7 @ H8 @ H9 @ H10
@H10 @ H11 @ H12
@H12 @ H13 @ H14 @ H15
@H15
H_3P0 H_3P8 H_3P0 H_12P0X7P5H_3P0 H_3P0 H_3P8 H_3P0 H_3P0 H_3P0 H_3P0 H_4P2 H_4P2 H_4P2 H_4P2
@FD2
@ FD2
1
1
FIDUCIAL MARK~D
@FD3
@
1
FD3
@ H16
@H16 @ H17 @ H18 @ H19
@H19 @ H20
@H20 @ H21 @ H22
@H22 @H23
@ H23 @ H24 @ H25 @ H26
@H26 @ H27 @ H28
@H28
FIDUCIAL MARK~D
H_3P0 H_3P6 H_3P0 H_3P6 H_3P0 H_3P0 H_3P6X3P0 H_3P6 H_3P6 H_3P0 H_1P2 H_1P2 H_1P2
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@ FD4
@FD4 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
PAD & Standoff & LED
1
1 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,

FIDUCIAL MARK~D PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.2
LA-9781P
5 4 3 2 1
5 4 3 2 1
Add WiGig card function
2 1
0_0402_5% @R694
@R694
@ D28
BT_RADIO_DIS#_CON 2 1
BT_RADIO_DIS# <44,50>
RB751S40T1_SOD523-2
D D
+3.3V_RUN
BlueTooth +3.3V_RUN
0.1U_0402_25V6K
1 2 BT_COEX_STATUS2
@ R1133 1K_0402_1%
1 2 BT_PRI_STATUS @ 1
C748
@ R1134 1K_0402_1%
1 2
+5V_ALW RSMRST# +3.3V_ALW_PCH +3.3V_ALW

@ R1623 0_0402_5%
+3.3V_ALW_PCH
2
1
JBT1
+3.3V_ALW 2 1
10K_0402_5% 9/25 2
10K_0402_5%
8.2K_0402_5%
3
<44> COEX1_BT_ACTIVE 3
1
2
@
33_0402_5%
C289 @ 4
<43> BT_COEX_STATUS2 4
R1630
R1622
R1633
R1624
1 2 5
<43> BT_PRI_STATUS 6 5
0.1U_0402_25V6K <52> BT_ACTIVE BT_RADIO_DIS#_CON 7 6
8 7
<44> COEX2_WLAN_ACTIVE
2
1
U18 8
5
9
1 10 9
P
<51> PCH_RSMRST# B 10
1 4 PCH_RSMRST#_Q <18,19> 11 13
VCC O <22> USBP11- 11 GND
3 RSMRST# 2 12 14
RESET# A <22> USBP11+ 12 GND
G
0.01U_0402_16V7K
2 U12
GND TC7SH08FU_SSOP5~D ACES_50228-0127N-001
1
3
CONN@
C290
RT9818A-44GU3_SC70-3~D
2
LInk CIS
100P_0402_50V8J
C PN change to SA00005A600, C
33P_0402_50V8J
10K_0402_5%
1
@ C754
@ @
wait symbol release. 1 1
C753
R904
2 2
2
10/15 pin swap for ME request
Keyboard
JKB1
KB_DET# 1 2 KB_DET#
<23> KB_DET# PS2_CLK_TS 3 1 2 4 PS2_CLK_TS
<49> PS2_CLK_TS 3 4 6
PS2_DAT_TS 5 PS2_DAT_TS
<49> PS2_DAT_TS 5 6 8
+3.3V_ALW 7 +3.3V_ALW
9 7 8 10 +5V_RUN
+5V_RUN 9 10 12
11 BC_INT#_ECE1117
<51> BC_INT#_ECE1117 13 11 12 14 BC_DAT_ECE1117
<51> BC_DAT_ECE1117 13 14 16
15
17 15 16 18 BC_CLK_ECE1117
<51> BC_CLK_ECE1117 17 18 20
B 19 B
19 20
E-T_6900K-G10N-40R
CONN@
LInk CIS
+3.3V_ALW +5V_RUN
0.1U_0402_25V6K
0.1U_0402_25V6K
1 @ 1 @
C756
C758
2 2
Place close to JKB1
A A
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BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Touch PAD/Int KB
LA-9781P 0.2

5 4 3 2 1
5 4 3 2 1
+1.05V_RUN Source
+PWR_SRC +PWR_SRC_S
+1.05V_M Q63 +1.05V_RUN
330K_0402_5%
330K_0402_5%
SI4164DY-T1-GE3_SO8
1
+3.3V_ALW2 @ 8 1
R933
R930
10U_0603_6.3V6M
7 2
1
20K_0402_5%
6 3 1
100K_0402_5%
C772
R931
5
+3.3V_ALW to +3.3V_MXM
2
R909
4
2
2
+1.05V_RUN_ENABLE
U34 +3.3V_MXM_PWR +3.3V_MXM
3
D D
100P_0402_50V8J
3.3V_RUN_GFX_ON 3
<20,50> 3.3V_RUN_GFX_ON ON
1
Q304B
1M_0402_5%
@ PJP92
R1611
1 7 2 1 RUN_ON_ENABLE# 5
100K_0402_5%
+3.3V_ALW VIN VOUT 2 1 <51,7> RUN_ON_ENABLE# 1

1
0.1U_0603_25V7K
1
10U_0603_6.3V6M
C773
@
2 8 JUMP_43X79
R301
4
VIN VOUT
C362
2
6
2
C400
2
2
Q349A
+5V_ALW 4
VBIAS 5 1 2 2
GND <49,50,59> RUN_ON
6 9 R762 0_0402_5%
CT GND
1
470P_0402_50V7K
1 1 2
<19,43,49,50,59> SIO_SLP_S3#
C539
TPS22965DSGR_SON8_2X2~D @ R781 0_0402_5%
2 +5V_RUN Source +3.3V_PCIE_FLASH
10U_0603_6.3V6M
U37
1 14
+5V_ALW +5V_ALW to +5V_MXM +3.3V_ALW
2 VIN1
VIN1
VOUT1
VOUT1
13 1
C546
U35 MCARD_MISC_PWREN 3 12
<50> MCARD_MISC_PWREN ON1 CT1
3.3V_RUN_GFX_ON 3 +5V_MXM_PWR +5V_MXM 2 1 4 11 2
ON R733 100K_0402_5% VBIAS GND
1 7 5 10 +5V_RUN_PWR +5V_RUN
VIN VOUT @ PJP93 ON2 CT2
2 8 2 1 6 9 @ PJP82
VIN VOUT 2 1 +5V_ALW VIN2 VOUT2
7 8 +5V_RUN_PWR 2 1
JUMP_43X79 VIN2 VOUT2
470P_0402_50V7K
470P_0402_50V7K
15 2 2 PAD-OPEN 4x4m
GPAD
10U_0805_10V4Z
10U_0805_10V4Z
+5V_ALW 4 1 1
C VBIAS C
C543
C545
5 TPS22966DPUR_SON14_2X3~D
GND
C356
C514
6 9
CT GND 1 1
2 2
470P_0402_50V7K
1
C436
+3.3V_RUN Source
+3.3V_ALW_PCH Source
+3.3V_RUN_PWR +3.3V_RUN
U36 @ PJP89
Solve S4/S5 +MXM_PWR_SRC leakage in DC mode. +3.3V_ALW 1 14 +3.3V_RUN_PWR 2 1
2 VIN1 VOUT1 13 2 1
VIN1 VOUT1
10U_0603_6.3V6M
JUMP_43X79
3 12
MXM_PWR_SRC Source ON1 CT1 1
C449
+PWR_SRC_MXM @ PJP78
1 2 +5V_ALW 4 11
+PWR_SRC_MXM Q186 +MXM_PWR +MXM_PWR_SRC VBIAS GND
2
100K_0402_5%
SI4835DDY-T1-E3_SO8 PAD-OPEN 4x4m PCH_ALW_ON 5 10 +3.3V_ALW_PCH_PWR +3.3V_ALW_PCH

<51,55> PCH_ALW_ON ON2 CT2
1
1 8
R940
2 7 6 9 @ PJP91
+3.3V_ALW VIN2 VOUT2
3 6 @ PJP79 7 8 2 1
10U_1206_25V6M VIN2 VOUT2 2 1
100K_0402_5%
5 1 2
470P_0402_50V7K
1000P_0402_50V7K
10U_0603_6.3V6M
1 15 2 2 JUMP_43X79
2
GPAD
R935
C435
PAD-OPEN 4x4m 1
4
C776
C417
C416
TPS22966DPUR_SON14_2X3~D
+MXM_SRC_EN#
2 1 1
10/15
2
1
2
20K_0402_5%
0.01U_0402_50V7K
R944
B B
1 R935 form 20K to 100K
C774
Power saving
1 2
D 2
3.3V_RUN_GFX_ON 2 Q87
S
+3.3V_M Source
3
+3.3V_SUS Source
+3.3V_M_PWR +3.3V_M
U40 @ PJP90
1 2 1 14 +3.3V_M_PWR 2 1
<51,58> A_ON +3.3V_ALW VIN1 VOUT1 2 1
+1.05V_RUN R878 0_0402_5% 2 13
VIN1 VOUT1
10U_0603_6.3V6M
JUMP_43X79
39_0402_5%
1 2 A_ON_R 3 12 1
<19,43,50,58> SIO_SLP_A# ON1 CT1
1
@ R877 0_0402_5%
@ R925
C513
4 11
+5V_ALW VBIAS GND
1 2 SUS_ON_R 5 10 2 +3.3V_SUS_PWR +3.3V_SUS
<50,57> SUS_ON ON2 CT2
R806 0_0402_5%
2
6 9 @ PJP94
+1.05V_RUN_CHG
+3.3V_ALW VIN2 VOUT2

1 2 7 8 2 1
<19,43,50,57> SIO_SLP_S4# VIN2 VOUT2 2 1
@ RD42 0_0402_5%
470P_0402_50V7K
470P_0402_50V7K
10U_0603_6.3V6M
15 2 2
1 2 GPAD JUMP_43X79
<50> USH_PWR_ON 1
C476
C477
C475
@ R1621 0_0402_5% TPS22966DPUR_SON14_2X3~D
1 1
2
1
D
A A
RUN_ON_ENABLE# 2
G @ Q70
S DMN65D8LW-7_SOT323-3
3
Title
Power Control
www.Vinafix.vn
LA-9781P 0.2
5 4 3 2 1
5 4 3 2 1
+COINCELL
EMI Part (35.33)
COIN RTC Battery
EMC@ PL1
1
C8B BPH 853025_2P
1 2 +PWR_SRC_MXM PR1
+PWR_SRC 1K_0402_5%
+3.3V_RTC_LDO
10U_0805_25V6K
0.1U_0603_25V7K
2
1
JRTC1
100U_25V_M
Z4012
1
1
+ 1
PC1
PC31
PC30
+COINCELL 1
2
2
2
D 2 D
@ @ 3
GND
2
4
+RTC_CELL GND
ESD Diodes
ACES_50271-0020N-001
PD1
1
PD2
EMC@ BAS40CW_SOT323-3 1
1 4 PC2
I/O1 I/O3 EMI Part (35.35) 1U_0603_10V4Z
2
2 5 Move to power schematic
GND VDD
3 6
I/O2 I/O4 EMI Part (35.33)
AZC099-04S.R7G_SOT23-6 EMC@ PL2 +3.3V_ALW
FBMJ4516HS720NT_2P
1 2
Primary Battery Connector
EMC@ PL6
EMI Part (35.33)
1
FBMJ4516HS720NT_2P
100K_0402_5%
PBATT1 PBATT+_C 1 2
PBATT+
11
PR2
GND 10
GND 1
PR3
2
9 2
8 3 Z4304 4 5
2200P_0402_50V7K
7 PBAT_SMBCLK <51>
4 Z4305 3 6
6 5 2 7 PBAT_SMBDAT <51>
Z4306
5 PBAT_PRES# <50,62>
1
6 1 8
EMC@ PC4
4 7
3 8 PQ1
2
2 9 100_0804_8P4R_5% NTR4502PT1G_SOT23-3
C C
1 PD5
SUYIN_200045GR009M28QZR 1 2 1 3
S
DOCK_SMB_ALERT# <48,50>
CONN@ SDMK0340L-7-F_SOD323-2
G
2
PR33
GND 1 2
<48,50,62> SLICE_BAT_PRES#
0_0402_5%
1
PC5
1500P_0402_50V7K
2
+3.3V_ALW
EMI Part (35.33) @ PR7 PU1
2.2K_0402_5%
2
1 2 1 6
<48> DOCK_PSID NO IN GPIO_PSID_SELECT <50>
0_0402_5%
PR8
2 5 +5V_ALW
EMC@ PL3 PR9 GND V+
1
BLM15BX102SN1D_2P 33_0402_5%
NB_PSID 2 1 1 3 1 2 NB_PSID_TS5A63157 3 4
D
S
NC COM PS_ID <51>
PQ2 74LVC1G3157GW SC-88 6P MUX
100K_0402_1%
2
FDV301N_G_NL_SOT23-3~D
G
2
+5V_ALW
PR10
10K_0402_1%
1
1
B B
C
2 PQ3
PR11
B MMST3904-7-F_SOT323-3
E
15K_0402_1%
3
2
2
PR12
PR13
1 2
PSID_DISABLE# <50>
1
@ 10K_0402_5%
DC_IN+ Source +PWR_SRC_S

+PWR_SRC
3 1
SI7149DP PQ5
+DC_IN +DC_IN_SS
100K_0402_1%
0.1U_0603_25V7K
0.22U_0603_25V7K
1
1
EMI Part (35.33)
1
2
PC7
PC8
@
PR15
3 5
0.022U_0603_50V7K
EMC@ PL4 @
2
C8B BPH 853025_2P @
2
1 2 +DC_IN PQ4 @
4
3
@ PR17 TP0610K-T1-E3_SOT23-3
1
22K_0402_1%
1M_0402_5%
VZ0603M260APT_0603
1 2 VSB_N_001
100K_0402_5%
10U_0805_25V6K
2
2
PR16
1VSB_N_003
1
PJPDC1
PD8
1
1
PQ8B
@ PR21
PR18
PC14
1000P_0402_50V7K
1 2
1
1 2VSB_N_002
4.7K_0805_5%
+3.3V_ALW
2
2 3
1
@ PR20
PC9
0.1U_0603_25V7K
3 4
1
SSM3K7002FU_SC70-3~D
1 2
PQ7
0_0402_5%
EMC@ PC11
SOFT_START_GC <62>
2
4
IMD2AT-108_SC74-6~D
4 5
1
IMD2AT-108_SC74-6~D PR23 @ 2
@ PR19
5 6
1
2 10K_0402_5% 1 2 @
@EMC@ PC15
G
1M_0402_5%
2
6 7 +DCIN_JACK <51,54> PCH_ALW_ON .1U_0402_16V7K S

2
3
7 8
1
0_0402_5%
PR22
PC16
A A
8 9 5
PQ8A
9 10 AC_DIS <50,62>
2
10 11 @
11
ACES_50493-0110N-001
6
CONN@ DELL CONFIDENTIAL/PROPRIETARY

www.Vinafix.vn
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D +DCIN
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 0.1
LA-XXXX
5 4 3 2 1
A B C D E
+3.3V_ALW2
+3.3V_RTC_LDO
PR100
6.49K_0402_1%
1 2 PR101
15K_0402_1%
1 2 1 1
1U_0603_10V6K
PR102 PR104
2
0_0402_5%
10K_0402_1% 10K_0402_1%
1
PR103
PC114
1 2 2 1
2
1
100K_0402_1%
2
110K_0402_1%
+DC1_PWR_SRC
PR106
PR105
+DC1_PWR_SRC +3.3V_ALW
1
<51> ALW_PWRGD_3V_5V
1
110K_0402_1%
EMC@PL100
EMC@ PL100
2
1UH_PCMB053T-1R0MS_7A_20%
PR119
2 1 PU101
10U_0805_25V6K
10U_0805_25V6K
1
1
PC109
PC104
+PWR_SRC
CS2
VFB2
VREG3
VFB1
CS1
2200P_0402_50V7K
10U_0805_25V6K
0.1U_0402_25V6
21
SIS412DN-T1-GE3_POWERPAK8-5
1
PAD
1
1
PC110
3V_5V_EN 6
2
EN2
5
@EMC@ PC105
@EMC@ PC106
PR118 14 @
EMI Part (35.33) VO1
5
0_0402_5%
2
1 2 7
PGOOD
PQ101
19
VCLK
PQ102
4 UG_3V 10 TPS51225CRUKR_QFN20_3X3
PC112 PR108 DRVH2 16 UG_5V 4
0.1U_0603_25V7K 2.2_0603_5% DRVH1 PR107 PC111
1 2 BST1_3V 1 2 BST_3V 9 2.2_0603_5% 0.1U_0603_25V7K
VBST2 17 BST_5V 1 2 BST1_5V1 2
EMI Part (35.33)
1
2
3
2 VBST1 2
3
2
1
SW2 8
SW2 18 SW1
VREG5
DRVL2
DRVL1
+3VALWP PL103 SW1 PL102
+5VALWP
EN1
VIN
2.2UH_ETQP3W2R2WFN_8.5A_20% 3.3UH_ETQP3W3R3WFN_7A_20%
2 1 1 2
3V_5V_EN
11
12
13
20
15
1
1
220U_6.3V_M
4.7_1206_5%
4.7_1206_5%
LG_3V LG_5V
@EMC@ PR109
@EMC@ PR110
1
220U_6.3V_M
PC101
+
1
SNUB_5V
PQ103
PQ104
SNUB_3V 2
PC102
4 4 +
2
56P_0402_50V8J~D
1
1U_0603_10V6K
PC199
0.1U_0603_25V7K
680P_0603_50V7K
680P_0603_50V7K
1
2
3
3
2
1
1
1
PC117
PC118
2
1
1
@EMC@ PC116
@EMC@ PC119
@
2
2
2
EMI Part (35.33)
+DC1_PWR_SRC +5V_ALW2
EMI Part (35.33)
3 3VALWP 3
Ripple voltage - 3V_5V_EN

5VALWP
Static load 3% / Dynamic load 5% Ripple voltage -
Frequency 350kHz PR112 Static load 3% / Dynamic load 5%
2K_0402_1%
TDC 6.1 A 1 2 Frequency 300kHz
<51> ALWON
Peak Current 8.7 A TDC 6 A
OCP current 10.5 A PR111 Peak Current 8.5 A
0_0402_5%
TYP MAX <27> THERM_STP#
1 2 OCP current 10.2 A
H/S Rds(on) 24mohm , 30mohm TYP MAX
L/S Rds(on) 10.3mohm , 12.4mohm H/S Rds(on) 24mohm , 30mohm
Choke DCR Max:17mohm
1U_0603_10V6K
L/S Rds(on) 10.3mohm , 12.4mohm

1
PJP100 PJP102
PC120
Choke Ityp:8.3A / Isat:10.8A +3VALWP

1 2 +3.3V_ALW+5VALWP 1 2
+5V_ALW Choke DCR Max:28mohm
Bulk cap ESR 15mohm
2
@
PAD-OPEN 4x4m PAD-OPEN 4x4m
Choke Ityp:6.6A / Isat:8.2A
PJP101 PJP103 Bulk cap ESR 15mohm
1 2 1 2
PAD-OPEN 4x4m PAD-OPEN 4x4m
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/01/17 Deciphered Date 2013/01/16 Title
www.Vinafix.vn
PWR-3VALWP/5VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9781P
A B C D E
5 4 3 2 1
0.675Volt +/- 5%
PJP201
TDC 1 A
VLDOIN_1.35V 2 1 +1.35V_MEN_P
EMI Part (35.33) Peak Current 1.4 A
+PWR_SRC PJP@PJP200
PR200 2
PAD-OPEN1x1m OCP Current 1.7 A
2 1 1.35V_B+ 1 BOOT_1.35V
2 1
2.2_0603_5%
JUMP_43X118
DH_1.35V
PC204 @EMC@
PC205 @EMC@
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2200P_0402_50V7K
+0.675V_P
2
SIR472DP-T1-GE3_POWERPAK8-5
22U_0805_6.3VAM
10U_0805_6.3V6M
1
1
PC206 SW_1.35V
PC202
PC203
5
0.22U_0603_10V7K
1
D D
1
@ DL_1.35V
PC207
PC208
16
17
18
19
20
PU200
PQ201
VLDOIN
BOOT
VTT
PHASE
UGATE
2
4 21 @
PAD
15 1
LGATE VTTGND
1
2
3
PR201 14 2
+1.35V_MEN_P PL201 6.49K_0402_1% PGND VTTSNS +V_DDR_REF
1.0UH_PCMC104T-1R0MN_20A_20% 1 2 CS_1.35V
1 2 13 3
PC213 CS RT8207MZQW_WQFN20_3X3 GND
5
1U_0603_10V6K
4.7_1206_5%
PR203 2 1 VDDP_1.35V 12 4 +V_DDR_REF
SIRA06DP-T1_POWERPAK-SO8-5~D
5.1_0603_5% VDDP VTTREF PJP203
PR202
330U_2.5V_M
1
2 1
@EMC@
+ 1 2 VDD_1.35V 11 5 PC209 2 1
PC201
1 SNUB_1.35V 2 VDD VDDQ +1.35V_MEN_P
PGOOD
4 0.033U_0402_16V7K JUMP_1x3m
PQ202
TON
2 +5V_ALW PC210
FB sense trace PJP204
FB
S5
S3
1U_0603_10V6K +1.35V_MEN_P 2 1 +1.35V_MEM
2
2 1
when FB pull down to GND
680P_0603_50V7K
3
2
1
10
6
JUMP_1x3m
+3.3V_ALW +5V_ALW
@EMC@
PC211 220P_0402_50V8J
PC212
1 2
PJP202
2
1
PR209 +0.675V_P 2 1 +0.675V_DDR_VTT
100K_0402_1% PR204
10K_0402_1%
1.35V_FB 2 1 PAD-OPEN1x1m
1.35VP
2
<51,7> 1.35V_SUS_PWRGD 1.35V_SUS_PWRGD
Ripple voltage - EMI Part (35.33)
PR205
C Static load 3% / Dynamic load 5% 1M_0402_1% C
2
@ PR206 1.35V_B+ 1 2
Frequency 250kHz
1
200K_0402_5% PR207
1 2 S5_1.35V PC214
1.35V_FB
TDC 8.5 A <19,43,50,54> SIO_SLP_S4# 12.4K_0402_1%
@ .1U_0402_16V7K
2
Peak Current 15 A PR208
1
PR240 100K_0402_5%
OCP current 18 A <50,54> SUS_ON
2 1
<50> 0.75V_DDR_VTT_ON
1 2 S3_1.35V
+3.3V_ALW @ PR211
TYP MAX
1
0_0402_5% PC215 150K_0402_1%
1
1 2
H/S Rds(on) :12.2mohm , 15mohm 1U_0402_6.3VX5R @ PR213
2
L/S Rds(on) :2.75mohm , 3.5mohm 10K_0402_5%
6
Choke DCR 2.35mohm
+3.3V_ALW @ PQ204A
2
+1.35V_MEN_P
Choke Ityp:21.3 / Isat:22.4A 2
1
Bulk cap ESR 17mohm @ PR216
10K_0402_5%
0.01U_0402_25V7K
1
10K_0402_5% @
FB sense trace
1
PQ204B
1
@ PR219
1.35V_FB
PC216
2
10K_0402_5%
PR217
1 2 5
<50> DDR_1.35V_CNTRL0
2
@
2
1
@
0.01U_0402_25V7K
4
1
1
PR220
PC219
75K_0402_1%
10K_0402_5%
PR218
2
@ @
DDR_1.35V_CNTRL1 DDR_1.35V_CNTRL0 DDR_VOUT
2
2
@
+3.3V_ALW
0 0 1.5 V
@ PR221
6
+3.3V_ALW 10K_0402_5%
@ PQ205A
B 0 1 1.45 V B
2
1
@ PR222 2
10K_0402_5%
1 0 1.4 V
1
3
@ PR223 @ PQ205B
1 1 1.35 V
10K_0402_5%
0.01U_0402_25V7K
2
10K_0402_5%
1
1 2 5
<50> DDR_1.35V_CNTRL1
1
PR224
PC220
0.01U_0402_25V7K
4
1
2
1
@ PR225 @ @
PC217
2
10K_0402_5%
2
@
2
A A
www.Vinafix.vn
PWR-1.35VP/0.675VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9781P
5 4 3 2 1
5 4 3 2 1
PJP300
+1.05VSP_B+ 2 1
+PWR_SRC
PAD-OPEN 1x2m~D
+3.3V_ALW
2200P_0402_50V7K
10U_0805_25V6K
4.7U_0805_25V6-K
0.1U_0402_25V6
1
1
@EMC@ PC303
@EMC@ PC302
PC304
PC305
2
D D
2
5
PR300
100K_0402_5% @
PQ301
1
<51> 1.05V_A_PW RGD
4
PC306
PU300 .1U_0603_25V7K
EMI Part (35.33)
PR301
1 10 BST_+1.05VSP 1 2 2 1
3
2
1
PGOOD VBST
PR302 2.2_0603_5%
S0 mode be high level 1 2 TRIP_+1.05VSP 2 9 UG_+1.05VSP PL301
TRIP DRVH 1UH_PCMC063T-1R0MN_11A_20%
100K_0402_1%
@ PR303 EN_+1.05VSP 3 8 SW _+1.05VSP 1 2
<19,43,50,54> SIO_SLP_A#
150K_0402_5% EN SW
+1.05V_MP
1 2 FB_+1.05VSP 4 7 +1.05VSP_5V
VFB V5IN +5V_ALW
0_0402_5% PR315 RF_+1.05VSP 5 6 LG_+1.05VSP
330U_2.5V_M
TST DRVL 1
1
1 2
2 1 11 +
PC301
<51,54> A_ON TP PC308 PR304 @EMC@
1
TPS51212DSCR_SON10_3X3 1U_0603_10V6K 4.7_1206_5%

1
PQ303
2
PC307 PR305 4
0.22U_0402_16V7K 470K_0402_1%
2
1
PC309 @EMC@
2
1000P_0402_50V7K
3
2
1
2
C C
PR306
4.99K_0402_1%
2 1
+1.05VSP
Ripple voltage -
2
Static load 3% / Dynamic load 5%

PR307 PJP301
10K_0402_1% 2 1 Frequency 290kHz
PAD-OPEN 1x2m~D TDC 4.5A
1
PJP302 Peak Current 6.3A

+1.05V_MP 2 1 +1.05V_M OCP current 7.5A
B PAD-OPEN 1x2m~D TYP MAX B
H/S Rds(on) 24mohm , 30mohm

L/S Rds(on) 10.3mohm ,12.4mohm
Choke DCR 11mohm
Choke Ityp:11A / Isat:14.5A
Bulk cap ESR 17mohm
A A

PWR-+1.05VSP
www.Vinafix.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9781P
5 4 3 2 1
A B C D
1 1
+1.5VSP
PR400
2 1
TDC 0.627A
+3.3V_RUN
Peak Current 0.812A
10K_0402_5% OCP current 3.5A
1.5V_RUN_PWRGD <51>
PU400 PL401
4
PJP400 1UH +-30% NRS4018T1R0NDGJ 3.2A
+3.3V_ALW 2 1 1.5VSP_VIN 10 2 1.5VSP_LX 1 2
PG
PVIN LX +1.5V_RUNP
22P_0402_50V8J
PJP@
PAD-OPEN 1x2m~D 9 3
PVIN LX
1
1
1
4.7_0603_5%
2 2
PC402
PC400 8
SVIN
@EMC@ PR401
22U_0805_6.3VAM PR402
6 1.5VSP_FB 30.1K_0402_1%
2
FB
22U_0805_6.3VAM
22U_0805_6.3VAM
5
2
EN
1
NC
NC
TP
PC403
PC404
11
2
SNUB_1.5VSP
1 2 EN_1.5VSP
<19,43,49,50,54> SIO_SLP_S3#
1
1
.1U_0402_16V7K
PR403 @
PC406
0_0402_5% SYN470DBC_DFN10_3X3 PR405
1
@ PR404 20K_0402_1%
47K_0402_5%
2
1 2 @
<49,50,54> RUN_ON
680P_0402_50V7K
PR406
@EMC@ PC407
0_0402_5%
EMI Part (35.33)
2
<Vo=1.5V> VFB=0.6V
3
Vo=VFB*(1+PR402/PR405)=0.6*(1+30.1K/20K)=1.5V 3
PJP401
2 1
+1.5V_RUNP +1.5V_RUN
PAD-OPEN 1x2m~D
4
DELL CONFIDENTIAL/PROPRIETARY 4

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL PWR-1.5VSP
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.2
A B C D
www.Vinafix.vn
5 4 3 2 1
+5V_ALW CPU_B+
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
PC501
1U_0603_10V6K
0.22U_0603_16V7K
1
1
2
1
0_0402_5%
PC500
PC502
PC503
PC504
1
PR501
2
+VCCIO_OUT PR500 130_0402_1% PR502
2
2 1 2.2_0603_5%
1
@ PR503 75_0402_5% PQ500 @
2
2 1 CSD87350Q5D_SON8~D
1
D PU501 D
PR504 54.9_0402_1% 6 1 UGATE3 2
2 1 VCC UGATE EMI Part (35.33)
7 2 BOOT3 PL500
FCCM BOOT 7 0.22UH_FDUE0640J-H-R2_25A_20%
PR505 0_0402_5% PWM3 3
PWM PHASE
8 PHASE3 3 6 P3_SW 2 1 +VCC_CORE
680P_0603_50V7K
<11> VIDSOUT 1 2 PR507 5
PR506 0_0402_5% 21K_0402_1% 4 5 LGATE3 4
GND LGATE
@EMC@ PC507
<11> VIDALERT_N 1 2 1 2 9 PQ501
PR508 0_0402_5% TP CSD87350Q5D_SON8~D PR510
1
<11> VIDSCLK 1 2 PR509 ISL6208BCRZ-T_QFN8_2X2 10K_0603_1%
2
3.24K_0402_1% UGATE3 2 2 1
8
1 2 SNB_CPU_P3
4.7_1206_5%
3.65K_0603_1%
ISEN3
10_0402_1%
PR514 7
@EMC@ PR515
PR511
PR512
PR513 0_0402_5% 21K_0402_1% PHASE3 3 6 @ PR516
<50> IMVP_VR_ON 1 2 1 2 5 1_0402_5%
LGATE3 4 V1N 1 2
@ PR517 +5V_ALW
1
<51> 1.05V_0.8V_PWROK 1 2 BOOT2 @ PR518
0_0402_5% UGATE2 1_0402_5%
ISUMP
PR519 1.91K_0402_1% PHASE2 V2N 1 2
ISUMN
2 1 SDA PR520
+3.3V_RUN ALERT# 0_0603_5%
<50> IMVP_PWRGD PC508
1U_0603_10V6K
32
31
30
29
28
27
26
25
VCORE_VDDP 1
1 2
PC509
VCC_core (Base on PDDG rev 1.1)
SDA
ALERT#
SLOPE/PROG1
PROG3
PROG2
BOOT2
UGATE2
PHASE2
1 2 TDC 40A
820P_0402_50V7K Peak Current 95A
PR522 SCLK 1 24 LGATE2 @
PR521 0_0402_5% VR_ON 2 SCLK LGATE2 23
PR523 DC Load line -1.5mV/A
93.1K_0402_1% 1 2 VCC_PGOOD 3 VR_ON VDDP 22 PWM3 2 1
2 1 IMON 4 PGOOD PWM3 21 LGATE1 0_0402_5% Icc_Dyn_VID1 60A
C IMON LGATE1 C
1
PR524
2 VR_HOT#
5
6 VR_HOT# PHASE1
20
19
PHASE1
UGATE1
OCP current 114A
<51,61,62,7> H_PROCHOT# NTC UGATE1
DCR 0.98m ohm
47P_0402_50V8J
0_0402_5% NTC COMP 7 18 BOOT1

COMP BOOT1
PC510
PR525 FB 8 17
FB VIN
1
1 2 2 1 PR526
FB2/VSEN
PH500 0_0402_5%
+PWR_SRC
ISUMN
ISUMP
ISEN3
ISEN2
ISEN1
3.83K_0402_1%
470K_0402_5%_ TSM0B474J4702RE 33 1 2CPU_B+ EMC@ PL510
VDD
RTN
2
PAD FBMA-L11-453215-800LMA90T_1812
0.22U_0603_25V7K
PR528 CPU_B+ 1 2
470P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
27.4K_0402_1% 9 PU500
10
11
12
13
14
15
16
1
2 1 PR529 ISL95812HRZ-T_QFN32_4x4
1 2
1
PC511
PC512
PC513
PC514
@EMC@ PC515
EMC@ PC516
2
6.04K_0402_1% @ PQ502
CSD87350Q5D_SON8~D
2
1
2
4700P_0402_25V7K 909_0402_1%
PR531 UGATE2 2
+5V_ALW
PR541
1_0402_1%
1 2
2
PHASE2 7 PL501
EMI Part (35.33)
4700P_0402_25V7K
PC525 3 6 P2_SW 0.22UH_FDUE0640J-H-R2_25A_20%

2 1
1
39P_0402_50V8J PC520 5 2 1
+VCC_CORE
1
680P_0603_50V7K
PR533 390P_0402_50V7K PC519 PR534 4
PC526
2 1 2 1 VCCSENSE .1U_0603_25V7K BOOT2 2 1 1 2 PR535
2
1
1
PC522
@EMC@ PC523
2.2_0603_5% 3.65K_0603_1%
1
10_0402_1% PC521 PQ503 1 2

619_0402_1%
LGATE2 0.22U_0603_16V7K CSD87350Q5D_SON8~D PR539

2
2
1
1
PR536 SNB_CPU_P2 10K_0603_1%
PR537
2 1 UGATE2 2 1 2
1
4.7_1206_5%
1
ISUMP
@EMC@ PR542
2.87K_0402_1% ISEN2
2
7 @ PR546 PR544
2
2
1.5K_0402_1%
PR543 PHASE2 3 6 1_0402_5% 10_0402_1%

PR545
2K_0402_1% 5 V1N 2 1
2
B LGATE2 4 B
2
@ PR547
2 1
1_0402_5%
1
ISUMN
V3N 2 1
PC527
8
330P_0402_50V7K~D
1
PC528
0.15U_0402_10V6K CPU_B+
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
1 2 1 1 1
100U_25V_M
100U_25V_M
100U_25V_M
PC529
+
PC530
+
PC531
ISEN3 +
1
PC533
PC534
PC535
PC532 PQ504
0.1U_0603_25V7K CSD87350Q5D_SON8~D
1
ISEN2 PR548 1 2 2 2 2
2
0_0402_5% UGATE1 2
1 2
ISEN1 @ PC538
0.033U_0603_25V7K 7
PC539 1 2 PHASE1 3 6 P1_SW PL502
0.22U_0402_6.3V6K 5 0.22UH_FDUE0640J-H-R2_25A_20%
<11> VCCSENSE
2 1 4 2 1
+VCC_CORE
680P_0603_50V7K
PR550 PR549
PC541 11K_0402_1% BOOT1 2 1 1 2 PQ505 @
@EMC@ PC545
0.22U_0402_6.3V6K @ PC542 1 2 2.2_0603_5% CSD87350Q5D_SON8~D
1
2 1 ISUMN 1 2 PC540 8
0.082U_0402_16V7K
0.22U_0603_16V7K UGATE1 2 PR552 PR553
2
PC544
PC543 330P_0402_50V7K PH501 PR551 LGATE1 SNB_CPU_P1 3.65K_0603_1% 10K_0603_1%

1
0.22U_0402_6.3V6K 10KB_0402_5%_ERTJ0ER103J 2.61K_0402_1% 1 2 1 2
1
4.7_1206_5%
2 1 1 2 1 2 7
@EMC@ PR554
PHASE1 3 6 ISEN1
2
1
ISUMP
PC546 @ 5
1 2 PR558 LGATE1 4 @ PR556 PR555
.1U_0402_16V7K
5.1M_0402_5% V2N 2 1 10_0402_1%
2
1
A A
0.01U_0402_50V7K 1 2 1_0402_5%
PC547
ISUMN 2
ISUMN ISUMP @ PR557
2
8
V3N 2 1
<11> VSSSENSE
10K_0402_1%
EMI Part (35.33)
Local sense put on HW site DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc.
www.Vinafix.vn
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +VCC_CORE
5 4 3 2 1
A B C D
Iada=0~12.3A(240W) +CHAGER_SRC
+PWR_SRC EMC@ PL700
ADP_I = 40*Iadapter*Rsense 1UH_PCMB053T-1R0MS_7A_20%
2 1
@ PD700 PR701 CC = 3.52A (Normal)
2 1 +SDC_IN 0.005_1206_1%
ES2AA-13-F 1 4
EMI Part (35.33) CV = 13.3V
PQ701 SI7149DP
0.1U_0603_25V7K
2 3
1 @
1
2
+DC_IN_SS 5 3
PC700
PR703
1
D
2 1 2 PQ702
<62> CSS_GC
4
G NTR4502PT1G_SOT23-3
PR700
1
D
S
3
1
2 1 0_0402_5% 2 PQ700 PQ703A @ PC746
1
DC_BLOCK_GC <62> 1 2
G NTR4502PT1G_SOT23-3 SI3993CDV
S
3
0_0402_5%
S
5 6 100P_0402_50V8J
D
DOCK_DCIN_IS+ <48>
1
BQ24737_VDD PR715
CSSN_1
CSSP_1
PR702
20_0402_1% PU701
G
1
PQ703B 1 6 2 1 ADP_I <51,61>
PR707 SI3993CDV REF Out
PR713
2
100K_0402_5%
100K_0402_1%
0_0402_5%
S
2 1 2 4 1 2
D
DOCK_DCIN_IS- <48>
PR772
1
10K_0402_1% PR771 PR711
PR709
100K_0402_1%
12.1_0402_1%
1
47K_0402_1% PR710 0_0402_5% 2 5 CSSN_2
G
3
GND IN-
1
<17,27,51,61,62> ACAV_IN ACAV_IN 0_0402_5%
2
PC702 PC703 3 4 PR706
PR712
10U_0805_25V6K
10U_0805_25V6K
+SDC_IN
2200P_0402_50V7K
0.1U_0603_25V7K
0.1U_0402_25V6 0.047U_0402_25V7K PC704 V+ IN+
33.2_0402_1%
0.1U_0603_25V7K
PR714
2
1
1 2 1 2 1 2 INA199A1DCKR_SC70-6
2
3
1
2 1 2 1 CSSP_2
@EMC@ PC705
@EMC@ PC706
PC707
PC708
PC701
DK_CSS_GC <62>
2
PR717 0.1U_0402_25V6
PQ707B
+SDC_IN
CSSP_2
2
12K_0402_1% 5 ACPRN 0_0402_5% PR708 6.8_0402_1%~D
2
VIN in detect limit
CSSN_2
499K_0402_1%
4
+SDC_IN=2.4V/82.5*(82.5+499)=16.9V sense adapter Discrete current monitor circuit
1
SIR472DP-T1-GE3_POWERPAK8-5
2 +DOCK_PWR_BAR
EMI Part (35.33)
PR762
PD701 PQ704
+CHG_VCC 1
PR732
2
5
82.5K_0402_1% 3
1 2 ACDET +DC_IN_SS
2
2 1 @ PR704 0_0402_5% PR775 BAT54CW_SOT323-3
CMPIN
ACN
CMPOUT
ACOK
ACP
1 2 10_1206_5%
<51,61> ADP_I
0.1U_0402_25V6 PC783 PR705 0_0402_5% 21 4
1 2 6 TP 1U_0603_25V6K
2 2
PC791
1
<51> BST_CHG_IMON ACDET
PC744 20 1 2
1 2 7 VCC PR723 +VCHGR
3
2
1
IOUT PL701 0.01_1206_1%
PR763 0_0402_5% 100P_0402_50V8J 19 5.6UH_PCMB104T-5R6MS_8A_20%
2 1 8 PU700 PHASE LX_CHG 1 2 CHG
1 4
<51> CHARGER_SMBDAT SDA
BQ24737RGRR_VQFN20_3P5X3P5
4.7_1206_5%
0_0402_5% PR766 18 DH_CHG 2 3
HIDRV
1
2 1 9 PQ705
<51> CHARGER_SMBCLK
FDMC7692S_MLP8-5
SCL
5
PR765 PC734 CSOP_1 CSON_1
@EMC@ PC717 @EMC@ PR724

2.2_0603_5% 0.047U_0603_50V7
PR764 20K_0402_1% 10 17 BST_CHG 1 2 2 1
10U_0805_25V5K~D
10U_0805_25V5K~D
10U_0805_25V5K~D
1 2 ILIM BTST PD703
Current limit +3.3V_ALW
2
1
1
SDMK0340L-7-F_SOD323-2 SNUB_CHG
PC718
PC719
PC715
LODRV
16 2 1 4
Charger :8A Vilim=1.6V :
GND
SRN
SRP
REGN
1
BM
PR758 PR760 26.7K_0402_1%
680P_0402_50V7K
2
Max Boost Charger 12A Vilim=2.4V 53.6K_0402_1% @
BQ24737_VDD
2
6 2
11
1 12
1 13
14
15
2
9 Cell (1.3C )
6.8_0603_5%
3
2
1
1
10_0603_5% PC745
PQ707A
PR761
PR759
1U_0603_25V6
2
2
2
PC792 DL_CHG
1
0.1U_0603_25V7K
10K_0402_5%
2
2 1
PR757
EMI Part (35.33)

PR718
1
2 1 24737_BST_CHG_MODE#
<50> BST_CHG_MODE#
1
PC786
0.1U_0603_25V7K
2
0_0402_5%
+3.3V_ALW
3
Maximum charging current is 7.2A 3
+3.3V_ALW2
+5V_ALW
+DC_IN BQ24737_VDD
H_PROCHOT# <51,60,62,7>
100P_0402_50V8J
0.01U_0402_25V7K
DYN_TUR_CURRENT_SET# PR734
10K_0402_1%
1M_0402_1%
232K_0402_1%
1
1
1 2
PC727
PC728
221K_0402_1%
2
PR739 PR737
PR735
PR736
PR738
+5V_ALW
210W High 0_0402_5% 48.7K_0402_1%
2
+3.3V_ALW2 @ @
+5V_ALW PR740
1
2
1.8M_0402_1%
1
8
1 2 PU703A
240W Low PR742
1
P
PR741 + 1 2 1
O ACAV_IN_NB <51,62>
6
100K_0402_1% PR743 2
12K_0402_1%
22.6K_0402_1%
40.2K_0402_1%
100P_0402_50V8J
-
8
G
20K_0402_1% PU703B
PQ706A
100P_0402_50V8J
0_0402_5%
1
ADP_I 1 2 5 LM393DR_SO8~D
PQ706B
P
2
4
+
1
7 2 PC729
PR744
PR745
PC730
PR746
6 O 5
-
G
1000P_0402_50V7K
220P_0402_50V8J
2
0.015U_0402_16V7K
LM393DR_SO8~D
4
2
1
PC731
523K_0402_1%
261K_0402_1%
+3.3V_ALW
PC735
PC736
100P_0402_50V8J
1
2
1
PR747
PR748
PC732
@
2
1
3 2
PR749
+3.3V_ALW 100K_0402_5%
PC733
<51> DYN_TUR_CURRNT_SET# 0.1U_0402_25V6
2
5 @
PR716 2 1
BST_CHG_MODE# 2 1 DIS_PROCHOT#
4
4 4
PQ708B DMN66D0LDW-7_SOT363-6
5
6
DMN66D0LDW-7_SOT363-6 PU704 PQ708A
0_0402_5% 1
P
4 B
O 2 2
A PROCHOT_GATE <50> ACAV_IN <17,27,51,61,62>
G
To preset system to throtlle

Adapter Protection Circuit for Turbo Mode
3
1
switching from AC to DC
74AHC1G08GW AND~D
www.Vinafix.vn
PWR-Charger
0.2
A B C D
5 4 3 2 1
PD1001
2
+DOCK_PWR_BAR
1
3
1
PQ1009 SI7149DP SI7149DP PQ1008 PDS5100H-13_POWERDI5-3~D
PR1001 PQ1001 SI7149DP
1 1 330K_0402_5%
2 2 1
5 3 3 5 2
2
5 3
1
0.1U_0603_25V7K
0.47U_0805_25V7K~D
1
200K_0402_1%
4
4
PC1099
PR1099
PC1001
2
2
D D
PR1002
1
2 1 STSTART_DCBLOCK_GC
PR1097
150K_0402_1% 0_0402_5%
2
1
PD1099
1
SDMK0340L-7-F_SOD323-2 D 100K_0402_5% PR1098
2 2 1
SLICE_BST_CHG_EN <50,62>
2
G PD1002
S PQ1010 2
3 1
SSM3K7002FU_SC70-3~D PR1003 3
330K_0402_5%
PDS5100H-13_POWERDI5-3~D
1 2 PQ1004 SI7149DP
PBATT+ SI7149DP PQ1003
PQ1005 PQ1002 1
SI4835DDY-T1-E3_SO8 SI4835DDY-T1-E3_SO8 1 2
+VCHGR 1 8 8 1 2 PBATT_IN_SS 5 3
+PWR_SRC
2 7 7 2 3 5
2200P_0402_50V7K
1
3 6 6 3
1K_1206_5%
3
5 5 PR1004
PR1005
0.1U_0402_25V6
4
1
2 1
PC1002
PC1003
4
4
2 0_0402_5%
2
PR1006
1U_0603_25V6K
1 2BLK_MOSFET_GC @ @
PQ1083B
1
0_0402_5% PC1004
PC1005
1U_0603_25V6K
4
IMD2AT-108_SC74-6~D
1
PR1026
2
IMD2AT-108_SC74-6~D 330K_0402_5%
C PQ1072 C
1
PR1033 NTR4502PT1G_SOT23-3
5 1 2
PQ1083A
SLICE_BST_CHG_EN <50,62>
2
D
3 1
+3.3V_ALW2
1
0_0402_5% PR1008
1 2 DK_PWR_BAR 0_0402_5% PR1009
100K_0402_5%
+DOCK_PWR_BAR
1
PR1007 0_0402_5%
PR1100
G
0_0402_5%
6
2
1 2 3301_DC_IN_SS PR1030
1
+DC_IN_SS PR1010 0_0402_5% <50,55> AC_DIS 2 1

DSCHRG_MOSFET_GC
2
SSM3K7002FU_SC70-3~D
0_0402_5%
2
PD1100
1
D
PQ1011
PD1010
1 2 CD3301_DCIN 1 2 2
+DC_IN <48,50,55,62> SLICE_BAT_PRES#
PR1011 47_0805_5% G 3
S
3
1
PC1006 SDMK0340L-7-F_SOD323-2 1
DOCK_AC_OFF <48> +3.3V_ALW H_PROCHOT# <51,60,61,7>
2
0.1U_0603_50V4Z 1 2 2 @ PC1080
2
PR1032 0_0402_5% PR1031 0.1U_0402_10V7K

P50ALW 1 2 1 2
36
35
34
33
32
31
30
29
28
<55> SOFT_START_GC +5V_ALW @ BAT54CW_SOT323-3 330K_0402_5%

PU1001 PR1012 0_0402_5%
6
PR1013 100K_0402_5% @
NC
CHARGERVR_DCIN
DK_PWRBAR
GND
NC
BLK_MOSFET_GC
DSCHRG_MOSFET_GC
PBatt+
DC_IN_SS
5
1 2 CD_PBATT_OFF 1 2 PU1080
+3.3V_ALW2 SLICE_BAT_ON <50>
PR1016 0_0402_5% SLICE_BAT_PRES# 1
P
B 4 2 DMN66D0LDW-7_SOT363-6
1 2 ACAVDK_SRC 1 2 SLICE_BAT_ON 2 O PQ1080A @
<48> ACAV_DOCK_SRC# A
G
PR1017 0_0402_5% 1 27 PR1014 0_0402_5%
1
2 DC_IN P50ALW 26 1 2 +3.3V_ALW
3
1 2 ERC1 3 SS_GC PBATT_OFF 25 DK_AC_OFF
+SDC_IN ERC1 DK_AC_OFF_EN 1M_0402_5%
PR1015 0_0402_5% 4 24 3301_ACAV_IN_NB 1 2
ACAVDK_SRC ACAV_IN_NB ACAV_IN_NB <51,61>
1
5 23 PR1019 0_0402_5% PR1018
CD3301_SDC_IN 6 GND GND 22 DK_AC_OFF_EN 1 2 PR1083 @ 74AHC1G08GW_SOT353~D
SDC_IN DK_AC_OFF_EN DOCK_AC_OFF_EC <50>
7 21 SL_BAT_PRES# PR1020 0_0402_5% 100K_0402_5%
<61> DC_BLOCK_GC ACAVIN 8 DC_BLK_GC SL_BAT_PRES# 20 BLKNG_MOSFET_GC
P33ALW2 9 ACAV_IN BLKNG_MOSFET_GC 19 +3.3V_ALW @
2
P33ALW2 NBDK_DCINSS
EN_DK_PWRBAR
1 2 @ PC1081
<17,27,51,61> ACAV_IN
SS_DCBLK_GC
PR1021 0_0402_5% 0.1U_0402_10V7K
PQ1080B
3
B B
DK_CSS_GC
1 2 1 2
SLICE_BAT_PRES# <48,50,55,62>
PWR_SRC
PR1023 0_0402_5% CD3301_NBDOCK_DC_IN_SS

CSS_GC
P33ALW
37
TP
5
D<50,55> PBAT_PRES#
ERC3
ERC2
1 2 1 2
CD3301_NBDOCK_DC_IN_SS PU1081 @ 5
GND
+3.3V_ALW2 +NBDOCK_DC_IN_SS
PR1022 0_0402_5% PR1024 0_0402_5% PR1070 SLICE_BAT_ON 2 PBAT_PRES# 1
P
G B 4
@ 0_0402_5%
4
CD3301BRHHR @ PQ1082 2 O
S
10
11
12
13
14
15
16
17
18
3
A
G
PQ1070
1
<61> CSS_GC NTR4502PT1G_SOT23-3 SSM3K7002FU_SC70-3~D
0.1U_0603_25V7K
3
P33ALW 1 2
ERC2
<61> DK_CSS_GC +3.3V_ALW
D
PR1025 0_0402_5% 3 1
+NBDOCK_DC_IN_SS
1
ERC3 74AHC1G08GW_SOT353~D
PC1007
240K_0402_5%
2
EN_DK_PWRBAR 1 2
G
EN_DOCK_PWR_BAR <50>
2
2
0.047U_0603_25V7K~D
PR1027 0_0402_5% 1 2
PR1071
<50> DIS_BAT_PROCHOT#
0.1U_0402_25V6
1 2 @ PR1081
0_0402_5%
PC1008
STSTART_DCBLOCK_GC 1M_0402_5%
PC1009
@ PR1028
2
@ 3301_PWRSRC 1 2
47K_0402_5%
+PWR_SRC +3.3V_ALW2
PR1029 0_0402_5%
PR1072
1
6 2
PR1073
100K_0402_5%
2
DMN66D0LDW-7_SOT363-6 2
PQ1071A
1
DMN66D0LDW-7_SOT363-6 5 DELL CONFIDENTIAL/PROPRIETARY

PQ1071B SLICE_BST_CHG_EN <50,62>
A
Compal Electronics, Inc. A
4
Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Selector
5 4 www.Vinafix.vn 3 2 1
5 4 3 2 1
Based on PDDG rev 0.7 Table 5-1.
+VCC_CORE +VCC_CORE
1 1 1 1
D 1 1 1 1 1 D
+ PC905 + PC906 @ + PC907 @ + PC908
PC900 PC901 PC902 PC903 PC904
10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM 330U_D2_2.5VM_R6M~D 330U_D2_2.5VM_R6M~D 330U_D2_2.5VM_R6M~D 330U_D2_2.5VM_R6M~D
2 2 2 2 2 2 2 2 2
1 1 1 1 1 1
PC909 PC910 PC911 PC912 PC913 PC914 1 1
10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM 10U_0805_4VAM
2 2 2 2 2 2 + + PC916
PC915 330U_D2_2.5VM_R6M~D
+VCC_CORE 2
330U_D2_2.5VM_R6M~D
2
1 1 1 1 1
PC917 PC918 PC919 PC920 PC921
22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM
2 2 2 2 2
C 1 1 1 1 1 C
PC922 PC923 PC924 PC925 PC926

2 2 2 2 2
1 1 1 1 1
PC935 PC936 PC937 PC938 PC939
2 2 2 2 2
1 1 1 1
PC940 PC941 PC942 PC943
22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM 22U_0805_6.3VAM
2 2 2 2
B B
A A
Title
PROCESSOR DECOUPLING
www.Vinafix.vn
5 4 3 2 1
5 4 3 2 1
+1.05V_RUN PCH SIO_PWRBTN#

PWRBTN#
Timing Diagram for S5 to S0 mode VCC

VCCIO
VCCUSBPLL
RSMRST#
PCH_RSMRST#
SIO_SLP_S5#
4
V_PROC_IO
+1.05V_M SLP_S5#
VCCCLK
VCCASW SIO_SLP_S4#
SLP_S4#
+1.5V_RUN SIO_SLP_S3#
VCCADAC1_5 SLP_S3#
VCCVRM
SIO_SLP_A#
5
+3.3V_ALW_PCH SLP_A#
VCCSUS3_3 SIO_SLP_LAN#
VCCSUSHDA SLP_LAN#
CPU +3.3V_RUN SIO_SLP_WLAN#
+VCC_CORE SLP_WLAN#/GPIO29
D PM_DRAM_PWRGD_CPU VCCADACBG3_3 D
SM_DRAMPWROK VCC SYS_PWROK
13 +VCCIO_OUT
VCC3_3_R30
VCC3_3_R32
SYS_PWROK
15
VCC3_3 RESET_OUT#
VCCIO_OUT PWROK
14 H_CPUPWRGD
PWRGOOD +VCOMP_OUT +3.3V_ALW
VCCCLK3_3
12
VCOMP_OUT
3 VDDDSW3_3 PM_DRAM_PWRGD
CPU_PLTRST#_R +1.35V_MEM
DRAMPWROK
13
16 PLTRSTIN
VDDQ PCH_PLTRST#
15 PLTRST#
PROCPWRGD
H_CPUPWRGD
14
PM_APWROK_R
7 APWROK
PCH_DPWROK
DPWROK
4
+3.3V_ALW
ENVDD_PCH
+LCDVDD SI3456DD DGPU_PWR_EN
MXM 10
+3.3V_ALW
Pop option
SIO_SLP_LAN#
6 +3.3V_M +3.3V_LAN SI3456DD
C C
+5V_ALW Power Button

RUN_ON
SIO_SLP_S3#
+5V_RUN +5V_HDD
SIO 5048 DMN3030L 1BAT 2AC
SIO_SLP_S4# +3.3V_ALW
+PWR_SRC 1BAT
5 ADAPTER
SIO_SLP_M#
DMN3030L +3.3V_RUN 9 ALWON +5V_ALW
SIO_SLP_LAN#
EC 5075 TPS5125
+3.3V_ALW 2AC
+1.05V_M
ALW_PWRGD_3V_5V
SI4164DY +1.05V_RUN
1.35V_SUS_PWRGD
+3.3V_ALW BATTERY 5048
SYN470DBC +1.5V_RUN
PCH_RSMRST#
B
4 B
+3.3V_ALW
+PWR_SRC
PCH_ALW_ON
IMVP_VR_ON
ISL95812 +VCC_CORE
SI3456DD +3.3V_ALW_PCH 3
11 PM_APWROK
IMVP_PWRGD
7 +3.3V_ALW
6 Pop option
A_ON
SI3456DD +3.3V_M +3.3V_LAN
+PWR_SRC 8 RESET_OUT#
SUS_ON 12 +PWR_SRC
+1.35V_MEM VDDQ A_ON
0.75V_DDR_VTT_ON
RT8207MZ VTT
DDR TPS51212 +1.05V_M 6
+0.675V_DDR_VTT SIO_SLP_S5#
1.35V_SUS_PWRGD
5 1.05V_A_PWRGD
5075
+3.3V_ALW +PWR_SRC
+3.3V_ALW
MCARD_MISC_PWREN
SUS_ON
SI3456DD +3.3V_SUS 8
PCH_ALW_ON
TP0610K +PWR_SRC_S 3
+3.3V_PCIE_FLASH
SI3456DD
+5V_ALW
+3.3V_ALW
MODC_EN
+3.3V_WLAN AUX_EN_WOWL SI3456DD +5V_MOD
SI3456DD 11
+PWR_SRC
+3.3V_ALW EN_INVPWR
MCARD_WWAN_PWREN FDC654P +BL_PWR_SRC
+3.3V_PCIE_WWAN
A
SI3456DD BC BUS A
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BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Power Sequence
LA-9781P
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List )

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
D D
1 07 HW 11/19 Compal PM_DRAM_PWRGD connection is wrong RC18.2 PM_DRAM_PWRGD change PM_DRAM_PWRGD_A X01(0.2)
2 15 HW 11/19 Compal Follow CRB De-populate CD58 X01(0.2)
3 45 HW 11/19 Compal For mSATA spec define, remove 1.5V_RUN Remove C609, C620 X01(0.2)
4 48 HW 11/19 Compal For ESD request De-populate C695, C696 X01(0.2)
5 51 HW 11/19 Compal Due to BIOS code ready De-populate R1986,R1197,R1118 X01(0.2)
6 30 ME 12/25 Compal Due to ME request Swap JLVDS1 pin X01(0.2)
7 43 HW 12/25 Compal Follow Intel DG 1.5 Change pin4,7,11 X01(0.2)

De-populate CC33, CC34, CC36, CC37, CC38, CC39, CC40, CC42, CC43,
8 11 HW 12/25 Compal Follow Intel DG 1.5 X01(0.2)
CC161, CC163, CC165, CC162, CC168, CC169, CC170, CC171,CC167
C C
9 23 HW 12/25 Compal TLS De-populate RH231, populate RH229 X01(0.2)
10 19 HW 12/25 Compal Deep sleep De-populate RH79,RH91, populate RH101, R802, RH75, R808 X01(0.2)
11 42 HW 12/26 Compal USB charger solution change Change from SLGC55584AVTR to SLG55594AVTR X01(0.2)
12 39 HW 12/26 Compal Due to EA test change 0ohm to 12nH L63~L70 change from 0ohm to 0603CS-120EJTS X01(0.2)
13 39 HW 12/26 Compal Due to CPU +VCCIO_OUT has 6k noise Populate CC66, and change to 1uf X01(0.2)
14 20 HW 12/26 Compal For crystal test CH13,CH14 change to 12pF X01(0.2)
15 39 HW 12/26 Compal For crystal test C470 change to 22pF,C471 change to 27pF X01(0.2)
16 51 HW 12/26 Compal For crystal test C741 change to 33pF,C743 change to 27pF X01(0.2)
B B
17 45 HW 12/27 Compal Debug card port change Jmini3 pin8,10,12,14,16,17,19 change to Jmini4 X01(0.2)
18 42 HW 01/05 Compal Follow Compal common rule C323,C324 change from 150U_D2_6.3VY_R15M to 220U_6.3V_M X01(0.2)
19 44 HW 01/05 Compal Follow Compal common rule C615 change from 150U_D2_6.3VY_R15M to 220U_6.3V_M X01(0.2)
20 34 HW 01/05 Compal Part count reduce(DDC) Remove U21, C365 X01(0.2)
21 30 HW 01/05 Compal For DFX request JLVDS1 Pin8 change to NC X01(0.2)
22 32 HW 01/05 Compal For DFX request JEDP1 Pin8 change to NC X01(0.2)

FDI function test pass, remove reserve
23 6 HW 01/05 Compal Remove RC3,RC87, connect directly X01(0.2)
component
Part reduce, change reserve resistors
24 7 HW 01/05 Compal Remove RC30,RC31,RC33,RC34,RC36,RC37,RC38,RC39, add test point X01(0.2)
to test points
A MXM function test pass, remove reserve Remove R1976, connect directly A
25 17 HW 01/07 Compal X01(0.2)
component R1970 change to short pad
Title
EE P.I.R (1/3)
www.Vinafix.vn
5 4 3 2 1
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Request
D D
26 17 HW 01/07 Compal P5 did not support GC6 Remove R198,R199, add test point X01(0.2)
DDC function test pass, remove reserve
27 34,36 HW 01/07 Compal Remove R1538,R1523,R2162,R2163 X01(0.2)
component
PCH function test pass, remove reserve
28 23 HW 01/07 Compal RH219 change to short pad X01(0.2)
component
HDD function test pass, remove reserve
29 37 HW 01/07 Compal Remove R1635,R1636, connect directly X01(0.2)
component
LAN function test pass, remove reserve
30 39 HW 01/07 Compal Remove R1187,R551,R552, connect directly X01(0.2)
component
KBC function test pass, remove reserve
component
SIO function test pass, remove reserve
32 50 HW 01/07 Compal Remove R866, connect directly X01(0.2)
component
WLAN function test pass, remove reserve
33 44 HW 01/07 Compal Remove R702,R707,R703, connect directly X01(0.2)
component
C Pink Pather function test pass, remove C
reserve component
WWAN function test pass, remove reserve
component
Don’t support O2 smart card, remove pop
36 43 HW 01/07 Compal Remove R220 X01(0.2)
option
C774 change from 2200pf to 0.01uf
37 54 HW 01/07 Compal Change for inrush current X01(0.2)
Add R944 use 20kohm
38 30,41,42 EMI 01/07 Compal For EMI request L10, L39, L51, L41 change from DLW21SN121SQ2L to DLW21HN900SQ2L X01(0.2)
L1, L2, L3 change from BLM18BB470SN1D to BLM15BB470SN1D
39 33 EMI 01/07 Compal For EMI request X01(0.2)
L4, L5 change from BLM18AG121SN1D to BLM15AG121SN1D
Don’t support O2 smart card, remove pop
option
41 28 HW 01/07 DELL Remove 130W protection SW circuitry Remove U60, R2180~R2187 X01(0.2)
B B
42 44 HW 01/07 Compal Follow connector list JSIM1 change from T-SOL_159-1000302600 to T-SOL_159-1000302602 X01(0.2)
Add R2195 reserved for SP_TPM_LPC_EN move from ECEOUT65
43 23,43 HW 01/07 Compal Follow GPIO3.0C X01(0.2)
Net name set to PCH_TPM_EN
44 30,50 ESD 01/07 Compal ESD request Remove D86,D87,C749,C750 X01(0.2)
LAN function test pass, remove reserve
45 40 HW 01/07 Compal Remove C500,C501,C502,C503 X01(0.2)
component
13,14, DDR function test pass, remove reserve
46 HW 01/07 Compal Remove RD12,RD9,RD17,RD18,RD28,RD29,RD35,RD38 X01(0.2)
15,16 component
47 17 HW 01/07 Compal Part count reduce(MXM) De-populate C90,C92,C94,C95,C96 X01(0.2)
48 30 HW 01/07 Compal Part count reduce(LVDS) De-populate C726 X01(0.2)
49 36 HW 01/07 Compal Part count reduce(HDMI) De-populate C437 X01(0.2)

A A
50 43 HW 01/07 Compal Part count reduce(TPM) De-populate C551 X01(0.2)
Title
EE P.I.R (2/3)
www.Vinafix.vn
5 4 3 2 1
5 4 3 2 1

Request
D D
51 17 HW 01/07 Compal Part count reduce(LAN) De-populate C478 X01(0.2)
52 53 HW 01/07 Compal Drop BT feature De-populate R1133,R1134,C748,C753,R904,C756,C758,R694 X01(0.2)
53 30 HW 01/07 Compal Part count reduce(CAMERA) De-populate C300 X01(0.2)
54 45 HW 01/07 Compal Drop Pink Pather function De-populate C626,C636,C634,C624,C637,C638,C633 X01(0.2)
55 46 HW 01/07 Compal For GPIO Map 3.0C Add populate RH218, de-populate RH214 X01(0.2)
56 41 HW 01/07 Compal Add for ESATA repeater 2nd source Add populate R840,R851, add de-populate R852,R853 X01(0.2)
57 37 HW 01/07 Compal Add for HDD repeater 2nd source Add de-populate R83,R84,R85,R90 X01(0.2)
58 30 ESD 01/08 Compal ESD request Remove D13 X01(0.2)

C C
59 33 ESD 01/08 Compal ESD request Remove D10,D11 X01(0.2)
60 30 HW 01/08 Compal For LCDVDD power SW 2nd source Remove C728 and U28 pin4 connect to +3.3V_ALW X01(0.2)
61 35 HW 01/09 Compal Remove reserve circuit of RTD2136S Remove U24,R1987,R1988,R1997,R1998 X01(0.2)
62 51 HW 01/12 Compal BOARD ID change R875 change to 130k X01(0.2)
B B
A A
Title
EE P.I.R (3/3)
www.Vinafix.vn
5 4 3 2 1
5 4 3 2 1

Request
D Unpop PR225, PR224, PR218, PR220, PR217, PR211, PR222, PR223, PC217 D
1 57 PWR 11/29/2012 COMPAL For 1.35V selector X01
PQ205, PR221, PC220, PR216, PR219, PC219, PQ204, PR213, PC216
2 56 PWR 11/29/2012 COMPAL For 3.3V OCP setting Change PR105 to 90.9K X01
3 57 PWR 11/29/2012 COMPAL For 1.5V output voltage setting Change PR402 to 30.1K, PR405 to 20K X01
4 56 PWR 11/29/2012 COMPAL For 3.3V/5V output voltage setting Change PR102 and PR104 to 10K 1% X01
5 58 PWR 11/29/2012 COMPAL Change better Vcore MOSFET Change PQ500, PQ501, PQ502, PQ503, PQ504, PQ505 to CSD87350Q5D X01
6 55 PWR 12/11/2012 COMPAL Main source have x1 code Change PQ1, PQ1070 to SB00000H500 X01
7 55 PWR 12/11/2012 COMPAL Main source have x1 code Change PU1 to SA00003DN00 X01
8 61 PWR 12/11/2012 COMPAL For part count reduction Combine PQ708, PQ709 to SB00000DH0L X01
C C
9 58 PWR 12/11/2012 COMPAL For part count reduction Unpop PC304, change PC305 to SE00000QK00 X01
10 57 PWR 12/11/2012 COMPAL For part count reduction Unpop PC208, change PC207 to SE000008L80 X01
11 55 PWR 12/20/2012 COMPAL Unite to same part number Change PQ1, PQ1070 to SB000007900 X01
12 57 PWR 12/21/2012 COMPAL For cost down Change PL201 to SH000004S00, PL701 to SH00000PO00 X01
13 62 PWR 12/26/2012 COMPAL For Japan's Energy star Add PQ1072, PQ1011, PD1010, PR1030, PD1100, PR1100, PR1031, PR1032 X01
14 62 PWR 12/26/2012 COMPAL For boost charger behavior Add PR1026, PQ1083 X01
15 61 PWR 12/26/2012 COMPAL For current sense accuracy Change PR706=33.2ohm, PR708=6.8ohm, PR713=12.1ohm, PR715=20ohm X01
16 60 PWR 01/03/2013 COMPAL For Vcore compensation Add PR558=5.1Mohm, PR537=619ohm, PR521=93.1Kohm, PC509=820pF X01
B B
17 60 PWR 01/03/2013 COMPAL For EMI request Pop PC516=470pF X01
18 61 PWR 01/07/2013 COMPAL Unite to same part number Change PD703 to SCS0340L010 X01
19 55 PWR 01/07/2013 COMPAL Change to small size bead Change PL3 to SM01000MB00 X01
20 61 PWR 01/08/2013 COMPAL Refer to E5 Change PR737.1 to +3.3V_ALW2 X01
21 56 PWR 01/10/2013 COMPAL To improve 3.3V low side induce voltage Reserve PC199= 56pF_0402_50V X01
A A
Title
PWR P.I.R (1/1)
www.Vinafix.vn
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VAR10 La-9781pp

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A B C D E

MODEL NAME : VAR10

EDP Panel DP(MXM)

LVDS Panel LVDS MUX rPGA CPU

P.35 DDID PS8520C P.37

DP 1.2 LVDS (MXM) DP_D P.6~12 SATA Port 5

W25Q32FVSSIQ USB2 Port 13

P.28 Int. Speaker

Date: Thursday, January 17, 2013 Sheet 2 of 68

Lane 2 10/100/1G LOM

USB3.0 DESTINATION Lane 3 MINI CARD-2 (WLAN)

Port 1 JUSB1 (Ext Right Side) Lane 4 NA

Port 2 JUSB2 (Ext Right Side) Lane 5 MINI CARD-1 (WWAN)

Port 3 Dock Lane 6 MINI CARD-3 (PP)

Port 4 NA Lane 7 EXPRESS CARD

Port 5 IO Board- JUSB2 Lane 8 MMI(Card reader)

Port 6 IO Board- JUSB1

Date: Thursday, January 17, 2013 Sheet 3 of 68

RT8205 3.3V_RUN_GFX_ON TPS22965

RUN_ON Pop option

Date: Thursday, January 17, 2013 Sheet 5 of 68

JCPU1A Haswell rPGA EDS

Date: Thursday, January 17, 2013 Sheet 6 of 68

SM_DRAMPWROK with DDR Power Gating Topology +VCCIO_OUT

Refer CRB 1.0

XDP_DBRESET#_R RC19 2 1 1K_0402_1%

XDP_TMS_R @ RC27 2 1 51_0402_1%

VCCPWRGOOD_0_R XDP_TDI_R @ RC29 2 1 51_0402_1%

SM_RCOMP0 RC42 1 2 100_0402_1% XDP_TCLK_R RC40 2 1 51_0402_1%

SM_RCOMP1 RC55 1 2 75_0402_1% XDP_TRST#_R RC41 2 1 51_0402_1%

CAD Note: SM_RCOMP2 RC49 1 2 100_0402_1%

NC 4 PCH_PLTRST#_BUF 1 2 @ RC54 2 1 0_0402_5% CPU_PLTRST#_R

Date: Thursday, January 17, 2013 Sheet 7 of 68

Date: Thursday, January 17, 2013 Sheet 8 of 68

JCPU1H Haswell rPGA EDS

T28 M27 EDP_CPU_AUX#

Compal Electronics, Inc.

CFG STRAPS for CPU

JCPU1I Haswell rPGA EDS

+VCC_CORE F25 RSVD CFG_19 Display Port Presence Strap

Note: Reserve this circuit CFG7

@ RC72 1: (Default) PEG Train immediately

+VCCIO2PCH_R A23 AF30

AL13 RSVD VCC AF35

CPU_PWR_DEBUG H27 AH25

+1.35V_MEM Y25 VCC N25

Date: Thursday, January 17, 2013 Sheet 11 of 68

JCPU1F Haswell rPGA EDS JCPU1G Haswell rPGA EDS

A10 AK34 B34 K10

All VREF traces should

CPU JDIMM1 Top Side

DDR_A_DQS4 137 138

B DDR_A_D35 143 144 B

DIMM Select DDR_A_D55 177

DDR_A_D57 181 182 DDR_A_D61

187 188 DDR_A_DQS7 4.99K_0402_1% 1

DIMM2 0 0 1 1 203 204

DIMM4 0 1 205 206

Date: Thursday, January 17, 2013 Sheet 13 of 68

All VREF traces should

DDR_A_D32 131 132 DDR_A_D36

DDR_A_DQS4 137 138