1.

Scan insertion flow & pre requisites

2.Pre DFT DRC-Violations
3.Post DFT DRC violations

1.Scan insertion flow & pre requisites:

Copy the Database from home director,

The DIRECTORY Structure & files:

Counter RTL Code -> inputs/counter.v.
Counter Synthesized netlist -> inputs/counter.vs.
Scripts file – Scripts.
Directory to save all reports -> Reports.
To Write out Scan Inserted netlist & SPF -> Outputs.
To save log files -> logs.

Invoke the Tool;

Invoke the DFT Compiler tool in shell mode.
Dc_shell | tee logs/filename.

Set the current design to top module.

Dc_shell > set current design.

Link the design with libraries.

Dc_shell > Link.

Set the Scan architecture type multiplexed Scan.

Dc_shell > set_scan_configuration -style multiplexed_flip_flop.

Convert normal flops to scan flops

Dc_shell > compile -scan.

Define the scan clock, on existing clock port with name “clk”
Dc_shell > set_dft_signal -view existing _dft -type Scan Clock -port clk -
timing [ list 40 60]
Define the reset with active state
Dc_shell > set_dft_signal -view existing _dft -type reset -port reset -
active_state 0

Create & define the Test mode signal

Dc_shell > create_port TestMode -dir IN
Dc_shell > set_dft_signal -view spec -type TestMode -port TestMode -
active_state 1

Create & define Scan Enable signal

Dc_shell > Create_port SCAN_EN -dir IN
Dc_shell > set_dft_signal -view spec -type ScanEnable -port SCAN_EN

Create & define Scan input & output ports

Dc_shell > create_port SCAN_IN -dir IN
Dc_shell > set_dft_signal -view spec -type ScanDataIN -port SCAN_IN

Dc_shell > create_port SCAN_OUT -dir OUT

Dc_shell > set_dft_signal -view spec -type ScanDataOut -port SCAN_OUT

Define Scan Chain

Dc_shell > Set_scan_path chain1 -view spec -scan_data_in SCAN_IN -
scan_data_out SCAN_OUT

Set scan configuration to single chain.

Dc_Shell > set_scan_configuration -chain_count 1

Create Test Protrocol

Dc_shell > create_test_protocol.

Run The DRC.

dft_drc
Here We check the DRC violations.
Once fix the violations are fixed completely, we can proceed to stitch the
scan chains.

Preview the design before stitching

Dc_shell > preview_dft

Stich the scan chain.

Dc_shell > insert_dft

Write out scan inserted netlist in Verilog format.

Dc_shell > write_file -format Verilog -hierarchy -output
outputs/scan_inserted.v

Here we understand the how scan chain stiched.

Write reports (number of scan chains, scan cells).

Dc_shell > report_scan_path -chain all > reports/scan_cell.rpt

Here we understand the scan cell report.

Write the output file in different format & also we by opening this file we
understand the concept.

Dc_shell > write_test_protocol -output outputs/scan_inserted.spf.

Dc_shell > write_test_model -format ddc -output -output

outputs/scan_inserted.ddc .

Dc_shell > write_test_model -format ctl -output

outputs/scan_inserted .ctl.

Exit the Dc shell.

2. PRE DFT DRC-Violations.

After dft_drc we are able to check the drc violations,

Once we enable dft_drc the pre DFT DRC is enabled

Then it is started to check the DRC violations As fallows.

Basic checks.
Basic sequential cell checks.
Checking for scan equivalents.
Checking vector rules.
Checking pre dft rules.

Begin pre_ dft violations we are facing below mentioned violations.

1. All internal clock must be controlled by port level clock signal (primary
input ) in scan test mode.

So clock is controllable with additional circuitry. So by adding a mux in the

circuit we control the clock.
2. Avoid implementation of combination feedback circuit. If present, the
feedback loop be broken to test.

The gate output is not testable for stuck at faults as it is usually held
constant during test.

The feedback signal may not testable in test mode.

Outputs of this circuit cannot be controlled by their inputs alone.

For combinational feedback loop is broken using test mode signal as shown
below.
3. Asynchronous SET/RESET pins of flipflop must be controlled by a level
RESET In scan test mode.

For above mentioned circuit by adding mux we control the reset

 4. Gated Clock must be controlled by scantest Mode.

Gated clocks can block the chain from shifting.

Gated clocks must be enabled in scan test mode.

Above fig shows the Muxed scan flip flop observer is not required if the
HOLD signal is directly issued from a scan flipflop.

5. Negative edge flops should be placed in the start of scan chain.

The below DRC Violations have been observed while executing the lab.

1. Clock Violations D1
2. RSTB Violations D3,

Clock violations,
RSTB Violations D3,