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Loc & Los Sss
Loc & Los Sss
Loc & Los Sss
In this case the launch will be at last shift of operation @ scan enable =1 &
capture operation will be scan enable =0
So, if we want to run at-speed test of a high-speed circuit it will critically case
for lowering shift enable for all flops.
In this type the both launch & capture do when the Scan enable =0.
So, we can test the circuit at high frequency with out touching shift enable.
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