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  • Codigo CP

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    camila mantilla
    22 views9 pages
    The document describes a VHDL design for counting boxes and packages. It contains the entity and architecture for a design module that uses edge detection, box counting, and package counting components. It also simulates the design using a testbench that generates clock and reset signals to test the counting.

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    codigo cp

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    The document describes a VHDL design for counting boxes and packages. It contains the entity and architecture for a design module that uses edge detection, box counting, and package counting components. It also simulates the design using a testbench that generates clock and reset signals to test the counting.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
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    22 views9 pages

    Codigo CP

    Uploaded by

    camila mantilla
    The document describes a VHDL design for counting boxes and packages. It contains the entity and architecture for a design module that uses edge detection, box counting, and package counting components. It also simulates the design using a testbench that generates clock and reset signals to test the counting.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as docx, pdf, or txt
    of 9

    --------------------------------------------------------------------------------

    -- Nombre: CAMILA FERNANDA MANTILLA ARIAS


    -- Documento: 1098662350
    -- Fecha: 29/06/2022
    -- Proyecto: COMPONENTE PRACTICO
    --------------------------------------------------------------------------------

    library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_std.all;
    use IEEE.std_logic_unsigned.all;

    entity design is
    Port (sensor, clk, reset: in STD_LOGIC;
    Contador_caj: out STD_LOGIC_VECTOR (2 downto 0);
    Contador_paq: out STD_LOGIC_VECTOR (3 downto 0)
    );
    end design ;

    architecture Behavioral of design is

    component flanco
    Port ( Q, clok, reset: in STD_LOGIC;
    salida : out STD_LOGIC;
    );
    end component;

    component contcajas
    Port (reset_c, enable_c: in STD_LOGIC;
    Salida_c : out STD_LOGIC_VECTOR (2 downto 0)
    );
    end component;

    component contpaq
    Port ( reset_p, enable_p : in STD_LOGIC;
    Control: out STD_LOGIC;
    Salida_p : out STD_LOGIC_VECTOR (3 downto 0)
    );

    end component;

    signal salida_flanco, s_control: STD_LOGIC;

    begin

    UO: flanco port map (


    Q => sensor,
    clok => clk,
    reset => reset,
    salida=> salida_flanco
    );

    U1: contpaq port map (


    enable_p => salida_flanco,
    reset_p => reset,
    control => s_control,
    salida_p=> Contador_paq
    );
    U2: contcajas port map (
    enable_c => s_control,
    reset_c => reset,
    salida_c=> Contador_caj
    );

    end Behavioral;

    library IEEE;

    use IEEE.STD_LOGIC_1164.ALL;

    entity Simulacion is

    end Simulacion;

    architecture Behavioral of Simulacion is

    component desing

    Port (sensor, clk, reset: in STD_LOGIC;

    Contador_caj: out STD_LOGIC_VECTOR (2 downto 0);

    Contador_paq: out STD_LOGIC_VECTOR (3 downto 0)

    );

    end component;

    signal clk : STD_LOGIC:= '0';


    signal reset: STD_LOGIC:= '0';

    signal sensor: STD_LOGIC:= '0';

    signal Contador_caj: STD_LOGIC_VECTOR (2 downto 0);

    signal Contador_paq: STD_LOGIC_VECTOR (3 downto 0);

    constant PERIODO : time := 10 ns;

    begin

    UO: desing port map (

    sensor => sensor,

    clk => clk,

    reset => reset,

    Contador_paq=> Contador_paq,

    Contador_caj=> Contador_caj

    );

    process begin

    clk <= '0';

    wait for PERIODO/2;

    clk <= '1';

    wait for PERIODO/2;

    end process;

    process begin

    sensor <= '0';

    wait for 50 ns;


    sensor <= '1';

    wait for 50 ns;

    end process;

    process begin

    wait for 20 ns;

    reset <= '1';

    wait for 50 ns;

    reset <= '0';

    wait for 50 ns;

    wait;

    end process;

    end Behavioral;
    --------------------------------------------------------------------------------
    -- Nombre: CAMILA FERNANDA MANTILLA ARIAS
    -- Documento: 1098662350
    -- Fecha: 29/06/2022
    -- Proyecto: COMPONENTE PRACTICO
    --------------------------------------------------------------------------------

    library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_std.all;
    use IEEE.std_logic_unsigned.all;

    entity flanco is
    Port (Q, clok, reset: in STD_LOGIC;
    salida: out STD_LOGIC
    );
    end flanco;

    architecture Behavioral of flanco is

    signal D: STD_LOGIC;

    begin

    process (clok)
    begin
    if clok 'event and clok ='1' then
    if reset = '1' then

    C <= '0';
    else
    C <= Q;
    end if;
    end if;

    end process;
    salida <= Q and not C;

    end Behavioral;

    library IEEE;

    use IEEE.STD_LOGIC_1164.ALL;

    entity Simulacion is

    end Simulacion;

    architecture Behavioral of Simulacion is

    component desing

    Port (sensor, clk, reset: in STD_LOGIC;

    Contador_caj: out STD_LOGIC_VECTOR (2 downto 0);

    Contador_paq: out STD_LOGIC_VECTOR (3 downto 0)

    );

    end component;
    signal clk : STD_LOGIC:= '0';

    signal reset: STD_LOGIC:= '0';

    signal sensor: STD_LOGIC:= '0';

    signal Contador_caj: STD_LOGIC_VECTOR (2 downto 0);

    signal Contador_paq: STD_LOGIC_VECTOR (3 downto 0);

    constant PERIODO : time := 10 ns;

    begin

    UO: desing port map (

    sensor => sensor,

    clk => clk,

    reset => reset,

    Contador_paq=> Contador_paq,

    Contador_caj=> Contador_caj

    );

    process begin

    clk <= '0';

    wait for PERIODO/2;

    clk <= '1';

    wait for PERIODO/2;

    end process;

    process begin

    sensor <= '0';


    wait for 50 ns;

    sensor <= '1';

    wait for 50 ns;

    end process;

    process begin

    wait for 20 ns;

    reset <= '1';

    wait for 50 ns;

    reset <= '0';

    wait for 50 ns;

    wait;

    end process;

    end Behavioral;

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