Digital Electronics Lab Worksheet: The Various Logical Gates Are

DIGITAL ELECTRONICS LAB
WORKSHEET
Student Name – BHAVIKA

Student UID – 21BCS5054
Section/Group – 503- A
Branch – Computer Science and Engineering
Semester – 2nd
Date of Performance – 21/02/2022
AIM OF THE EXPERIMENT
Validate truth table for:

• NAND gates HD74LS00
• NOR gates HD74LS02
• NOT gates HD74LS04
• AND gates HD74LS08
• OR gate HD74LS32
• XOR gates HD74LS86
The various logical gates are:

· AND
· OR
· NOT
· NAND
· NOR
· XOR
WORKSHEET
Requirements
IC for 7400, 7402, 7404, 7408, 7432, 7486, breadboard, connecting
wires, 2 momentary switches, two 10 KΩ resistors, 220 Ω resistor,
LED.
Logic AND Gate

The output state of a digital logic AND gate only returns “LOW”
again when ANY of its inputs are at a logic level “0” (Fig 1). In other
words for a logic AND gate, any LOW input will give a LOW output.
The logic or Boolean expression is given for a digital logic AND gate
is that for Logical Multiplication which is denoted by a single dot or
full stop symbol, (.) giving us the Boolean expression of: . Then we
can define the operation of a digital 2-input logic AND gate as being:
Circuit diagram for AND Gate:

“If both A and B are true, then Q is true”
Figure : Truth table & Symbol for AND gate

WORKSHEET
Simulation Results on Tinkercad For AND Gate
Logic OR Gate
The output, Q of a “Logic OR Gate” only returns “LOW” again when
ALL of its inputs are at a logic level “0” (Fig 2). In other words for a
logic OR gate, any “HIGH” input will give a “HIGH”, logic level “1”
output. The logic or Boolean expression is given for a digital logic OR
gate is that for Logical Addition which is denoted by a plus sign, (+)
giving us the Boolean expression of: A+B=Q. Then we can define the
operation of a 2-input logic OR gate as being:
“If either A or B is true, then Q is true”

WORKSHEET
Figure: Truth table & Symbol for OR gate
Figure: Schematic for Logic OR Gate

WORKSHEET
Simulation Results on Tinkercad For OR Gate
WORKSHEET
Logic NOT Gate

Inverting NOT gates are single-input devices which have an output
level that is normally at logic level “1” and goes “LOW” to a logic
level “0” when its single input is at logic level “1” (Fig 3), in other
words, it “inverts” (complements) its input signal. The output from a
NOT gate only returns “HIGH” again when its input is at logic level
“0” giving us the Boolean expression of: --. Then we can define the
operation of a single input digital logic NOT gate as being:
“If A is NOT true, then Q is true”
Figure: Truth table & Symbol for NOT gate
Figure: Schematic for Logic NOT Gate

WORKSHEET
Simulation Results on Tinkercad For NOT Gate
Logic NAND Gate

The NAND (Not – AND) gate has an output that is normally at logic
level “1” and only goes “LOW” to logic level “0” when ALL of its inputs
are at logic level “1” (Fig 4). The Logic NAND Gate is the reverse or
“Complementary” form of the AND gate. The logic or Boolean
expression given for a logic NAND gate is that for Logical Addition,
which is the opposite to the AND gate, and which it performs on the
complements of the inputs. The Boolean expression for a logic NAND
gate is denoted by a single dot or full stop symbol, (.) with a line or
Overline, (‾‾) over the expression to signify the NOT or logical
WORKSHEET
negation of the NAND gate giving us the Boolean expression of: -----
----. Then we can define the operation of a 2-input digital logic NAND
gate as being:
“If either A or B are NOT true, then Q is true”
Figure: Truth table & Symbol for NAND gate
Figure: Schematic for Logic NAND Gate

WORKSHEET
Simulation Results on Tinkercad For NAND Gate
Logic NOR Gate

The inclusive NOR (Not-OR) gate has an output that is normally at
logic level “1” and only goes “LOW” to a logic level “0” when ANY of
its inputs are at logic level “1” (Fig 5). The Logic NOR Gate is the
reverse or “Complementary” form of the inclusive OR gate. The logic
or Boolean expression is given for a logic NOR gate is that for Logical
Multiplication which it performs on the complements of the inputs.
The Boolean expression for a logic NOR gate is denoted by a plus
sign, (+) with a line or Overline, (‾‾) over the expression to signify the
NOT or logical negation of the NOR gate giving us the Boolean
expression of: Then we can define the operation of a 2-input digital
logic NOR gate as being:
WORKSHEET
“If both A and B are NOT true, then Q is true”
Figure: Truth table & Symbol for NOR gate
Figure: Schematic for Logic NOR Gate
Simulation Results on Tinkercad For NOR Gate

WORKSHEET
Exclusive-OR Gate
The output of an Exclusive-OR gate ONLY goes “HIGH” when its two
input terminals are at “DIFFERENT” logic levels with respect to each
other (Fig 6). An odd number of logics “1’s” on its inputs gives a logic
“1” at the output. These two inputs can be at logic level “1” or at
logic level “0” giving us the Boolean expression of :
Figure: Truth table for XOR gate
Figure: Schematic for Logic XOR Gate

WORKSHEET
Simulation Result on Tinkercad For XOR Gate
Result
The truth tables of logic gates NAND, NOR, AND, NOT, OR, XOR was
verified on circuits over a breadboard.
Learning / Observation
We learn how to make a circuit using various Logic Gate.
Troubleshooting
A problem that occurred during the experiment is that on high
voltage IC was busted, I added a resistor, which prevents IC from
blasting.
EXPERIMENT NUMBER-2
NAME- BHAVIKA BRANCH- BE(CSE)

UID- 21BCS5054 CLASS ANDSECTION- 503A
DATE OF PERFORMANCE- 03/03/2022 SUBJECT NAME- DIGITAL ELECTRONICS
1. Design a Burglar alarm using AND gate such that the alarm should turn on
whenever the light falling on the LDR is disrupted.
2. Design a voting system such that a valid vote will be considered when a person
sitting at a desk press both the buttons. IN case only one button is pressed
during the casting of the vote will be considered invalid.
Also, a valid casted vote will be represented by green light and an invalid
casted vote will be represented by a red light.
3. Design an automatic heater controller using NOT gate such that at a
temperature below 10oC the heater should turn ON (the heater can be
represented by using an LED).
APPARATUS REQUIRED:
1. Photoresistor, slide switch, 7408, Two Resistor =10K ohm, One Resistor =
330 ohm, Piezo, Power supply= 5 Voltage 5 Ampere, LED
2. Slide switch, 7432, Two Resistor =10K ohm, One Resistor = 220 ohm,
Piezo, Power supply= 5 Voltage 5 Ampere, LED
Problem statement
1. An AND gate gives an output of logic 1 when input A AND input B are at
logic 1, i.e., when the alarm switch is ON and the LDR sensor detects a
light (flashlight that burglar uses), only then the Alarm will ring,
otherwise, it will not ring in any of the other cases.
AND gates are available in IC packages. The 7408 IC is a well-known QUAD 2-

Input AND gates IC and contains four independent gates each of which performs
the logic AND function.
In order to design the burglar alarm, the alarm switch which is a SPST (toggle)
switch and the person detection is achieved by the light falling on the sensor (
because of the light source used by the burglar) made from LDR, is used. The
schematic of the circuit is shown as below.
Simulation can be made to check the schematic as given during the
demonstration of the online lab session.
Simulation when light is not falling over the LDR.

Simulation when light is falling over the LDR.
PROBLEM STATEMENT
1. The Logic OR Gate is a type of digital logic circuit whose output goes HIGH
to a logic level 1 only when one or more of its inputs are HIGH. It is
required that the doorbell should ring when someone presses either the
front door switch or the back door switch.
7432 IC Pinout.
OR gates are available in IC packages. The 7432 IC is a well-known QUAD 2-
Input OR gates IC and contains four independent gates each of which performs
the logic OR function.
In order to implement the doorbell ringer, the SPST (toggle) switches are used
as inputs to the OR gate, the output of the OR gate is attached to a Buzzer
which will ring when any one of the switches is pressed.
Figure: Schematic of doorbell ringer.
Simulation when both the doorbell switches are closed.

Simulation when one of the door bell switches is pressed.
Problem Statement
The Logic NOT Gate is the most basic of all the logic gates and is often referred to as an Inverting
Buffer or simply an Inverter. It is required to control the central heating to turn on/off according
to the temperature threshold. The temperature is sensed by the LM-35 temperature sensor
having a linear relation of the output voltage to the temperature by 10mV/oC. The decision of
this temperature is above or below a threshold temperature is taken by OP Amp working as a
comparator. Since the relation is linear we know this that at 30 oC the output of LM-35 must be
300mV so we will make Vref of Op-Amp as 300mV.
If the temperature at –ve terminal or Op-AMP is above 30 oC then voltage output of LM-35 will be
greater than 300mV and output will be 0V which will act as logic LOW at the input of NOT gate
and in return, it will give logic HIGH at output turning the fan ON.
Whereas, if the temperature at –ve terminal or Op-AMP is below 30 oC then voltage output of LM-
35 will be less than 300mV and output will be 5V which will act as a logic HIGH at the input of
NOT gate and in return, it will give logic LOW at output turning the fan OFF.
Figure: 7404 IC Pinout
Each 7404 NOT gate IC has 6 NOT gates arranged as shown in Fig 12. 14th pin is the VCC (+5V) and
the 7th pin is the GND (Ground). In order to implement the experiment, the temp sensor input
needs to be given to the input terminal of any one of the NOT gate inside this IC, and the output
actuator can be driven from the output terminal of the same gate.
Schematic of a NOT gate circuit.

Simulation can be made to check the schematic as given during the demonstration of the online
lab session
Simulation when the temperature is 29oC
Simulation when the temperature is 31C

Result
The integrated circuits and their connections on the breadboard were studied
and implemented. The practical applications of logic gates (AND & OR) were
studied and implemented.
LEARNING OUTCOMES
• Remember the concepts related to fundamentals of C language, draw flowcharts

and write algorithm/pseudocode.
• Understand the way of execution and debugging programs in C language.
• Apply various constructs, loops, functions to solve a mathematical and scientific

problem.
• Analyze the dynamic behavior of memory by the use of pointers.
• Design and develop modular programs for real-world problems using control
structure and selection structure.
EVALUATION COLUMN (To be filled by concerned faculty only)
Sr. No. Parameters Maximum Marks

Marks Obtained
1. Worksheet Completion including 10
writing learning objective/ Outcome
2. Post-Lab Quiz Result 5
3. Student engagement in Simulation/ 5

Performance/ Pre-Lab Questions
4. Total Marks 20
DIGITAL
ELECTRONICS LAB
WORKSHEET
BHAVIKA
21BCS5054
EXPERIMENT NUMBER-3
Student Name: BHAVIKA Branch: BE-CSE

UID: 21BCS5054 Section/Group: 503A
Date of Performance: 19-03-2022 Subject Name: Digital Electronics

(a) Design a two-way switch for room light (XOR).
b) Design a multiplayer game trigger mechanism (NOR).
The task to be done.

1. We connect the power supply with the breadboard with the help of
wires.
2. We use various gates and provide the desired inputs in order to receivethe
output.
3. We then verify the truth table for each input/ output combination.
4. We gently start the stimulation. And stop the stimulation when the
required output is obtained.
Requirements.
➢ Hardware components.
• 5,5 power supply.
• Breadboard.
• Slide Switches.
• LED (Light emitting diode).
DIGITAL
ELECTRONICS LAB
WORKSHEET
BHAVIKA
21BCS5054
• Resistors.
• XOR Gate IC7486
• NOR Gate IC7402
➢ Software component.
• Tinker cad web application.
(a) Two-way switch for room light using XOR gate
The Exclusive-OR logic function is a very useful circuit that can be used in many
different types of computational circuits. There are two other types of digital logic
gates which although they are not a basic gate in their own right as they are
constructed by combining together other logic gates, their output Boolean function
is important enough to be considered as complete logic gates. These two “hybrid”
logic gates are called the Exclusive-OR (Ex-OR) Gate and its complement the
Exclusive-NOR (Ex-NOR) Gate. The output of an Exclusive-OR gate ONLY goes “HIGH”
when its two input terminals are at “DIFFERENT” logic levels with respect to each
other. An odd number of logic “1’s” on its inputs gives a logic “1” at the output.
Circuit diagram :
DIGITAL
ELECTRONICS LAB
WORKSHEET
BHAVIKA
21BCS5054
SIMULATION RESULT
When both the switches are on OFF (0) state, the LEDis OFF
(0).
DIGITAL
ELECTRONICS LAB
WORKSHEET
BHAVIKA
21BCS5054
When one of the switches is on the “ON” state and theother is

on the “OFF” state, the LED will be glowing (1).
When both the switches are on the “ON” state; the LED willnot
glow (0).
DIGITAL
ELECTRONICS LAB
WORKSHEET
BHAVIKA
21BCS5054
(b) Multiplayer game trigger using NOR gate
In order to implement the multiplayer game trigger mechanism, it required to

initiate the game when the detection of both the players competing in the game
as present at the designated completing stations. The circuit for the same is
given below.
Circuit Diagram :
SIMULATION RESULT
DIGITAL
ELECTRONICS LAB
WORKSHEET
BHAVIKA
21BCS5054
When both the switches are on OFF (0) state, the LED is ON(1).
When one of the switches is on the “ON” state and theother is

on the “OFF” state, the LED is OFF(0).
DIGITAL
ELECTRONICS LAB
WORKSHEET
BHAVIKA
21BCS5054
When both the switches are on the “ON” state; the LED willnot
glow (0).
Concept used.
The basic concept of logic gates for forming the truth table. We
now use the knowledge of K- mapping in order to check
variouslogic gates and their validation.
RESULT:
The practical applications of logic gates (NAND, NOR & XOR) were
studied and implemented.
Troubleshooting.
1. Be very careful while joining the connections.
DIGITAL
ELECTRONICS LAB
WORKSHEET
BHAVIKA
21BCS5054
Learning/ observation.
After performing the experiment, we learned that
1. The application of NOR Gate and XOR Gate.
2. By performing the experiment, we verify the truth table of

NOR and XOR Gate.
WORKSHEET
EXPERIMENT NUMBER: - 4
Student Name: BHAVIKA UID: 21BCS5054

Date of Performance: 19-03-22 Branch: BE(CSE)
Section/Group: 503A
Subject Name Digital Electronics
Design and realize a given function using K-maps and verify its performance.
The task to be done.

wires.
2. We use various gates and provide the desired inputs in order to receivethe
output.
Requirements.
➢ Hardware components.
• 5,5 power supply.
• Breadboard.
• Slide Switches.
• LED (Light-emitting diode).
• Resistors.
• XOR Gate IC7486
➢ Software component.
• Tinker cad web application.
WORKSHEET
Circuit diagram/ Block diagram.
Simulation Results:
When both the switches are on OFF (0) state, the LED is OFF
(0).
WORKSHEET
When one of the switches is on “ON” state and theother is on

the “OFF” state, the LED will be glowing (1).
When both the switches are on the “ON” state; the LED will not
glow (0).
WORKSHEET
Concept used
The basic concept of logic gates for forming the truth table. We
now use the knowledge of K- mapping in order to check
variouslogic gates and their validation.
Learning/ observation
By performing this worksheet, we learnt about:
1. The application of AND, OR, NOT gate in order to form
XOR gate.
2. Designing a given function with the basic knowledge of K-
map and verifying it.
Troubleshooting
Be very careful while joining the connections.
EXPERIMENT-2.1
Student Name: BHAVIKA Branch: BE(CSE)
UID: 21BCS5054 Section/Group:503A
Aim of the experiment

To design and verify operation of half adder and full adder.
THE TASK TO BE DONE

wires.
2. We use various gates and provide the desired inputs in order to receive the
output.
REQUIREMENTS
Breadboard, connecting wires, power supply, LED, Resistor, IC 7408, IC 7486, IC 7432,
and IC Trainer Kit and tinkercad.
Circuit diagram/ Block diagram
TO REALIZE HALF ADDER

EXPERIMENT-2.1
TO REALIZE FULL ADDER

EXPERIMENT-2.1
Simulation Results:
EXPERIMENT-2.1
Concept used
Half-Adder: A combinational logic circuit that performs the addition of two data bits, A and
B, is called a half-adder. The addition will result in two output bits; one of which is the sum
bit, S, and the other is the carry bit, C. The Boolean functions describing the half-adder are:
S =A XOR B C=AB
Full-Adder: The half-adder does not take the carry bit from its previous stage into account.
This carry bit from its previous stage is called a carry-in bit. A combinational logic circuit that
adds two data bits, A and B, and a carry-in bit, Cin, is called a full-adder. The Boolean
functions describing the full-adder are:
S = (x xor y) xor Cin C = xy + Cin (x xor y)

EXPERIMENT-2.1
LEARNING OUTCOMES
1) I have learned about full adder and half adder.
2) I have learned the application of AND, XOR and OR gate.
3) I have learned the truth table of half adder and full adder.
Troubleshooting
1. In connecting AND, OR, and XOR gate.
2. Be careful while joining connections.
EXPERIMENT-2.2
Student Name: BHAVIKA Branch: CSE

Design a data acquisition system using a multiplexer.
THE TASK TO BE DONE

➢ IC identification and circuit diagram
➢ Hardware connections on breadboard
REQUIREMENTS
IC74153, Resistances (470 ohms,1K ohms,1.5 k ohms,2.2 k
ohms), 5V Power Supply, Breadboard, Connecting wires.
CIRCUIT DIAGRAM/BLOCK DIAGRAM
Schematic Diagram
EXPERIMENT-2.2
SIMULATION RESULT: -
EXPERIMENT-2.2
EXPERIMENT-2.2
CONCEPT USED
We assemble the circuit over a breadboard and check if they are working. To do
that we have used two pushbuttons are inputs for the control pins A and B. And,
used a series of potential divider combinations to provide variable voltages for
pins 12, 14, 15, and 11. The output pin 13 is connected to an LED. The variable
voltages supplied to the LED will make it to vary the brightness based on the
control signals. The circuit once built will look something like this below:-
EXPERIMENT-2.2
Inputs Output
S A1 A2 Out
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
SIMULATION RESULT:
We choose to execute the simulation of the circuits so as to understand and study
the various effects of the circuits. Over the course of the many simulations that
led to the final ones presented here, we understood that OrCAD Capture is a
highly resource-intensive simulation package. Once we gained enough
confidence over our circuit model and general proficiency in logic gates
implementation by using Josephson Junctions, we moved further to simulate the
Multiplexer formed by the logic circuits made earlier. The run configuration we
designed allowed us to use the multiple Josephson Junctions available in our
design.
LEARNING OUTCOMES
• I am able to identify the different types of digital circuits and
their difference and to illustrate the various types of gates.
• I am able to understand the various elements of the digital
system and implement their applications.
• I am able to illustrate the relation between Combinational &
Sequential Circuits and apply them for practical applications.
• I am able to solve the basic problems related to different types
of digital circuits and calculate them using various numerical
problems.
EXPERIMENT-2.2
• I am able to create different hardware and software-based digital
applications.
TROUBLESHOOTING
CONNECTIONS SHOULD BE CONNECTED PROPERLY AND
CAREFULLY.
EXPERIMENT-2.3
Student Name: BHAVIKA Branch: BE(CSE)

UID: 21BCS5054 Section/Group: ON21BCS503A
Date of Performance:07-04-2022 Subject Name: Digital Electronics
Aim
Design a home appliance control system with a 3-to-8 decoder.

The task to be done:
➢ Hardware connections on the breadboard
Requirements:
74LS138 IC, 10K ohms resistances, LED’s, +5v Power Supply, Bread
Board, Connecting Wires.
Circuit diagram/ Block diagram:
EXPERIMENT-2.3
Simulation Results:
When both the switches are on then led -1 will glow.
When the first switch is on and the second switch is off then led-2 will
glow.
EXPERIMENT-2.3
When the first switch is off and the second one is on then led-3 will glow.
When both the switches are off then led-4 will glow
EXPERIMENT-2.3
Concept used:
74LS138 is a member of ‘the 74xx’family of TTL logic gates. The chip is
designed for decoding or de-multiplexing applications and comes with 3 inputs
to 8 output setups. The design is also made for the chip to be used in high-
performance memory-decoding or data-routing applications, requiring very short
propagation delay times. In high-performance memory systems, these decoders
can be used to minimize the effects of system decoding. The three enable pins of
the chip (in which Two active-low and one active-high) reduce the need for
external gates or inverters when expanding.
Figure: 74LS138 Decoder Pinout
Overview of 74LS138 Decoder:
As mentioned earlier the chip is specifically designed to be used in high-

performance memory-decoding or data-routing applications which require very
short propagation delay times. The memory unit data exchange rate determines
the performance of any application and the delays of any kind are not tolerable
there. In such applications using 74LS138 line decoder is ideal because the delay
times of this device are less than the typical access time of the memory. This
means that the effective system delay introduced by the decoder is negligible to
affect the performance.
How to use 74LS138 Decoder?
For understanding the working of device let us construct a simple application

circuit with a few external components as shown below.
EXPERIMENT-2.3
Figure: Home Appliance system design using Decoder
About circuit:
Here the outputs are connected to LED to show which output pin goes LOW and
do remember the outputs of the device are inverted. We are using a single device
so we will connect G2A and G2B pin to the ground followed by connecting G1
to VCC to enable the chip. The three buttons here represent three input lines for
the device.
For understanding the working let us consider the truth table of the device.
EXPERIMENT-2.3
Figure: Truth Table of Decoder
H = HIGH, L = LOW and X = Don’t Care
Learning/ observation:
1. I am able to learn about Decoder and they will be able to extract relevant
information from the Decoder Datasheet.
2. I am able to learn how Decoder works and how changing the Inputs of different
appliances can be made to turn on and off.
Result
The home appliance control system has been Designed and Implemented using 3 to 8
Decoder.
Troubleshooting:
No errors were encountered during performing the stimulation.
EXPERIMENT NUMBER-3.1
Student Name: BHAVIKA UID:21BCS5054

Date of Performance: 21-04-2022 Branch: BE(CSE)
Section/Group:503A Subject Name: Digital Electronics

Design a Shift Register Circuit using IC 74HC595.
The task to be done

➢ Tinker CAD Simulation
Requirements
• 74HC595
• LEDs
• 220Ω resistors
• Arduino Uno R3
• Tinkercad Simulator.

Shift Register Circuit:
Figure: Shift Register Circuit Design with Pushbuttons.

Simulation Results:
Concept used
In Serial in Parallel Out (SIPO) shift registers, the data is stored into the
register serially while it is retrieved from it in parallel-fashion. Figure 1
shows an n-bit synchronous SIPO shift register sensitive to positive edge
of the clock pulse.
Here the data word which is to be stored (Data in) is fed serially at the
input of the first flip-flop (D1 of FF1). It is also seen that the inputs of all
other flip-flops (except the first flip-flop FF1) are driven by the outputs of
the preceding ones like the input of FF2 is driven by the output of FF1. In
this kind of shift register, the data stored within the register is obtained as
a parallel-output data word (Data out) at the individual output pins of the
flip-flops (Q1 to Qn).
In general, the register contents are cleared by applying high on the clear
pins of all the flip-flops at the initial stage. After this, the first bit, B1 of the
input data word is fed at the D1 pin of FF1.This bit (B1) will enter into FF1,
get stored and thereby appears at its output Q1 on the appearance of first
leading edge of the clock. Further at the second clock pulse, the bit B1
right-shifts and gets stored into FF2 while appearing at its output pin Q2
while a new bit, B2 enters into FF1. Similarly, at each clock pulse the data
within the register moves towards right by a single bit while a new bit of
the input word enters into the register.
Meanwhile one can extract the bits stored within the register in parallel-
fashion at the individual flip-flop outputs.
Analysing on the same grounds, one can note that the n-bit input data word
is obtained as an n-bit output data word from the shift register at the rising
edge of the nth clock pulse. This working of the shift-register can be
summarized as in Table I and the corresponding waveforms are given by
figure 2.
DE LAB WORKSHEET
In the right-shift SIPO shift register, data bits shift from left to right for
each clock pulse. However, if the data bits are made to shift from right to
left in the same design, one gets a left-shift SIPO shift register as shown
in figure 3.
Nevertheless, the basic working principle remains the same except for
the fact that now Bn down to B1 is stored in Qn down to Q1 i.e., Q1 =
B1, Q2 = B2 … Qn = Bn at the nth clock pulse.
1. At the end of this experiment, I am able to learn about shift
registers and they will be able to extract relevant information
from the shift register Datasheet.
2. I am able to learn how the shift register works manually by
using Pushbutton.
Troubleshooting
Fault detection. Observe the circuit/system operation and compare
it with the expected correct operation.
Fault isolation. Perform tests and make measurements to isolate
the fault.
DE LAB WORKSHEET
Fault correction. Replace the faulty component, repair the faulty
connection, remove the short, and so on.
Date of Performance:29-04-2022 Subject Name: Digital Electronics

Design a light-based object counter with a 7-segment display (CD4026).
The task to be done

Requirements
LDR, CD4026 IC, 7-segment display, 5V Power Supply, Breadboard,
Connecting wires, Windows 10 PC

Simulation Results:
Concept used
Object counters or product counters are important applications used in industries,

shopping malls, etc. They count objects or products automatically and so reduce
human efforts. They are used at different places for different purposes and
different usages. They can be used as visitor counter, vehicle counter
material/product counter etc. Following are some of the examples where object
counters are used.
• In LIFT to count and display number of persons inside the lift at a particular
given time
• In any big super market or shopping malls as a visitor counter, to keep track
of the number of visitors who have visited the Mall.
• On the conveyor belt in the industry to count number of objects passed
• In vehicle parking place to count and display number of vehicles inside the
parking lot
Thus the application areas are varied where object counters are used. The object
counter is made up of sensor, counter and display. Sensor senses any object that
passes in front of it and gives output pulse to the counter. Counter increments
count by one when it gets pulse input from sensor. Current count is displayed on
any type of display like the 7-segment or LCD display.
The light source from the torch is continually hit on the LDR if so the resistance
of LDR is too low and the voltage drop across LDR and ground is less than 0.6V.
When an object is passed
between the light beams, light will not hit on the LDR so the resistance of LDR
becomes high. We have V=I x R (Voltage = Current x Resistance) i.e., the
resistance of LDR is the high voltage across LDR become high. As soon as the
object crosses the light beam a LOW and HIGH voltage transition occurs, which
is given to the Clock (input) of CD4026 IC, it will start to count with the clock
and display the count on 7- segment display.
Result
The working object counter using LDR, CD4026 and 7-segment was verified on
simulation software, and implemented on breadboard.
1. I have learned about 7-segement display.
2. I have learned about how 7-segement display work.
3. I have learned about how to connect devices on tinkercad.
Troubleshooting
BE CAREFUL WHILE CONNECTING APPLIANCES.
UID: 21BCS5054 Section/Group:503A
Date of Performance:05-05-22 Subject Name: Digital electronics

Design traffic lights using D Flip Flop.
THE TASK TO BE DONE

REQUIREMENTS
555 timer IC (NE555), D flip flop IC (7474), 5V Power Supply,
Breadboard, Connecting wires, Tinker cad simulator.
CIRCUIT DIAGRAM
Schematic Representation:
SIMULATION RESULT:
CONCEPT USED
Basically, D flops follow the input when the clock is enabled i.e. it
takes enable as a positive edge trigger and remains in the previous
state when the clock is disabled.
Initially
Input at flip flop 1 is 0.
Input at flip flop 2 is 0.
So, if you code Q of a first flip flop as Yellow led, Q' of a second flip
flop as the red led and Green led is coded to the combination Q' of first
and Q of the second. At the first positive edge trigger, you give input
as 0 to flip flop 1 so the output is also 0 and the output at Q' which is 1
will act as a positive edge trigger at flip flop 2 which will again give
input as 0 to Q of flip flop 2 so the output is also 0 and the output at
Q' of flip flop 2 which is 1 will turn ON the red led connected to it.
After the first positive edge:
Input at flip flop 1 is 1 (equal to Q' of flip flop 1)
Input at flip flop 2 is 1
At the second positive edge:
At flip flop 1 the input 1 is given to output Q which is connected to

yellow LED and Q' turns 0 giving the clock at flip flop 2 a 0, turning
the red led OFF.
After second positive edge
Input at flip flop 1 is 0 (equal to Q' of flip flop 1)
Input at flip flop 2 is 1
At the third positive edge at flip flop 1 the input which is 0 is given to
the output which is also made 0 and the output at Q' which is 1 will act
as a positive edge trigger at flip flop 2 which will again give input as 1
to Q of flip flop 2. Now Q of flip flop 2 and Q' of flip flop 1 which are
both at 1 will give 1 to the yellow LED turning it on.
And the loop will continue.
Now once led glows make sure that the next positive edge trigger will
come after the required time in other words change the frequency of
clock pulse according to your requirement (you can use 555 timer to
generate required clock pulse) so that LED will stays glowing and after
that particular time give 1 as Input at positive edge of the clock the
other LED glows and maintain the same clock frequency.
RESULT:
The practical applications of D flip flop in designing traffic
lights are studied and implemented.
LEARNING OUTCOMES
• I can identify the different types of digital circuits and their

difference and illustrate the various gate types.
• I can understand the various elements of a digital system and
implement their applications.
• I can illustrate the relationship between Combinational &
Sequential Circuits and apply them for practical applications.
• I am able to solve the basic problems related to different types of
digital circuits and calculate them using various numerical
problems.
• I am able to create different hardware and software-based digital
applications.
TROUBLESHOOTING
Be careful while making connections.
DATE: 120
PAGE NO.
signment
UNI-1-
Name -Bhavika
UID-2BCS5054
Uass od Sechon - 503
C3=Design a duLwt whose oulpud it Lhoa

evey even inbuc a
eNegu 3-brt numbe.
z F
O
O
F z
Z
BHAVIKA DATE 2
31 Bcs 5o54 PAGE NO
-9. who is meant byAtandasud SoP um3

i n standAl
CenveseE he ellousing untion
SOP and Pos Gum
FCA,B,.CD)=A+BDAC
Fe SoP Feam
F=A BeD+AC
FEA B+B) (A+A)8.+ A(B-+C
= (AB+AE)+A8-C DA BC tABC
ART
=AB+A B) CC+T)+A 8.CD+ABLD+

CABT + ABT)(DTD)-
LABC+ ABC+ABC+ 8T)+ ABLD+AB
tAB? t ABTD+ ABCD +ABTD
=(A
B AB A BT FAB) (p+D) ABO
tABCD tABTDABTD+ABD
HBDABTD+ ABtD +A5p 8LA
ABCD+A8(i ABLS+ABLD +ABTD
ABD ABD tABZD
+ABTD+ AeTD BCT A6LD1

ABTD ABD ABCD A8TD
DATE: 20
PAGE NO.
Fo PoS Oum
F =A BC A
F A BcD A
A LB4T +D)(A+T)
A (Bt4D)(
= (A B+AT+AD) CA+)
AAB t AATA ARC ACCACD
AA =0 cEO
0 8 +0 OD - ABC+ AD +A:CD
X 0 =O O.XF0
F=ABC+ ACD
F= ABC+ACD
F AB) (AC D)
ArBT) ( +T+D)
= (A +B+T) (At+D)
Sondastd CoP lem mea taydasA um
IHOdutr Fesurn9o his LOm Pach pacduE
team need notlontan Cul tOals
Name-BhawiRa
OID-91 BLSSo54
ABC+ABCABC
-3 SimpB ly A'BLt LIblha
Boolean algebua
SolAB + ABC+
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LCCA B-+ABY)+ CCA'B+ A8
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DATE: 20
PAGE NO.
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DATE 20
PAGE NO
2/22
ASS nNMENT
UNIT-2
Name-BhauiRa
UID- 2Bcsso54
laas ond Sechon- 503A
Subiect Daitol 2ect.onits
Conat suc o 5x 32 deLodes uaing 2x
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DIGITAL ELECTRONICS LAB

Student Name – BHAVIKA

Date of Performance – 21/02/2022

AIM OF THE EXPERIMENT

Validate truth table for:

The various logical gates are:

Logic AND Gate

Circuit diagram for AND Gate:

Figure : Truth table & Symbol for AND gate

“If either A or B is true, then Q is true”

Figure: Truth table & Symbol for OR gate

Figure: Schematic for Logic OR Gate

Logic NOT Gate

Figure: Truth table & Symbol for NOT gate

Figure: Schematic for Logic NOT Gate

Simulation Results on Tinkercad For NOT Gate

Logic NAND Gate

Figure: Truth table & Symbol for NAND gate

Figure: Schematic for Logic NAND Gate

Logic NOR Gate

Figure: Truth table & Symbol for NOR gate

Figure: Schematic for Logic NOR Gate

Simulation Results on Tinkercad For NOR Gate

Figure: Truth table for XOR gate

Figure: Schematic for Logic XOR Gate

Simulation Result on Tinkercad For XOR Gate

NAME- BHAVIKA BRANCH- BE(CSE)

AIM OF THE EXPERIMENT

AND gates are available in IC packages. The 7408 IC is a well-known QUAD 2-

Simulation when light is not falling over the LDR.

Figure: Schematic of doorbell ringer.

Simulation when both the doorbell switches are closed.

Schematic of a NOT gate circuit.

Simulation when the temperature is 29oC

Simulation when the temperature is 31C

• Remember the concepts related to fundamentals of C language, draw flowcharts

• Understand the way of execution and debugging programs in C language.

• Apply various constructs, loops, functions to solve a mathematical and scientific

• Analyze the dynamic behavior of memory by the use of pointers.

EVALUATION COLUMN (To be filled by concerned faculty only)

Sr. No. Parameters Maximum Marks

3. Student engagement in Simulation/ 5

Student Name: BHAVIKA Branch: BE-CSE

AIM OF THE EXPERIMENT

b) Design a multiplayer game trigger mechanism (NOR).

The task to be done.

(a) Two-way switch for room light using XOR gate

When one of the switches is on the “ON” state and theother is

(b) Multiplayer game trigger using NOR gate

In order to implement the multiplayer game trigger mechanism, it required to

When one of the switches is on the “ON” state and theother is

After performing the experiment, we learned that

1. The application of NOR Gate and XOR Gate.

2. By performing the experiment, we verify the truth table of

Student Name: BHAVIKA UID: 21BCS5054

AIM OF THE EXPERIMENT

The task to be done.