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Multiple Choice: A. To make a transition from a low B. Rise times

level to a high level C. Fall times
1. The purpose of the fetch cycle in a B. To make a transition from a high D. B and C above
computer is to:
level to a low level
C. For the output signal to start 12. A logic gate is an electronic circuit
A. Obtain input data
making a transition to a high level which
B. Obtain memory data
C. Obtain an instruction from the time an input signal
A. makes logic decision
D. Implement a specific operation causes the transition to occur B. allows electron flow only in one
D. Between midpoints of a square direction
2. A three-state buffer is a device that: wave signal C. works on binary data
D. alternates between 0 and 1 values
A. Has three different output lines 7. The purpose of the logic analyzer is
B. Has three different logic levels to: 13. The logic gate which produces a 0 or
C. Has a high impedance state in
low-level output when one or both of
addition to normal 0 and 1 levels A. Verify the logic operation of the the inputs are 1 is called ______ gate.
D. Is a special type of storage
gates in a system
register
B. Sample and display system A. AND C. OR
signals B. NOR D. NAND
3. A sequential logic system has outputs
that depend on: C. Analyze the functional logic
14. The hold time for a D-type flip-flop
operations of a system is the time the:
A. Only the inputs to the system at D. None of these
the current time
A. Data will be held on the output
B. Present as well as past inputs 8. If a NAND latch has a 1 on the SET after a clock signal
C. Memory device outputs input and 0 on the CLEAR input,
independent of system inputs B. Data must be held on the input
then the SET input goes to 0, the
D. None of these after a clock edge
latch will be:
C. Clock must be high
4. A static memory will store A. HIGH D. Clock must be low
information: B. LOW
C. Invalid 15. A NOR gate is ON only when all its
A. Even when power is not applied D. None of these inputs are
to the memory
B. As long as power is applied to the 9. The fan-in of a logic gate refers to A. ON C. Positive
memory the number of B. High D. OFF
C. As long as power is applied and
the memory is refreshed A. input devices that can be 16. The first person who used Boolean
periodically connected algebra for the design of relay
D. None of these B. input terminals switching circuits was
C. output terminals
5. Clock periods are measured from: D. circuits output can drive A. Aristotle
B. Boole
A. Similar points on the clock 10. In digital circuits Schottky transistors C. Shannon
waveform are preferred over normal transistor D. Ramanujam
B. From the low level to the high because of their
level 17. An XOR gate produces an output
C. From the high level to the low A. lower propagation delay only when its two inputs as
level B. higher propagation delay
D. From the time the clock pulse is C. lower power dissipation A. high C. low
at 50% of its low-to-high D. higher power dissipation B. different D. same
transition until it is at 50% of its
high-to-low transition 11. A dual threshold display in a logic 18. While obtaining minimal sum of
analyzer provides information about: product expression,
6. The rise time of a signal is the time:
A. Glitch occurrences A. all don’t cares are ignore

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 EXCEL FIRST REVIEW AND TRAINING CENTER, INC.
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B. all don’t cares are treated as logic 25. The digital equivalent of an electric A. The function of main system
1s series circuit is the _____ gate. memory
C. all don’t cares are treated as logic B. Involves transfer of data only
0s A. NOR C. NAND from memory to processor or
D. only such don’t cares that aid B. OR D. AND back
minimization are treated as logic C. Provides only arithmetic or logic
1s 26. A half-adder can be constructed from operations
D. Is the central control element of
19. Boolean algebra is essential based on A. two XNOR gates only the system
B. one XOR and one OR gate with
A. symbols C. logic their outputs connected in parallel 32. A dynamic memory will store
B. truth D. numbers C. one XOR and one OR gate with information:
their inputs connected in parallel
20. The most obvious identifying feature D. one XOR gate and one AND gate A. Even when power is not applied
of a TTL gate is its to the memory
27. A unique operating feature of ECL B. As long as power is applied to the
A. large fan-out circuit is its
memory
B. high power dissipation
C. interconnected transistors A. very high speed C. As long as power is applied and
D. multiemitter transistor B. high power dissipation the memory is refreshed
C. series base resistor periodically
21. A 555 IC timer can be used to D. compatibility with other logic D. None of these
operate as series
33. To cause a three-state buffer to
A. a monostable multivibrator 28. For getting an output from an XNOR output 0 or 1 levels, the following
B. an astable multivibrator gate, its both inputs must be must be true:
C. a voltage controlled oscillator
D. All of these A. high A. The information must have been
B. low stored within the buffer
22. A decoder is an MSI circuit whose C. at the same logic level B. The output enable must be true
output lines are controlled by: D. at the opposite logic levels
C. The output enable must be false
A. A binary input select code 29. A glitch is a: D. The signal ̅̅̅̅
OE must be at a logic
B. A similar set of input lines 1
C. An output enable A. Momentary 0-to-1-to-0 signal
sequence 34. The dual of the statement (A+1)=1 is
D. A clock input
B. Momentary 1-to-0-to-1 signal
A. A.1 = A
23. A dynamic memory generally sequence B. A.0 = 0
contains: C. A noise pulse C. A+A = A
D. Any of the above D. A.A = 1
A. No decoders
B. Row decoders 30. Rise and fall times are measured 35. A unique advantages feature of
C. Column decoders from: CMOS logic family is its
D. Both row and column decoders
A. 50% points on a waveform A. use of NMOS circuits
24. The purpose of a clock input to a B. 0 voltage level time to 1 voltage B. power dissipation in nanowatt
flip-flop is to level time range
C. 10% to 90% points on the voltage C. speed
A. clear the device D. dependent on frequency for
transition
B. set the device power dissipation
C. always cause the output to change D. The input signal to the output
the states signal 36. If a multiplexer circuit has four input
D. cause the output to assume a state lines and a single output line, how
dependent on the controlling 31. The processor in a computer many bits of line select code are
inputs performs: required?

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 EXCEL FIRST REVIEW AND TRAINING CENTER, INC.
Cebu: JRT Bldg. Imus Ave, Cebu City | Davao: 2nd Fl. MERCO Bldg. Rizal St. cor. Bolton St. Elec 15-01 to Elec 15-06
Manila: CMFFI Bldg. R. Papa St. Sampaloc | Baguio: 4th Fl. De Guzman Bldg., Legarda Road Digital Electronics

A. 0 C. 1 44. The purpose of the processing A. Provides for delivering one of

B. 2 D. 4 function in a system is: two or more inputs to an output
B. Selects a given output line based
37. The pulse-width of an active high A. To store information that is
on a binary input code
clock pulse is the time the: needed later
C. Provides an output code that
B. To generate outputs on the basis
A. Data will be held on the output corresponds to which of a set of
of present and past inputs
after a clock signal input lines is true
C. To get information into, act on it,
B. Data must be held on the input D. Provides a storage of a certain
and output it from the system number of binary bits
after a clock edge D. None of these
C. Clock must be high
D. Clock must be low 45. The main advantage of CMOS logic
family over the TTL family is its END
38. Which of the following circuits is
used for production of delays? A. much reduced power
B. increased speed of operation
A. Astable multivibrator C. extremely low cost
B. Bistable multivibrator D. series base resistor
C. Monostable multivibrator
D. Schmitt-trigger 46. A static memory generally contains:

39. What is the decimal equivalent of the A. No decoders

hexadecimal number 3E8? B. Row decoders
C. Column decoders
A. 576 C. 1000
D. Both row and column decoders
B. 1025 D. 8350
47. The set-up time for a D-type flip-flop
40. The typical number of bits in a static is the time that the:
memory location is:
A. Data will be held on the output
A. 1 C. 2
after a clock signal
B. 8 D. 16
B. Data must be held on the input
after a clock edge
41. Like a latch, the flip-flop belongs to a
category of logic circuits known as C. Clock must be high
D. Data must be stable prior to a
A. monostable multivibrators clock edge
B. astable multivibrators
C. bistable multivibrators 48. A flip-flop which can have an
D. None of these uncertain output state is:

42. According to the absorptive Laws of A. J-K flip-flop

Boolean algebra, expression (A+AB) B. S-C flip-flop
equals C. D flip-flop
D. T flip-flop
A. A C. B
B. AB D. A 49. The chief advantage of Schotty TTL
logic family is its least
43. The invalid state of a NAND latch
occurs when A. power dissipation
B. propagation delay
A. S=1, C=0 C. fan-in
B. S=0, C=1 D. noise immunity
C. S=1, C=1
D. S=0, C=0 50. An encoder is an MSI circuit that:

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