3.

2 CONTROL UNIT (fetch, decode, and Execution)

# Software contains programs. Programs are sequence of instruction(steps).

For each step, a logical or arithmetic operation is done. For each
operation, a different set of control signal is needed.

# A microprocessor carries out instructions in a three-step process (fetch,

decode, execute). It simply repeats the three-step operation with almost no
variation, as long as power is applied to it.

Fetch

# It is the term used to indicate that the microprocessor is retrieving an

instruction from memory. The instructions are fetch one at a time, and
microprocessor brings them into the instruction decoder where they are
decoded.

# Steps in fetch process:

 Program Counter (PC) registers point to (MAR) and (MAR) places
an address on the address bus. This address appears almost
immediately at the memory unit
 Inside the memory the address is decoded. At the same time the
address is placed on the address bus, a control signal is sent to the
memory. This signal puts the memory into the read mode of
operation.
 Processor then fetches instruction from memory location pointed to
by program counter.
 Program counter is incremented to point to the next sequential
instruction.
 The instruction is then output to the data bus. The instruction is
propagated along the data bus and arrives inside the
microprocessor (MBR) to be latched into the Instruction Register
(IR).

Figure 6: A Fetch Cycle Operations

# The illustrated fetch cycle above (Figure 6) can be summarised by the
following points:

PC => MAR
MAR => memory => MBR
MBR => IR
PC incremented

# After the CPU has finished fetching an instruction, the CU checks the
contents of the IR and determines which type of execution is to be carried
out next. This process is known as the decoding phase. The instruction is
now ready for the execution cycle.

Decode

# The decode phase begins as soon as the instruction is in the Instruction

register (IR). The decoding is done by a PLA (Programmable Logic Array).
The array will output the internal and external control signals necessary to
carry out the instruction with the help of micro-code inside the processor
design.

Execute

# The phase begins as soon as the micro-code outputs the control signals
necessary to carry out the instruction. The length of time needed to
complete the execution phase varies considerably with the type of
instruction involved. Some instructions are several bytes long. Each byte is
fetched and decoded one at a time. After each byte is decoded, the
necessary control signals are executed.

# The actions within the execution cycle can be categorised into the
following four groups:
1. CPU - Memory: Data may be transferred from memory to the CPU or
from the CPU to memory.
2. CPU - I/O: Data may be transferred from an I/O module to the CPU or
from the CPU to an I/O module.
3. Data Processing: The CPU may perform some arithmetic or logic
operation on data via the arithmetic-logic unit (ALU).
4. Control: An instruction may specify that the sequence of operation may
be altered. For example, the program counter (PC) may be updated
with a new memory address to reflect that the next instruction fetched,
should be read from this new location.

# Clock cycles - Microprocessors must perform all operations under a very

strict timing sequence. Exact timing is archived by using a crystal-
controlled oscillator. The times required for fetching, decoding, and
executing are measured in the number of elapsed clock cycles.
# Instruction Cycle - The time begins when the address for retrieving an
instruction from memory is placed on the address bus for a fetch, and
ending when the execution phase is completed.

# The fastest microprocessor requires at least 1 clock cycle to complete

fetch operation.

Instruction Set and Type

# Instruction set is a complete collection of instructions that are understood

by a CPU. The instruction set is ultimately represented in binary machine
code also referred to as object code. The sets are represented by
assembly codes to human programmer.

# Elements of an instruction

 Operation Code (opcode)

Usually 8 bits, used to indicate what to do.
 Source Operand Reference(s)
Do the operation to the value at this address.
 Result Operand Reference(s)
Put the answer here
 Next Instruction Reference

# Operands are used to specify which register, which memory location, or

which I/O device, we’ll need some addressing scheme for each.

# In machine code each instruction has a unique bit pattern. For human
consumption a symbolic representation is used called mnemonic.
Examples of mnemonic are ADD, SUB, LOAD etc.

LOAD ACC, memory

# This operation loads the accumulator (ACC) with data that is stored in the
memory location specified in the instruction. The operation starts off by
transferring the address portion of the instruction from the IR to the memory
address register (MAR). The CPU then transfers the instruction located at
the address stored in the MAR to the memory buffer register (MBR) via the
data lines connecting the CPU to memory. This transfer from memory to
CPU is coordinated by the CU. To finish the cycle, the newly fetched data
is transferred to the ACC.

# The illustrated LOAD operation (Figure 7) can be summarised in the

following points:

IR [address portion] => MAR

MAR => memory => MBR
MBR => ACC
ADD ACC, memory

# This operation adds the data stored in the ACC with data that is stored in
the memory location specified in the instruction using the ALU. The
operation starts off by transferring the address portion of the instruction
from the IR to the MAR. The CPU then transfers the instruction located at
the address stored in the MAR to the MBR via the data lines connecting
the CPU to memory.

# This transfer from memory to CPU is coordinated by the CU. Next, the
ALU adds the data stored in the ACC and the MBR. To finish the cycle, the
result of the addition operation is stored in the ACC for future use.

# The illustrated ADD operation (Figure 8) can be summarised in the

following points:

IR [address portion] => MAR

MAR => memory => MBR
MBR + ACC => ALU
ALU => ACC

# After the execution cycle completes, if an interrupt is not detected, the next
instruction is fetched and the process starts all over again.