CHAPTER 4

ASSEMBLY LANGUAGE

What is Assembly Language?

 A specific set of instructions for a particular computer system.

 It provides a direct correspondence between symbolic statements and
machine language.
 a programming language with a one-to-one correspondence between
its statement and a computer’s machine language
 Assembly language is called a low-level language because it is close to
machine language in structure and function. Each assembly language instruction
corresponds to one machine instruction. In contrast, high-level languages such as
Pascal, BASIC, FORTRAN and COBOL contain powerful statements that are
translated into many machine instructions by the compiler.

What is an Assembler?

 An assembler is a program that converts source-code programs into machine

language.
 An assembler is a program that translates a program written in assembly language
into machine language.
 Each type of computer has a different assembly language, because the computer’s
design influences the instructions it can execute.

Assembly Language Assembler Machine Language

(source code) (object code)

What is a Compiler?

A compiler is a program, that translate the high-level language programming into

machine language.
A single command of high-level language is translated into many machine
instructions by the compiler.

High-level language Compiler Machine Language

(source code) (object code)

1
1.5 Editor

An assembly language can be written using any text editor and save in a
computer as a text file. Example: EDIT, notepad, etc.

1.6 Debugger

A debugger is a program that allows you to examine registers and memory and
to step through a program one statement at a time to see what is going on. In
assembly language, you will depend upon this ability to see what the CPU is
doing.

2.3 REGISTERS

Within the CPU are high–speed storage areas, which are directly linked to the
control unit and the arithmetic logic unit. Because of this, instructions using only
registers execute more quickly than do instructions using conventional memory.
The Intel instruction set requires the use of at least one register for nearly all
instructions.

Registers are special work areas inside the CPU, designed to be accessed at
high speed. The registers are 16 bits long, but you have the option of
accessing the upper or lower halves of the four data registers: AX, BX, CX
and DX

Type of registers

1. Data Registers

AX, BX CX and DX

 Data registers or general-purpose registers, are used for arithmetic and

data movement.
 Each register may be addresses as either a 16-bit or 8-bit value.

Example:

16-bit AX register

AH register AL register
(8 bit) Upper bits (8 bits) lower
bits

Instructions may address either 16-bit or 8-bit data registers from the
following list:

2
 AX BX CX DX

AH AL BH BL CH CL DH DL

For example, if AX = 126Fh, AL will equal to 6Fh.

Each general-purpose register has special attributes:

AX (accumulator). AX is called the accumulator register because it is

favored by the CPU for arithmetic operations.

BX (base). BX register can perform arithmetic and data movement, and it

has special addressing abilities. It can hold a memory address that points to
another variable. Three other registers with this ability are SI, DI and BP.

CX (counter). The CX register acts as a counter for repeating or loping

instructions. These instructions automatically repeat and decrement CX and
quit when it equals 0.

DX (data) . The DX register has a special role in multiply and divide

operations. When multiplying, for example, DX holds the high 16 bits of the
product.

2. Segment registers

 The CPU contains four segment registers, used as base locations for
program instructions, data , and the stack.

 The segment registers are as follows:

CS (code segment). The CS register holds the base location of all

executable instructions (code) in a program.

DS (data segment). The DS register is the default base location for

variables. The CPU calculates their locations using the segment
value in DS.

SS (stack segment). The SS register contains the base location of

the stack.

ES (extra segment). The ES register is an additional base location

for memory variables.

3. Index Registers

3
 Index registers contain the offsets of variables. The term offsets refers to the
distance of a variable, label, or instruction from its base segment Index
registers speed up processing of strings, array, and other data structures
containing multiple elements. The index registers are:

SI (source index). This register takes its name from the string movement
instructions, in which the source string is pointed to by the SI register. SI
usually contains an offset value from the DS register, but it can address
any variable.

DI (destination index). The DI register acts as the destination for string

movement instructions. It usually contains an offset from the ES register,
but it can address any variable.

BP (base pointer) . The BP register contains an assumed offset from

the SS register, as does the stack pointer. The BP register is often used
by a subroutine to locate variables that were passed on the stack by a
calling program.

4. Special Registers.

IP (instruction pointer). The IP register always contains the offset of

the next instruction to be executed. CS and IP combine to form the
complete address of the next instruction about to be executed.

SP (stack pointer). The SP register contains the offset, or distance from

the beginning of the stack segment to the top of the stack. The SS and
SP registers combine to form the complete top-of-stack address.

5. Flags Register

The flags register is a special 16-bit register with individual bit positions
assigned to show the status of the CPU or the results of arithmetic operations.
Each relevant bit position is given a name; other positions are undefined.

Bit Position

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

x x x x O D I T S Z x A x P x C

O = Overflow S = Sign
D = Direction Z = Zero
I = Interrupt A = Auxiliary Carry
T = Trap P = Parity
x = undefined C = Carry

4
 A flag or bit is set when it equals 1 ; it is clear (or reset) when it equals 0.
The CPU sets flags by turning on individual bits in the Flags register. There
are two basic types of flags : control flags and status flags.

Flags

 Control Flags
Individual bits may be set in the Flags register by the programmer to
control the CPU’s operation. These are the Direction, Interrupt, and
Trap flags

The Direction flag controls the assumed direction used by string

processing instructions. The flag values are 1 = up and 0 = down.
The programmer controls this flag, using the STD and CLD
instructions.

The Interrupt flag makes it possible for external interrupts to occur.

These interrupts are caused by hardware devices such as the keyboard,
disk drives, and the system clock timer. Often we briefly disable
interrupts when peerforming some critical operation that cannot be
interrupted. The flag values are 1 = enabled, and 0 = disabled;
they are controlled by the CLI and STI instructions.

The Trap flag determines whether or not the CPU will be halted after
each instruction. Debuggers set this flag so programmers can single-
step (trace) through their programs one instruction at a time. The
flags values are 1 = trap on and , 0 = trap off; the flag may be set
by the INT 3 instruction.

 Status Flags

The Status flag bits reflect the outcome of arithmetic and logical
operations performed by the CPU. These are the Overflow, Sign,
Zero, Auxiliary Carry, Parity, and Carry flags.

The Carry flag is set when the result of an unsigned arithmetic

operation is too large to fit into the destination. For example, if the
values 200 and 56 were added together and placed in an 8-bit register
(such as AL ), the result would be too large to fit; the Carry flag
would be set. The flag values are 1 = carry, 0 = no carry.

The Overflow flag is set when the signed result of an arithmetic

operation is too large to fit the destination area. The flag values are 1
= overflow and 0 = no overflow.

5
 The Sign flag is set when the result of an arithmetic or logical
operation generates a negative result. Since a negative number always
has a 1 in the highest bit position, the Sign flag is always a copy of
the destination’s sign bit. The flag values are 1 = negative, 0 =
positive.

The Zero flag is set when the result of an arithmetic or logical

operations generates a result of zero. The flag is used primarily by
jump and loop instructions, in order to allow branching to a new
location in a program based on the comparison of two values. The flag
values are 1 = zero, 0 = not zero.

The Auxiliary Carry flag is set when an operation causes a carry from
bit 3 to bit 4 (or borrow from bit 4 to bit 3) of an operand. It is
rarely used by the programmer. The flag values are 1 = carry, and
0 = no carry.

The Parity flag reflects the number of bits in the result of an operation
that are set. If there is an even number of bits, the Parity is even. If
there is an odd number of bits, the Parity is odd. This flag is used by
the operating system to verify memory integrity and by
communications software to verify correct transmission of data.

3.1 Data Definition Directives

 Define Byte (DB)

 Define Word (DW)
 Define Doubleword (DD)

A variable is a symbolic name for a location in memory where some data are
stored. In assembly language, variables are identified by labels. Each label
shows the starting location of a variable.

Example:

Declaration
aList db ‘ABCD’

So if the first letter were at offset 0, the next letter would be at offset 1, the next
at 2, and so on.

We use data definition directives to allocate storage, based on the following

predefined types:

6
 Description Bytes Attribute
DB Define byte 1 byte
DW Define word 2 word
DD Define doubleword 4 doubleword

Define Byte (DB)

The DB directives allocates storage for one or more 8-bit values. The following
syntax diagram shows that name is optional, and only one initialvalue is required.
If more are supplied, they must be separated by commas:

Syntax:

[name] DB initialvalue [, initialvalue]....

Initialvalue can be one or more 8-bit numeric values, a string constant, a constant
expression, or a question mark (?).

If the value is signes, it has a range of -128 to +127; if unsigned, the range is 0
to 255.

Examples:

char db ‘A’ ; ASCII character

signed1 db -128 ; smallest signed value
signed2 db +127 ; largest signed value
unsigned1 db 0 ; smallest unsigned value
unsigned2 db 255 ; largest unsigned value

Multiple values

A list of 8-bit numbers may be grouped under a single label, with the values
separated by commas.

Example:

list db 10, 20, 30, 40

Note:

7
 When a hexadecimal number begins with a letter (A - F), a leading zero is
added to prevent the assembler from interpreting it as a label.

Example: size db 0Ah

 A variables contents may be left undefined by using the question mark (?). Or
numeric expression can initialize a variable with a value that is calculated at
assembly time.

Example : count db ?

ages db ?, ? , ?, ?,?

size db 10*20

 A string may be assigned to a variable.

Example : c_string db “Good afternoon”

Define Word (DW)

The DW directive creates storage for one or more 16-bit words.

Syntax:

[name] DW initialvalue [, initialvalue]

Initialvalue may be any 16-bit numeric value from 0 to 65,535 (FFFFh)

If initialvalue is signes, the acceptable range is -32,768 (8000h) to +32,767

(7FFFh).

Reverse Storage Format

The assembler reverses the bytes in a word value when storing it in memory; the
lowest byte occurs at the lowest address. When the variable is moved to a 16-bit
register, the re-reverses the bytes.

Example : 2AB6h is stores in memory as B6 2A

Data declaration: value1 dw 2AB6h

8
 Storage : B6 2A

Define Doubleword (DD)

The DD directive creates storage for one or more 32-bit doublewords.

Syntax :

[name] DD initialvalue [, initialvalue]

Example: the value 12345678h would be stored in memory as

Offset: 00 01 02 03
Value: 78 56 34 12

3.2 Data Transfer Instructions

i. MOV Instruction

Because MOV copies data from one operand to another, it is called a data
transfer instruction.

Syntax :

MOV destination , source

The data are really copied, so the source operand is not changed. The source may
be an immediate value, a register, or a memory operand. The destination may be
a register or a memory operand.

Register Operands. A move involving only registers is the most efficient. Any
register may be used as a source operand, and any register except CS and IP
may be destination operands

Immediate Operands. An immediate value (integer constant) may be moved to

any register (except a segment register or IP) and be moved to memory. A
common error is to make the immediate value larger than the destination operand.

Direct Operands. A variable may be one (but not both) of the operands in a
MOV instruction. The contents of the variable are either the source or destination
of the move.
Examples of MOV with all three types of operands are shown here:

mov al , bl ; 8-bit register to register

9
 mov dx , cx ; 16-bit register to register
mov bl , 1 ; 8-bit immediate to register
mov bx , 8FE2h ; 16-bit immediate to register
mov al , count ; 8-bit memory to register
mov total , ax ; 16-bit register to memory
mov total, 1000h ; 16-bit immediate to memory

.
.
.
count db 10
total dw 0

Operands do have a few limitations, which are based on both the physical design
of the processor and its instruction set. The following are not allowed:

 CS or IP as the destination register

 Moving immediate data to segment register
 Moving from segment register to segment register
 source and destination operands of different size
 Immediate value as destination
 Memory to memory moves

Samples of illegal moves are shown here:

mov ip , ax ; IP destination
mov ds , 1000h ; immediate to segment
mov ds , es ; segment to segment
mov al , bx ; mismatching operands sizes
mov word_1 , al ; mismatching operands sizes
mov 1000h , ax ; immediate destination
mov word_2 , word_1 ; memory to memory

.
.
.
word_1 dw 1000h
word_2 dw 0

ii. XCHG Instruction

The XCHG instruction exchanges the contents of two registers or of a register

and a variable. The syntax is:

XCHG op1 , op2

10
 The two operands may be registers or memory operands, as long as one operand
is a register.

XCHG is the most efficient way to exchange two 8-bit or 16-bit operands
because you don’t need a third register or variable to hold a temporary value.
Paticularly in sorting applications, this instruction provides a speed advantage.
One or both operands may be registers, or a register may be combined with a
memory operand. Two memory operands may not be used together. The
following are all valid examples:

Xchg ax, bx ; exchange BX with AX

xchg ah, al ; exchange upper, lower register halves
xchg var1, bx ; exchange memory operand with BX

3.3 Arithmetic Instructions

i. INC and DEC Instructions

The INC and DEC instructions add 1 to or subtract 1 from a single

operand, respectively. Their syntax is

INC destination
DEC destination

Destination may be an 8 - or 16-bit register or memory operand. INC

and DEC are faster than the ADD and SUB instructions, so they should
be used where practical. All status flags are affected except the Carry
flag. Examples :

inc al ; increment 8-bit register

dec bx ; decrement 16-bit register
inc membyte ; increment memory operand

ii. ADD Instruction

The ADD instruction adds an 8- or 16-bit source operand to a

destination operand of the same sizes. The syntax is:

ADD destination , source

Source is unchanged by the operation. The sizes of the operands must

match, and only one memory operand may be used. A segment register
may not be the destination. All status flags are affected. Examples:

11
 add al, 1 ; add immediate value to 8-bit
register
add cl, al ; add 8-bit register to register
add bx, 1000h ;add immediate data to 16-bit register
add var1, ax ; add 16-bit register to memory
add dx, var1 ; add 16-bit memory to register
add var1, 10 ; add immediate value to memory

iii. SUB Instruction

The SUB instruction subtracts a source operand from a destination

operand. The syntax is:

SUB destination, source

The sizes of the two operands must match, and only one may be a
memory operand. A segment register may not be the destination
operand. On the bit level, what really happens is that the source operand
is negated and then added to the destination. For example , 4 - 1 is
really 4 + ( -1). Recall that twos complement notation is used for
negative numbers, so -1 is stored as 11111111b:

0 0 0 0 0 1 0 0 (4)
+ 1 1 1 1 1 1 1 1 (-1)

0 0 0 0 0 0 1 1 (3)

As a matter of fact, this addition resulted in a carry out of the highest bit (setting
the Carry flag), but the carry is ignored when working with signed numbers.

Examples:

sub al , 1 ; subtract immediate from 8-bit register

sub cl, al ; subtract 8-bit register from register
sub bx, 1000h ; subtract immediate from 16-bit register
sub var1, ax ; subtract 16-bit register from memory
sub dx,var1 ; subtract 16-bit memory from register
sub var1,10 ; subtract immediate value from memory

Flags Affected by ADD and SUB

If either ADD or SUB generates a result of zero, the Zero flag is set; if the
result is negative, the Sign flag is set. In the following example, line 2
generates a result of zero and line 4 generates a result of -1 (FFFFh).

12
 mov ax , 10
sub ax , 10 ; AX = 0 , ZF = 1
mov bx , 1
sub bx , 2 ; BX = FFFF , SF = 1

The Zero flag is set when the result of an arithmetic operation equals 0. Note that
INC and DEC affect the Zero flag, but not the Carry flag:

mov bl , 4Fh
add bl , 0B1h ; BL = 00
mov ax, 0FFFFh
inc ax ; NO CARRY, ZF = 1

The decision as to whether operands are signed or unsigned is completely up to

the programmer. The CPU updates the Carry and Overflow flags to cover both
possibilities.

Unsigned Operations.

For unsigned arithmetic, we are only concerned with the Carry flag. If the result
of an addition operation is too large for the destination operand, the carry flag is
set. For example, the sum of 0FFh + 1 should equal 100h; but only the two
lowest digits (00) fit into AL. The operation sets the Carry flag:

mov ax, 00FFh

add al, 1 ; AX = 0000 , CF = 1

i. Boolean and Comparison Instruction

Each of instruction in this section affect the Flags register.

 The zero flag is set when the result of an operation is zero
 The carry flag is set when the result of operation is too large for the
destination operand or subtraction operation requires aborrow.
 The sign flag is set when the highest bit of the destination operand is
set, indicating a negative result.

i. AND instruction

Performs the boolean AND operation using 8-bit or 16-bit operands and
places the result in the destination operand. The syntax is:

AND Destination, Souce

13
 The operand must be the same size and only one of them may be a memory
operand. For each matching bit in the two operand, the following rule applies:
if both bits equal 1, the result bit is 1; otherwise, it is 0. Example of AND
operation:

0 0 1 1
0 1 0 1
0 0 0 1

ii. OR instruction

Performs the boolean OR operation using 8-bit or 16-bit operands and places
the result in the destination operand. The syntax is:

OR Destination, Source

The operand must be the same size and only one of them may be a memory
operand. For each matching bit in the two operand, the following rule applies:
For each matching bit in the two operand, the following rule applies: if both
bits equal 0, the result bit is 0; otherwise, it is 1. Example of OR operation:

0 0 1 1
0 1 0 1
0 1 1 0

iii. XOR instruction

Performs the boolean exclusive OR operation using 8-bit or 16-bit operands

and places the result in the destination operand. The syntax is:

XOR Destination, Source

The operand must be the same size and only one of them may be a memory
operand. For each matching bit in the two operand, the following rule applies:
If both bits are the same(both 0 or both 1) the result is 0; otherwise the result
is 1. Example of XOR operation:

0 0 1 1
0 1 0 1
0 1 1 0

iv. NOT instruction

The NOT instruction reverses all the bits in an operand, changing 1 to 0 and
vice versa. The result is called 1st compliment. The syntax is:

NOT Destination

CPU stores negative number in 2nd compliment form. You can create the 2 nd
compliment of a number using the NOT and INC instruction.

14
v. NEG instruction

The NEG instruction converts a number from positive to negative and vice
versa. It does by converting the number to its 2nd compliment: The syntax is:

NEG Destination

The instruction reverses all bits in the destination operand and add 1 to the
result.

vi. TEST instruction

Perform an implied AND operation on the destination operand, using the

source operand. The flag are affected, but neither operand is changed. The
syntax is:

TEST Destination, Source

The TEST instruction is particularly valuable when you want to know if

individual bits in an operand are set. Ex: to check the status of printer.

vii. CMP instruction

Perform the comparison operation of two 8-bit or 16-bit operands. The result
reflected in the state of the flags register. The CMP perform an implied
subtraction of the source operand from the destination operand, but neither
operand is actually changed. The syntax is:

CMP Destination, Source

Only one operand may be a memory operand. The destination can be neither
an immediate operand nor the IP register. Neither operand may be a
segment register. The following table shows how the flags registers affected
by the CMP instruction.

Resul of Comparison Flag(s) Affected

Destination < Source Carry flag = 1
Destination = Source Zero Flag = 1
Destination > Source Carry Flag = 0, Zero Flag = 0

CMP is a valuable instruction because it provides the basis for most

conditional logic structure especially to perform conditional jump.

15
ii. Jump and Conditional Jump

i. LOOP instruction

The LOOP instruction is the easiest way to repeat a block of statements a

specific number of times. CX is automatically used as a counter and
decremented each time the repeats. The syntax is:

LOOP destination

First , the LOOP instruction subtracts 1 from CX. Then, if CX is greater than
zero, control transfers to destination.

In the following example. The loop repeats five times:

Mov cx,5 ; cx is the loop counter

Start: . ; loop destination/label
.
.
Loop Start ; jump to label Start

If CX is equal to zero after having been decremented, no jump takes place

and control passes to the following LOOP instruction. The flag are not
affected when CX is decremented, even if equals to zero.

ii. Conditional jump

A conditional jump instruction transfers control to a destination address when

a flag condition is true. The syntax is:

Jcond destination

Each conditional jump instruction checks one or more flsgs, returning a result
of true or false. If the result true, the jump is taken: otherwise, the program
does nothing and continue to the next instruction.

Commonly, conditional used together with CMP instruction in order to

determine the condition is true or false. Example:

label1: mov ax, 4

mov bx, 5
inc ax

cmp ax, bx
je label1
.
.
Int 21

16
 Example of conditional jump

Mnemonic Description Flag condition(s)

JZ Jump if zero ZF=1
JE Jump if equal; (if op1 = op2) ZF=1
JA Jump if above; (if op1 > op2) CF=0 and ZF = 0
JAE Jump if above or equal; (if op1 >= op2) CF=0
JB Jump if below; (if op1 < op2) CF = 1
JC Jump if carry; (if op1< op2) CF=1
JBE Jump if below or equal; (if op1 <= op2) CF =1 or ZF=1
JCXZ Jump if CX = 0 CX = 0
JS Jump if sign SF = 1

iii. MULTIPLICATION AND DIVISION INSTRUCTION

i. MUL Instructions

The MUL and IMUL instructions multiply an 8-bit or 16-bit operand by AL

or AX.

If an 8-bit source operand is supplied, it is automatically multiplied by AL,

and the result is stored in AX.

If a 16-bit source operand is supplied, it is multiplied by AX , and the result

is stored in DX and AX (the high 16 bits are in DX). The syntax is:

MUL source

IMUL source

The source operand may be either a register or a memory operand, bit it

may not be immediate data. The destination (either AX or DX:AX ) is
implied and may not be changed.

Example 1. Multiply AL by 10h:

mov al, 6h
mov bl, 10h
mul bl ;AX = 0060h

17
 Example 2. Multiply AX by 10h:

Mov ax, var1

Mul var2 ; dx = 0002h , AX = 0000h
.
.
.
var1 dw 2000h
var2 dw 0010h

ii. IMUL Instructions

The IMUL (integer multiply) instruction multiplies signed binary values. It

sign-extends the result through the highest bit of AX or DX:AX, depending
on the size of the source operand. An 8-bit operation sign-extends AL
into AH; a 16-bit operation sign-extends AX into DX. This is shown here
for the value -16:

Result = -16

8-bit operation: AX = FFF0h

16-bit operation: DX = FFFFh , AX = FFF0h

For an 8-bit multiplication, IMUL sets the Carry and Overflow flags if the
resulting AH is not a sign extension of AL (i.e., if the product is larger than
8 bits)

For a 16-bit multiplication, the Carry and Overflow flags are set if DX is not
a sign extension of AX ( the product is larger than 16 bits).

Example 1. 8-bit Operation : 48 x 4 = 192`

mov al, 48
mov bl, 4
imul bl ;AX = 00C0h +192), CF = 1, OF = 1

The product in AX is 00C0h (+192). Since AH is not a sign extension of

AL, the Carry and Overflow flags were set. This tells you that the signed
magnitude of the result is greater than 8 bits.

18
 Example 2: 8-bit Operation : -4 x 4 = -16

mov al , -4
mov bl , 4
imul bl ;AX = FFF0h(-16), CF = 0, OF = 0

The product in AX is FFF0h (-16), and AH is a sign extension of AL. In

other words, the signed result fits within AL.

Example 3: 16-bit Operation: 48 x 4 = 192

mov ax , 48
mov bx , 4
imul bx ;DX=0000, AX=00C0h(+192),CF = 0,OF = 0

iii. DIV

The DIV and IDIV instructions perform both 8- and 16-bit division, signed
and unsigned. A single operand is supplied (register or memory operand),
which is assumed to be the divisor. Syntax:

DIV source

IDIV source

If the divisor is 8-bits long, AX is the dividend, AL the quotient, and AH

the remainder.

If the divisor is 16 bits, DX:AX is the dividend, AX the quotient, and DX

the remainder.

Dividend / Divisor = Quotient Remainder

AX Operand AL AH
DX:AX Operand AX DX

Example 1. 8-bit division (83h/2 = 41h, remainder 1)

mov ax , 0083h ; dividend

19
 mov bl , 2 ; divisor
div bl ; AL = 41h, AH = 01h
Example 2. 16-bit division(8003h/100h = 80h, remainder 3). After the
division, the quotient is in AX and the remainder is in DX.

Mov dx,0 ; Clear dividend(high)

Mov ax,8003h ; dividend (low)
Mov cx,100h ; divisor
Div cx ; AX = 0080h, DX=0003h

3.7 SHIFT AND ROTATE INSTRUCTION

The shift and rotate instruction provide a way to move bits around in and
operand.

i. SHL instruction

The SHL (shift left) instruction shifts each bit in a destination operand to the
left, filling the lowest bit with 0. The highest bit is moved to the carry flag, and
the bit that was in the carry flag is lost.

0
CF

There are two formats for SHL,

SHL Destination, 3

SHL Destination, cl

Mutiplication: One of the most powerful uses of SHL instruction is for

performing high-speed multiplication. The multiplication must always be a
power of 2, and the number of times you shift is actually the exponent. For
example, shifting left one position is the same as multiplying by 2 1, shifting 2 to
left is same as multiplying by 22, and so on. The example shows the decimal
value of DL after each shift.

shl dl, 1 ; dl = 1
shl dl, 1 ; dl = 2
shl dl, 1 ; dl = 4
shl dl, 1 ; dl = 8
shl dl, 1 ; dl = 16
shl dl, 1 ; dl = 32

20
 ii. SHR instruction

The SHR (shift right) instruction shifts each bit in a destination operand to the
right, filling the highest bit with 0. The lowest bit is moved to the carry flag, and
the bit that was in the carry flag is lost.

0
CF
There are two formats for SHL,

SHR Destination, 3

SHR Destination, cl

Division: One of the most powerful uses of SHR instruction is for performing
high-speed division. The division must always be a power of 2, and the
number of times you shift is actually the exponent. For example, shifting right
one position is the same as dividing by 2 1, shifting 2 to left is same as dividing
by 22, and so on. The example shows the decimal value of DL after each shift.

iii. SAL and SAR instructions

SAL (shift arithmetic left) and SAR (shift arithmetic right) are shift instruction
for sign number. SAL is identical to SHL and included in the instruction set
only for completeness. SAR shift each bit to the right and makes a copy of the
sign bit.

CF

SAR copies the lowest bit of the destination operand into the carry flag, shift
bit of operand 1 position to the right and duplicate the original sign bit.

The syntax for SAR and SHR is identical to that of SHL and SHR:

SAR Destination, 3

SAR Destination, cl

21
iv. ROL instruction

The ROL (rotate left) instruction moves each bit to the left. The highest bit is
copied both into Carry flag and into the lowest bit.

CF

The syntax for ROL :

ROL Destination, 3

ROL Destination, cl

v. ROR instruction

The ROR (rotate right) instruction moves each bit to the right. The lowest bit is
copied into the Carry flag and into the highest bit.

CF

The ROL (rotate/left) instruction moves each bit to the left. The highest bit is
copied both into Carry flag and into the lowest bit.

The syntax for ROR:

ROL Destination, 3

ROL Destination, cl

22
vi. RCL and RCR instruction

The RCL (rotate carry left) instruction shifts each bit to the left and copies the
highest bit into the Carry flag. The carry flag is copied into the lowest bit of the
operand.

CF

The syntax for RCL:

RCL Destination, 3

RCL Destination, cl

The RCR (rotate carry right) instruction shifts each bit to the right and copies
the lowest bit into the Carry flag. The carry flag is copied into the higest bit of
the operand.

CF

The syntax for RCR:

RCR Destination, 3

RCR Destination, cl

23