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Mk Fdc2214 技术手册
Mk Fdc2214 技术手册
Mk Fdc2214 技术手册
40 MHz
FDC2114 / FDC2214 VDD
CLKIN VDD
0.1 µF 1 µF
Int. Osc. GND
IN0A
Resonant SD
GPIO
L C IN0B circuit driver INTB
GPIO MCU
Cap 3.3 V
Sensor 0 Core GND
IN3A ADDR
Resonant SDA I2C
I2C
L C IN3B circuit driver SCL peripheral
Cap
Sensor 3
Copyright © 2016, Texas Instruments Incorporated
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNOSCZ5
FDC2212, FDC2214, FDC2112, FDC2114
ZHCSDX2A – JUNE 2015 – REVISED JUNE 2015 www.ti.com.cn
目录
1 特性 ........................................................................... 1
9.3 Feature Description ................................................... 12
2 应用 ........................................................................... 1 9.4 Device Functional Modes...........................................21
3 说明 ........................................................................... 1 9.5 Programming...............................................................21
4 修订历史记录 ............................................................. 2 9.6 Register Maps.............................................................22
5 说明 (续) ............................................................... 3 10 Application and Implementation ........................ 39
6 Device Comparison Table ...................................... 3 10.1 Application Information.............................................39
7 Pin Configuration and Functions .......................... 4 10.2 Typical Application ...................................................40
8 Specifications .......................................................... 5 10.3 Do's and Don'ts ........................................................46
8.1 Absolute Maximum Ratings ........................................ 5
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11 Power Supply Recommendations ...................... 46
8.2
8.3
ESD Ratings................................................................. 5
Recommended Operating Conditions ........................ 5
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12 Layout.................................................................... 46
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8.4 Thermal Information..................................................... 5 o b
a 13
Layout Guidelines .....................................................46
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12.2 Layout Example ........................................................46
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8.5 Electrical Characteristics ............................................. 6 器件和文档支持 ...................................................... 51
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8.6 Timing Requirements .................................................. 7 13.1 器件支持 ....................................................................51
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8.7 Switching Characteristics - I2C ................................... 8 13.2 相关链接 ....................................................................51
8.8 Typical Characteristics ................................................ 9 13.3 社区资源 ....................................................................51
9 Detailed Description ............................................. 11 13.4 商标 ...........................................................................51
9.1 Overview..................................................................... 11 13.5 静电放电警告 ............................................................51
9.2 Functional Block Diagrams ....................................... 11 13.6 Glossary ....................................................................51
14 机械、封装和可订购信息........................................ 51
4 修订历史记录
Changes from Original (June 2015) to Revision A Page
• 已添加 完整数据表。 ................................................................................................................................................................ 1
5 说明 (续)
FDC221x 经过优化,分辨率高达 28 位,而 FDC211x 的采样速率高达 13.3ksps,便于实现 使用 快速移动目标的
应用。250nF 超大最高输入电容支持使用远程传感器并跟踪环境随时间、温度和湿度的变化情况。
FDC2x1x 系列器件面向接近感测和液位感测 应用, 适用于所有液体类型。如果非导电液位感测 应用 存在干扰
(例如人手),建议使用集成有源屏蔽驱动器的 FDC1004。
a obao 4 WQFN-16
FDC2212 28 bit
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FDC2214 28 bit
//ci 4 WQFN-16
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FDC2112/FDC2212 WSON
DNT-12
Top View
SCL 1 12 IN1B
SDA 2 11 IN1A
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CLKIN 3 10 IN0B
9.cIN0A
DAP
bao
ADDR 4
o
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INTB 5 8 GND
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SD 6 7 VDD
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h
FDC2114/FDC2214 WQFN
RGH-16
Top View
IN3B
IN3A
IN2B
IN2A
16
15
14
13
SCL 1 12 IN1B
SDA 2 11 IN1A
DAP
CLKIN 3 10 IN0B
ADDR 4 9 IN0A
5
8
INTB
SD
VDD
GND
Pin Functions
PIN
TYPE(1) DESCRIPTION
NAME NO.
SCL 1 I I2C Clock input
SDA 2 I/O I2C Data input/output
CLKIN 3 I Master Clock input. Tie this pin to GND if internal oscillator is selected
I2C Address selection pin: when ADDR=L, I2C address = 0x2A, when ADDR=H, I2C address =
ADDR 4 I
0x2B.
INTB 5 O Configurable Interrupt output pin
SD 6 I Shutdown input
VDD 7 P Power Supply
GND 8 G Ground
IN0A 9 A Capacitive sensor input 0
IN0B 10 A Capacitive sensor input 0
IN1A 11 A Capacitive sensor input 1
IN1B 12 A Capacitive sensor input 1
IN2A 13 A Capacitive sensor input 2 (FDC2114 / FDC2214 only)
IN2B 14 A Capacitive sensor input 2 (FDC2114 / FDC2214 only)
(2) There is an internal electrical connection between the exposed Die Attach Pad (DAP) and the GND pin of the device. Although the DAP
can be left floating, for best performance the DAP should be connected to the same potential as the device's GND pin. Do not use the
DAP as the primary ground for the device. The device GND pin must always be connected to ground.
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8 Specifications
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8.1 Absolute Maximum Ratings
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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1mH inductor, 10kHz oscillation 250 nF
CIN Sensor pin parasitic capacitance
tt.t a 4 pF
NBITS Number of bits
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FDC2112, FDC2114
RCOUNT ≥ 0x0400
12 bits
(1) Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in
very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables
under conditions of internal self-heating where TJ > T A. Absolute Maximum Ratings indicate junction temperature limits beyond which
the device may be permanently degraded, either mechanically or electrically.
(2) Register values are represented as either binary (b is the prefix to the digits), or hexadecimal (0x is the prefix to the digits). Decimal
values have no prefix.
(3) Limits are ensured by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are ensured through
correlations using statistical quality control (SQC) method.
(4) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(5) I2C read/write communication and pull-up resistors current through SCL, SDA not included.
(6) Sensor capacitor: 1 layer, 20.9 x 13.9 mm, Bourns CMH322522-180KL sensor inductor with L=18µH and 33pF 1% COG/NP0 Target:
Grounded aluminum plate (176 x 123 mm), Channel = Channel 0 (continuous mode) CLKIN = 40 MHz, CHx_FIN_SEL = b10,
CHx_FREF_DIVIDER = b00 0000 0001 CH0_RCOUNT = 0xFFFF, SETTLECOUNT_CH0 = 0x0100, DRIVE_CURRENT_CH0 = 0x7800.
(7) Lower VSENSORMIN oscillation amplitudes can be used, but will result in lower SNR.
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8.6 Timing Requirements
t.ta
tSDWAKEUP Wake-up time from SD high-low transition to I2C readback 2 ms
tSLEEPWAKEUP Wake-up time from sleep mode
i r t 0.05 ms
tWD-TIMEOUT
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Sensor recovery time (after watchdog timeout) 5.2 ms
I2C TIMING CHARACTERISTICS
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fSCL Clock frequency 10 400 kHz
tLOW Clock low time 1.3 μs
tHIGH Clock high time 0.6 μs
Hold time (repeated) START condition: after this period, the first clock
tHD;STA 0.6 μs
pulse is generated
tSU;STA Setup time for a repeated START condition 0.6 μs
tHD;DAT Data hold time 0 μs
tSU;DAT Data setup time 100 ns
tSU;STO Setup time for STOP condition 0.6 μs
tBUF Bus free time between a STOP and START condition 1.3 μs
tVD;DAT Data valid time 0.9 μs
tVD;ACK Data valid acknowledge time 0.9 μs
tSP Pulse width of spikes that must be suppressed by the input filter (1) 50 ns
(1) This parameter is specified by design and/or characterization and is not tested in production.
SDA
tBUF
tf tLOW tHD;ST A tr
tr tf tSP
SCL
tHD;STA tSU;STA tSU;STO
tHIGH
tHD;DAT tSU;DAT
3.25 3.25
VDD = 2.7 V
3.225 VDD = 3V
VDD = 3.3 V
3.2 VDD = 3.6 V 3.2
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IDD CH0 Current (mA)
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3.15
a o b 3.15
3.125
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3.1
p s :// 3.1 -40°C 50°C
3.075 h tt -20°C
0°C
85°C
100°C
25°C 125°C
3.05 3.05
-40 -20 0 20 40 60 80 100 120 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6
Temperature (°C) VDD (V)
D003 D004
Includes 1.57 mA sensor current Includes 1.57 mA sensor current
–40°C to +125°C
Figure 2. Active Mode IDD vs. Temperature Figure 3. Active Mode IDD vs. VDD
60 65
VDD = 2.7 V -40°C 0°C 50°C 100°C
55 VDD = 3V 60 -20°C 25°C 85°C 125°C
VDD = 3.3 V
VDD = 3.6 V 55
50
Sleep Current (µA)
50
45
45
40
40
35
35
30 30
25 25
-40 -20 0 20 40 60 80 100 120 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6
Temperature (°C) D005
VDD (V) D006
–40°C to +125°C
Figure 4. Sleep Mode IDD vs. Temperature Figure 5. Sleep Mode IDD vs. VDD
1.4 1.6
VDD = 2.7 V -40°C 0°C 50°C 100°C
1.2 VDD = 3V 1.4 -20°C 25°C 85°C 125°C
VDD = 3.3 V
VDD = 3.6 V 1.2
Shutdown Current (µA)
1
1
0.8
0.8
0.6
0.6
0.4
0.4
0.2 0.2
0 0
-40 -20 0 20 40 60 80 100 120 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6
Temperature (°C) D007
VDD (V) D008
–40°C to +125°C
Figure 6. Shutdown Mode IDD vs. Temperature Figure 7. Shutdown Mode IDD vs. VDD
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43.35
43.35
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43.34
43.34
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43.33 43.33
43.32 43.32
-40 -20 0 20 40 60 80 100 120 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6
Temperature (°C) D009
VDD (V)
D010
–40°C to +125°C Data based on 1 unit
Figure 8. Internal Oscillator Frequency vs. Temperature Figure 9. Internal Oscillator Frequency vs. VDD
9 Detailed Description
9.1 Overview
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可以被转换成一个等效电容
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9.2 Functional Block Diagrams
3.3 V
3.3 V
CLKIN VDD
40 MHz
0.1 µF 1 µF
Int. Osc. GND
IN0A
Resonant SD
GPIO
L C IN0B circuit driver INT B
GPIO MCU
Cap 3.3 V
Sensor 0 Core GND
IN1A ADDR
Resonant 2 SDA I2 C
IC
L C IN1B circuit driver peripheral
SCL
Cap
Sensor 1
Copyright © 2016, Texas Instruments Incorporated
3.3 V
3.3 V
CLKIN VDD
40 MHz
0.1 µF 1 µF
Int. Osc. GND
IN0A
SD
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Resonant
GPIO
IN0B circuit driver INT B
L C
b a o GPIO MCU
a o
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Cap 3.3 V
Sensor 0 Core GND
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IN3A
Resonant
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IC
ADDR
SDA I2 C
L C IN3B circuit driver SCL peripheral
Cap
Sensor 3
Copyright © 2016, Texas Instruments Incorporated
FDC 由前端谐振电路的驱动程序,紧随其后的是一个多路复用器序列通过活动渠道,连接他们的核心措施
和数字化传感器频率(fSENSOR)。核心使用参考频率(fREF)测量传感器的频率。fREF 来自一个内部参考时钟
(振荡器),或外部提供的时钟。每个通道的数字化输出正比于 fSENSOR / fREF 的比率。I2C 接口是用来支持
设备配置和传输数字化主机处理器的频率值或外部提供的时钟。每个通道的数字化输出正比于 fSENSOR /
fREF 的比率。I2C 接口是用来支持设备配置和传输数字化主机处理器的频率值
IN0A
Cap L
÷m tfIN0t
Sensor 0 fSENSOR0 IN0B
CH0_FIN_SEL (0x14)
IN1A
Cap L tfIN1t
÷m
Sensor 1 fSENSOR1 IN1B
IN2A
(1)
CH1_FIN_SEL (0x15)
m / fINt
Cap (1) L ÷m
.c o (1)
tfIN2 t
Sensor 2 fSENSOR2
(1)
IN2B (1)
o b ao
CH2_FIN_SEL (0x16)(1)
Cap IN3A
(1)
tt.t a
(1)
L
c i r ÷m tfIN3(1)t
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Sensor 3 fSENSOR3
(1)
IN3B(1) CONFIG (0x1A)
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CH3_FIN_SEL (0x17)(1) MUX_CONFIG
Core
(0x1B)
÷n fREF0t
CH0_FREF_DIVIDER (0x14)
REF_CLK_SRC
(0x1A) ÷n fREF1
fCLKIN CLKIN
CONFIG (0x1A)
CH3_FREF_DIVIDER (0x17)(1) MUX_CONFIG
(0x1B)
在图 12 中,关键的时钟是鳍,fREF,fCLK。fCLK 选择从内部时钟源或外部时钟源(CLKIN)。频率测量参考
时钟,fREF 来源于 fCLK 来源。建议精密应用程序使用一个外部主时钟提供所需的稳定性和精度要求的应用
程序。内部振荡器可用于需要低成本的应用程序,不需要精度高。fINx 时钟来自传感器频率 x 频
道,fSENSORx。fREFx 和 fINx 必须满足表 1 中列出的需求,取决于 fCLK(主时钟)是内部或外部时钟。
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Single-ended sensor
.
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b10: 0.01MHz to
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(1) Channels 2 and 3 are only available for FDC2114 and FDC2214.
(2) Refer to Sensor Configuration for information on differential and single-ended sensor configurations.
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Table 2 shows the clock configuration registers for all channels.
(1) Channels 2 and 3 are only available for FDC2114 and FDC2214
FDC的多通道方案允许用户保存板空间和支持灵活的系统设计例如,温度漂移可以经常导致组件值转变,导致传感器的谐振频
率的变化。使用第二个传感器作为参考提供了消除温度变化的能力。当在多渠道经营模式时,顺序FDC样品活动频道。在单通道
模式下,FDC样品单通道,这是可选择的。表3显示的是用于配置寄存器和值单通道或多通道模式。
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Multi-channel
b a o 00 = Ch0, Ch 1
MUX_CONFIG addr 0x1B
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RR_SEQUENCE [14:13] 01 = Ch0, Ch 1, Ch 2
Table 4 illustrates the registers that contain the fixed point sample values for each channel.
(1) Channels 2 and 3 are only available for FDC2114 and FDC2214.
(2) The DATA_CHx.DATAx register must always be read first, followed by the DATA_LSB_ CHx.DATAx register of the same channel to
ensure data coherency.
(3) A DATA value of 0x0000000 = under range for FDC2212/FDC2214.
Copyright © 2015, Texas Instruments Incorporated 1
(4) A DATA value of 0xFFFFFFF = over range for FDC2212/FDC2214.
FDC2212, FDC2214, FDC2112, FDC2114
ZHCSDX2A – JUNE 2015 – REVISED JUNE 2015 www.ti.com.cn
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a o b
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When the FDC sequences through the channels in multi-channel mode, the dwell time interval for each channel
is the sum of three parts:
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1. sensor activation time
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2. conversion time
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3. channel switch delay
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h t tp of settling time required for the sensor oscillation to stabilize, as shown
The sensor activation time is the amount
in Figure 13. The settling wait time is programmable and should be set to a value that is long enough to allow
stable oscillation. The settling wait time for channel x is given by:
tSx = (CHX_SETTLECOUNTˣ16)/f REFx (3)
Table 5 illustrates the registers and values for configuring the settling time for each channel.
Channel 0 Channel 0 Channel Channel 1 Channel 1 Channel Channel 0
Sensor Conversion switch delay Sensor Conversion switch delay Sensor
Activation Activation Activation
Channel 0
Channel 1
Active Channel
Sensor Signal
(1) Channels 2 and 3 are available only in the FDC2114 and FDC2214.
(2) fREFx is the reference frequency configured for the channel.
Round the result to the next highest integer (for example, if Equation 4 recommends a minimum value of 6.08,
program the register to 7 or higher).
The conversion time represents the number of reference clock cycles used to measure the sensor frequency.
It is set by the CHx_RCOUNT register for the channel. The conversion time for any channel x is:
tCx = (CHx_RCOUNT ˣ 16 + 4) /f REFx (5)
The reference count value must be chosen to support the required number of effective bits (ENOB). For
13
example, if an ENOB of 13 bits is required, then a minimum conversion time of 2 = 8192 clock cycles is
required. 8192 clock cycles correspond to a CHx_RCOUNT value of 0x0200.
(1) Channels 2 and 3 are available only for FDC2114 and FDC2214.
The typical channel switch delay time between the end of conversion and the beginning of sensor activation of
the subsequent channel is:
Channel Switch Delay = 692 ns + 5 / fref (6)
The deterministic conversion time of the FDC allows data polling at a fixed interval. For example, if the
programmed RCOUNT setting is 512 FREF cycles and SETTLECOUNT is 128 FREF cycles, then one conversion
takes 1.8ms (sensor-activation time) + 3.2ms (conversion time) + 0.75ms (channel-switch delay) = 16.75ms per
channel. If the FDC is configured for dual-channel operation by setting AUTOSCAN_EN = 1 and
RR_SEQUENCE = 00, then one full set of conversion results will be available from the data registers every
33.5ms.
A data ready flag (DRDY) is also available for interrupt driven system designs (see the STATUS register
description in Register Maps).
MSB LSB
Conversion result 15 12 11 8 7 4 3 0
Output_gain = 0x3 11 0
Output_gain = 0x2 11 0
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Output_gain = 0x1 11
b a o. 0
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Output_gain = 0x0
(default) 11 0
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11 0 Data available in DATA_MSB_CHx.DATA_CHx [11:0]
For systems in which the sensor signal variation is less than 25% of the full-scale range, the FDC can report
conversion results with higher resolution by setting the Output Gain. The Output Gain is applied to all device
channels. An output gain can be used to apply a 2-bit, 3-bit, or 4-bit shift to the output code for all channels,
allowing access to the 4 LSBs of the original 16-bit result. The MSBs of the sample are shifted out when a gain is
applied. Do not use the output gain if the MSBs of any active channel are toggling, as the MSBs for that channel
will be lost when gain is applied.
Example: If the conversion result for a channel is 0x07A3, with OUTPUT_GAIN=0x0, the reported output code is
0x07A. If OUTPUT_GAIN is set to 0x3 in the same condition, then the reported output code is 0x7A3. The
original 4 MSBs (0x0) are no longer accessible.
An offset value may be subtracted from each DATA value to compensate for a frequency offset or maximize the
dynamic range of the sample data. The offset values should be < fSENSORx_MIN / fREFx. Otherwise, the offset might
be so large that it masks the LSBs which are changing.
(1) Channels 2 and 3 are only available for FDC2114 and FDC2214.
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The sensor capacitance CSENSE of a differential sensor configuration can be determined by:
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CSENSOR =
1
−C
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L × (2ν × ƒSENSORx )2
a o b
where
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C = parallel sensor capacitance (see Figure 55)
p (7)
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The FDC2112 and FDC2114 sensor frequency fSENSORx can be determined by:
{
ƒ = CHx_FIN_SEL × ƒ × DATAx +
CHxOFFSET
(1) Channels 2 and 3 are available for FDC2114 and FDC2214 only.
20 Copyright © 2015, Texas Instruments Incorporated
FDC2212, FDC2214, FDC2112, FDC2114
www.ti.com.cn ZHCSDX2A – JUNE 2015 – REVISED JUNE 2015
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The CHx_IDRIVE field should be programmed such that the sensor oscillates at an amplitude between 1.2Vpk
this mode. h t t
cannot be achieved with the highest IDRIVE Set the HIGH_CURRENT_DRV register bit to b1 to enable
(1) Channels 2 and 3 are available for FDC2114 and FDC2114 only.
See the STATUS and STATUS_CONFIG register description in the Register Map section. These registers can
be configured to trigger an interrupt on the INTB pin for certain events. The following conditions must be met:
1. The error or status register must be unmasked by enabling the appropriate register bit in the
STATUS_CONFIG register
2. The INTB function must be enabled by setting CONFIG.INTB_DIS to 0
When a bit field in the STATUS register is set, the entire STATUS register content is held until read or until the
DATA_CHx register is read. Reading also de-asserts INTB.
Interrupts are cleared by one of the following events:
1. Entering Sleep Mode
2. Power-on reset (POR)
3. Device enters Shutdown Mode (SD is asserted)
4. S/W reset
5. I2C read of the STATUS register: Reading the STATUS register will clear any error status bit set in STATUS
along with the ERR_CHAN field and de-assert INTB
Setting register CONFIG.INTB_DIS to b1 disables the INTB function and holds the INTB pin high.
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9.4 Device Functional Modes
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9.4.1 启动模式
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当FDC权力,它进入睡眠模式和将等待配置。一旦设备配置,退出睡眠模式通过设置配置。SLEEP_MODE_EN b0。
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建议配置FDC在睡眠模式。如果在FDC需要更改设置,返回设备睡眠模式,修改相应的寄存器,然后退出睡眠模式。
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9.4.2 正常(转换)模式
当在正常(转换)模式下工作时,FDC周期性地采样传感器的频率并生成用于有源信道的采样输出。
9.4.3 睡眠模式
进入睡眠模式通过设置配置。SLEEP_MODE_EN注册字段为1。在这种模式下,寄存器内容维护。退出睡眠模式,设置配置。
SLEEP_MODE_EN注册字段为0。在设置CONT.SLIPEPMODEDEN到B0之后,第一个转换的传感器激活将在16384个FIFT时钟
周期之后开始。在睡眠模式下,I2C接口是功能性的,从而可以执行寄存器读写。 在睡眠模式下,不执行转换。此外,进入睡眠
模式将清除任何错误条件,并取消断言ItB引脚。
9.4.4 关机模式
当SD引脚设置为高,FDC将进入关机模式。关机模式是最低的电源状态。为了退出关机模式,将SD引脚设置为低。进入关
机模式将返回所有寄存器到它们的默认状态。
在关闭模式下,不执行转换。此外,进入关机模式将清除任何错误条件和取消断言的ItB引脚。当设备处于关机模式时,不可能通过I2C接
口从设备读取或写入。
9.4.4.1重置
FDC可以通过写入ReSeTyDe.ReStEdVE来重置。转换将停止,所有寄存器值将返回到它们的默认值。该寄存器位在读取时将始终返回0B
9.5 程序设计
FDC设备使用I2C接口访问控制和数据寄存器。
9.5.1 I2C接口规范
FDC使用扩展的I2C启动序列进行寄存器访问。I2C接口的最大速度是400千比特/秒。这个序列遵循标准的I2C 7位从地址,之后是8位指针
Programming (continued)
1 9 1 9
SCL
SDA A6 A5 A4 A3 A2 A1 A0 R/W R7 R6 R5 R4 R3 R2 R1 R0
Start by Ack by Ack by
Master Slave Slave
Frame 1 Frame 2
Serial Bus Address Byte Slave Register
from Master Address
1 9 1
m / 9
SCL
. c o
SDA D15 D14 D13 D12 D11 D10 D9 D8
o b ao
D7 D6 D5 D4 D3 D2 D1 D0
tt.t
Ack by
a Ack by Stop by
Frame 3
c i r Slave
Frame 4
Slave Master
p s ://
Data MSB from
Master
Data LSB from
Master
SDA A6 A5 A4 A3 A2 A1 A0 R/W R7 R6 R5 R4 R3 R2 R1 R0
Start by Ack by Ack by
Master Slave Slave
Frame 1 Frame 2
Serial Bus Address Byte Slave Register
from Master Address
1 9 1 9 1 9
SCL
rtt.t
0x0000 信道0 MSB转换结果和状态(仅FDC2212/FDC2214)
0x01 DATA_LSB_CH0 0x0000
s : //ci 信道0
读取
LSB转换结果。必须在寄存器地址0x00(仅FDC2212/FDC2214)之后
0x02 DATA_CH1
h ttp0x0000 信道 1 转换结果和状态(仅 FDC2112/FDC2114)
0x0000 信道1 MSB转换结果和状态(仅FDC2212/FDC2214)
0x03 DATA_LSB_CH1 0x0000 信道1 LSB转换结果。必须在寄存器地址0x02(仅FDC2212/FDC2214)之后
读取
0x04 DATA_CH2 0x0000 信道2转换结果和状态(仅FDC2114)
0x0000 信道2 MSB转换结果和状态(仅FDC2214)
0x05 DATA_LSB_CH2 0x0000 信道2 LSB转换结果。必须在寄存器地址0x04(仅FDC2214)之后读取
7 6 5 4 3
m /2 1 0
DATA0
ao .co
o b
r t ta
Table 12. Address 0x00,.DATA_CH0
t Field Descriptions
Type/ci Reset
Bit Field
s : / Description
http R
15:14 RESERVED R 00 Reserved.
13 CH0_ERR_WD 0 Channel 0 Conversion Watchdog Timeout Error Flag. Cleared by
reading the bit.
12 CH0_ERR_AW R 0 Channel 0 Amplitude Warning. Cleared by reading the bit.
11:0 DATA0 (FDC2112 / FDC2114 only) R 0000 0000 Channel 0 Conversion Result
0000
DATA0[27:16] (FDC2212 /
FDC2214 only)
7 6 5 4 3 2 1 0
DATA0
7 6 5 4 3 2 1 0
DATA1
7 6 5 4 3 2 1 0
DATA1
7 6 5 4 3 2 1 0
DATA2
7 6
h5 ttp 4 3 2 1 0
DATA2
7 6 5 4 3 2 1 0
DATA3
7 6 5 4 3 2 1 0
DATA3
i r tt.ta
CH0_RCOUNT
: // c
t p s
Table 20. Address 0x08, RCOUNT_CH0 Field Descriptions
Bit Field ht Type Reset Description
15:0 CH0_RCOUNT R/W 0000 0000 Channel 0 Reference Count Conversion Interval Time
1000 0000 0x0000-0x00FF: Reserved
0x0100-0xFFFF: Conversion Time (tC0) =
(CH0_RCOUNTˣ16)/fREF0
7 6 5 4 3 2 1 0
CH1_RCOUNT
7 6 5 4 3 2 1 0
CH2_RCOUNT
7 6 5 4 3 2 1 0
CH3_RCOUNT
//ci
(CH3_RCOUNTˣ16)/f REF3
s :
9.6.14
http(FDC21112 / FDC2114 only)
Address 0x0C, OFFSET_CH0
7 6 5 4 3 2 1 0
CH0_OFFSET
7 6 5 4 3 2 1 0
CH1_OFFSET
7 6 5 4 3 2 1 0
CH2_OFFSET
i r tt.ta
CH3_OFFSET
:// c
t p s
Table 27. Address 0x0F, OFFSET_CH3 Field Descriptions
Bit Field ht Type Reset Description
15:0 CH3_OFFSET R/W 0000 0000 Channel 3 Conversion Offset. fOFFSET_3 =
0000 0000 (CH3_OFFSET/216)*fREF3
7 6 5 4 3 2 1 0
CH0_SETTLECOUNT
7 6 5 4 3 2 1 0
CH1_SETTLECOUNT
a o .co
(tS1)= (CH1_SETTLECOUNTˣ16) ÷ fREF1
o b
9.6.20 Address 0x12, SETTLECOUNT_CH2 (FDC2114,
r tt . ta FDC2214 only)
//ci 0x12, SETTLECOUNT_CH2
Figure 37. :Address
s
15 14 h13ttp 12 11 10 9 8
CH2_SETTLECOUNT
7 6 5 4 3 2 1 0
CH2_SETTLECOUNT
7 6 5 4 3 2 1 0
CH3_SETTLECOUNT
7 6 5 4 3 2 1 0
CH0_FREF_DIVIDER
tt.t
00
ao Channel 0 Sensor frequency select
c i r for differential sensor configuration:
s://
b01: divide by 1. Choose for sensor frequencies between
0.01MHz and 8.75MHz
13:12 CH0_FIN_SEL
http R/W b10: divide by 2. Choose for sensor frequencies between 5MHz
and 10MHz
for single-ended sensor configuration:
b10: divide by 2. Choose for sensor frequencies between
0.01MHz and 10MHz
11:10 RESERVED R/W 00 Reserved. Set to b00.
00 0000 Channel 0 Reference Divider Sets the divider for Channel 0
0000 reference. Use this to scale the maximum conversion frequency.
9:0 CH0_FREF_DIVIDER R/W b00’0000’0000: Reserved. Do not use.
CH0_FREF_DIVIDER≥b00’0000’0001: fREF0 =
fCLK/CH0_FREF_DIVIDER
7 6 5 4 3 2 1 0
CH1_FREF_DIVIDER
7 6 5 4 3 2 1 0
CH2_FREF_DIVIDER
cirt
for differential sensor configuration:
7 6 5 4 3 2 1 0
CH3_FREF_DIVIDER
7 6 5 4 3 2 1 0
RESERVED DRDY RESERVED CH0_UNREA CH1_ CH2_ CH3_
DCONV UNREADCONV UNREADCONV UNREADCONV
T tt.t
RESERVED WD_ RESERVED
ERR2OUT
/ c i r T
7 6 5
p s :/ 4 3 2 1 0
RESERVED
ht t
WD_ERR2INT RESERVED DRDY_2INT
7 6 5 4 3 2 1 0
aoMode Enable
FDC2214 only)
13 SLEEP_MODE_EN R/W 1
o b
Sleep
a Enter or exit low power Sleep Mode.
cirtt.t b0: Device is active.
p s :// b1: Device is in Sleep Mode.
12
11
RESERVED
SENSOR_ACTIVATE_SEL h tt R/W
R/W
0
1
Reserved. Set to b1.
Sensor Activation Mode Selection.
Set the mode for sensor initialization.
b0: Full Current Activation Mode – the FDC will drive maximum
sensor current for a shorter sensor activation time.
b1: Low Power Activation Mode – the FDC uses the value
programmed in DRIVE_CURRENT_CHx during sensor
activation to minimize power consumption.
10 RESERVED R/W 0 Reserved. Set to b1.
9 REF_CLK_SRC R/W 0 Select Reference Frequency Source
b0: Use Internal oscillator as reference frequency
b1: Reference frequency is provided from CLKIN pin.
8 RESERVED R/W 0 Reserved. Set to b0.
7 INTB_DIS R/W 0 INTB Disable
b0: INTB pin will be asserted when status register updates.
b1: INTB pin will not be asserted when status register updates
6 HIGH_CURRENT_DRV R/W 0 High Current Sensor Drive
b0: The FDC will drive all channels with normal sensor current
(1.5mA max).
b1: The FDC will drive channel 0 with current >1.5mA.
This mode is not supported if AUTOSCAN_EN = b1 (multi-
channel mode)
5:0 RESERVED R/W 00 0001 Reserved Set to b00’0001
7 6 5 4 3 2 1 0
RESERVED DEGLITCH
t.ta
frequency.
c i r t b001: 1MHz
://
b100: 3.3MHz
tt p s b101: 10MHz
b111: 33MHz
h
9.6.30 Address 0x1C, RESET_DEV
7 6 5 4 3 2 1 0
RESERVED
7 6 5 4 3 2 1 0
RESERVED
a o b 00111: 0.044mA
rtt.t
01000: 0.052mA
ci
01001: 0.060mA
7 6 5 4 3 2 1 0
RESERVED
7 6 5 4 3 2 1 0
RESERVED
tt. t a + conversion time of Channel 2 sensor clock. Set such that 1.2V
p s : 00000: 0.016mA
h tt 00001: 0.018mA
00010: 0.021mA
...
11111: 1.571mA
10:0 RESERVED – 000 0000 Reserved
0000
7 6 5 4 3 2 1 0
RESERVED
7 6 5 4 3 2 1 0
MANUFACTURER_ID
http
7:0 DEVICE_ID R 0011 0000 Device ID
0101 0100 0x3054 (FDC2112, FDC2114 only)
0x3055 (FDC2212, FDC2214 only)
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
://ci
6.5 MHz oscillation frequency. In the single-ended configuration in Figure 54, a conductive plate is connected
tt p s
IN0A. Together with a target object, the conductive plate forms a variable capacitor.
h
Target object
Sensor plate
FDC211x / FDC221x
IN0A
L C
18 µH 33 pF
IN0B
In the differential sensor configuration in Figure 55, one conductive plate is connected to IN0A, and a second
conductive plate is connected to IN0B. Together, they form a variable capacitor. When using an single-ended
sensor configuration, set CHx_FIN_SEL to b10 (divide by 2).
Target object
IN0A
L C
18 µH 33 pF
IN0B
The single-ended configuration allows higher sensing range than the differential configuration for a given total
sensor plate area. In applications in which high sensitivity at close proximity is desired, the differential
configuration performs better than the single-ended configuration.
10.1.2 Shield
in order to minimize interference from external objects, some applications require an additional plate which acts
as a shield. The shield can either be:
• actively driven shield: The shield is a buffered signal of the INxA pin. The signal is buffered by an external
amplifier with a gain of 1.
CLKIN VDD
40 MHz 0.1 µF 1 µF
Int. Osc. GND
IN0A
LEVEL
SENSOR
Resonant
IN0B circuit driver
m / SD
INT B
GPIO
ENVIRONMENT AL L C
c o GPIO MCU
ao.
SENSOR
3.3 V
Cap
Sensor 0
a o b Core GND
rtt. t
ci ADDR
s://
IN1A
2
Resonant 2 SDA IC
IC
http
LIQUID IN1B circuit driver peripheral
L C SCL
SENSOR
Cap
Sensor 1
IN2A
Resonant
L C IN2B circuit driver
Cap
Sensor 2
IN3A
Resonant
IN3B circuit driver
4.7
4.65
4.6
4.55
4.5
Level (pF)
4.45
4.4
4.35
m /
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4.3
4.25
b a o
4.2
a o
rtt.t
4.15
4.1
10
://
15 ci 20 25 30 35 40
sensor frequency. When the sensor capacitance is added, the frequency will decrease.
Using a system master clock of 40 MHz applied to the CLKIN pin allows flexibility for setting the internal
clock frequencies. The sensor coils are connected to channel 0 (IN0A and IN0B pins), channel 1 (IN1A and
IN1B pins), and channel 2 (IN2A and IN2B pins).
After powering on the FDC, it will be in Sleep Mode. Program the registers as follows (example sets registers
for channel 0 only; channel 1 and channel 2 registers can use equivalent configuration):
1. Set the dividers for channel 0.
(a) Because the sensor is in an single-ended configuration, the sensor frequency select register should be
set to 2, which means setting field CH0_FIN_SELto b10.
(b) The design constraint for fREF0 is > 4 × fSENSOR. To satisfy this constraint, fREF0 must be greater than 20.6
MHz, so the reference divider should be set to 1. This is done by setting the CH0_FREF_DIVIDER field
to 0x01.
(c) The combined value for Chan. 0 divider register (0x14) is 0x2001.
2. Sensor drive current: to ensure that the oscillation amplitude is between 1.2V and 1.8V, measure the
oscillation amplitude on an oscilloscope and adjust the IDRIVE value, or use the integrated FDC GUI feature
to determine the optimal setting. In this case the IDRIVE value should be set to 15 (decimal), which results in
an oscillation amplitude of 1.68 V(pk). The INIT_DRIVE current field should be set to 0x00. The combined
value for the DRIVE_CURRENT_CH0 register (addr 0x1E) is 0x7C00.
3. Program the settling time for Channel 0 (see Multi-Channel and Single-Channel Operation).
(a) CHx_SETTLECOUNT > Vpk × fREFx × C × π 2 / (32 × IDRIVEX) → 7.5, rounded up to 8. To provide margin
to account for system tolerances, a higher value of 10 is chosen.
(b) Register 0x10 should be programmed to a minimum of 10.
(c) The settle time is: (10 x 16)/40,000,000 = 4 µs
(d) The value for Chan. 0 SETTLECOUNT register (0x10) is 0x000A.
4. The channel switching delay is ~1μs for fREF = 40 MHz (see Multi-Channel and Single-Channel Operation)
5. Set the conversion time by the programming the reference count for Channel 0. The budget for the
conversion time is : 1/N * (TSAMPLE – settling time – channel switching delay) = 1/3 (10,000 – 4 – 1) = 3.33
ms
(a) To determine the conversion time register value, use the following equation and solve for CH0_RCOUNT:
Conversion Time (t C0)= (CH0_RCOUNTˣ16)/fREF0.
(b) This results in CH0_RCOUNT having a value of 8329 decimal (rounded down). Note that this yields an
ENOB > 13 bits.
175.0
150.0
125.0
Ls (µH)
100.0
75.0
50.0
25.0
0.0
m /
.co
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
b a o
Frequency (MHz)
a o
Figure 58. Example Coil Inductance vs. Frequency
ci rtt.t
p s ://
The example inductor in Figure 58, has a SRF at 6.38 MHz; therefore the inductor should not be operated above
0.8×6.38 MHz, or 5.1 MHz.
h tt
25 0.14
20
0.12
m /
a o
0.1
.co
Capacitance (pF)
Capacitance (pF)
15
a o b 0.08
10
//c i rtt.t 0.06
0.02
0 0
0 2 4 6 8 10 12 14 16 18 20 20 22 24 26 28 30 32 34 36 38 40
Target Distance (mm) with 20.9 x 13.9 mm Sensor D028
Target Distance (mm) with 20.9 x 13.9 mm Sensor D029
Figure 59. FDC2212 / FDC2214: Capacitance vs. Target Figure 60. FDC2112 / FDC2114: Capacitance vs. Target
Distance (0 to 20mm) Distance (20 to 40mm)
0.035 10
4.08 ksps
9
0.03 610 sps
38 sps
Measurement Precision (mm)
8
0.025 7
Capacitance (pF)
6
0.02
5
0.015
4
0.01 3
2
0.005
1
0 0
40 42 44 46 48 50 52 54 56 58 60 0 20 40 60 80 100
Target Distance (mm) with 20.9 x 13.9 mm Sensor D030
Target Distance (mm) with 20.9 x 13.9 mm Sensor D032
Figure 61. FDC2212 / FDC2214: Capacitance vs. Target Figure 62. Measurement precision in Distance vs. Target
Distance (40 to 60mm) Distance (0 to 60mm)
Greater current savings can be realized by use of shutdown mode during inactive periods. In shutdown mode,
device configuration is not retained, and so the device must be configured for each sample. For this example,
configuring each sample takes approximately 1.2 ms (13 registers * 92.5 µs per register). The total active time is
20.6 ms. The average current is 20 ms * 3.6 mA active current + 980 ms * 2 µA of shutdown current, which is
approximately 75 µA of average supply current.
12 Layout
m/
ao .co
a o b
ci rtt.t
p s ://
h tt
m/
ao .co
a o b
ci rtt.t
p s ://
h tt
m/
ao .co
a o b
ci rtt.t
p s ://
h tt
m/
ao .co
a o b
ci rtt.t
p s ://
h tt
13 器件和文档支持
13.1 器件支持
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 相关链接
m /
o
表 48 列出了快速访问链接。范围包括技术文档、支持与社区资源、工具和软件,以及样片或购买的快速访问。
b a o.c
a
表 48. 相关链接
. t o
t
器件 产品文件夹 样片与购买
: / / cirt 技术文档 工具与软件 支持与社区
FDC2212 请单击此处
t t p s请单击此处
请单击此处 请单击此处 请单击此处 请单击此处
FDC2214
FDC2112
请单击此处
请单击此处
h 请单击此处 请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
请单击此处
FDC2114 请单击此处 请单击此处 请单击此处 请单击此处 请单击此处
13.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本,请查阅左侧的导航栏。
www.ti.com 26-Jun-2016
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan
m /
Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2)
o .co(6) (3) (4/5)
FDC2112DNTR ACTIVE WSON DNT 12 4500
ba
Green (RoHS
a o CU SN Level-1-260C-UNLIM -40 to 125 FDC2112
.t
& no Sb/Br)
t (RoHS
tGreen
FDC2112DNTT ACTIVE WSON DNT 12
:
250
/ / cir CU SN Level-1-260C-UNLIM -40 to 125 FDC2112
s & no Sb/Br)
FDC2112QDNTRQ1 ACTIVE WSON DNT
htt12p 4500 Green (RoHS
& no Sb/Br)
CU SN Level-3-260C-168 HR -40 to 125 FDC2112
Q1
FDC2112QDNTTQ1 ACTIVE WSON DNT 12 250 Green (RoHS CU SN Level-3-260C-168 HR -40 to 125 FDC2112
& no Sb/Br) Q1
FDC2114QRGHRQ1 ACTIVE WQFN RGH 16 4500 Green (RoHS CU SN Level-3-260C-168 HR -40 to 125 FC2114Q
& no Sb/Br)
FDC2114QRGHTQ1 ACTIVE WQFN RGH 16 250 Green (RoHS CU SN Level-3-260C-168 HR -40 to 125 FC2114Q
& no Sb/Br)
FDC2114RGHR ACTIVE WQFN RGH 16 4500 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 FDC2114
& no Sb/Br)
FDC2114RGHT ACTIVE WQFN RGH 16 250 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 FDC2114
& no Sb/Br)
FDC2212DNTR ACTIVE WSON DNT 12 4500 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 FDC2212
& no Sb/Br)
FDC2212DNTT ACTIVE WSON DNT 12 250 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 FDC2212
& no Sb/Br)
FDC2212QDNTRQ1 ACTIVE WSON DNT 12 4500 Green (RoHS CU SN Level-3-260C-168 HR -40 to 125 FDC2212
& no Sb/Br) Q1
FDC2212QDNTTQ1 ACTIVE WSON DNT 12 250 Green (RoHS CU SN Level-3-260C-168 HR -40 to 125 FDC2212
& no Sb/Br) Q1
FDC2214QRGHRQ1 ACTIVE WQFN RGH 16 4500 Green (RoHS CU SN Level-3-260C-168 HR -40 to 125 FC2214Q
& no Sb/Br)
FDC2214QRGHTQ1 ACTIVE WQFN RGH 16 250 Green (RoHS CU SN Level-3-260C-168 HR -40 to 125 FC2214Q
& no Sb/Br)
FDC2214RGHR ACTIVE WQFN RGH 16 4500 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 FDC2214
& no Sb/Br)
FDC2214RGHT ACTIVE WQFN RGH 16 250 Green (RoHS CU SN Level-1-260C-UNLIM -40 to 125 FDC2214
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 26-Jun-2016
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
m /
.co
OBSOLETE: TI has discontinued the production of the device.
ba o
(2)
a o
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
.t
information and additional product content details.
cir tt
TBD: The Pb-Free/Green conversion plan has not been defined.
s : / /
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
http
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Sep-2016
m /
a o .co
a o b
cirtt.t
p s ://
h tt
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Sep-2016
m /
a o .co
a o b
ci rtt.t
p s ://
h tt
Pack Materials-Page 2
PACKAGE OUTLINE
RGH0016A SCALE3 .00 0
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
B 4.1 A
3.9
0.5
0.3
m /
PIN 1 INDEX AREA
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4.1
3.9 0.2
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tt p s OPTIONAL TERMINAL
h TYPICAL
DIM A
OPT 1 OPT 1
(0.1) (0.2)
C
0.8 MAX
SEATING PLANE
0.05
0.00 0.08
4X 17 SYMM
1.5
1
12
16X 0.3
0.2
0.1 C A B
PIN 1 ID 16 13 0.05
SYMM
(OPTIONAL)
16X 0.5
0.3
4214978/B 01/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RGH0016A WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
( 2.6)
SYMM
16 13
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16X (0.6)
ci
(R0.05)
s://
1 TYP
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12
(1)
9
4
12X (0.5)
( 0.2) TYP
VIA
5 8
(1)
(3.8)
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RGH0016A WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.15)
m /
(0.675) TYP
16
a
13
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16X (0.6)
1
h tt
(0.675)
12 TYP
16X (0.25)
SYMM
(3.8)
12X (0.5)
9
4
EXPOSED METAL
TYP
5 8
(R0.05) SYMM
TYP
(3.8)
EXPOSED PAD 17
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4214978/B 01/2017
NOTES: (continued)
6.Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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MECHANICAL DATA
DNT0012B WSON - 0.8mm max
height
SON (PLASTIC SMALL OUTLINE - NO LEAD)
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h tt
SDA12B (Rev A)
4214928/A 03/2013
NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is designed to be soldered to a thermal pad on the board for thermal and mechanical performance.
For more information, refer to QFN/SON PCB application note in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
m/
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