IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 9, NO.

2, MAY 1996 215

An Efficient Method for Determining

Threshold Voltage, Series Resistance and
Effective Geometry of MOS Transistors
Peter R. Karlsson and Kjell 0. Jeppson, Senior Member, ZEEE

Abstract- An accurate and robust method of extracting the (after Terada and Muta [5], and Chern et al. [ 6 ] ) and the
threshold voltage, the series resistance and the effective geometry CMP method (after Ciofi, Maccucci and Pellegrini [7]), which
of MOS transistors is presented. The method is based on efficient methods are also discussed by Ng and Brews [3]. McAndrew
nonlinear optimization using an iterative linear regression proce-
dure which usually converges in less than four rounds. Thereby and Layman [SI developed a nonlinear optimization procedure
extracted parameters are obtained from analytical expressions and claimed a significantly more accurate and robust method
for the solutions to a linear system of equations whereby time- after careful comparisons with the other methods mentioned
consuming numerical differentiationsare avoided. MOSFET pa- above.
rameters are explicitely identified as parameters of an underlying In this paper we will evaluate a new method for determining
widely used device model that is a good approximation for
operation in the linear region. The method is particularly suitable the threshold voltage, the series resistance and the effective
for process characterizationand can be used on as few as twelve geometries of MOS transistors [9] and emphasize its potential
data points (three data points from each of four different size for becoming a standard method for rapid and accurate process
transistors). By connecting external resistors in series with the control and technology characterization. The proposed method
transistors, we show that the extracted values of the parameters is simple and robust and uses nonlinear optimization by means
are independent of the series resistance.
of iterative least square fitting procedures to determine triplets
of parameters rather than pairs of parameters.
I. INTRODUCTION

T HE threshold voltage, the series resistance, and the ef-

fective geometry of an MOS transistor are important
parameters in process monitoring as well as in device modeling
11. THE TRANSISTOR
MODEL
The method is based on a simple, widely used transistor
model. Measurements are taken in the region where the
for integrated circuit design. Many methods of extracting these model is valid and used to determine the model parameters.
parameters have been discussed in the literature over the Since the model is based on physical principles, the model
years. Standard methods have evolved including the peak- parameters can be regarded as physical parameters. The most
gm method [l] for determining the threshold voltage V, commonly used model for MOS transistors biased in the linear
and the current gain ,O, the ,O vs. W and the 1/p vs. L region is based on the gradual channel approximation and on
methods for determining the channel narrowing AW and the assumption that the mobility, although depending on the
channel shortening AL and the Suciu and Johnston method transverse electric field, is constant along the channel. The
[2] for determining the source/drain series resistance Rs. MOSFET model, valid in the linear region, can be written,
The strengths and weaknesses of these methods have been
discussed in an excellent review paper by Ng and Brews [3].
For instance, they show how the peak-g, method introduces
errors in A L if the transconductance peak occurs at different
values of V& - VT, or if there is a source/drain series
where V, is the threshold voltage, ,O the transistor gain and
resistance in the transistor. This points out the importance
6' the mobility reduction factor due to the transverse electric
of knowing the series resistance when determining other
field. VhS and VASdenote the internal gate-source and drain-
transistor model parameters since it affects the values extracted source voltages, respectively. Initially, ,O and I9 are regarded
for several of them [4]. Other ways of determining the series
as substrate-bias-independent parameters for each transistor
resistance and channel shortening include the TMC method geometry, while VT will be assumed to depend on the substrate
bias. (The case that p and 6' also depend on the substrate bias
Manuscript received August 21, 1995; revised December 5, 1995. This
work was supported in part by the Swedish National Board for Technical and will be discussed later.)
Industrial Development (NUTEK). By introducing the observables a, b, and c (after Hamer [lo])
K. 0. Jeppson is with the Department of Solid-State Electronics, Chalmers as defined by
University of Technology, S-412 96 Goteborg, Sweden.
P. R. Karlsson is with Bofors Missiles, Chalmers Teknikpark, S-412 88
Goteborg, Sweden.
Publisher Item Identifier S 0894-6507(96)03261-7.

0894-6507/96$05.00 0 1996 IEEE

216 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 9, NO. 2, MAY 1996

(the maximum channel conductance) In three subsequent steps linear regression of Eo on L,, AEo
on L, - AL, and A E on Eo yields AL, R s and 0.
(3) The second method is the CMP method (after Ciofi, Mac-
cucci and Pellegrini [7]) which was the first method for process
characterization to determine VT consistent with /3 and 0, even
(the average threshold voltage at mid-channel, sometimes
referred to as vnt [ll]), and
if the V&/2-term in (1) was unnecessarily dropped in this
process. Although not explicitely stated in the paper and not
very CPU efficient in its implementation, the CMP method
(4) introduced a nonlinear fit to the data. Assuming VT known a
linear regression of 1/(VGs -VT) on l / I D s was used to obtain
where VDSis the external drain-source voltage (VDS= VAS + +
,B from the slope and H = 19 2PRs from the intercept. This
2 R , l ~ s )the
, model can be written as a rational function in procedure was repeated for different assumed values of VT
the observables until a minimum was found. The error function they used for
optimization can very roughly be approximated by
(5)

where x = VGS- AV, and y = VAS - AVT (VGS is the

+
external gate-source voltage (VGS= VAS R , l ~ s ) )AV, . is
a small correction term to account for the threshold voltage
shift caused by the internal substrate bias due to the voltage
drop across the source resistance). For measurements deep in
the linear region, i.e., VGS- VT >> VDS, y = VGS- &IDS -
AV, = VGSis a justified approximation (Rs is the series
source/drain resistance). Under these circumstances ( 5 ) can be
rewritten
where a' and c' are redefined according to
I PR s
=0+2P
(7)
and
Finally, the transistor gain is related to the effective geom-
etry of the transistor by
p = k'
w, - AW (9)
L, - AL
where k' is the intrinsic transistor gain, W, the mask channel
width, L, the mask channel length and where AW and AL
are the channel narrowing and channel shortening, respec-
tively. This model assumes that AW and AL are process
induced parameters constant for all transistor geometries.
EXTRACTION
111. PARAMETER
A. Existing Methods
Before we proceed by describing the new extraction algo-
rithm it might for comparison be appropriate to briefly review
three existing methods of interest. The first is the the combined
peak-g, and SJ method (after Suciu and Johnston [2]) which
uses the peak-g, method [l] to determine VT and linear
regression of E = (VGS- VT)VDS/IDS on VGS- VT to
determine slope A E = 0 / p + 2Rs and intercept Eo = l/p.
which is the sum of squares of the differences between model
and experiment for each of the N measurements weighted by
~ H .for each device.
I z s . This method results in V T ,and
Linear regression of 1/P on L , results in AL while linear
+
regression of H = 0 2PRs on P results in Rs and 0.
The third method is the multi-step optimization procedure
developed by McAndrew and Layman using a general-purpose
nonlinear optimizer to determine VT,0, Rs and A L without
the approximations leading to (6). They also used a linear
relationship between VT and VSBobtained from the peak-g,
method to compensate for the internal body-effect. They used
the sum of the squares of the relative differences between
model and measurements for the optimization procedure.
B. The New Extraction Algorithm
The new extraction algorithm has been designed to extract
the model parameters in consistency with the model and to
overcome the computational inefficiencies of the CMP method
and the nonlinear optimization procedure of McAndrew and
Layman.
'In short, the method operates on one set of measurement
data obtained from a number of transistors of different geome-
tries and the subsequent calculations can be divided into three
steps. First, the three observables a', b, and c' are calculated
for each transistor and from b the individual threshold voltages
are extracted. Second, from the same observables the mobility
reduction factor due to the transverse electric field and the se-
ries resistance are calculated for each set of transistors having
equal channel widths but different channel lengths. Finally, the
transistor gains are derived from the observables and used to
extract the intrinsic transistor gain, the channel shortening and
the channel narrowing for a number of transistors of different
channel lengths and widths. These three steps are described in
more detail in the following subsections.
Step 1) Single Device Parameter Extraction: In our meth-
od a nonlinear optimization procedure based on iterative linear
regression is used to obtain a', b, and c' [9]. The method is
both accurate and computationally simple and uses y = VGS
as its only approximation, which is valid for measurements
deep in the linear region, i.e., VGS - VT >> VDS.
KARLSSON AND JEPPSON: AN EFFICIENT METHOD FOR DETERMINING THRESHOLD VOLTAGE
The sum of squares of all differences between the measure-
ments and the model, (6), can be written
N r
where N ( > 3 ) is the number of data points. Equation (11) can
also be expressed as
For a rational function the unknown observables occur
nonlinearly in the normal equations which makes them difficult
to solve for. Hamming [12] suggested an iterative procedure
to get around these difficulties by assuming the value of
c’ in the denominator to be known. We use c’ = 0 if no
good initial approximation is known for c’. The unknown
observables now appear linearly in the normal equations and
can be solved for. The value obtained for c’ can then be used in
the denominator in the next round of extraction. Usually the
extracted values converge in less than four rounds, making
the procedure computationally efficient. It is also possible to
use a preestimate value for c’ in the denominator for direct
extraction of the unknown observables if one is willing to
accept a nonstandard error function for the least squares fitting.
Alternatively, the sum of the squared relative differences,
2 voltage shift AV- due to the body effect, i.e.,
[IDS% - a ’ s v ; ~ ~ ]
&=E a=1 I&%
(13)
can be minimized following a similar procedure which in-
cludes replacing [y - c’I2 in the denominator of (12) by
I&%[y - c’I2. Besides being more computationally efficient
than the CMP method, the proposed method has the important
advantage of offering freedom of choice when it comes to
selecting the error function, while the CMP method restrains
the user to a useful but nonstandard error function.
To obtain accurate values of the extracted parameters it is
very important that all data points are in the correct region of
operation, in this case deep in the linear region. We therefore
use a small drain-source voltage (VDS = 50 mV) to obtain a
constant transverse field along the channel, and a gate-source
voltage such that VGS - V- >> VDSto guarantee that all data
points are well within the linear region. A procedure has been
developed by which data measured for gate voltages within
0.3 V of the threshold voltage are filtered out.
Step 2) Series Resistance Extraction: In the first step the
threshold voltage for each individual transistor was calcu-
lated from the observable b. In the second step the mobility
reduction factor and the series resistance are obtained by
linear regression’ of l / ( b - c’ - vDS/2) = 0 2PRs on +
a’/(b - e’ - vDS/2) = 0.This step is identical to the CMP
method in that it effectively plots the equivalent mobility
reduction factor against the transistor gain for a number of
transistors having the same series resistance but different
‘Altematively, linear regression of l / a ‘ = O/p + 2Rs on ( b - c’ -
V~s/2)/a‘= 1/p as in the SJ-method [2].
211
gains (i.e., having equal channel widths but different channel
lengths).
Step 3) Effective Geometiy Extraction: Finally, the effec-
tive geometries are determined from the transistor gains of a
number of transistors of different geometries using the model
in (9). This equation, being a rational function of the same
type as (3,means that k’,AW, and A L can be determined
using the same iterative least square fitting method as used in
step 1. This method opens the opportunity of determining one
value of AL common for all channel widths while in previous
methods the value of A L is determined for each channel width.
Step 4 ) Iterative Improvements: Once the series resistance
is known, the internal voltages are also known and the first two
steps of the extraction procedure can be repeated using the
calculated internal voltages instead of the external voltages.
From the new 0’ vs. P relationship a correction term to the
series resistance can be obtained together with a new value of
8. This procedure is then repeated until only negligible correc-
tion terms are obtained for the series resistance. However, with
parameter extraction based on measurements well in the linear
region (VGS - V - >> V D Sonly ) negligible improvements are
expected for each parameter.
It is also possible to increase the accuracy of the extraction
procedure by accounting for the body effect of each device.
This can be done by repeating the single device parameter
extraction step for a second substrate bias using the same
approximation as McAndrew and Layman for the threshold
AI+ = D v IDSRs (14)
where D v = aV,/aV& and V- is the threshold voltage at
the substrate bias VSB of interest.. Again, with measurements
performed deep in the linear region (VGS - VT >> V D S )a
small body effect (V& - VT >> AV-) is not expected to alter
the values of the extracted parameter significantly.
Similarly, it is possible to handle the influence of the
substrate bias on the mobility and the mobility reduction factor
for each device. If, by repeating the single device parameter
extraction step at a second substrate bias, we find that the
internal substrate bias IDSRScauses a shift AD and/or A@of
the transistor gain and mobility reduction factor, respectively,
the values of x and y for each measurement should be modified
according to
and
Ab’
y = VAS - AV- - -(VAS - VT) (16)
e
and the parameters reextracted using the values extracted in
the previous round for P, 0, and V - to calculate x and y.
I v . MEASUREMENT
SYSTEM AND
EXPERIMENTAL
RESULTS
To evaluate the accuracy and robustness of the new method
several tests were performed using a semiconductor parameter
analyzer (HP 4145A) for the measurements. A test chip
218 EEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 9, NO. 2, MAY 1996

TABLE I 0.35 I I /

N - AND ?)-CHANNEL DEVICE MODELPAFMVIETERS EXTRACTED IN FOUR W=2.4p 3.2pm 4.8pm

DIFFERENT WAYS THEDIRECTEXTRACTION COLUMNS I N D I C A E THAT A
NONITERATIVE EXTRACTION PROCEDURE WAS USED (USING C' = 0 IN 0.30
THE DENOMINATOR OF (12)), WHILE ? ANONLINEAR
N O ITHE Z IMI T PO
COLUMNS INDICATE THATA FOUR-ROLIND ITERATIVE EXTRACTION
PROCEDURE WAS USED FORTHE TOTALERRORCOLUMN THE TOTAL 0.25
ERROROF (11) WAS USED FOR OPTIMIZATION WHILE FOR THE
RELATIVE ERROR COLUMN THE RELATIVE EFXOROF (13) WAS USED
0.20
method
n-channel 0.15
VT [VI

P rllAnn1 0.10
e' [VI]

total error
0.05
relative emr 53

0 0.5 1.o

Gain [mA/V2]
Fig. 1. The effective mobility reduction factor plotted versus the gain with
the channel width as a parameter for n-channel devices. The series resistances
are proportional to the slopes of these plots.

containing n- and p-channel transistors of different geometric

sizes was designed and fabricated in a 1 pm CMOS process
-E
500

available through Norchip. Lightly-doped drain (LDD) transis- 400

tors of four different channel widths (2.4, 3.2, 4.8, and 30 pm)
and eight different channel lengths (1, 1.5, 2, 3, 4, 6, 10, and
30 pm) were available to cover the design space. To obtain
equal series resistances for all devices of the same channel
width the designs of the source and drain areas were identical.
In the first step the proposed method is used to extract the
observables a', b, and c' for each transistor size. From these
observables the individual values of VT,,B, and 6" = 6' 2PR.9
are extracted for each transistor size. The results of such a
single device parameter extraction for the minimum sized n-
and p-channel devices are shown in Table I. This table shows
that the extracted parameter values slightly depend on the
extraction method used.
The robustness of the single-device extraction step was
tested by use of external resistors in series with the source
and drain. 6 ' was the only parameter found to depend on the
series resistance while constant values were extracted for VT
and ,B [4]. This is in contrast to the peak-g, method which
has been shown to yield a value for V - that depends on Rs
U 11.
In the second step the series resistance is determined using
8' vs. P-plots as previously described. An example of such
a plot showing very good linearity is given in Fig. 1 for a
number of n-channel devices having series resistances in the
range of 35 to 500 0. In our example we used eight devices of
different channel lengths for each of the four channel widths,
but as a minimum number only two different channel lengths
are required.
Again, the robustness of the proposed extraction algorithm
was checked by connecting external resistors in series with
2
+
0 50 100 150 200 250
External Resistance [Ohm]
Fig. 2. Internal series resistance versus external series resistance extracted
for five different external resistors.
the transistors. As shown in Fig. 2, constant values of the
internal series resistance were obtained for each channel width
independent of the external resistors. Minor fluctuations were
observed which are probably due to measurement noise. Sim-
ilar results were obtained when using the minimum number of
only two devices of different lengths for each channel width
instead of using all eight devices with different lengths.
The results of the effective geometry processing is shown
in Fig. 3 in forms of traditional P vs. W,- and 1/P vs.
L,-plots. However, contrary to the traditional method where
each straight line is fitted individually to measurements, in
our method all lines (from both figures) are simultaneously
 -

KARLSSON AND JEPPSON: AN EFFICIENT METHOD FOR DETERMINING THRESHOLD VOLTAGE 219

4.5 L

4.0 .-g
lE 1.0 1; -
A
Y
. A
Aw A

3.5 m -
C
'5
0.8 -
f
3.0
E 2.5 2
U
U s 0.6 -
2.0 a
.-K
3l 1.5

1.o

0.5

0
0 5 10 15 20 25 30 0 50 100 150 200 250
Channel Width [pm] External Resistance [Ohms]
(a)
Fig. 4. Channel shortening and channel narrowing versus extemal series
resistance extracted for five different external resistors.
300
I4O m
7 250
E
cu'
> 200
Y

.-ac e [V-~I
(Wfi1.440.8) vT [VI 1"21 Rs [a1
150
-
(3
Model values 0.800 0.1300 0.05 300
8 Round 1 0.800 0.1305 0.049985 300.25
2 100 Round 2 0.800 0.1300 0.049999 300.00
.-
Q
0

&! 50
0 The accuracy of the extraction procedure has been investi-
0 5 10 15 20 25 30
Channel Length [pm]
(b)
Fig. 3. (a) The gain versus the channel width, and (b) the reciprocal gain
versus the channel length for n-channel transistors. The insert plots are
enlargements of the intercept with the z-axis.
fitted to measurements, yielding one single value of A W and
one single value of AL. This is consistent with an underlying
model which assumes the same channel shortening A L for
all channel widths and the same channel narrowing A W due
to oxide encroachment for all channel lengths. For the n-
channel devices of the 1 pm CMOS process manufactured by
AMS and delivered through Norchip, we obtained a channel
narrowing A W = 1.0 pm and a channel shortening AL =
0.4 pm.
Since the existence of series resistances has been shown to
lead to an underestimation of A L when ,B is determined from
the peak-g, method [3], we wanted to verify that the values
extracted for the channel shortening and channel narrowing
using our method are not influenced by the series resistance.
The extraction procedure was therefore repeated using external
resistors connected in series with the transistors. The results
are shown in Fig. 4 which confirms that neither AL nor A W
was affected by the series resistance.
gated and the results compared to those obtained after iterative
improvement. During this experiment we used synthetic data
generated from the MOSFET model to avoid problems with
measurement noise and model inaccuracies. Four transistors
with different channel lengths and but equal channel widths
were simulated. Different values were assumed for the thresh-
old voltage of each channel length. The results obtained for
one of the transistor sizes are compiled in Table 11.
The values extracted for the model parameters are within
0.5% of the model values already after the first round. In the
second round, the value obtained from the first round for the
series resistance was used to calculate the internal voltages.
New values of VT,p, and 13' were then extracted for each
device and linear regression of 0' on ,6 was used to extract
a correction term A R s to the series resistance and a new
value of .'6 In the second round, the substrate bias dependence
of the threshold voltage (and other parameters) could also be
accounted for.
We have also investigated the sensitivity to noise in mea-
surement data since this is an important characteristic of any
extraction method. This aspect of parameter extraction has
been extensively studied by McAndrew and Layman who
compared several well-known extraction methods. For our
220 E E E TRANSACTIONS ON SEMICONDUCTORMANUFACTURING, VOL. 9, NO. 2, MAY 1996

study synthetic data, for devices of the same geometries as -7 ,

the test chip devices, were degraded through multiplication by . 1W=2.4vm

1 + NLN(O,1) where N L is the noise level and N(0,l) is a
normal distribution of mean zero and unit standard deviation.
For each transistor 1000 data sets were generated at a 1% noise
level, and the extraction procedure was run on each ,of the
1000 data sets. The mean value and standard deviation were
then computed for each extracted parameter. Very small mean
shifts were obtained (less than 0.05%). The standard deviation
and its dependence on the number of data points used for
extraction and on the voltages for which they were measured
were studied extensively and the results will be discussed in
detail elsewhere. For the threshold voltage a standard deviation 0 -1 -2 -3 -4 -5
of less than 1% was obtained while for 19, which was the Gate-Source Voltage [VI
parameter most sensitive to noise, a standard deviation of
about 6% was obtained at the 1% noise level. These results are
compatible with those obtained by McAndrew and Layman.
Finally, a comparison between measured data and model
playback is shown in Fig. 5 for one device width (W, = -1.2

2.4 pm). For the model playback, individual values of VT s

Y

c
c
was used for each device, while one set of values common for
P
5 -0.8
all transistors in the group was used for IC', 8, AW, and AL.
0
._
S
s
V. DISCUSSION -0.4

In a way the proposed extraction method can be regarded

as a more efficient implementation of the CMP method since 0
it follows a similar sequential procedure. The single-step 0 1 -2 -3 -4 -5

extraction of parameter triplets, rather than repeated extrac-
tion of parameter pairs (repeated until the best combination
of parameter values is found), provides an efficient means
for rapid device characterization. However, the method also
provides certain advantages over the CMP method: first, it
does not ignore the V&/2 term when determining V, thereby
significantly improving the accuracy of VT as discussed by
McAndrew and Layman [8], second, it offers the user complete
freedom when it comes to choosing the error function for the
least square fitting procedure (instead of restraining him to
a nonstandard error function), third, it provides a means of
determining one single value of A L common to all channel
widths consistently with the transistor model (while still re-
taining the option of determining AL for each channel width
for the purpose of checking the validity of the model).
Further, the method extends the direct extraction method
proposed by Hamer [lo], which was limited to three data
points for extracting the three observables, so it becomes useful
for any number of data points. The technique is based on linear
regression which means that it is simple and efficient and
that the observables are obtained from analytical expressions
for the solutions of a system of linear equations. In addition,
by use of an iterative linear regression procedure it turns the
direct procedure into a nonlinear optimization method suitable
for any number of data points. Again, it is a simple and
efficient technique converging in less than four rounds where
the observables are obtained without use of numerical (or
analytical) differentiations.
Our method uses the same transistor geometry model as
Hamer to simultanously determine one value A L for the chan-
Gate-Source Voltage [VI
Fig. 5. Measured data (squares) and model playback with data simulated
using extracted parameter values (solid lines) for eight p-channel devices of
different channel lengths but identical channel width.
ne1 shortening and one value A W for the channel narrowing.
This is in contrast to the conventional methods where A L is
determined from 1/p vs. Lm-plots for one transistor width
at a time, which means that different values of A L can be
obtained for each channel width. Similarly, when A W is
determined from the ,D vs. Wm-plots, different values of A W
can be obtained for each channel length. However, the channel
narrowing due to the combined effects of oxide encroachment
and over-etching of the gate is a parameter not discussed
by CMP or by McAndrew and Layman [8]. Their method
was, however, recently most elegantly extended to include
the channel narrowing 1131. By use of external resistors
we have also shown that the values extracted for AW and
AL are not influenced by the series resistance as is the case
when using the peak-g, method to determine the transistor
gain ,D.
In addition, the iterative improvement scheme in our method
offers the possibility of acGounting for first-order variations
of VT with IDsRs-a phenomenon which previously was
only taken into account by the optimization technique used
by McAndrew and Layman. Thereby the same accuracy can
be obtained at a much lower computational cost. Also, in our
method D v is obtained from values of VT determined con-
sistently with the underlying MOSFET model at two different
values of V&, while McAndrew and Layman obtained Dv
KARLSSON AND JEPPSON AN EFFICIENT METHOD FOR DETERMINING THRESHOLD VOLTAGE 221

from VT determined at two different values of VBSby using the that simply minimizes the differences between measurements
peak-g, method. Of course, the value of the iterative improve- and model by circuit designers.
ment can be discussed since the parameter values extracted
typically vary by less than 1% if the dependence of VT on VI. CONCLUSION
IDS& is neglected. On the other hand this is a phenomenon A new and simple method for accurate extraction of thresh-
that may become important for devices with heavily doped old voltages, series resistances, and effective transistor geome-
substrates and small feature sizes, as discussed by McAndrew tries of MOS transistors has been presented and validated for
and Layman. The iterative improvement scheme also offers accuracy and robustness. The new method explicitely inter-
the possibility of accounting for first-order variations of both prets MOS device parameters as parameters of an underlying
p and 6’ with I D & y - a phenomenon which McAndrew and MOSFET model. Parameters are extracted consistent with this
Layman discussed but did not account for. Again, note that model using a rapidly converging iterative linear regression
the extracted parameters depend on VBS and different values procedure to fit measured data to the nonlinear model. The
are obtained for each specified value of VBS. method does not require any numerical differentiations and is
Most of the model shortcomings are discussed in great computationally efficient.
detail by McAndrew and Layman and need not be repeated The accuracy and robustness of the method have also been
here. As in their work (and most other works), the mobility verified. By accuracy we mean that the method 1) should
degradation parameter is assumed to be independent of channel return the correct model parameters when parameter extraction
length. In our model this assumption is used to separate the is performed from synthetic data generated by the model,
influence of the series resistance from the influence of the and, 2 ) should result in small errors when measurements
mobility degradation. An interesting observation we made, are compared to model playbacks using extracted parameter
and that we have not seen discussed elsewhere, is that we values. By robustness we mean that the method 1) should
found the mobility degradation parameter to depend on the have both a small shift of mean parameter value with noise
channel width. This observation can be explained as being level and a small standard deviation at any given noise level,
the result of the gate-voltage dependence of the channel and, 2) should return parameter values that are insensitive to
width-when the gate voltage overdrive increases, the channel the series resistance (and the initial value of e’).
electrically widens into the oxide encroachment region [13]. If In our opinion, the method is well suited for automated
this phenomenon is not specifically included in the underlying measurement systems and that its simplicity and robustness,
MOSFET model, but the channel width (and hence ,f3) is together with its potential for rapid process monitoring, should
assumed to be independent of the gate voltage, it will instead make it attractive for industrial use.
result in a width dependent contribution to 6’ [9].
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[2] P. I. Suciu and R. L. Johnston, “Experimental derivation of the source
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222 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 9, NO. 2, MAY 1996

Peter R.Karlsson received the M.S. degree in elec- Kjell 0. Jeppson (S’68-M76-SM’83) received
trical engineenng in 1988 and the Ph.D. degree in the M.S. degree in electrical engineering in 1970
solid-state electronics in 1994, both from Chalmers and the Ph.D in solid-state electronics in 1977,
University of Technology, Goteborg, Sweden. both from Chalmers University of Technology,
Between 1988 and 1994, he was a member of the Goteborg, Sweden.
research and teaching staff, Department of Solid- He has been a lecturer (associate professor) in
State Electronics, Chalmers University. His main the Department of Solid-state Electronics, Chalmers
research interest involved transistor modeling and University, since 1978. He spent the academic year
parameter extraction. Since 1995, he has been with 1973-74 with Rockwell International, Anaheim,
Bofors Missiles, Goteborg, Sweden, where he works CA, and the fall semester 1985 at the Southampton
with microsensor and microelectronics systems. University Microelectronics Centre, UK. His main
research interest is focused on MOS devices and CMOS VLSI design. He has
published several papers on MNOS nonvolatile memories, MOS transistor
modeling and parameter extraction, CMOS gate delay, and hierarchical
DRC of VLSI circuits. He has also authored a textbook (in Swedish) on
semiconductor devices.