ASIC design flow

A typical design workflow for standard cell based ASIC is described below (some steps were simplified for the sake of clarity). The workflow for full custom ASIC contains these stages as well as some other stages connected with new cells design. 1. The ASIC design process begins from writing a functional description containing detailed requirements for the chip. We can start design on basis of a functional description prepared by the customer. Alternatively, we can create the functional description document based on the customer's demands expressed in any form. At no time will we share your information with anyone without your explicit permission. 2. Based on your demands, our team estimates the amount of resources needed and produces a Statement of Work. After reaching an agreement, the actual work is started. 3. The first step is similar to FPGA design. The following tasks are run in parallel: o o o Writing a synthesizable RTL (register transfer level) description (either on Verilog or VHDL) of the device. Writing a behavioral model, which is used to verify that the design meets its requirements. Writing a verification plan and a corresponding verification environment which describes and implements the method of proving the design correctness.

4. The RTL description is verified against the behavioral model by out dedicated Validation and Verification Department. This approach reduces the probability of the design error since no RTL designer tests his own code.

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