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PM5D PM5DRH C
PM5D PM5DRH C
PM5D/PM5D-RH
SERVICE MANUAL
OPTION(オプション)
CONTENTS(目次)
SPECIFICATIONS(総合仕様)................................... 4 SAVING FILE to a MEMORY CARD
CONNECTOR PIN ASSIGNMENTS (メモリーカードに任意のファイルをセーブする). 249/251
(コネクターピンアサイン表)................................ 13 INITIALIZING THE PM5D’s INTERNAL MEMORY
PANEL LAYOUT(パネルレイアウト)................... 15 (PM5Dの内蔵メモリーを初期化する)................ 253
DIMENSIONS(寸法図)......................................... 29 WARNING MESSAGES
CIRCUIT BOARD LAYOUT (ワーニングメッセージ).............................. 254/256
(ユニットレイアウト)........................................... 30 ERROR MESSAGES(エラーメッセージ)... 255/257
DISASSEMBLY PROCEDURE(分解手順)............ 36 MIDI IMPLEMENTATION CHART
LSI PIN DESCRIPTION (LSI端子機能表).............. 71 (MIDIインプリメンテーションチャート)............ 258
IC BLOCK DIAGRAM(ICブロック図)................... 84 MIDI DATA FORMAT
CIRCUIT BOARDS(シート基板図) ........................ 92 (MIDIデータフォーマット).................................. 259
INSPECTIONS(検査).................................. 191/203 PARTS LIST
SERVICE CHECK PROGRAM BLOCK DIAGRAM (ブロックダイアグラム)
(サービス検査プログラム)......................... 215/225 OVERALL CONNECTOR CIRCUIT DIAGRAM
PANEL TEST(パネルテスト)..................... 235/240 (総コネクター接続回路図)
UPDATING THE PROGRAM CIRCUIT DIAGRAM (回路図)
(プログラムのアップデート)..................... 245/246 PW800W SERVICE MANUAL
INSTALLING an OPTION CARD PSL120 PARTS LIST
(オプションカードの取り付け).................. 247/248
PA 011740
PM5D: 200408-オープンプライス
PM5D-RH: 200408-オープンプライス HAMAMATSU, JAPAN 1
PW800W: 200408-オープンプライス Copyright (c) Yamaha Corporation. All rights reserved. PDF-K75301 ’04.09
PSL120: 200408-オープンプライス
PM5D/PM5D-RH
IMPORTANT NOTICE
This manual has been provided for the use of authorized Yamaha Retailers and their service personnel. It has been assumed that basic
service procedures inherent to the industry, and more specifically Yamaha Products, are already known and understood by the use rs,
and have therefore not been restated.
WARNING : Failure to follow appropriate service and safety procedures when servicing this product may result in personal injury,
destruction of expensive components and failure of the product to perform as specified. For these reasons, we advise
all Yamaha product owners that all service required should be performed by an authorized Yamaha Retailer or the
appointed service representative.
IMPORTANT : This presentation or sale of this manual to any individual or firm does not constitute authorization certification,
recognition of any applicable technical capabilities, or establish a principal-agent relationship of any form.
The data provided is belived to be accurate and applicable to the unit(s) indicated on the cover. The research engineering, and service
departments of Yamaha are continually striving to improve Yamaha products. Modifications are, therefore, inevitable and changes in
specification are subject to change without notice or obligation to retrofit. Should any discrepancy appear to exist, please contact the
distributor’s Service Division.
WARNING : Static discharges can destroy expensive components. Discharge any static electricity your body may have accumulated
by grounding yourself to the ground bus in the unit (heavy gauge black wires connect to this bus.)
IMPORTANT : Turn the unit OFF during disassembly and parts replacement. Recheck all work before you apply power to the unit.
DO NOT PLACE SOLDER, ELECTRICAL/ELECTRONIC OR PLASTIC COMPONENTS IN YOUR MOUTH FOR ANY REASON WHAT SO EVER!
Avoid prolonged, unprotected contact between solder and your skin! When soldering, do not inhale solder fumes or expose eyes to solder/
flux vapor!
If you come in contact with solder or components located inside the enclosure of this product, wash your hands before handling food.
リチウム電池の取り扱い
<注意>
リチウム電池を誤って交換すると爆発する危険があります。交換する場合は、サービスマニュアルで指定された部品を使用して
ください。
WARNING
Components having special characteristics are marked and must be replaced with parts having specification equal to those
originally installed.
印の商品は、安全を維持するために重要な部品です。交換する場合は、安全のために必ず指定の部品をご使用ください。
2
PM5D/PM5D-RH
PM5D-RH
PM5D
PW800W
PW800W
PW800W
PSL120
3
PM5D/PM5D-RH
SPECIFICATIONS(総合仕様)
1. General Specifications(一般仕様)
Internal: 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz
Sampling Frequency External: 44.1 kHz (-10%) to 48 kHz (+6%)
88.2 kHz (-10%) to 96 kHz (+6%)
PM5D: Less than 2.3 ms INPUT to STEREO A,B (@Fs = 48 kHz)
Less than 1.15 ms INPUT to STEREO A,B (@Fs = 96 kHz)
Signal Delay
PM5D-RH: Less than 2.5 ms INPUT to STEREO A,B (@Fs = 48 kHz)
Less than 1.25 ms INPUT to STEREO A,B (@Fs = 96 kHz)
Fader 100mm motorized x38
Fader Resolution +10 to -138, -∞ dB (1024 steps/100 mm)
PM5D: 84 dB INPUT1-48 to Each Output
Maximum Voltage Gain
PM5D-RH: 86 dB INPUT1-48 to Each Output
Crosstalk (@1kHz) -80 dB Adjacent Input Channels (INPUT1-48)
Dimensions 1551 x 950 x 283 mm (W x D x H)
PM5D: 98 kg
Net Weight
PM5D-RH: 97 kg
PM5D: 480W, DC 24V, 20A (Use PW800W Only)
Power Requirements
PM5D-RH: 528W, DC 24V, 22A (Use PW800W Only)
Operation free-air Temperature Range +10˚C to + 35˚C
Storage Temperature Range -20˚C to + 60˚C
Owner's Manual
Gooseneck Lamps x 3
Included Accessories Power Supply PW800W Connection Cable
Studio Manager CD-ROM
Studio Manager Installation Guide
mini YGDAI cards
Optional Accessories Power Supply PW800W
Power Supply Link Cable PSL120
4
PM5D/PM5D-RH
Analog Input (2TR IN ANALOG1,2 [L,R]) STEREO A,B [L,R] MIX1-24 MATRIX1-8
Connector XLR-3-31 Type (Balanced) x4 Connector XLR-3-32 Type (Balanced)
Gain Switch +24 dBu (default) / +18 dBu DA Converter 24bit linear, 128 times oversampling
AD Converter 24bit linear, 128 times oversampling
Oscillator
Level 0 to –96dB (1dB step)
On/Off Dedicated switch and software control
MODE: Sine Wave 1ch, Sine Wave 2ch, Pink
Waveform Noise, Burst Noise
Sine Waveform: 100Hz, 1kHz, 10kHz
Routing MIX1-24, MA TRIX1-8, STEREO A,B (L,R)
5
PM5D/PM5D-RH
2. Inputs/Outputs Characteristics(入出力特性)
*1. Sensitivity is the lowest level that will produce an output of +4 dBu (1.23 V) or the nominal output level when the unit is set to maximum gain. (All faders
and level controls are maximum position.)
*2. XLR-3-31 type connectors are balanced. (1=GND, 2=HOT, 3=COLD)
*3. Phone jacks are balanced. (Tip=HOT, Ring=COLD, Sleeve=GND )
*4. There are switches inside the body to preset the maximum input level.
6
PM5D/PM5D-RH
MONITOR OUT +24 dB (default) +4 dBu (1.23 V) +24 dBu (12.28 V) XLR-3-32 Type
150Ω 600Ω Lines
[L,R,C] +18 dB –2 dBu (616 mV) +18 dBu (6.16 V) (Balanced)*1
+24 dB (default) +4 dBu (1.23 V) +24 dBu (12.28 V) XLR-3-32 Type
CUE OUT [L,R] 150Ω 600Ω Lines
+18 dB –2 dBu (616 mV) +18 dBu (6.16 V) (Balanced)*1
+24 dB (default) +4 dBu (1.23 V) +24 dBu (12.28 V) XLR-3-32 Type
MATRIX OUT 1-8 150Ω 600Ω Lines
+18 dB –2 dBu (616 mV) +18 dBu (6.16 V) (Balanced)*1
+24 dB (default) +4 dBu (1.23 V) +24 dBu (12.28 V) XLR-3-32 Type
MIX OUT 1-24 150Ω 600Ω Lines
+18 dB –2 dBu (616 mV) +18 dBu (6.16 V) (Balanced)*1
Phone Jack (TRS)
INSERT OUT 1-48 150Ω 10kΩ Lines — +4 dBu (1.23 V) +24 dBu (12.28 V)
(Balanced)*2 *5
8Ω Phones 75 mW *6 150 mW Stereo Phone Jack
PHONES (x 2) 15Ω —
40Ω Phones 65 mW *6 150 mW (TRS) (Unbalanced)*3
7
PM5D/PM5D-RH
8
PM5D/PM5D-RH
9
PM5D/PM5D-RH
3. Electrical Characteristics(電気特性)
All faders are nominal when measured. Output impedance of signal generator: 150ohms
Frequency Respones Fs= 44.1 kHz or 48 kHz @20 Hz–20 kHz, referenced to the nominal output level @1 kHz
Fs= 88.2 kHz or 96 kHz @20 Hz–40 kHz, referenced to the nominal output level @1 kHz
Input Output RL Conditions Min. Typ. Max. Unit
STEREO A,B
MIX OUT
MATRIX OUT 600Ω PM5D: GAIN: Max., PAD: Off –1.5
INPUT 1-48
MONITOR OUT PM5D-RH: GAIN: Max.
0.0 0.5 dB
CUE OUT
PHONES 8Ω –3.0
STEREO A,B
2TR IN ANALOG 1,2 600Ω –1.5
MONITOR OUT
10
PM5D/PM5D-RH
Dynamic Range
Input Output RL Conditions Min. Typ. Max. Unit
PM5D: AD + DA, GAIN: Min.,
Fs= 44.1/48 kHz 108
INPUT 1-48 STEREO A,B PAD: On
PM5D-RH: AD + DA, GAIN: Min. Fs= 88.2/96 kHz 106
STEREO A,B
600Ω dB
MIX OUT
— MATRIX OUT DA Converter 110
MONITOR OUT
CUE OUT
* Dynamic range is measured with a 6 dB/octave filter @12.7 kHz; equivalent to a 20 kHz filter with infinite dB/octave attenuation.
Sampling Frequency
Parameter Conditions Min. Typ. Max. Unit
Normal Rate 39.69 50.88
External Clock Frequency Range
Double Rate 79.39 101.76
Word Clock : Int 44.1kHz 44.1
kHz
Word Clock : Int 48kHz 48
Frequency
Word Clock : Int 88.2kHz 88.2
Word Clock : Int 96kHz 96
Word Clock : Int 44.1kHz
Word Clock : Int 48kHz
Internal Clock Accuracy 50 ppm
Word Clock : Int 88.2kHz
Word Clock : Int 96kHz
Word Clock : Int 44.1kHz
Word Clock : Int 48kHz
Jitter 5 ns
Word Clock : Int 88.2kHz
Word Clock : Int 96kHz
11
PM5D/PM5D-RH
4. Other Functions(その他機能)
68 37 36 35
1 5 5 1
6 9 9 6
HA REMOTE RS422 REMOTE
Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name
1 GND 6 RX+ 1 GND 6 GND
2 RX– 7 RTS 2 RX– 7 RX+
3 TX– 8 CTS 3 TX+ 8 TX–
4 TX+ 9 GND 4 GND 9 GND
5 N.C 5 N.C
13
PM5D/PM5D-RH
13 3 2 1 4 3 2 1
9 8 7 6 5
15 14 13 12 11 10
20 19 18 17 16
23 22 21
25 16 15 14
14
PM5D/PM5D-RH
PANEL LAYOUT(パネルレイアウト)
1. Top Panel(トップパネル)
q w
y i
r t u
15
PM5D/PM5D-RH
o
!4 !5 !6
!7
!8
!0
!8
!1 !3 !2
@0 !9
o Display (ディスプレイ)
!0 FADER MODE section: ( P.24) (フェーダーモードセクション)
!1 DCA strip section: ( P.24) (DCA ストリップセクション)
!2 ST IN / FX RTN (Stereo in / Effect return) (ステレオイン / エフェクトリターンチャンネルスト
channel strip section: ( P.25) リップセクション)
!3 STEREO strip section: ( P.25) (ステレオストリップセクション)
!4 SCENE MEMORY section: ( P.26) (シーンメモリーセクション)
!5 CUE / MONITOR section: ( P.26) (キュー / モニターセクション)
!6 OSCILLATOR / TALKBACK section: ( P.27)(オシレーター / トークバックセクション)
!7 DISPLAY ACCESS section: ( P.27) (ディスプレイアクセスセクション)
!8 USER DEFINED KEYS section: ( P.27) (ユーザー定義キーセクション)
!9 Data entry section: ( P.27) (データエントリーセクション)
@0 ASSIGN MODE section: ( P.28) (アサインモードセクション)
16
PM5D/PM5D-RH
2. Rear Panel(リアパネル)
e q
r y
(PM5D-RH model)
w
(PM5D model)
!2 !1 o !0 !3
u i C R L R L
R L R L
8 7 6 5 4 3 2 1
17
PM5D/PM5D-RH
!4 @2 @1 @0 @4 @5
R L R L
OUT IN 2 1 2 1
IN
75 3 3
ON OFF
THRU OUT IN
!7 !5 !8 !6 !9 @3 @6 @7
3. Front Panel(フロントパネル)
6 5 6 5
4 3 4 3
2 1 2 1
q w e r
@8 @9
q MEMORY CARD slot (メモリーカードスロット)
@8 Fan grille(ファン通風孔) w MOUSE connector (マウス端子)
@9 SLOT 1-4(スロット 1 ∼ 4) e KRYBOARD connector (キーボード端子)
r PHONES (Headphone) jack(ヘッドフォン端子)
18
PM5D/PM5D-RH
q q
w w e
y
e
i
r u
t
q [+48V ON/OFF] switch ([+48V ON/OFF] スイッチ) q [+48V ON/OFF] LED ( [+48V ON/OFF] LED)
w [PAD] switch ([PAD] スイッチ) w [PEAK]/[SIGNAL] LED ( [PEAK] / [SIGNAL] LED)
e [GAIN] knob ([GAIN] ノブ) e [LAMP DIMMER] knob ( [LAMP DIMMER] ノブ)
r [PEAK]/[SIGNAL] LED ([PEAK] / [SIGNAL] LED)
t [INSERT ON/OFF] switch ([INSERT ON/OFF] スイッチ)
y ST IN [GAIN] knob (ST IN [GAIN] ノブ)
u ST IN [PEAK]/ST IN [SIGNAL] LED(ST IN [PEAK] /ST IN [SIGNAL] LED)
i [LAMP DIMMER] knob ([LAMP DIMMER] ノブ)
q [CH 1-24] [CH 25-48] keys ([CH 1-24] /[CH 25-48] キー)
w [PRE] key ([PRE] キー)
e ENCODER [ON] key (ENCODER [ON] キー)
w r Encoder (エンコーダー)
e t [SEL] key ([SEL] キー)
y Name indicator (ネームインジケーター)
r u CH [ON] key (CH [ON] キー)
t !0 q i Fader (フェーダー)
!1 o
y !2 [CUE] key ([CUE] キー)
!0 [TO ST] LED ([TO ST] LED)
!1 [COMP] LED ([COMP] LED)
u !3 !2 [GATE] LED ([GATE] LED)
!3 Meter LEDs (メーター LED)
!4 DCA assign LEDs (DCA アサイン LED)
!5 MUTE assign LEDs (MUTE アサイン LED)
!4 !6 [RCL SAFE] / [MUTE SAFE] LEDs([RCL SAFE] / [MUTE SAFE] LED)
!5
!6
i
o
19
PM5D/PM5D-RH
w e r t
20
PM5D/PM5D-RH
w q
e
q DCA group LEDs (DCA グループ LED)
r
w MATRIX [PAIR] LED (MATRIX [PAIR] LED)
e MATRIX [ON] key (MATRIX [ON] キー)
t r MATRIX encoder (MATRIX エンコーダー)
t MATRIX [CUE] key (MATRIX [CUE] キー)
y y MATRIX [SEL] key (MATRIX [SEL]キー)
e q
w e
r t y
r u
q w
21
PM5D/PM5D-RH
e q
e
w w
e
w
q r q
t
y
u
w i
o !0
22
PM5D/PM5D-RH
o !0
4-6-9 EQUALIZER(イコライザー)
rt y
q
w
e
u
i
23
PM5D/PM5D-RH
CH 1 -24 MIX
ST IN/ MATRIX
PEAK
/ST IN HOLD
w er t
1 L 1R 2L 2R 3L 3R 4L 4R
1 2 3 4 5 6 7 8 L R L R L R
OVER OVER OVER OVER
-3 -3 -3 -3
-6 -6 -6 -6
-9 -9 -9 -9
-12 -12 -12 -12
-15 -15 -15 -15
-18 -18 -18 -18
-24 -24 -24 -24
-30 -30 -30 -30
-40 -40 -40 -40
-50 -50 -50 -50
-60 -60 -60 -60
ST IN / / MATRIX STEREO A STEREO B CUE
y u
q w w
r
t
4-10 ST IN/FX RTN channel strip section 4-11 STEREO strip section
(ST IN/FX RTN チャンネルストリップ) (STEREO ストリップセクション)
e
w q
q e
r w r
!0
t
!1
y !2 t
u !3
!4
!5
!6
i y
o u
q [ST IN 1-4]-[FX RTN 1-4] key ([ST IN 1-4] / [FZ RTN 1-4]キー) q [TO MATRIX] LED ([TO MATRIX] LED)
w [PRE] key ([PRE] キー) w [COMP] LED ([COMP] LED)
e ENCODER [ON] key (ENCODER [ON] キー) e STEREO A/B [SEL] key(STEREO A/B [SEL] キー)
r Encoder (エンコーダー) r STEREO [MONO] key (STEREO [MONO] キー)
t [SEL] key ([SEL] キー) t STEREO [ON] key (STEREO [ON] キー)
y Name indicator (ネームインジケーター) y STEREO fader (STEREO フェーダー)
u CH [ON] key (CH [ON]キー) u STEREO [CUE] key (STEREO [CUE] キー)
i Fader (フェーダー)
o [CUE] key ([CUE]キー)
!0 [TO ST] LED ([TO ST] LED)
!1 [COMP] LED ([COMP] LED)
!2 [GATE] LED ([GATE] LED)
!3 Meter LEDs (メーター LED)
!4 DCA assign LEDs (DCA アサイン LED)
!5 MUTE assign LEDs (MUTE アサイン LED)
!6 [RCL SAFE] / [MUTE SAFE] LEDs([RCL SAFE] / [MUTE SAFE] LED)
25
PM5D/PM5D-RH
q y
u
i
q w
e y
q r
r u
w t t i
e o !1
!0 !2
26
PM5D/PM5D-RH
w
q
e w
q Global functions(グローバルファンクション)
w Output functions(アウトプット系ファンクション)
e Input functions (インプット系ファンクション)
u
q
w
y
e
r
t
27
PM5D/PM5D-RH
28
PM5D/PM5D-RH
DIMENSIONS(寸法図)
PM5D
283
271
260
865
950
1450
1551 Units: mm
(単位)
PM5D-RH
283
271
260
865
950
1450
1551 Units: mm
(単位)
29
PM5D/PM5D-RH
Panel 1 assembly:
(パネル1 Ass'y)
See page 32.
Panel 2 assembly:
(パネル2 Ass'y) Bottom assembly:
See page 33. (ボトム Ass'y)
See page 31.
Panel 1 assembly:
(パネル1 Ass'y)
See page 32.
Panel 2 assembly:
(パネル2 Ass'y) Bottom assembly:
See page 33. (ボトム Ass'y)
See page 31.
30
PM5D/PM5D-RH
DRN
DRL
DA2
JK1
DR
ANI3
JK2
DA3
DA1 #4
(MTRX OUT)
DA1 #1
OPT (MIX1-8OUT) DA1 #2
CN1R (MIX9-16OUT)
∗PM5D-RH only DA1 #3
(PM5D-RHのみ) (MIX17-24
OUT
)
BRG4
DSP
BRG5
MAIN
BRG1
PHN2
31
PM5D/PM5D-RH
<Bottom view>
FDB
BRG2
PN3 #4
PN3 #3
PN3 #2 FDA
PN3 #1
SL
PN2 #2
PN1
PN2 #1
32
PM5D/PM5D-RH
<Bottom view>
TB CUVOL
TBVOL MNVOL
BRG3
PHN1
TPSW
PN8
FDC
SR 1/2
SR 2/2
PN6
PN5
PN4
33
PM5D/PM5D-RH
ANI1 #3
ANI1 #1 ANI1 #5 ANI1 #9
ANI1 #7 ANI1 #11 <Top view>
AD1
ANI1 #12
ANI1 #2 ANI1 #6
ANI1 #10
ANI1 #4 ANI1 #8
<Top view>
LED #2 LED #4
LED #1 LED #3
AD2
LPVOL
<Side view>
ANI2 #1
ANI2 #3
ANI2 #2 ANI2 #4
34
PM5D/PM5D-RH
LD
AD3
STLD
AD3
LPVOL
SW48
35
PM5D/PM5D-RH
■ DISASSEMBLY PROCEDURE(分解手順)
* Install the filament tape and the harness clamp in the ※ フィラメントテープ、 束線止めは、 取り外す前と同じように取
same way as they were before removal. り付けてください。
* When installing the flat cable, use care not to insert it ※ フラットケーブルの表・裏を逆に差し込まないように注意し
with its front and back inverted. て取り付けてください。
* After replacing the FDA/FDB/FDC circuit board or fader ※ FDAシート、 FDBシート、FDCシート又はフェーダーAss’
yを
assembly, be sure to calibrate the faders. (See page 192.) 交換後は、フェーダーのキャリブレーションを実施してくだ
さい。(204 ページ参照)
G. Disassembly Procedure of Rear Top 1/Rear Top 3 Assembly R (PM5D-RH)(リアトップ1/リアトップ3 Ass’y Rの分解)
G-4. AD3 Circuit Board, LD Circuit Board(AD3シート、LDシート) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
36
PM5D/PM5D-RH
[1410] x 3 [1430] x 3
Panel 1 assembly
(パネル1 Ass'y)
Panel 2 assembly
(パネル2 Ass'y)
[1910] x 3 [1930] x 3
Panel 1 assembly
(パネル1 Ass'y)
Panel 2 assembly
(パネル2 Ass'y)
Support JIG 1-L Support JIG 1-R Support JIG 2-L Support JIG 2-R
(サポートJIG 1-L) (サポートJIG 1-R) (サポートJIG 2-L) (サポートJIG 2-R)
● When fixing the Panel 1 Assembly and Panel 2 Assembly both opened
(パネル1 Ass’yとパネル2 Ass’
yを両方共開けて固定する場合)
Support JIG 1-R or support JIG 2-L
Panel 2 assembly (サポートJIG 1-RまたはサポートJIG 2-L)
Panel 1 assembly (パネル2 Ass'y) Panel 2 assembly Panel 1 assembly
(パネル1 Ass'y) (パネル1 Ass'y)
(パネル2 Ass'y)
Fig. 2 (図2)
1 2 3
Fig. 3 (図3)
38
PM5D/PM5D-RH
Fig. 4 (図4)
Fig. 5 (図5)
39
PM5D/PM5D-RH
[1360]
[1390]
Fig. 7 (図7)
40
PM5D/PM5D-RH
[1740B]
[1790]
Cannon connector L Cannon connector R
(キャノンコネクタL) (キャノンコネクタR)
Cannon connector C
(キャノンコネクタC) [1740C]
[1800]
Fig. 8 (図8)
41
PM5D/PM5D-RH
Rear top 2 assembly R Rear top 3 assembly R Rear top 1 assembly R-(B) Rear top 1 assembly R-(A)
(リアトップ2 Ass'y R)(リアトップ3 Ass'y R)(リアトップ1 Ass'y R-(B)) (リアトップ1 Ass'y R-(A))
Fig. 9 (図9)
42
PM5D/PM5D-RH
● PM5D [120A]
Side pad L
(サイドパッドL)
[230]
[125]
[215]
Side pad R
(サイドパッドR)
[310]
[190]
[50A]
[110A]
[50A]
Corner pad L
● PM5D-RH (コーナーパッドL)
[170] [50A]
[50A]
Fig. 14(図14)
44
PM5D/PM5D-RH
[1320B]
[1380] x 9
Shield
(シールド
BRG5)
Rear pad R
(リアパッドR)
[260]
[1380]
[1320A]
[1320B] Rear pad angle R
(リアパッドアングルR)
45
PM5D/PM5D-RH
[1720]
[1700A] [1664] x 8 [350A]
[1700B]
[1720] x 9
Shield
(シールド
BRG5) Rear pad R
(リアパッドR)
[340]
[1720]
[1700A]
[1700B] Rear pad angle R
(リアパッドアングルR)
46
PM5D/PM5D-RH
47
PM5D/PM5D-RH
48
PM5D/PM5D-RH
DSP
[430]
[430]
[1040]
[470] [459] [459]
MAIN
[454] PHN2
[450] [1060]
[1050] PHN2 angle
[2120]
(PHN2アングル)
Heat sink(ヒートシンク)
Heat sink(放熱板)
Fig. 17(図17)
49
PM5D/PM5D-RH
* The lithium battery is not part of the MAIN circuit board. ※ リチウム電池はMAINシートの構成部品ではありません。
When you replace the MAIN circuit board, you should MAINシートを交換する際には、本体のシートからリチウ
remove the lithium battery from the board, and install ム電池を取り外して、新しいシートに取り付けてくださ
in the holder on the new circuit board. い。
* Before replacing the lithium battery be sure to save all ※ リチウム電池の交換を行う前には、 PM5D/PM5D-RH内部
the setting data in PM5D/PM5D-RH into a memory card. の全ての設定データをメモリーカードにセーブ(保存)し
(See page 249.) てください。(251ページ参照)
● PM5D-RH
[970] Heat sink holder(放熱板金具)
[930]
[950]
[930] Heat sink(放熱板)
DSP
[610]
[610]
[1590]
[810] [780] [760]
MAIN
[730] PHN2
[710] [1610]
[1600] PHN2 angle
[2720]
(PHN2アングル)
Heat sink(ヒートシンク)
Heat sink(放熱板)
Fig. 18(図18)
Litihium battery
• Lithium Battery(リチウム電池)
Battery VN103500
VN103600(Battery holder for VN103500)
MAIN
Notice for back-up battery removal Battery
Push the battery as shown in figure,
then the battery will pop up.
Druk de batterij naar beneden zoals
aangeven in de tekening de batterij
springt dan naar voren. Battery holder
MEMORY
CARD
MOUSE KEYBOARD
Fig. 19(図19)
50
PM5D/PM5D-RH
● PM5D
51
PM5D/PM5D-RH
● PM5D
*1 When removing the JK1 circuit board, remove the ANI3 *1 JK1シートを外す時は、先にANI3シートを外します。
circuit board first. *2 JK2シートを外す時は、 先にANI3シートとJK1シートを外
*2 When removing the JK2 circuit board, remove the ANI3 します。
and JK1 circuit boards first. *3 DA3シートを外す時は、先にDA2シートを外します。
*3 When removing the DA3 circuit board, remove the DA2 *4 DA1 (#4)シートを外す時は、先にDA2シートとDA3シート
circuit board first. を外します。
*4 When removing the DA1(#4) circuit board, remove the *5 DA1 (#2)シートを外す時は、
先にDA1 (#1)シートを外しま
DA2 and DA3 circuit boards first. す。
*5 When removing the DA1(#2) circuit board, remove the *6 DA1 (#3)シートを外す時は、先にDA1 (#1)シートとDA1
DA1(#1) circuit board first. (#2)シートを外します。
*6 When removing the DA1(#3) circuit board, remove the *7 先にシールドBRG5を外します。 (11項参照)
DA1(#1) and DA1(#2) circuit boards first.
*7 Remove the shield BRG5 first. (See procedure 11.)
Receptacle assembly
(レセプタクル Ass'y)
PM5D: [390]
PM5D-RH: [560]
PM5D
Fig. 20(図20)
52
PM5D/PM5D-RH
● PM5D-RH
Circuit board and Assembly Ref. No. Screw QTY Fig.
CN1R Circuit Board(CN1Rシート) 665 Bind Head Screw 4.0x8 SP MFZN2Y(VZ538000)(+バインドBタイト) 6 22
OPT Circuit Board(OPTシート) 440 Bind Head Screw 4.0x8 SP MFZN2Y(VZ538000)(+バインド小ネジ) 4 22
400A Pan Head Screw SP 4.0x20 MFZN2BL (VB671600)(+ナベ小ネジ) 4 22
Fan Motor L(ファンモーターL) 390A Fan Guard (ファンガード) 1 22
380A Fan Guide (FANガイド) 2 22
400B Pan Head Screw SP 4.0x20 MFZN2BL (VB671600)(+ナベ小ネジ) 4 22
Fan Motor R(ファンモーターR) 390B Fan Guard (ファンガード) 1 22
380B Fan Guide (FANガイド) 2 22
DRN Circuit Board(DRNシート) 1540A Bonding Tapping Screw-B 3.0x8 MFZN2BL (VN413300)(ボンディングBタイト) 2 22
DRL Circuit Board(DRLシート) 1540B Bonding Tapping Screw-B 3.0x8 MFZN2BL (VN413300)(ボンディングBタイト) 2 22
1260 Bind Head Tapping Screw-B 2.6x8 MFZN2BL (VB096700)(+バインドBタイト) 8 22
ANI3 Circuit Board(ANI3シート)
1270 Bind Head Tapping Screw-B 3.0x6 MFZN2BL (EP600230)(+バインドBタイト) 2 22
1200 Bonding Tapping Screw-B 3.0x8 MFZN2BL (VN413300)(ボンディングBタイト) 6 22
1210 Bind Head Tapping Screw-B 2.6x8 MFZN2BL (VB096700)(+バインドBタイト) 6 22
JK1 Circuit Board *1(JK1シート)
1220 Bonding Screw 3.0x8 MFZN2BL (VP157800)(+ボンディング小ネジ) 3 22
1230 Bind Head Tapping Screw-B 3.0x6 MFZN2BL (EP600230)(+バインドBタイト) 3 22
990 Hex. Locking Screw JFS-2.6S-BIW (VS604900)(6角ロックネジ) 6 22
B Hex. Locking Screw (6角ロックネジ) 2 22
JK2 Circuit Board *2(JK2シート)
1000 Bonding Tapping Screw-B 3.0x8 MFZN2BL (VN413300)(ボンディングBタイト) 2 22
1010 Bind Head Tapping Screw-B 3.0x6 MFZN2BL (EP600230)(+バインドBタイト) 3 22
1420A Bonding Tapping Screw-B 3.0x8 MFZN2BL (VN413300)(ボンディングBタイト) 10 22
DA2 Circuit Board(DA2シート) 2 22
1445A Bind Head Screw 3.0x6 MFZN2BL (EG330360)(+バインド小ネジ)
1420B Bonding Tapping Screw-B 3.0x8 MFZN2BL (VN413300)(ボンディングBタイト) 8 22
1430 DA Mount Angle (DAマウントアングル) 1 22
DA3 Circuit Board *3(DA3シート)
1440A Bind Head Tapping Screw-B 3.0x6 MFZN2BL (EP600230)(+バインドBタイト) 2 22
1445B Bind Head Screw 3.0x6 MFZN2BL (EG330360)(+バインド小ネジ) 2 22
DR Circuit Board(DRシート) 1300 Bonding Tapping Screw-B 3.0x8 MFZN2BL (VN413300)(ボンディングBタイト) 2 22
DA1 (#4) Circuit Board *4 1330A Bonding Tapping Screw-B 3.0x8 MFZN2BL (VN413300)(ボンディングBタイト) 16 22
(MIX OUT)(DA1シート) 1440B Bind Head Tapping Screw-B 3.0x6 MFZN2BL (EP600230)(+バインドBタイト) 2 22
DA1 (#1) Circuit Board 1330B Bonding Tapping Screw-B 3.0x8 MFZN2BL (VN413300)(ボンディングBタイト) 16 22
(MONITOR OUT)(DA1シート) 1345A Bind Head Screw 3.0x6 MFZN2BL (EG330360)(+バインド小ネジ) 2 22
DA1 (#2) Circuit Board *5 1330C Bonding Tapping Screw-B 3.0x8 MFZN2BL (VN413300)(ボンディングBタイト) 16 22
(MONITOR OUT)(DA1シート) 1345B Bind Head Screw 3.0x6 MFZN2BL (EG330360)(+バインド小ネジ) 2 22
DA1 (#3) Circuit Board *6 1330D Bonding Tapping Screw-B 3.0x8 MFZN2BL (VN413300)(ボンディングBタイト) 16 22
(MONITOR OUT)(DA1シート) 1340 Bind Head Tapping Screw-B 3.0x6 MFZN2BL (EP600230)(+バインドBタイト) 2 22
Receptacle Assembly *7 540 Bind Head Tapping Screw-B 3.0x8 MFZN2BL (EP600190)(+バインドBタイト) 4 22
(レセプタクル Ass’ y) 560 Bind Head Tapping Screw-B 4.0x8 MFZN2BL (EG340190)(+バインドBタイト) 1 20
BRG5 Circuit Board *7(BRG5シート) 1070 Bind Head Tapping Screw-B 3.0x6 MFZN2BL (EP600230)(+バインドBタイト) 7 22
*1 When removing the JK1 circuit board, remove the ANI3 *1 JK1シートを外す時は、先にANI3シートを外します。
circuit board first. *2 JK2シートを外す時は、 先にANI3シートとJK1シートを外
*2 When removing the JK2 circuit board, remove the ANI3 します。
and JK1 circuit boards first. *3 DA3シートを外す時は、先にDA2シートを外します。
*3 When removing the DA3 circuit board, remove the DA2 *4 DA1 (#4)シートを外す時は、先にDA2シートとDA3シート
circuit board first. を外します。
*4 When removing the DA1(#4) circuit board, remove the *5 DA1 (#2)シートを外す時は、
先にDA1 (#1)シートを外しま
DA2 and DA3 circuit boards first. す。
*5 When removing the DA1(#2) circuit board, remove the *6 DA1 (#3)シートを外す時は、先にDA1 (#1)シートとDA1
DA1(#1) circuit board first. (#2)シートを外します。
*6 When removing the DA1(#3) circuit board, remove the *7 先にシールドBRG5を外します。 (11項参照)
DA1(#1) and DA1(#2) circuit boards first.
*7 Remove the shield BRG5 first. (See procedure 11.)
53
PM5D/PM5D-RH
● PM5D
[300A] [310A]
Receptacle assembly
(レセプタクル Ass'y)
Fan motor L
(ファンモーターL) [370]
[310B]
JK1
[300B]
[310B]
[290A]
DRN
OPT [680A]
DRL
DA2
[342] ANI3
[730]
[905A]
DR
DA3
[570]
Fan motor R
[905B]
(ファンモーターR)
[582] [290B]
DA1 #4
[582] JK2
BRG5 [900B] [805A]
[805B] DA1 #1
[800] DA1 #2
DA1 #3
[805A]
[900A] [805B]
[890]
[800]
Cannon connector C
(キャノンコネクタC)
Cannon connector R [1010B] x 2 Cannon connector L
(キャノンコネクタR) [670] x 3 [650] x 6 (キャノンコネクタL)
[1010C] x 2 [660] x 2 [1010A] x 2
[790B] x 16 [770] [880A] x 10 [720] x 8 [990B] [990A]
Fig. 21(図21)
54
PM5D/PM5D-RH
● PM5D-RH
[400A]
Fan motor L Receptacle assembly
CN1R [390A] (レセプタクル Ass'y)
[665] (ファンモーターL)
[665] [540]
JK1 [400B]
[380A] [390B]
[400B]
OPT DRN
[1230]
DRL
[440]
DA2
ANI3
[1270]
[1445A]
DR
DA3
[1010]
Fan motor R
[1445B]
[1070] (ファンモーターR)
DA1 #4 [380B]
[1070] JK2
BRG5 [1440B] [1345A]
[1345B]
DA1 #1
[1340] DA1 #2
DA1 #3
[1345A]
[1440A] [1345B]
[1430]
[1340]
Fig. 22(図22)
55
PM5D/PM5D-RH
[390B]
Encoder knobs
(エンコーダーノブ)
[370A]
Encoder knobs
(エンコーダーノブ)
[370B]
Encoder knobs
(エンコーダーノブ)
[420] PN1 [390A]
Switch knobs Encoder knobs
(SWノブ) (エンコーダーノブ)
[380A]
Fader knobs Encoder knob
(フェーダーノブ)
(エンコーダーノブ)
[360]
Encoder knob
(エンコーダーノブ)
SL
PN2 x 2 [380A]
Encoder knob
PN3 x 4 (エンコーダーノブ)
Fig. 23(図23)
56
PM5D/PM5D-RH
24 ch [320A]
[330A]
Fader assembly
(フェーダーAss'y)
[330B]
[330C]
FDB
1 ch
SL
FDA
PN1
PN2 x 2
PN3 x 4
[350B]
Fig. 24(図24)
57
PM5D/PM5D-RH
58
PM5D/PM5D-RH
C1 reinforcement angle 10
[320D] (C1補強アングル10) [320B]
SL
CP1 reinforcement angle 7
CP1 reinforcement angle 5 [320D]
[340A] (CP1補強アングル7)
(CP1補強アングル5)
[330D]
PN2 x 2
[320G]
PN3 x 4 [340B]
[320C]
[320E]
[340A]
[320F]
PN1
[330E]
[30A]
PN3
Switch knobs
(SWノブ)
[40A]
[40A]
[40A]: Bind Head Tapping Screw-B (+バインドBタイト) 3.0x6 MFZN2BL (EP600230)
Fig. 26(図26)
59
PM5D/PM5D-RH
60
PM5D/PM5D-RH
[420] A
Encoder knobs
[505] (エンコーダーノブ)
LCD angle 3 [470] SCINE MEMORY section
(LCDアングル3) Switch knobs Coursor buttons
(SWノブ) (カーソルボタン)
[460], [470]
Switch knobs
(SWノブ)
[400A] [400B]
Fader knobs
(フェーダーノブ) [690A] [690B] [400B]
SR [700B]
2/2
[410]
[700C]
[680B]
[510C]
PN4
TB
A
PN6
SR CUVOL
Coursor buttons [500B] 1/2
(カーソルボタン)
[700A]
MNVOL TBVOL
PN8
1/2 CP2 angle 5
TPSW
(CP2アングル5)
[510B]
Whell knob PN8
(ホイールノブ) 2/2 PHN1
Fig. 27(図27)
61
PM5D/PM5D-RH
[520A] [520B]
FDC
BRG3
N
[520B]
Fader assembly
(フェーダーAss'y)
SR 1/2
800
TPSW
SR 2/2
PN8
2/2
PN8
1/2
PN6
PN4
[500C]
SR [510H]
1/2 [530A]
[510E] PN6
[510E]
[510F]
[530B]
[520C] [530A]
[510D]
TPSW
[520D]
PN5
Washer
(ワッシャー)
Hexagonal nut
(六角ナット)
PN6
PN4 [40C]
[30B] [40B]
[30C] Switch knobs
Switch knobs
Switch knobs (SWノブ)
(SWノブ)
[40B] (SWノブ) [40C]
[40B]: Bind Head Tapping Screw-B 3.0x6 MFZN2BL (EP600230) [40C]: Bind Head Tapping Screw-B 3.0x6 MFZN2BL (EP600230)
(+バインドBタイト) (+バインドBタイト)
Fig. 30(図30) Fig. 31(図31)
64
PM5D/PM5D-RH
C-12-5. Remove the four (4) switch knobs marked [460] and C-12-5. PN6シートから[460]のSWノブ4個と[30C]のSWノ
the six (6) switch knobs marked [30C] from the PN6 ブ6個を外します。 (図27、図31)
circuit board. (Fig. 27, Fig. 31)
65
PM5D/PM5D-RH
LCD(液晶ディスプレイ)
[90B] [90B]
[100]
[90A]
[130] [130] DC-AC INVERTER
[130] [130]
[130]
66 Fig. 32(図32)
PM5D/PM5D-RH
Knobs (small)
(ノブ(ショウ))
ANI1
Push buttons
[30A] (プッシュボタン)
[60A]
[60A]
[70A]
[60B]
Shield 1 (top)
(シールドトップ 1)
ANI1
Shield 1 (bottom)
(シールドボトム 1)
ANI2
[47]
LED
Knobs (upper) [30B]
(ノブ(ウエ)) [80B]
[30B]
[60C]
[60C]
[70B]
[120B] AD2
Shield 2 (top)
(シールドトップ 2) LPVOL
[130A]
Shield 2 (bottom)
(シールドボトム 2)
[90A]
LD
[90A]
[70C]
Shield 1 (top)
(シールドトップ 1RH)
[70C]
AD3
(upper) [50B]
[30C] [50C]
AD3
(lower) [30C]
[30C]
[40E]
[30C]
AD3 [50D]
[40F] [90B]
[40F]
[40F]
FDA: IC26
FDB: IC526
PN1: IC100, 101
SL: IC150, 901
SGH603064F-62F (XV973A00) GATE ARRAY SR: IC901
PIN PIN
NAME I/O FUNCTION NAME I/O FUNCTION
NO. NO.
1 RA1 I 33 D0 O Data bus
2 RB1 I
Encoder input 34 D1 O
3 RA2 I 35 VSS Ground
4 RB2 I 36 D2 O Data bus
5 VSS Ground 37 D3 O
6 RA3 I 38 VSS Ground
7 RB3 I Encoder input 39 D4 O Data bus
8 RA4 I 40 D5 O
9 RB4 I 41 VSS Ground
10 VSS Ground 42 D6 O Data bus
11 RA5 I 43 D7 O
12 RB5 I Encoder input 44 VSS Ground
13 RA6 I 45 NC
Not used
14 RB6 I 46 NC
15 VSS Ground 47 RA9 I
16 RA7 I 48 RB9 I
17 RB7 I Encoder input 49 RA10 I
18 RA8 I 50 RB10 I
19 RB8 I 51 RA11 I
20 A0 I 52 RB11 I Encoder input
21 A1 I Address bus 53 RA12 I
22 A2 I 54 RB12 I
23 VSS Ground 55 RA13 I
24 RDN I Read 56 RB13 I
25 CSN I Chip select 57 RA14 I
26 VDD Power supply +5V 58 VDD Power supply +5V
27 ASN I Address strobe 59 RB14 I
28 A3N I Address bus 60 RA15 I
29 SEL I Bus select 61 RB15 I Encoder input
30 NC 62 RA16 I
31 NC Not used 63 RB16 I
32 NC 64 VSS Ground
71
PM5D/PM5D-RH
72
PM5D/PM5D-RH
73
PM5D/PM5D-RH
74
PM5D/PM5D-RH
MSM82C51A-2GS-KR1 (XV513A00)
USART (Universal Synchronous Asynchronous Receiver Transmitter) MAIN: IC65
PIN PIN
NAME I/O FUNCTION NAME I/O FUNCTION
NO. NO.
1 D2 I/O Data Bus 17 TXRDY O Character data
2 D3 I/O Data Bus 18 SYNDET/BD I/O Character data
3 RXD I Serial Data 19 /CTS I Input terminal for modem interface
4 NC 20 NC
5 GND Ground 21 TXEMPTY O Character data
6 D4 I/O Data Bus 22 TXD O Character data
7 D5 I/O Data Bus 23 CLK I Clock
8 D6 I/O Data Bus 24 RESET I Reset
9 D7 I/O Data Bus 25 /DSR I Input port for modem interface
10 /TXC I Clock 26 /RTS O Output port for modem interface
11 /WR I Write signal 27 /DTR O Output port for modem interface
12 /CS I Device select 28 /RXC I Clock
13 NC 29 NC
14 C//D I Access select signal 30 VCC I Power supply
15 /RD I Read signal 31 D0 I/O Data Bus
16 RXRDY O Character data 32 D1 I/O Data Bus
75
PM5D/PM5D-RH
76
PM5D/PM5D-RH
DSP: ICB01-B14
YSS919B-H (XZ693B00) DSP7 (Digital Signal Processor) AD3: IC902 (PM5D-RH)
PIN PIN
NAME I/O FUNCTION NAME I/O FUNCTION
NO. NO.
1 PLLEN I PLL enable input (0: PLL unuse, 1: PLL use) 105 SIO32 I/O
2 /TEST I Test mode setting (0: TEST, 1: Normal) 106 SIO33 I/O
3 AVss Analog ground 107 SIO34 I/O
4 CPO PLL filter 108 SIO35 I/O
Serial data bus
5 AVdd Power supply (2.5 V) 109 SIO36 I/O
6 Vss Ground 110 SIO37 I/O
7 Vdd Power supply (3.3 V) 111 SIO38 I/O
8 /IC I Initial clear 112 SIO39 I/O
9 /MUTE I Mute control (0: SIO mute, 1: SIO normal in-out) 113 Vdd Power supply (2.5 V)
10 /SSYNC I Serial I/O Sync. signal input 114 Vss Ground
11 MCKS I Serial I/O master clock input (128 x Fs) 115 SIO40 I/O
12 XI I System master clock input (60 MHz or 15 MHz) 116 SIO41 I/O
13 BTYP I Data bus type select (0: 16 bits, 1: 32 bits) 117 SIO42 I/O
14 /CS I Chip select 118 SIO43 I/O
Serial data bus
15 /WR I Write enable input 119 SIO44 I/O
16 /RD I Read enable input 120 SIO45 I/O
17 CA7 I 121 SIO46 I/O
18 CA6 I 122 SIO47 I/O
19 CA5 I 123 Vss Ground
20 CA4 I CPU address bus 124 Vdd Power supply (3.3 V)
21 CA3 I 125 SIO48 I/O
22 CA2 I 126 SIO49 I/O
23 Vss Ground 127 SIO50 I/O
24 Vdd Power supply (3.3 V) 128 SIO51 I/O
Serial data bus
25 CD31/CA1 I/O CPU data bus / CPU address bus 129 SIO52 I/O
26 CD30 I/O 130 SIO53 I/O
27 CD29 I/O 131 SIO54 I/O
28 CD28 I/O 132 SIO55 I/O
29 CD27 I/O CPU data bus 133 Vss Ground
30 CD26 I/O 134 SIO56 I/O
31 CD25 I/O 135 SIO57 I/O
32 CD24 I/O 136 SIO58 I/O
33 Vdd Power supply (2.5 V) 137 SIO59 I/O
Serial data bus
34 Vss Ground 138 SIO60 I/O
35 CD23 I/O 139 SIO61 I/O
36 CD22 I/O 140 SIO62 I/O
37 CD21 I/O 141 SIO63 I/O
38 CD20 I/O 142 Vdd Power supply (2.5 V)
CPU data bus
39 CD19 I/O 143 Vss Ground
40 CD18 I/O 144 Vdd Power supply (3.3 V)
41 CD17 I/O 145 DA00 I/O
42 CD16 I/O 146 DA01 I/O
43 Vss Ground 147 DA02 I/O
44 Vdd Power supply (3.3 V) 148 DA03 I/O
Memory data bus
45 CD15 I/O 149 DA04 I/O
46 CD14 I/O 150 DA05 I/O
47 CD13 I/O 151 DA06 I/O
48 CD12 I/O 152 DA07 I/O
CPU data bus
49 CD11 I/O 153 Vss Ground
50 CD10 I/O 154 DA08 I/O
51 CD09 I/O 155 DA09 I/O
52 CD08 I/O 156 DA10 I/O
53 Vss Ground 157 DA11 I/O
Memory data bus
54 CD07 I/O 158 DA12 I/O
55 CD06 I/O 159 DA13 I/O
56 CD05 I/O 160 DA14 I/O
57 CD04 I/O 161 DA15 I/O
CPU data bus
58 CD03 I/O 162 Vss Ground
59 CD02 I/O 163 Vdd Power supply (3.3 V)
60 CD01 I/O 164 DA16 I/O
61 CD00 I/O 165 DA17 I/O
62 /WAIT O Wait output 166 DA18 I/O
63 Vdd Power supply (2.5 V) 167 DA19 I/O
Memory data bus
64 Vss Ground 168 DA20 I/O
65 Vdd Power supply (3.3 V) 169 DA21 I/O
66 SIO00 I/O 170 DA22 I/O
67 SIO01 I/O 171 DA23 I/O
68 SIO02 I/O 172 Vdd Power supply (2.5 V)
69 SIO03 I/O 173 Vss Ground
Serial data bus
70 SIO04 I/O 174 DA24 I/O
71 SIO05 I/O 175 DA25 I/O
72 SIO06 I/O 176 DA26 I/O
73 SIO07 I/O 177 DA27 I/O
74 178 Memory data bus
Vss Ground DA28 I/O
75 SIO08 I/O 179 DA29 I/O
76 SIO09 I/O 180 DA30 I/O
77 SIO10 I/O 181 DA31 I/O
78 SIO11 I/O 182 Vss Ground
Serial data bus
79 SIO12 I/O 183 Vdd Power supply (3.3 V)
80 SIO13 I/O 184 /WE O Memory write enable signal
81 SIO14 I/O 185 /CAS O Column address strobe
82 SIO15 I/O 186 SDCK O Clock (SDRAM)
83 Vss Ground 187 CKE O CKE (SDRAM)
84 Vdd Power supply (3.3 V) 188 /RAS O Row address strobe
85 SIO16 I/O 189 Vdd Power supply (2.5 V)
86 SIO17 I/O 190 Vss Ground
87 SIO18 I/O 191 BA1 O
88 192 Bank select (SDRAM)
SIO19 I/O BA0 O
Serial data bus
89 SIO20 I/O 193 A12 O
90 SIO21 I/O 194 A11 O
91 SIO22 I/O 195 A10 O Memory address (SDRAM, DRAM)
92 SIO23 I/O 196 A09 O
93 Vdd Power supply (2.5 V) 197 A08 O
94 Vss Ground 198 Vss Ground
95 SIO24 I/O 199 Vdd Power supply (3.3 V)
96 SIO25 I/O 200 A07 O
97 SIO26 I/O 201 A06 O
98 SIO27 I/O 202 A05 O
Serial data bus
99 SIO28 I/O 203 A04 O
100 204 Memory address (SDRAM, DRAM)
SIO29 I/O A03 O
101 SIO30 I/O 205 A02 O
102 SIO31 I/O 206 A01 O
103 Vss Ground 207 A00 O
104 Vdd Power supply (3.3 V) 208 Vss Ground
77
PM5D/PM5D-RH
78
PM5D/PM5D-RH
DSP: ICC01-C11
MBCG61594-130 (X3299A00) ATSC2A AD3: IC921 (PM5D-RH)
PIN PIN
NAME I/O FUNCTION NAME I/O FUNCTION
NO. NO.
1 VDD Power supply +3.3V 73 VDD Power supply +3.3V
2 XTST I LSI test pin 74 PB_H_M4_SEL I Port B audio data input buffer active select
3 VSS Ground 75 PB_O_MUTE I Port B mute
4 WT_X I CPU interface write input 76 VSS Ground
5 RD_X I CPU interface read input 77 PB_SO0_ATO O
6 CS_X I CPU interface chip select input 78 PB_SO1 O
Port B audio data output
7 HS_SEL I Chip active select 79 PB_SO2 O
8 RES_X I System reset input 80 PB_SO3 O
9 VSS Ground 81 VSS Ground
10 ADD[0] I 82 PB_O_H_MODE[0] I
11 ADD[1] I 83 PB_O_H_MODE[1] I Port B audio data output mode select
12 ADD[2] I 84 PB_O_H_MODE[2] I
13 ADD[3] I 85 PC_I_H_MODE[0] I
CPU interface address bus
14 ADD[4] I 86 PC_I_H_MODE[1] I Port C audio data input mode select
15 ADD[5] I 87 PC_I_H_MODE[2] I
16 ADD[6] I 88 PC_H_M4_SEL I Port C audio data input buffer active select
17 ADD[7] I 89 PC_SI0_ATI I Port C audio data input
18 VDD Power supply +3.3V 90 VDD Power supply +3.3V
19 VSS Ground 91 VSS Ground
20 DAT[0] I/O 92 PC_SI1 I
21 DAT[1] I/O 93 PC_SI2 I Port C audio data input
CPU interface data bus
22 DAT[2] I/O 94 PC_SI3 I
23 DAT[3] I/O 95 PC_I_SW_SEL I Port C audio data input sync/wc select
24 VDD Power supply +3.3V 96 PC_SYNC_WC_SI I Port C audio data input sync/wc input
25 VSS Ground 97 PC_FS256_SI I Port C audio data input bit clock input (256fs)
26 DAT[4] I/O 98 VSS Ground
27 DAT[5] I/O 99 PC_FS256_SO I Port C audio data output bit clock input (256fs)
CPU interface data bus
28 DAT[6] I/O 100 PC_SYNC_WC_SO I Port C audio data output sync/wc input
29 DAT[7] I/O 101 PC_O_SW_SEL I Port C audio data output sync/wc select
30 VSS Ground 102 VSS Ground
31 VDD Power supply +3.3V 103 PC_SO0 O
32 PA_I_H_MODE[0] I 104 PC_SO1 O Port C audio data output
33 PA_I_H_MODE[1] I Port A audio data input mode select 105 PC_SO2 O
34 PA_I_H_MODE[2] I 106 PC_SO3 O
35 PA_O_H_MODE[0] I 107 VSS Ground
36 PA_O_H_MODE[1] I Port A audio data output mode select 108 PC_O_MUTE I Port C mute
37 PA_O_H_MODE[2] I 109 PC_O_H_MODE[0] I
38 PA_SI0_ATI I 110 PC_O_H_MODE[1] I Port C audio data output mode select
39 PA_SI1 I Port A audio data input 111 PC_O_H_MODE[2] I
40 PA_SI2 I 112 PC_CLK_ATI I Port C ADAT clock input
41 PA_SI3 I 113 VSS Ground
42 PA_I_SW_SEL I Port A audio data input sync/wc select 114 PD_I_H_MODE[0] I
43 PA_SYNC_WC_SI I Port A audio data input sync/wc input 115 PD_I_H_MODE[1] I Port D audio data input mode select
44 PA_FS256_SI I Port A audio data input bit clock input (256fs) 116 PD_I_H_MODE[2] I
45 VSS Ground 117 VSS Ground
46 PA_FS256_SO I Port A audio data output bit clock input (256fs) 118 PD_H_M4_SEL I Port D audio data input buffer active select
47 PA_SYNC_WC_SO I Port A audio data output sync/wc input 119 PD_SI0 I
48 PA_O_SW_SEL I Port A audio data output sync/wc select 120 PD_SI1 I Port D audio data input
49 VSS Ground 121 PD_SI2 I
50 PA_SO0 O 122 PD_SI3 I
51 PA_SO1 O 123 PD_I_SW_SEL I Port D audio data input sync/wc select
Port A audio data output
52 PA_SO2 O 124 PD_SYNC_WC_SI I Port D audio data input sync/wc input
53 PA_SO3 O 125 PD_FS256_SI I Port D audio data input bit clock input (256fs)
54 VDD Power supply +3.3V 126 VDD Power supply +3.3V
55 VSS Ground 127 VSS Ground
56 PA_CLK_ATI I Port A ADAT clock input 128 PD_FS256_SO I Port D audio data output bit clock input (256fs)
57 PA_H_M4_SEL I Port A audio data input buffer active select 129 PD_SYNC_WC_SO I Port D audio data output sync/wc input
58 PA_O_MUTE I Port A mute 130 PD_O_SW_SEL I Port D audio data output sync/wc select
59 PB_SI0 I 131 VSS Ground
60 PB_SI1 I 132 PD_SO0_ATO O
Port B audio data input
61 PB_SI2 I 133 PD_SO1 O Port D audio data output
62 PB_SI3 I 134 PD_SO2 O
63 PB_I_SW_SEL I Port B audio data input sync/wc select 135 PD_SO3 O
64 PB_SYNC_WC_SI I Port B audio data input sync/wc input 136 VSS Ground
65 PB_FS256_SI I Port B audio data input bit clock input (256fs) 137 PD_O_MUTE I Port D mute
66 VSS Ground 138 VSS Ground
67 PB_FS256_SO I Port B audio data output bit clock input (256fs) 139 PD_O_H_MODE[0] I
68 PB_SYNC_WC_SO I Port B audio data output sync/wc input 140 PD_O_H_MODE[1] I Port D audio data output mode select
69 PB_O_SW_SEL I Port B audio data output sync/wc select 141 PD_O_H_MODE[2] I
70 PB_I_H_MODE[0] I 142 XSM I LSI test pin
71 PB_I_H_MODE[1] I Port B audio data input mode select 143 PA_WC_ATI O Port A ADAT word clock output
72 PB_I_H_MODE[2] I 144 PC_WC_ATI O Port C ADAT word clock output
79
PM5D/PM5D-RH
80
PM5D/PM5D-RH
SL: IC200
S1D13704F00A100 (X3498A00) LCDC (LCD Controller) SR: IC200
PIN PIN
NAME I/O FUNCTION NAME I/O FUNCTION
NO. NO.
1 COREVDD Power supply +3.3V 41 COREVDD Power supply +3.3V
2 /WAIT O Wait signal 42 DRDY O TFT/D-TFD display enable
3 DB15 I/O 43 LCDPWR O LCD power control
4 DB14 I/O 44 TESTEN I Test enable input
5 DB13 I/O 45 CNF4 I
6 DB12 I/O Data bus 46 CNF3 I
7 DB11 I/O 47 CNF2 I Configure the S1D13704
8 DB10 I/O 48 CNF1 I
9 DB9 I/O 49 CNF0 I
10 IOVDD Power supply +3.3V 50 VSS Ground
11 DB8 I/O 51 CLKI I Input clock
12 DB7 I/O 52 IOVDD Power supply +3.3V
13 DB6 I/O 53 AB15 I
14 DB5 I/O 54 AB14 I
15 DB4 I/O Data bus 55 AB13 I
16 DB3 I/O 56 AB12 I Address bus
17 DB2 I/O 57 AB11 I
18 DB1 I/O 58 AB10 I
19 DB0 I/O 59 AB9 I
20 VSS Ground 60 VSS Ground
21 COREVDD Power supply +3.3V 61 COREVDD Power supply +3.3V
22 GPIO0 I/O General purpose input/output 62 AB8 I
23 FPDAT11 O 63 AB7 I
24 FPDAT10 O
Panel data 64 AB6 I
25 FPDAT9 O 65 AB5 I
26 FPDAT8 O 66 AB4 I Address bus
27 VSS Ground 67 AB3 I
28 FPSHIFT O Shift clock 68 AB2 I
29 IOVDD Power supply +3.3V 69 AB1 I
30 FPDAT7 O 70 AB0 I
31 FPDAT6 O 71 BCLK I System bus clock
32 FPDAT5 O 72 VSS Ground
33 FPDAT4 O
Panel data
73 /RESET I Reset
34 FPDAT3 O 74 /CS I Chip select signal
35 FPDAT2 O 75 /BS I Bus start signal
36 FPDAT1 O 76 /RD I Read signal
37 FPDAT0 O 77 /WE0 I Write enable signal for the lower data byte
38 FPLINE O Line pulse 78 /WE1 I Write enable signal for the upper data byte
39 FPFRAME O Frame pulse 79 RD//WR I Read/write signal
40 VSS Ground 80 VSS Ground
DSP: IC143
YM3436D-FZ (XG948E00) DIR2 (Digital Format Interface Receiver) AD3: IC059 (PM5D-RH)
PIN PIN
NAME I/O FUNCTION NAME I/O FUNCTION
NO. NO.
1 DAUX I Auxiliary input for audio data 23 RSTN I System reset input
2 HDLT O Asynchronous buffer operation flag 24 Vdda VCO section power (+5V)
3 DOUT O Audio data output 25 CTLN I VCO control input N
4 VFL O Parity flag output 26 PCO O PLL phase comparison output
5 OPT O Fs x 1 Synchronous output signal for DAC 27 (NC)
6 SYNC O Fs x 1 Synchronous output signal for DSP 28 CTLP I VCO control input P
7 MCC O Fs x 64 Bit clock output 29 Vssa VCO section power (GND)
8 WC O Fs x 1 Word clock output 30 TSTN I Test terminal. Open for normal use
9 MCB O Fs x 128 Bit clock output 31 KM2 I Clock mode switching input 2
10 MCA O Fs x 256 Bit clock output 32 KM0 I Clock mode switching input 0
11 SKSY I Clock synchronization control input 33 FS1 O Channel status sampling frequency
display output 1
12 XI I Crystal oscillator connection or external 34 FS0 O Channel status sampling frequency
clock input display output 0
13 XO O Crystal oscillator connection 35 CSM I Channel status output method selection
14 P256 O VCO oscillating clock connection 36 EXTW I External synchronous auxiliary input
word clock
15 LOCK O PLL lock flag 37 DDIN I EIAJ (AES/EBU) data input
16 Vss Logic section power (GND) 38 LR O PLL word clock output
17 TC O PLL time constant switching output 39 Vdd Logic section power (+5 V)
18 DIM1 I Data input mode selection 40 ERR O Data error flag output
19 DIM0 I Data input mode selection 41 EMP O Channel status emphasis control code
output
20 DOM1 I Data output mode selection 42 CD0 O 3-wire type microcomputer interface data
output
21 DOM0 I Data output mode selection 43 CCK I 3-wire type microcomputer interface clock
input
22 KM1 I Clock mode switching input 1 44 CLD I 3-wire type microcomputer interface load
input
81
PM5D/PM5D-RH
82
PM5D/PM5D-RH
AK5385AVS-E2 (X4662A00) ADC (Analog to Digital Converter) AD3: IC105, 305, 505, 705 (PM5D-RH)
PIN PIN
NAME I/O FUNCTION NAME I/O FUNCTION
NO. NO.
1 VREFL I Lch voltage reference input 15 SDTOI O Audio serial data output
2 AVSS Analog ground 16 CKS1 I Master clock select
3 VCOM O Common voltage output 17 MCLK I Master clock input
4 LIN+ I Lch analog positive input 18 DFS0 I Sampling speed select
5 LIN- I Lch analog negative input 19 HPFE I High pass filter enable
6 CKS0 I Master clock select 20 DFS1 I Sampling speed select 1
7 DVDD Digital power supply +3.0~5.25V 21 BVSS Substrate ground
8 DVSS Digital ground 22 AVSS Analog ground
9 OVF O Analog input overflow detect 23 AVDD Analog power supply +4.75~5.25V
10 PDN I Power down mode 24 RIN- I Rch analog negative input
11 DIF I Audio interface format 25 RIN+ I Rch analog positive input
12 M/S I Master / Slave mode 26 TEST I Test
13 LRCK I/O Output channel clock 27 AVSS Analog ground
14 BICK I/O Audio serial data clock 28 VREFR I Rch voltage reference input
83
PM5D/PM5D-RH
3A 5 10 5Y
6 9
3Y 4A
TC74VHC08F (XT014A00) 74VHC14SJX (XZ200A00) 7 8
Vss
TC74VHCT08AF (XV495A00) TC74VHC14F-EL (XW876A00) 4Y
1Y 2 13
1A 1 14 VDD 6A
2A 3 12
1B 2 13 4B 6Y 1A 1 14 Vcc
2Y 4 11 5A 1B 2 13 2D
1Y 3 12 4A
3A 5 10 NC 2C
5Y 3 12
2A 4 11 4Y
6 9
3Y 4A 1C 4 11 NC
2B 5 10 3B
GND 7 8 4Y
2Y 6 9 3A 1D 5 10 2B
3Y 1Y 6 9 2A
VSS 7 8
GND 7 8 2Y
D
1CK 3 CK 12 2D
SL: IC204 L H X X H L
1A 1 14 Vcc
SR: IC204 1PR 4 PR CK 11 2CK H L X X L H
1B 2 13 4B L L X X H H
1Q 5 Q 10 H H f H H L
PR 2PR
1Y 3 12 4A H H f L L H
6 Q 9
1Q Q 2Q H H L X QO QO
2A 4 11 4Y
GND 7 Q 8 2Q
2B 5 10 3B
2Y 6 9 3A
GND 7 8 3Y
84
PM5D/PM5D-RH
6 G1 Y4 11
G1 Y4
Output Y7 7 Y7 Y5 10 Y5
Y6
GND 8 9 Y6
1A 2 1A G 15 STROBE
DATA 4 IC2
2G
2C3 13
SR: IC103
1B 3 1B 4A 14 4A
INPUTS
5 IC1 2C2 12
B B
DATA 1Y 4 1Y 4B 13 4B
6 IC0 2C1 11 INPUTS
B B
2A 5 2A 4Y 12 4Y
A A 1G 1 20 VDD (Vcc)
OUTPUT 1Y 7 1Y 2C0 10
A A 6 2B 3A 11
2B 3A
1A1 2 19 2G
GND 8 2Y 9 OUTPUT 2Y
2Y 7 2Y 3B 10 3B
3Y
2Y4 3 18 1Y1
GND 8 9 3Y
1A2 4 17 2A4
2Y3 5 16 1Y2
1A3 6 15 2A3
2Y2 7 14 1Y3
SN74LV164ANSR (IS016410) TC74HC238AF (XT163A00) 1A4 8 13 2A2
8-Bit Shift Register 3 to 8 Line Decoder 2Y1 9 12 1Y4
MAIN: IC060 FDB: IC545
FDC: IC902 (GND) Vss 10 11 2A1
PN1: IC501
SL: IC202
A 1 14 VCC SR: IC202
SIRIAL
A
INPUT
B 2 B QH 13 QH
A 1 16 Vcc
QA 3 QA QG 12 QG A
Select
B 2 B Y0 15 Y0
OUTPUTS Inputs
QB 4 QB QF 11 QF
C 3 C Y1 14 Y1
OUTPUTS
QC 5 QC QE 10 QE
G2A 4 G2A Y2 13 Y2
QD CLEAR Outputs
6 QD CLEAR 9 Enable
CK A 5 G2B Y3 12 Y3
Inputs G2B
GND 7 8 CLOCK
6 G1 Y4 11 Y4
G1
Output Y7 7 Y7 Y5 10 Y5
Y6
GND 8 9 Y6
85
PM5D/PM5D-RH
86
PM5D/PM5D-RH
DIR 2 A1 3 2 B 22 /G
A6 8 17 B5
Logic
Level B1
A2 4 3 D 21
G 22 Converter A7 9 16 B6
A3 5 4 D 20 B2
A8 10 15 B7
A1 3 21 B1
A4 6 5 G2 19
B3
GND 11 14 B8
A5 7 6 G1 18 B4
GND 12 13 GND
A8 10 Same as above block 14 B8
A6 8 7 15 17 B5
(TOP VIEW)
11 12 13
INPUTS FUNCTION
A7 9 8 14 16 B6
OUTPUTS
G DIR A-BUS B-BUS
A8 10 9 13 15
L L A=B OUTPUT INPUT B7
L H B=A INPUT OUTPUT
GND 11 10 12 14 B8
H X Z High lmpedance 11
X : Don't Care
GND 12 13 GND
Z : High lmpedance
Y1
Channel IN/OUT Channel IN/OUT 2Y 2 2Y 2X 15 2X Switches IN/OUT Commons OUT/IN
2 X6 X2 15
Y0
2 Y0 Y 15
Y
X6 X2
Commons OUT/IN X1 Channel IN/OUT Y-COM 3 Y-COM 1X 14 1X Switches IN/OUT 3 X Commons OUT/IN
X
3 X 14
Z1
Z1 14
X
X1
Channel IN/OUT 4 X7 X0 13 Channel IN/OUT 3Y 4 3Y X-COM 13 X-COM Commons OUT/IN 4 Z X1 13 Swiches IN/OUT
X7 X0 Z X1
Control Inhibit Control Input INH 6 INH 3X 11 3X Control Inhibit INH A Control Input
6 INH A 11
A
6 11
A
B B
1B 2 15 2F 1B 2 15 1S 1A 2 15 1D
1C 3 14 2E 2R 3 14 1R 1R 3 14 1Y
1D 4 13 2D 2S 4 13 1Y 1DE 4 13 1Z
1E 5 12 2C 2A 5 12 3A 2R 5 12 2DE
1F 6 11 2B 2B 3S 6 11
6 11 2A 2Z
1Y 7 10 2A 2Y 7 10 3R 2B 7 10 2Y
87
PM5D/PM5D-RH
H H H
L X L NC 1 5 Vcc
X L L
IN A 2
GND 3 4 OUT Y
A 1 8 Vcc
B 2 7 ST
IN B 1 5 Vcc IN B 1 5 Vcc
Y 3 6 SELECT
IN A 2 IN A 2
GND 4 5 A
GND 3 4 OUT Y GND 3 4 OUT Y
INPUT A 2 + 15 1Y 2 15
- INPUT B 4A
+ INPUT ENABLES OUTPUTS
OUTPUT A 3 14 INPUT B 1Z 3 14 4Y
A G G Y Z
ENABLE G H H X H L
ENABLE 4 13 OUTPUT B 4 13 4Z
L H X L H
OUTPUT C 5 12 ENABLE 2Z 5 12 ENABLE G H X L H L
L X L L H
INPUT C 6
+ 11 OUTPUT D 2Y 6 11 3Z X L H Z Z
88
PM5D/PM5D-RH
TB62705CF(EL) (XV013A00)
LED Driver
FDA: IC029-031, 033-035, 037-039
FDB: IC533-535, 537-539, 541-543
FDC: IC802, 803, 805, 807
PN1: IC601-604, 606-609, 611-614, 616
SL: IC300-320
SR: IC300-306
OUT 0 OUT 1 OUT 7
5 6 12
GND 1 16 VDD
R - EXT 15 I - REG.
SERIAL - IN 2 15 R - EXT
ENABLE 13
LATCH 4 13 ENABLE
Q Q Q
OUT 0 5 12 OUT 7
ST D ST D ST D
OUT 1 6 11 OUT 6
LATCH 4
CK CK CK OUT 3 8 9 OUT 4
CLOCK 3
TB62707F(EL) (X5127A00)
LED DRIVER
AD3: TA961 (PM5D-RH)
LATCH 1 24 VDD OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7
VDD 24 21 20 19 18 17 16 15 14
ENABLE 2 23 REXT
NC 3 22 P-GND 13 22
23
INO 4 21 OUT0
IN3 7 18 OUT3
IN4 8 17 OUT4
2
IN5 9 16 OUT5
IN7 11 14 OUT7
4 5 6 7 8 9 10 11 12
L-GND 12 13 P-GND
IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7
- +
INPUT Inverting 6 + -
9 Inverting
Vcc Vcc Input B Input C
Output B 7 8 Output C
OUT3 5 8 OUT6
OUT4 7 10 OUT5
IN4 8 9 IN5 89
PM5D/PM5D-RH
+DC Voltage
+
A B Output A 1 +V 8
Supply
- -
Inverting
2 7 Output B
Input A - +
1 2 3 4 5 6 7 8 Non-Inverting Inverting
3 6
Input A + - Input B
OUT -IN +IN -V +IN -IN OUT +V
A A A B B B -DC Voltage Supply 4 -V 5 Non-Inverting
Input B
NC 2 13 OUTPUT1
3 12
+
GND1 OUTPUT1
A B
- -
+INPUT1 4 11 +V
+
1 2 3 4 5 6 7 8 -
-INPUT1 5 10
- -INPUT2
OUT -IN +IN -V +IN -IN OUT +V +
6 9
A A A B B B -V +INPUT2
OUTPUT2 7 8 GND2
TPS2211IDBR (XY906A00)
PCMCIA Power Interface Switch
MAIN: IC037 TPS2211
CARD
S1
3.3V 3 CS 13 17 Vcc1
S2 12 51 Vcc2
3.3V 4
S3 11
5V 5
S4
1 16 5V 6
VCCD0 SHDN S5
18 Vpp1
VCCD1 2 15 S6
VPPD0 12V 9 CS 10 52 Vpp2
5V 5 12 AVCC 15 VPPD0
14 VPPD1
5V 6 11 AVCC
CONTROLLER 1 VCCD0
GND 7 10 AVPP 2 VCCD1 GND
8 OC
OC 8 9 12V
7
90
PM5D/PM5D-RH
CY2305SXC-1T (XY937A00)
Clock Buffer
MAIN: IC013
Block Diagram
8
PLL MUX CLKOUT
1 3 Pin No. Signal Function
REF CLKA1
2 REF 1 8 CLK OUT 1 REF Input reference frequency, 5V-tolerant input
CLKA2 2 CLK2 Buffered clock output
5 CLK2 2 7 CLK4 3 CLK1 Buffered clock output
CLKA3
7 4 GND Ground
CLK1 3 6 VDD
CLKA4 5 CLK3 Buffered clock output
3 4
6 VDD 3.3V supply
GND 5 CLK3
S2 CLKB1 7 CLK4 Buffered clock output
Select Input 2 8 CLKOUT Buffered clock output, internal feedback on this pin
CLKB2
Decoding 5
S1 CLKB3
7
CLKB4
TLC2932IPWR (XV064A00)
PLL LOGIC V DD FIN-B PFD INHIBIT VCO INHBIT VCO VDD VCO OUT SELECT
AD3: IC058 (PM5D-RH) 1 5 9 10 14 3 2
DSP: IC146, 158
SELECT 2 13 RBIAS
VCO OUTPUT 1/2
MUX
VCO OUT 3 12 VCOIN
6 9
PFD OUT PFD INHIBIT
LOGIC GND 7 8 NC
7 4 6 12 13 11 8
LOGIC GND FIN-A PFD OUT VCOIN RBIAS VCO GND NC
LTC1735CS (X2005A00)
DC-DC Converter
DSP: IC290
VIN
+
13 VIN CIN
RSENSE
91
PM5D/PM5D-RH
■ CIRCUIT BOARDS(シート基板図)
AD1 (XZ020C0) . . . . . . . . . . . . . . . . . . . . 158/160 JK2 (X4117C0) . . . . . . . . . . . . . . . . . . . . . . . . 156
AD2 (X4144C0) . . . . . . . . . . . . . . . . . . . . . 162/163 LED (X4164B0) . . . . . . . . . . . . . . . . . . . . . 170/171
AD3 (X4874C0) . . . . . . . . . . . . . . . . . . . . . 164/166 LD (X4974C0) . . . . . . . . . . . . . . . . . . . . . . . . . 184
ANI1 (XZ032C0) . . . . . . . . . . . . . . . . . . . . 168/169 LPVOL (X4144C0)(PM5D) . . . . . . . . . . . . . . . 187
ANI2 (X4164B0) . . . . . . . . . . . . . . . . . . . . 170/171 LPVOL (X4974C0)(PM5D-RH) . . . . . . . . . . . . 187
ANI3 (X4168C0) . . . . . . . . . . . . . . . . . . . . 172/173 MAIN (X4042B0) . . . . . . . . . . . . . . . . . . . . . . 94/96
BRG1 (X4613B0) . . . . . . . . . . . . . . . . . . . 106/108 MNVOL (X4143C0) . . . . . . . . . . . . . . . . . . . . . . 93
BRG2 (X4099B0) . . . . . . . . . . . . . . . . . . . 110/111 OPT (X4116C0) . . . . . . . . . . . . . . . . . . . . . . . 182
BRG3 (X4100B0) . . . . . . . . . . . . . . . . . . . 112/113 PHN1 (X4143C0) . . . . . . . . . . . . . . . . . . . . . . 189
BRG4 (X4530B0) . . . . . . . . . . . . . . . . . . . 114/116 PHN2 (X4171B0) . . . . . . . . . . . . . . . . . . . . . . 188
BRG5 (X4613B0) . . . . . . . . . . . . . . . . . . . 118/119 PN1 (X4092B0) . . . . . . . . . . . . . . . . . . . . . 128/130
CN1R (X4976B0) . . . . . . . . . . . . . . . . . . . 180/181 PN2 (X4091B0) . . . . . . . . . . . . . . . . . . . . . . . . 132
CUVOL (X4143C0) . . . . . . . . . . . . . . . . . . . . . . 93 PN3 (X4090C0) . . . . . . . . . . . . . . . . . . . . . 134/135
DA1 (X4169B0) . . . . . . . . . . . . . . . . . . . . . 174/175 PN4 (X4095B0) . . . . . . . . . . . . . . . . . . . . . 136/138
DA2 (X4170B0) . . . . . . . . . . . . . . . . . . . . . 176/177 PN5 (X4095B0) . . . . . . . . . . . . . . . . . . . . . 137/139
DA3 (X4171B0) . . . . . . . . . . . . . . . . . . . . . 178/179 PN6 (X4096C0) . . . . . . . . . . . . . . . . . . . . . 140/141
DR (XW326D0) . . . . . . . . . . . . . . . . . . . . . . . . . 92 PN8 1/2 (X4097B0) . . . . . . . . . . . . . . . . . . 142/143
DRL (XW326D0) . . . . . . . . . . . . . . . . . . . . . . . . 92 PN8 2/2 (X4097B0) . . . . . . . . . . . . . . . . . . 142/143
DRN (XW326D0) . . . . . . . . . . . . . . . . . . . . . . . . 92 SL (X4093B0) . . . . . . . . . . . . . . . . . . . . . . 120/122
DSP (X4115B0) . . . . . . . . . . . . . . . 98/100/102/104 SR (1/2) (X4094B0) . . . . . . . . . . . . . . . . . . 124/126
FDA (X4098C0) . . . . . . . . . . . . . . . . . . . . 144/146 SR (2/2) (X4094B0) . . . . . . . . . . . . . . . . . . . . . 121
FDB (X4158C0) . . . . . . . . . . . . . . . . . . . . 148/150 STLD (X4974C0) . . . . . . . . . . . . . . . . . . . . . . 186
FDC (X4141D0) . . . . . . . . . . . . . . . . . . . . . . . 152 SW48 (X4974C0) . . . . . . . . . . . . . . . . . . . . . . 187
HIC-HA (X4876B0) . . . . . . . . . . . . . . . . . . . . . 167 TB (X4143C0) . . . . . . . . . . . . . . . . . . . . . . . . . 190
JK1 (X5102B0) . . . . . . . . . . . . . . . . . . . . . . . . 154 TBVOL (X4143C0) . . . . . . . . . . . . . . . . . . . . . . 93
Note : See parts list for details of circuit board conponent parts.
注:シートの部品詳細は、
パーツリストをご参照ください。
to FAN
DR: to BRG1-CN410
to LPVOL-CN100
to DRL-CN100
DRL: to DR-CN100
to DRN-CN100
DRN: to DRL-CN100
2NAP-WD27560 1
92
PM5D/PM5D-RH
MONITOR CUE
PHONES LEVEL
Component side
(部品側)
to PHN1-CN600 to DA2-CN904
to PHN2-CN600
Pattern side
(パターン側)
TALKBACK MONITOR
LEVEL LEVEL
MEMORY
CARD
MOUSE
KEYBOARD
to TPSW-CN101 to LCD
A'
2NAP-WA77120-1 2
94
PM5D/PM5D-RH
• Lithium Battery
A not installed
(リチウム電池)
Battery VN103500
VN103600(Battery holder for VN103500)
Battery
Battery holder
to DSP-CN102
to DSP-CN101
to LCD (INVERTER)-CN1
to BRG1-CN401
Component side
(部品側)
to CARD (EPSON) to BRG1-CN402
A'
not installed
2NAP-WA77120-1 2
95
PM5D/PM5D-RH
B'
2NAP-WA77120-1 2
96
PM5D/PM5D-RH
Pattern side
B'
(パターン側)
2NAP-WA77120-1 2
97
PM5D/PM5D-RH
to OPT-CN802
to OPT-CN804
to OPT-CN801
to OPT-CN803
C'
2NAP-WA77130-1 1
98
PM5D/PM5D-RH
PM5D-RH: N.C
PM5D: to AD2-CN003
PM5D-RH: to CN1R-CN102
C to JK2-CN507 PM5D-RH: to CN1R-CN107 PM5D: N.C PM5D: JUMPER CONNECTOR
to JK1-CN901 PM5D: to AD2-CN002 to JK2-CN506 to JK2-CN509 PM5D-RH: to CN1R-CN108
to DA1-4-CN901
to DA1-1-CN901
to ANI3-CN001
to DA1-1-CN903
to DA1-2-CN903
to DA1-4-CN903
to DA1-3-CN903
to DA3-CN903
to DA2-CN903
to PHN2-CN502
to TB-CN100
to BRG1-CN403
to BRG1-CN404
N. C.
to MAIN-CN6
Component side
(部品側)
to MAIN-CN5 N. C.
C'
2NAP-WA77130-1 1
99
PM5D/PM5D-RH
D'
2NAP-WA77130-1 1
100
PM5D/PM5D-RH
2 layer(2層)
Component side
(部品側)
D'
2NAP-WA77130-1 1
101
PM5D/PM5D-RH
E'
2NAP-WA77130-1 1
102
PM5D/PM5D-RH
7 layer(7層)
Component side
(部品側)
E'
2NAP-WA77130-1 1
103
PM5D/PM5D-RH
F'
2NAP-WA77130-2
104
PM5D/PM5D-RH
Pattern side
(パターン側)
F'
2NAP-WA77130-2
105
PM5D/PM5D-RH
to BRG5-CN810
to BRG5-CN809
to BRG5-CN807
to BRG5-CN808
to MAIN-CN7
to MAIN-CN14
to FDA-
G'
2NAP-WC21950-1 1
106
PM5D/PM5D-RH
G
to CN1R-CN101 to ANI3-CN002 to DA1(1)-CN001 to DA1(4)-CN001
to LPVOL-CN501
to DR-CN100
PM5D: N.C
PM5D-RH: to SW48-CN401
PM5D: to AD1-CN001
PM5D-RH: to AD3-CN981
Component side
(部品側)
to FDA-CN30 to FDB-CN532 to FDC-CN703 to TB-CN200 to PHN2-CN500 to PHN1-CN500
G'
2NAP-WC21950-1 1
107
PM5D/PM5D-RH
H'
2NAP-WC21950-2 1
108
PM5D/PM5D-RH
Pattern side
(パターン側)
H'
2NAP-WC21950-2 1
109
PM5D/PM5D-RH
I
to BRG5-CN812
2NAP-WA82930-1 2
110
PM5D/PM5D-RH
J'
Pattern side
J' (パターン側)
2NAP-WA82930-1 2
111
PM5D/PM5D-RH
to FDC-CN701
to FDC-CN702
to SR(1/2)-CN101
to BRG5-CN813
Component side
(部品側)
2NAP-WB05710-1 2
112
PM5D/PM5D-RH
Pattern side
(パターン側)
2NAP-WB05710-1 2
113
PM5D/PM5D-RH
K
to OPT-CN807 to OPT-CN806
2NAP-WC21930-1 1
114
PM5D/PM5D-RH
2NAP-WC21930-1 1
115
PM5D/PM5D-RH
L'
2NAP-WC21930-1 1
116
PM5D/PM5D-RH
2NAP-WC21930-1 1
117
PM5D/PM5D-RH
to BRG2-CN201
to BRG3-CN201
to BRG1-CN201 to BRG4-CN202
to BRG4-CN203
to BRG1-CN204
to BRG1-CN202
to BRG1-CN203
to DC POWER
INPUT connector
PM5D-RH only
to AD3-CN981
to DC POWER
INPUT connector
PM5D-RH only
to AD3-CN981
Component side
(部品側)
2NAP-WC21950-1 1
118
PM5D/PM5D-RH
Pattern side
(パターン側)
2NAP-WC21950-1 1
119
PM5D/PM5D-RH
● SL Circuit Board M
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
OVER OVER
OVER
-3 -3 -3
-6 -6 -6
-9 -9 -9
CH 1-24/ST IN/
FX RTN
MIX CH 25-48/
FX RTN-ST IN
SEND
ON
1 1
UPPER
RECALL
SAFE ENC
2 2 FREQUENCY
ENCODER HPF
LOWER
ON
TIME ENCODER HPF EQUALIZER
3 3
DELAY
STEREO
MUTE
SAFE
4 4
TO
PAN STEREO
OVER
ENCODER ENCODER
-3 GAIN/
5 5 ATT ENC
-6
GAIN/
-9 ATTENUATION/
-12
6 6 -15
-18
-24 0 0
-30 3 3
7 7 -40 6 6
-50 10 10
-60 20 20
ATTACK ATTACK
30 30
8 8
GR GR ENC
DCA
MUTE
GROUP
HOLD RELEASE
ENC
2NAP-WA76870-1 1
120
PM5D/PM5D-RH
17 18 19 20 21 22 13 24
41 42 43 44 45 46 47 48
OVER SCENE
-3 MEMORY
-6
-9
-12
-15
-18 1
-24
-30
-40
-50 2
-60 to SR (1/2)-CN600
CH 1-24/ST IN/ 3
FX RTN
MIX
MATRIX
4
REAK
HOLD
CH 25-48/
FX RTN-ST IN
5
6
ON
7
UPPER HIGH
Q GAIN
ENCODER ENCODER 8
FREQUENCY
ENCODER
LOWER
EQUALIZER
ATTACK
Q GAIN
ENCODER ENCODER
FREQUENCY LOW
ENCODER MID
RELEASE
RATIO LOW
LOW
Q GAIN
ENCODER ENCODER
FREQUENCY
ENCODER
SL: 2NAP-WA76870-1 1
SR (2/2): 2NAP-WB08480-1 1
121
PM5D/PM5D-RH
● SL Circuit Board
N
to MAIN-CN1 to FDB-CN527 to FDB-CN526
WH007
WH006
WH002 C181
WH005
WH004
WH003
N'
2NAP-WA76870-2 3
122
PM5D/PM5D-RH
to PN1-CN102
to PN1-CN101
to BRG2-CN207
Pattern side
(パターン側)
N'
2NAP-WA76870-2 3
123
124
●
ST IN/FX RTN/MATRIX
STEREO A STEREO B CUE
1L 1R 2L 2R 3L 3R 4L 4R
1 2 3 4 5 6 7 8 L R L R L R
-3 -3 -3 -3
-6 -6 -6 -6
-9 -9 -9 -9
-12 -12 -12 -12
-15 -15 -15 -15
-18 -18 -18 -18
-24 -24 -24 -24
-30 -30 -30 -30
-40 -40 -40 -40
SR (1/2) Circuit Board
CUE
SOLO LAST
OUTPUT
CUE
PFL
MONITOR
2TR 2TR
IN D1 IN A2
2TR STEREO A
IN D1
LCR
STEREO B
SCENE MEMORY
OSCILLATOR
2TR
IN D2
2TR DEFINE ON
IN D3
LEVEL PHONES TALKBACK
PREVIEW
UNDO
to SR (2/2)-CN900
2NAP-WB08480-1
O
O'
1
DOWN
PREVIEW
UNDO
-CN900
O
O'
DOWN
STORE REULL
2NAP-WB08480-1
ON
UP
1
ON MONO
DISPLAY ACCESS
GLOBAL
OUTPUT
INPUT
1 2 3 4 5 6 7 8
ENCODER
9 10 11 12 13 14 15 16
SEL
ST IN 1 ST IN 2 ST IN 3 ST IN 4 17 18 19 20 21 22 23 24
FX RTN 1 FX RTN 2 FX RTN 3 FX RTN 4
(部品側)
USER DEFINED KEYS
Component side
125
PM5D/PM5D-RH
PM5D/PM5D-RH
to PN8(1/2)-CN100
to FDC-CN601
P'
2NAP-WB08480-2 1
126
PM5D/PM5D-RH
to BRG3-CN202 to MAIN-CN2
Pattern side
P'
(パターン側)
2NAP-WB08480-2 1
127
PM5D/PM5D-RH
MIX 1 MIX 2
MIX 3
to SL-CN450
to SL-CN451
to BRG2-CN208
SEL CUE
MIX 9 MIX 10 MIX 11
FADER ENCODER
FLIP MODE
GAIN/
PAN ATT ALT
LAYER
16
9 10 11 12 13 14 15
17 18 19 20 21 22 23 24
CUE SEL CUE SEL CUE SEL
2NAP-WA76880-1 1
128
PM5D/PM5D-RH
Q
MATRIX 2 MATRIX 3 MATRIX 4 MATRIX 5 MATRIX 6 MATRIX 7 MATRIX 8
MATRIX
ON
MATRIX
ENCODER
CUE SEL CUE SEL CUE SEL CUE SEL CUE SEL CUE SEL CUE SEL
MIX 2 MIX 4
MIX
ON
MIX
ENCODER
MIX
ON
MIX
ENCODER
CUE SEL CUE SEL CUE SEL CUE SEL CUE SEL CUE SEL CUE SEL
MIX
ON
MIX
ENCODER
CUE SEL CUE SEL CUE SEL CUE SEL CUE SEL SEL CUE SEL
CUE
Q'
Component side
(部品側)
2NAP-WA76880-1 1
129
PM5D/PM5D-RH
WH002
R'
2NAP-WA76880-2 1
130
PM5D/PM5D-RH
02
WH003
Pattern side
(パターン側)
R'
2NAP-WA76880-2 1
131
PM5D/PM5D-RH
ENCODER
SEL
T'
2NAP-WA76880-1 1
132
PM5D/PM5D-RH
S to FDA-CN31 to FDA-CN25
to FDB-CN539 to FDB-CN525
ON
RE ON PRE ON PRE ON PRE ON PRE ON PRE PRE
Pattern side
T' (パターン側)
2NAP-WA76880-1 1
133
PM5D/PM5D-RH
OVER
-6
-12
-18
ON -30
-60
DCA
1
2
3
4
5
6
7
8
MUTE
1
2
3
4
5
6
7
8
RCL
MUTE
SAFE
CUE
2NAP-WB18060-1
134
PM5D/PM5D-RH
Pattern side
(パターン側)
2NAP-WB18060-1
135
PM5D/PM5D-RH
CH 1-24
CH 25-48
(US
A B C D E F DCA
FADER MODE
MUTE
NOMINAL
RCL
SAFE
CUE
2NAP-WB08470-1 1
136
PM5D/PM5D-RH
(STEREO B)
MONO
COMP
MTRX
TO
(STEREO B)
ST IN 1-4
SEL
COMP
MTRX
FX RTN 1-4
TO
(STEREO A)
25
(USER DEFINED KEY)
SEL
8
to FDC-CN707
STEREO STEREO
ON ON
7
6
5
4
3
to FDC-CN709
2
1
V'
2NAP-WB08470-1 1
138
PM5D/PM5D-RH
Pattern side
(パターン側)
Pattern side
V' (パターン側)
OVER
-6
-12
-18
ON -30
-60
DCA
1
2 DCA
3 (ASSIGN MODE)
4
5
6 MUTE
7 (ASSIGN MODE)
8
MUTE
1
2
3
4
5
6
7
8
RCL
MUTE
SAFE
CUE
Component side
(部品側)
ST IN 1 ST IN 2 ST IN 3 ST IN 4
FX RTN 1 FX RTN 2 FX RTN 3 FX RTN 4
2NAP-WA76960-1
140
PM5D/PM5D-RH
Pattern side
(パターン側)
2NAP-WA76960-1
141
PM5D/PM5D-RH
(DEL) (INC)
to SR-CN500
Component side
(部品側)
to PN8 (2/2)-CN200
to PN8 (1/2)-CN101
Component side
(部品側)
DATA
ENCODER
Pattern side
(パターン側)
Pattern side
(パターン側)
W
to BRG2-CN205 to BRG2-CN206 to BRG1-CN407
to FDB-CN537
to FDB-CN540
W'
2NAP-WA76990-1 2
144
PM5D/PM5D-RH
to MOTORIZED FADER
2NAP-WA76990-1 2
145
PM5D/PM5D-RH
X'
2NAP-WA76990-1 2
146
PM5D/PM5D-RH
Pattern side
(パターン側)
X'
2NAP-WA76990-1 2
147
PM5D/PM5D-RH
Y
to SL-CN800 to SL-CN801
2NAP-WA7700-1 2
148
PM5D/PM5D-RH
Y
N801 to BRG1-CN408 to BRG2-CN204 to BRG2-CN203
to MOTORIZED FADER
to FDA-CN29
to FDA-CN26
2NAP-WA7700-1 2
149
PM5D/PM5D-RH
Z'
2NAP-WA7700-1 2
150
PM5D/PM5D-RH
Pattern side
Z' (パターン側)
2NAP-WA7700-1 2
151
PM5D/PM5D-RH
b'
2NAP-WA86540-1 3
152
PM5D/PM5D-RH
a
to PN5-CN400 to PN4-CN201 to PN4-CN101 to PN5-CN401
Pattern side
b' (パターン側)
2NAP-WA86540-1 3
153
PM5D/PM5D-RH
d'
2NAP-WA80640-1 2
154
PM5D/PM5D-RH
c
to DSP-CN110 to DSP-CN111
Pattern side
d' (パターン側)
2NAP-WA80640-1 2
155
PM5D/PM5D-RH
e
to BRG1-CN406 to DSP-CN113 to DSP-CN112
THRU OUT
GPI RS422 REMOTE HA REMOTE
MIDI
e'
f'
2NAP-WA77100-1
156
PM5D/PM5D-RH
e
to DSP-CN115 to DSP-CN114
OUT IN
CASCADE OUT CASCADE IN
MIDI Component side
e' (部品側)
Pattern side
f' (パターン側)
2NAP-WA77100-1
157
PM5D/PM5D-RH
g
to ANI1-CN100 to ANI1-CN100 to ANI1-CN100 to ANI1-CN100 to ANI1-CN100 to ANI1-CN100 to AN
2NAP-V863020-2 1
158
PM5D/PM5D-RH
g
CN100 to ANI1-CN100 to ANI1-CN100 to ANI1-CN100 to ANI1-CN100 to ANI1-CN100 to ANI1-CN100
2NAP-V863020-2 1
159
PM5D/PM5D-RH
h'
2NAP-V863020-2 1
160
PM5D/PM5D-RH
Pattern side
h' (パターン側)
2NAP-V863020-2 1
161
PM5D/PM5D-RH
to BRG1-CN424,CN425,CN426,
CN428,CN429,CN430, to DSP-CN124 to DSP-CN125
CN431,CN433
Component side
(部品側)
2NAP-WB08540-1
162
PM5D/PM5D-RH
Pattern side
(パターン側)
2NAP-WB08540-2
163
PM5D/PM5D-RH
CN115
not installed
R L
not installed
not installed
ST IN 4 i'
2NAP-WC22220-1 1
164
PM5D/PM5D-RH
i
o HIC-HA- to HIC-HA- to HIC-HA- to HIC-HA- to HIC-HA- to HIC-HA- to HIC-HA- to BRG1-CN429,
CN101 CN101 CN101 CN101 CN101 CN101 CN101 430, 431, 433
Component side
(部品側)
L R L R L R L
INPUT
T IN 4 i' ST IN 3 ST IN 2 ST IN 1
2NAP-WC22220-1 1
165
PM5D/PM5D-RH
j'
2NAP-WC22220-1 1
166
PM5D/PM5D-RH
Component side
(部品側)
Pattern side
(パターン側)
Pattern side
(パターン側)
j'
AD3: 2NAP-WC22220-1 1
HIC-HA: 2NAP-WC06320-1
167
PM5D/PM5D-RH
+48V ON/OFF
PAD
GAIN
PEAK
SIGNAL
INSERT
to AD1-CN101,CN102,
CN201,CN202,
CN301,CN302,
CN401,CN402,
CN501,CN502,
CN601,CN602
Component side
(部品側)
2NAP-V628760-2 3
168
PM5D/PM5D-RH
Pattern side
(パターン側)
2NAP-V628760-2 3
169
PM5D/PM5D-RH
SIGNAL
PEAK
INPUT L
ST IN
INPUT R
ST IN
to AD2-CN301,
to LED-CN202
401, 501, 601
Component side
(部品側)
SIGNAL
to ANI2-CN201
PEAK
Component side
(部品側)
Pattern side
(パターン側)
Pattern side
(パターン側)
+18dB +24dB
Component side
(部品側)
to DSP-CN126 to BRG1-CN414
2NAP-WA77030-1
172
PM5D/PM5D-RH
Pattern side
(パターン側)
2NAP-WA77030-1
173
PM5D/PM5D-RH
+18dB
+24dB
8 7 6 5 4 3 2 1
16 15 14 13 12 11 10 9
24 23 22 21 20 19 18 17
MIX OUT (MATRIX OUT) Component side
(部品側)
2NAP-WA77060-1 2
174
PM5D/PM5D-RH
Pattern side
(パターン側)
2NAP-WA77060-1 2
175
PM5D/PM5D-RH
to MNVOL-CN300
to CUVOL-CN401
to MNVOL-CN300
+18dB
+24dB
2NAP-WA77070-1 3
176
PM5D/PM5D-RH
Pattern side
(パターン側)
2NAP-WA77070-1 3
177
PM5D/PM5D-RH
STEREO A STEREO B
L R L R
+18dB
+24dB
2NAP-WB17690-1 2
178
PM5D/PM5D-RH
Pattern side
(パターン側)
2NAP-WB17690-1 2
179
180
●
PM5D/PM5D-RH
(部品側)
Component side
2NAP-WC22190-1
1
PM5D/PM5D-RH
Pattern side
(パターン側)
2NAP-WC22190-1 1
181
PM5D/PM5D-RH
to DSP-CN108 to BRG4-CN204
k
SLOT 4
to DSP-CN109
SLOT 2
to DSP-CN107
k'
l'
2NAP-WA77110-1
182
PM5D/PM5D-RH
k to BRG4-CN205 to DSP-CN106
SLOT 3
SLOT 1
Component side
(部品側)
to DSP-CN105
k'
Pattern side
(パターン側)
l'
2NAP-WA77110-1
183
PM5D/PM5D-RH
● LD Circuit Board
+48V
PEAK
SIGNAL
m'
n'
2NAP-WC31430-1 2
184
PM5D/PM5D-RH
to AD3-1-CN961
Component side
to AD3-3-CN961
to AD3-5-CN961 (部品側)
m'
Pattern side
(パターン側)
n'
2NAP-WC31430-1 2
185
PM5D/PM5D-RH
SIGNAL
PEAK
+48V
ST IN 1
ST IN 2
ST IN 3
ST IN 4
to AD3-7-CN961
2NAP-WC31430-1 2
186
PM5D/PM5D-RH
to BRG1-CN422
to DR-CN100
to BRG1-CN411 to BRG1-CN411
to DR-CN100
Component side
Component side (部品側)
(部品側)
Pattern side
Pattern side
(パターン側)
(パターン側)
to PHN1-CN501
to DSP-CN136
PHONES (FRONT)
to CUVOL-CN400
to BRG1-CN415
Component side
(部品側)
Pattern side
(パターン側)
2NAP-WB17690-1 2
188
PM5D/PM5D-RH
to PHN2-CN503 to CUVOL-CN400
to BRG1-CN432
Component side
(部品側)
PHONES (PANEL)
Pattern side
(パターン側)
2NAP-WB08530-1 1
189
PM5D/PM5D-RH
● TB Circuit Board
to BRG1-CN421 to DSP-CN131
to TBVOL-CN102
Component side
(部品側)
TALKBACK
Pattern side
(パターン側)
2NAP-WB08530-1 1
190
PM5D/PM5D-RH
■ INSPECTIONS
(2) How to write programs
1. Preparations For the program writing procedure, refer to the "UPDATING
THE PROGRAM" section. (See page 245)
1-1. Parameters
◆ The parameter settings are as follows unless otherwise 1-3. Initialization
specified. All of the contents that have been saved in memory will be
• Set WORD CLOCK INT to 96 kHz. lost if you initialize the internal memory. You must use extreme
• Turn on only the channel being measured. caution when performing this operation.
PAN: Center
GAIN: MIN 1 While holding down the SCENE MEMORY [STORE]
PAD SW (only PM5D): ON key on the panel, turn on the power of the PW800W
INSERT SW (only PM5D): OFF power supply.
FADER: NOMINAL (0 dB) After the opening screen, the initialization menu screen
MIX MASTER LEVEL: NOMINAL (0 dB) will appear as shown below.
MATRIX MASTER LEVEL: NOMINAL (0 dB)
MONITOR LEVEL: MAX
CUE LEVEL: MAX
PHONES LEVEL: MAX
TALKBACK LEVEL: MAX
+48V MASTER SW (only PM5D-RH): ON
PAN NOMINAL POSITION - MONO: CENTER
- PAIR: L ⇔ R
• 0 dBu = 0.775 Vrms
• 0dBFS = 0 dB, full scale
• Set the oscillator output impedance to 150Ω.
• Input impedance of oscilloscope, level gauge shall be over
100 kΩ.
• Correct the noise measurement with a 12.7 kHz, -6 dB/
octave low pass filter. (For measurement, use the average
values and not effective values.)
• Correct the distortion measurement with an 80 kHz, -18
2 Click one of the following buttons to select the desired
type of initialization.
dB/octave low pass filter.
• INITIALIZE ALL MEMORIES
All memories including scene memories and libraries
◆ For analog output inspection, add or change parameter
will return to their factory-set condition.
settings as follows.
• INITIALIZE CURRENT MEMORIES
• For maximum output measurement, unless otherwise
Memories other than scene memories and libraries will
specified, output 0 dB from the internal oscillator.
return to their factory-set condition.
• Set the analog output loads as follows.
• CANCEL
STEREO A, B (L, R): 600 Ω
The initialization procedure will be canceled, and the
MONITOR OUT (L, R, C): 600 Ω
PM5D will start up in the normal operating mode.
CUE OUT (L, R): 600 Ω
MATRIX OUT 1 - 8: 600 Ω
Note If the voltage of the backup battery runs low, or if an
MIX OUT 1 - 24: 600 Ω
error occurs in the internal memory, a warning
INSERT OUT 1 - 48: 10 kΩ message will appear at the bottom of the screen, and
PHONES (x2): 8Ω the initialization menu will appear automatically. Please
note that if you click the [CANCEL] button while the
1-2. Updating the Program warning message is displayed and start in the normal
If the main program is not the latest version, it is necessary to operating mode, proper operation of the system will
update it to the latest version. not be guaranteed.
* For the latest version, download the latest program from
the YSISS home page and save it in the memory card. 3 When a message asking you for confirmation of
initialization is displayed, click the [OK] button.
(1) How to check the version of the main program When the internal memory has been initialized, the
Press the DISPLAY ACCESS [UTILITY] button and select PM5D will start up in the normal operating mode.
the PREFERENCE 2 page in the LCD screen. Then the current
version will be displayed on the right side of the screen. 191
PM5D/PM5D-RH
1-4. Fader Calibration 6 After setting the fader to the correct position, press
the [ENTER] key.
1 While holding down the [ENTER] key of the panel, Processing will proceed to the next fader position.
turn on the power of the PW800W power supply.
After the opening screen, the calibration menu screen 7 Repeat steps 5 and 6 for each fader position q to r.
will appear as shown below.
8 Verify that calibration has been completed and that all
fader select buttons are now off. Then click the [OK]
button.
The calibration settings will be stored in the internal
memory. If a fader select button remains on (green),
calibration has failed. Execute calibration once again.
3 Click the fader select button to add a check mark to 1 kHz +10 dBu +4 dBu +4±2 dBu
[6] Crosstalk between adjacent channels (STEREO A, B) [5] MIX OUT 1 - 24 level difference
Parameters:Set PAN of CH1 fully to the L side for L channel Adjust the range of difference in the gain measured in item
output and set it fully to the R side for R channel [1] above as follows.
output. Permissible range
Execute output only from one output channel and Within 1 dB
measure the noise level of the adjacent channels.
[6] Crosstalk between adjacent channels (MIX OUT 1 - 24)
Input frequency Output level Permissible range
Parameters: Turn on only MIX OUT of one odd number
(STEREO AL) (STEREO AR) channel for output with MIX OUT of other channels
1 kHz +23 dBu -57 dBu or below turned off and measure the noise level of even number
channels next to the odd number channel on both side.
Input frequency Output level Permissible range Input frequency Output level (Odd number channel) Permissible range (Even number channel)
(STEREO AR) (STEREO AL) 1 kHz +23 dBu -57 dBu or below
(STEREO BL) Perform the same check on the even number channel side.
1 kHz +23 dBu -57 dBu or below
[7] Maximum output (MIX OUT 1 - 24)
Input frequency Output level Permissible range Parameter: Assign only the built-in oscillator to MIX OUT 1
(STEREO BL) (STEREO AR) - 24.
(STEREO BR) Input frequency Output level Permissible range Distortion factor
1 kHz +24 dBu +24±0.5 dBu 0.006% or below
1 kHz +23 dBu -57 dBu or below
[2] f characteristic (MIX OUT 1 - 24) [4] Residual noise (MATRIX OUT 1 - 8)
Parameter: 1 kHz is used as reference of the permissible range Parameter: Turn off MATRIX 1 - 8.
Permissible range
Input frequency Input level Permissible range
-86 dBu or below
20 Hz +10 dBu -1.5~+0.5 dB
40 kHz +10 dBu -1.5~+0.5 dB
[5] Level difference (MATRIX OUT 1 - 8)
[3] Distortion factor (MIX OUT 1 - 24) Adjust the range of difference in the gain measured in the
Input frequency Output level Permissible range item [1] above as follows.
1 kHz +22 dBu 0.007% or below Permissible range
Within 1 dB
[6] Crosstalk between adjacent channels (MATRIX OUT 1 - 8) Input frequency Output level Permissible range
Parameters: Turn on only MATRIX OUT of one odd number (MONITOR OUT R) (MONITOR OUT L)
channel for output with MATRIX OUT of other (MONITOR OUT C)
channels turned off and measure the noise level 1 kHz +23 dBu -57 dBu or below
of even number channels next to the odd number
channel on both side. Input frequency Output level Permissible range
Input frequency Output level (Odd number channel) Permissible range (Even number channel) (MONITOR OUT C) (MONITOR OUT R)
1 kHz +23 dBu -57 dBu or below 1 kHz +23 dBu -57 dBu or below
Perform the same check on the even number channel side.
[7] Maximum output (MONITOR OUT L, R, C)
[7] Maximum output (MATRIX OUT 1 - 8) Parameter: Turn off INSERT of MONITOR.
Parameter: Assign only the built-in oscillator to MATRIX OUT At L, R output, assign the built-in oscillator to
1 - 8. STEREO B (L, R) and SOURCE of MONITOR
Input frequency Output level Permissible range Distortion factor to STEREO B.
1 kHz +24 dBu +24±0.5 dBu 0.006% or below At C output, switch STEREO B to CENTER BUS
in the above state.
2-1-4. MONITOR OUT L, R, C Input frequency Output level Permissible range Distortion factor
Parameters: Input from INPUT (XLR) of CH1. 1 kHz +24 dBu +24±0.5 dBu 0.006% or below
Assign CH1 to MONITOR INSERT INPUT L,
R, C and turn on INSERT.
Turn on MONITOR SW.
2-1-5. CUE OUT L, R,
Parameters: Input from INPUT (XLR) of CH1
[1] Gain (MONITOR OUT L, R, C) Turn on CUE of CH1.
Input frequency Input level Specified output level Permissible range Set INPUT CUE to POST PAN.
1 kHz +10 dBu +4 dBu +4±2 dBu
[1] Gain (CUE OUT L, R)
[2] f characteristic (MONITOR OUT L, R, C) Input frequency Input level Specified output level Permissible range
Parameter: 1 kHz is used as reference of the permissible range 1 kHz +10 dBu +4 dBu +4±2 dBu
Input frequency Input level Permissible range
20 Hz +10 dBu -1.5~+0.5 dB [2] f characteristic (CUE OUT L, R)
40 kHz +10 dBu -1.5~+0.5 dB Parameter: 1 kHz is used as reference of the permissible range
Input frequency Input level Permissible range
[3] Distortion factor (MONITOR OUT L, R, C) 20 Hz +10 dBu -1.5~+0.5 dB
Input frequency Output level Permissible range 40 kHz +10 dBu -1.5~+0.5 dB
1 kHz +22 dBu 0.007% or below
[3] Distortion factor (CUE OUT L, R)
[4] Residual noise (MONITOR OUT L, R, C) Input frequency Output level Permissible range
Parameter: Turn off MONITOR INSERT. 1 kHz +22 dBu 0.007% or below
Monitor level Permissible range
MAX -86 dBu or below [4] Residual noise (CUE OUT L, R)
MIN -100 dBu or below Parameter: Turn off CUE of CH1.
CUE level Permissible range
[5] Level difference (MONITOR OUT L, R, C) MAX -86 dBu or below
Adjust the range of difference in the gain measured in item MIN -100 dBu or below
[1] above as follows.
Permissible range [5] L to R level difference
Within 1 dB Adjust the range of difference in the gain measured in item
[1] above as follows.
[6] Crosstalk between adjacent channels (MONITOR OUT L, R, C) Permissible range
Parameters: Turn on only INSERT of one output channel for Within 1 dB
output with INSERT of other channels turned off
and measure the noise level of adjacent channels [6] Crosstalk between adjacent channels (CUE OUT L, R)
of the output channel. Parameters: At CUE OUT L output, set PAN of CH1 fully to
the L side and at CUE OUT R output, set it fully
Input frequency Output level Permissible range
(MONITOR OUT L) (MONITOR OUT R) to the R side.
(CUE OUT R) Set only one output channel for output and
1 kHz +23 dBu -57 dBu or below measure the noise level of adjacent channels of
194 this output channel.
PM5D/PM5D-RH
Input frequency Output level Permissible range [5] PHONES L, R (x2) level difference
(CUE OUT L) (CUE OUT R) Adjust the range of difference in the gain measured in item
1 kHz +23 dBu -57 dBu or below [1] above as follows.
Permissible range
Input frequency Output level Permissible range Within 2 dB
(CUE OUT R) (CUE OUT L)
(MONITOR OUT L) [6] Maximum output (PHONES L, R (x2))
1 kHz +23 dBu -57 dBu or below Parameter: Assign the built-in oscillator only to STEREO A
(L, R) and output -27 dB.
Input frequency Output level Permissible range Distortion factor
[7] Maximum output (CUE OUT L, R) 1 kHz +3 dBu +3±0.5 dBu 0.15% or below
Parameter: Assign the built-in oscillator only to STEREO A
(L, R) and turn on CUE of STEREO A. [7] L to R crosstalk.
Input frequency Output level Permissible range Distortion factor Parameter: Set PAN fully to the L side.
1 kHz +24 dBu +24±0.5 dBu 0.006% or below Input frequency Output level (L) Permissible range (R)
1 kHz +3 dBu -56 dBu or below
2-1-6. Output Level Difference Perform the same check on the R side.
Parameters: Adjust the difference range of gain of following
test items measured at 1 kHz as specified below. 2-1-8. 2TR IN ANALOG 1 (L, R), 2TR IN
STEREO A (L, R), STEREO B (L, R) ANALOG 2 (L, R)
MIX OUT 1 - 24 Parameter: Use STEREO A (L) for this inspection.
MATRIX OUT 1 - 8 [1] Gain (2TR IN ANALOG 1 (L, R), 2TR IN ANALOG 2 (L, R))
MONITOR OUT L, R, C Input frequency Input level Specified output level Permissible range
CUE OUT L, R 1 kHz +4 dBu +4 dBu +4±2 dBu
Permissible range
Within 2 dB [2] f characteristic (2TR IN ANALOG 1 (L, R), 2TR IN ANALOG 2 (L, R))
Parameter: 1 kHz is used as reference of the permissible range.
2-1-7. PHONES L, R (x2: 2 terminals on the Input frequency Input level Permissible range
panel surface and front surface) 20 Hz +4 dBu -1.5~0.5 dB
Parameters: Input from INPUT (XLR) of CH1 40 kHz +4 dBu -1.5~0.5 dB
Assign CH1 to STEREO A.
Set MONITOR SOURCE to STEREO A. [3] Distortion factor (2TR IN ANALOG 1 (L, R), 2TR IN ANALOG 2 (L, R))
Set MONO of PAN NOMINAL POSITION to Input frequency Output level Permissible range
"L ⇔ R". 1 kHz +22 dBu 0.007% or below
Set PAN of CH1 fully to the L side when
measuring L and fully to the R side when [4] Residual noise (2TR IN ANALOG 1 (L, R), 2TR IN ANALOG 2 (L, R))
measuring R. Parameter: Short 2TR IN ANALOG 1, 2 with 150Ω.
Permissible range
[1] Gain (PHONES L, R (x2)) -82 dBu or below
Input frequency Input level Specified output level Permissible range
1 kHz 0 dBu 0 dBu 0±2 dBu [5] 2TR IN ANALOG 1 (L, R), 2TR IN ANALOG 2 (L, R) level difference
Adjust the range of difference in the gain measured in item
[2] f characteristic (PHONES L, R (x2)) [1] above as follows.
Parameter: 1 kHz is used as reference of the permissible range. Permissible range
Input frequency Input level Permissible range Within 1 dB
20 Hz 0 dBu -3~0.5 dB
40 kHz 0 dBu -3~+0.5 dB [6] Crosstalk between adjacent channels (2TR IN ANALOG 1, 2 (L, R))
Parameters: Input signals to one input channels only and make
[3] Distortion factor (PHONES L, R (x2)) them output at the level specified in the table below
Input frequency Output level Permissible range from STEREO A (L). In this state, turn off the
1 kHz 0 dBu 0.15% or below signal input channel and short the signal input
channel and the input channel adjacent to it on
[4] Residual noise (PHONES L, R (x2)) both sides with 150Ω. Then turn on only the input
Parameter: Turn off STEREO A. channel where the noise level is to be measured
PHONES level Permissible range and measure the noise level of STEREO A (L).
MAX -79 dBu or below
MIN -86 dBu or below
195
PM5D/PM5D-RH
Input frequency Output level Permissible range [2] Distortion factor (CH IN 1 - 48)
(2TR IN ANALOG 1L input) (2TR IN ANALOG 1R input) Input frequency Output level Permissible range
1 kHz +23 dBu -57 dBu or below 1 kHz +22 dBu 0.007% or below
Input frequency Output level Permissible range [3] Noise level (CH IN 1 - 48)
(2TR IN ANALOG 1R input) (2TR IN ANALOG 1L input) Parameter: Short CH IN to be measured with 150Ω.
(2TR IN ANALOG 2R input) Permissible range
1 kHz +23 dBu -57 dBu or below -80 dBu or below
Input frequency Output level Permissible range [4] INSERT OUT gain (CH IN 1 - 48)
(2TR IN ANALOG 2L input) (2TR IN ANALOG 1R input) Input frequency Input level Specified output level Permissible range
(2TR IN ANALOG 2R input) 1 kHz +10 dBu +4 dBu +4±1.5 dBu
1 kHz +23 dBu -57 dBu or below
[5] INSERT OUT noise level (CH IN 1 - 48)
Input frequency Output level Permissible range Parameter: Short CH IN to be measured with 150Ω.
(2TR IN ANALOG 2R input) (2TR IN ANALOG 2L input) Permissible range
1 kHz +23 dBu -57 dBu or below -90 dBu or below
2-1-9. CH IN 1 - 48 (PM5D only) [6] Operation check of level meter (CH IN 1 - 48)
Parameter: Use STEREO A (L) for this inspection. Parameters: Input the specified level to the channel to be
Turn of INSERT SW. measured.
It is possible to input to CH 1 - 48 simultaneously.
A. GAIN MAX, PAD OFF Check turning on and off of PEAK and SIGNAL
[1] Gain (CH IN 1 - 48) LEDs visually.
Input frequency Input level Specified output level Permissible range LED ON
1 kHz -60 dBu +4 dBu +4±2 dBu LED level Input frequency Input level Output level as reference
(INSERT OUT)
[2] f characteristic (CH IN 1 - 48) PEAK 1 kHz +29 dBu +23 dBu
Parameter: 1 kHz is used as reference of the permissible range. SIGNAL 1 kHz -2 dBu -8 dBu
Input frequency Input level Permissible range LED OFF
20 Hz -60 dBu -1.5~0.5 dB LED level Input frequency Input level Output level as referecnce
40 kHz -60 dBu -1.5~0.5 dB (INSERT OUT)
PEAK 1kHz +25 dBu +19 dBu
[3] Distortion factor (CH IN 1 - 48) SIGNAL 1kHz -6 dBu -12 dBu
Input frequency Output level Permissible range
1 kHz +22 dBu 0.02% or below C. Phantom voltage (CH IN 1 - 48)
With No.2 and No.3 pins of XLR shorted and 10 kΩ load
[4] Noise level EIN (CH IN 1 - 48) connected between No.2 and No.1 pins, adjust the voltage
Parameter: Short CH IN to be measured with 150Ω. when the phantom switch is turned on as follows.
Permissible range Permissible range
-63 dBu or below DC 33~37V
If the measured value is out of the above permissible range, Also, check that discharging starts quickly when the phantom
check for: switch is turned off.
Measured value - (gain at 1kHz) ≦ -127
2-1-10. ST IN 1 - 4 (L, R) (PM5D only)
[5] Level difference (CH IN 1 - 48) Parameters: Set PAN of the L channel fully to the L side and
Adjust the range of difference in the gain measured in item that of the R channel fully to the R side. Use STEREO
[1] above as follows. OUT A (L) when measuring the L channel and
Permissible range STEREO OUT A (R) when measuring the R channel.
Within 2 dB
A. GAIN MAX
B. GAIN MIN, PAD ON [1] Gain (ST IN 1 - 4 (L, R))
[1] Gain (CH IN 1 - 48) Input frequency Input level Specified output level Permissible range
Input frequency Input level Specified output level Permissible range 1 kHz -34 dBu +4 dBu +4±2 dBu
1 kHz +10 dBu +4 dBu +4±2 dBu
196
PM5D/PM5D-RH
[2] f characteristic (ST IN 1 - 4 (L, R)) 2-1-11. CH IN 1 - 48, ST IN 1 - 4 (L, R) (PM5D - RH only)
Parameter: 1 kHz is used as the reference of the permissible Parameters: Use STEREO A (L) of CH IN 1 - 4 for this
range. inspection. For ST IN 1 - 4 (L, R) inspection, set
Input frequency Input level Permissible range PAN of L channel fully to the L side and PAN of
20Hz -34 dBu -1.5~0.5 dB the R channel fully to the R side. Use STEREO
40 kHz -34 dBu -1.5~0.5 dB OUT A (L) for L channel measurement and
STEREO OUT A (R) for R channel measurement.
[3] Distortion factor (ST IN 1 - 4 (L, R)) A. GAIN MAX
Input frequency Output level Permissible range [1] Gain (CH IN 1 - 48, ST IN 1 - 4 (L, R))
1 kHz +22 dBu 0.015% or below Input frequency Input level Specified output level Permissible range
1 kHz -62 dBu +4 dBu +4±2 dBu
[4] Noise level EIN (ST IN 1 - 4 (L, R))
Parameter: Short CH IN to be measured with 150Ω. [2] f characteristic (CH IN 1 - 48, ST IN 1 - 4 (L, R))
Permissible range Parameter: 1 kHz is used as reference of the permissible range
-65 dBu or below Input frequency Input level Permissible range
If the measured value is out of the above permissible range, 20 Hz -62 dBu -1.5~0.5 dB
check for: 40 kHz -62 dBu -1.5~0.5 dB
Measured value - (gain at 1kHz) ≦ -103
[3] Distortion factor (CH IN 1 - 48, ST IN 1 - 4 (L, R))
[5] Level difference (ST IN 1 - 4 (L, R)) Input frequency Output level Permissible range
Adjust the range of difference in the gain measured in item 1 kHz +22 dBu 0.02% or below
[1] above as follows.
Permissible range [4] Noise level EIN (CH IN 1 - 48, ST IN 1 - 4 (L, R))
Within 2 dB Parameter: Short CH IN to be measured with 150Ω.
Permissible range
B. GAIN MIN -61 dBu or below
[1] Gain (ST IN 1 - 4 (L, R)) If the measured value is out of the above permissible range,
Input frequency Input level Specified output level Permissible range check for:
1 kHz +10 dBu +4 dBu +4±2 dBu Measured value - (gain at 1kHz) ≦ -127
[2] Distortion factor (ST IN 1 - 4 (L, R)) [5] Level difference (CH IN 1 - 48, ST IN 1 - 4 (L, R))
Input frequency Output level Permissible range Adjust the range of difference in the gain measured in item
1 kHz +22 dBu 0.007% or below [1] above as follows.
Permissible range
[3] Noise level (ST IN 1 - 4 (L, R)) Within 2 dB
Parameter: Short CH IN to be measured with 150Ω.
Permissible range B. GAIN MIN
-80 dBu or below [1] Gain (CH IN 1 - 48, ST IN 1 - 4 (L, R))
Input frequency Input level Specified output level Permissible range
[4] Operation check of level meter (ST IN 1 - 4 (L, R)) 1 kHz +10 dBu +4 dBu +4±2 dBu
Parameters: Input the specified level to the channel to be
measured. [2] Distortion factor (CH IN 1 - 48, ST IN 1 - 4 (L, R))
It is possible to input to ST IN 1 - 4 (L, R) Input frequency Output level Permissible range
1 kHz +22 dBu 0.007% or below
simultaneously.
Check turning on and off of PEAK and SIGNAL
LEDs visually. [3] Noise level (CH IN 1 - 48, ST IN 1 - 4 (L, R))
Parameter: Short CH IN, ST IN to be measured with 150Ω.
LED ON
Permissible range
LED level Input frequency Input level Output level as reference -80 dBu or below
(STEREO A)
PEAK 1 kHz +29 dBu +23 dBu
C. Phantom voltage (CH IN 1 - 48, ST IN 1 - 4 (L, R))
SIGNAL 1 kHz -2 dBu -8 dBu
With No.2 and No.3 pins of XLR shorted and 10 kΩ load
LED OFF connected between No.2 and No.1 pins, adjust the voltage
LED level Input frequency Input level Output level as referecnce
when the phantom switch is turned on as follows.
Permissible range
(STEREO A)
PEAK 1kHz +25 dBu +19 dBu DC 33~37V
SIGNAL 1kHz -6 dBu -12 dBu Also, check that discharging starts quickly when the phantom
switch is turned off. 197
PM5D/PM5D-RH
2-2. ANALOG IN/OUT WORD CLOCK INT 48 [2] Residual noise (MONITOR OUT L, R, C)
kHz Inspection Parameter: Turn off MONITOR INSERT.
MONITOR level Permissible range
2-2-1. STEREO A (L, R), STEREO B (L, R) MAX -86 dBu or below
Parameters: Input from INPUT (XLR) of CH1.
Assign CH1 to STEREO A, B. 2-2-5. CUE OUT L, R,
Parameters: Input from INPUT (XLR) of CH1.
[1] Distortion factor (STEREO A (L, R), STEREO B (L, R)) Turn on CUE of CH1.
Input frequency Output level Permissible range Set INPUT CUE to POST PAN.
1 kHz +22 dBu 0.015% or below
[1] Distortion factor (CUE OUT L, R)
[2] Residial noise (STEREO A (L, R), STEREO B (L, R)) Input frequency Output level Permissible range
Parameter: Turn off STEREO A, B. 1 kHz +22 dBu 0.015% or below
Permissible range
-86 dBu or below [2] Residual noise (CUE OUT L, R)
Parameter: Turn off CUE of CH1.
2-2-2. MIX OUT 1 - 24 CUE level Permissible range
Parameters: Input from INPUT (XLR) of CH1 MAX -86 dBu or below
Turn on the channel to be measured only.
Assign CH1 to MIX 1-24 and set all MIX SEND
LEVEL to NOMINAL (0 dB).
198
PM5D/PM5D-RH
2-2-6. PHONES L, R (x2: 2 terminals on the [2] Noise level (ST IN 1 - 4 (L, R))
panel surface and front surface) Parameter: Short CH IN to be measured with 150Ω.
Parameters: Input from INPUT (XLR) of CH1. Permissible range
Assign CH1 to STEREO A. -82 dBu or below
Set MONITOR SOURCE to STEREO A.
Set MONO of PAN NOMINAL POSITION to 2-2-10. CH IN 1 - 48, ST IN 1 - 4 (L, R) (PM5D-
"L ⇔ R". RH only)
Set PAN of CH1 fully to the L side when Parameters: Use STEREO A (L) of CH IN 1 - 4 for this
measuring L and fully to the R side when inspection.
measuring R. For ST IN 1 - 4 (L, R) inspection, set PAN of L
[1] Distortion factor (PHONES L, R (x2)) channel fully to the L side and PAN of the R
Input frequency Output level Permissible range channel fully to the R side. Use STEREO OUT
1 kHz 0 dBu 0.15% or below A (L) when measuring the L channel and
STEREO OUT A (R) when measuring the R
[2] Residual noise (PHONES L, R (x2)) channel.
Parameter: Turn off STEREO A. Set GAIN to MIN.
PHONES level Permissible range [1] Distortion factor (CH IN 1 - 48, ST IN 1 - 4 (L, R))
MAX -79 dBu or below Input frequency Output level Permissible range
1 kHz +22 dBu 0.015% or below
2-2-7. 2TR IN ANALOG 1 (L, R), 2TR IN
ANALOG 2 (L, R) [2] Noise level (CH IN 1 - 48, ST IN 1 - 4 (L, R))
Parameter: Use STEREO A (L) for this inspection. Parameter: Short CH IN to be measured with 150Ω.
[1] Distortion factor (2TR IN ANALOG 1 (L, R), 2TR IN ANALOG 2 (L, R)) Permissible range
Input frequency Output level Permissible range -82 dBu or below
1 kHz +22 dBu 0.015% or below
2-2-11. TALKBACK
[2] Residual noise (2TR IN ANALOG 1 (L, R), 2TR IN ANALOG 2 (L, R)) Parameters: Use STEREO A (L) for this inspection.
Parameter: Short 2TR IN ANALOG 1, 2 with 150Ω. Turn on TALKBACK SW.
Permissible range [1] Distortion factor
-82 dBu or below Input frequency Output level Permissible range
1 kHz +22 dBu 0.015% or below
2-2-8. CH IN 1 - 48 (PM5D only)
Parameter: Use STEREO A (L) for this inspection. [2] Noise level EIN
Turn of INSERT SW. Parameter: Short CH IN to be measured with 150Ω.
Set GAIN to MIN and PAD to ON. Permissible range
-70 dBu or below
[1] Distortion factor (CH IN 1 - 48) If the measured value is out of the above permissible range,
Input frequency Output level Permissible range check for:
1 kHz +22 dBu 0.015% or below Measured value - (gain at 1kHz) ≦ -124
199
PM5D/PM5D-RH
[2] f characteristic (2TR OUT DIGITAL 1) [3] Distortion factor (2TR IN DIGITAL 1)
Parameter: 1 kHz is used as reference of the permissible range Input frequency Output level Permissible range
Input frequency Input level Permissible range 1 kHz +22 dBu 0.006% or below
20 Hz +10 dBu -1.0~0.5 dB
40 kHz +10 dBu -1.0~0.5 dB B. 48 kHz
Parameters: Adjust the frequency (Sample Rate) of System
[3] Distortion factor (2TR OUT DIGITAL 1) Two to 48 kHz.
Input frequency Output level Permissible range Turn off 2TR IN DIGITAL SRC.
1 kHz -2 dBFS 0.005% or below
[1] Distortion (2TR IN DIGITAL 1)
B. WORD CLOCK INT 48 kHz Input frequency Output level Permissible range
Parameters: Adjust WORD CLOCK INT to 48 kHz. 1 kHz +22 dBu 0.02% or below
Turn off 2TR OUT DIGITAL SRC.
C. SRC Operation
[1] Distortion factor (2TR OUT DIGITAL 1) Parameters: Adjust WORD CLOCK INT to 96 kHz.
Input frequency Output level Permissible range Use 2TR OUT DIGITAL 1 for this inspection.
1 kHz -2 dBFS 0.002% or below Set the frequency (Sample Rate) of System Two
to 44.1 kHz.
C. SRC Operation Turn on SRC of the channel to be measured.
Parameters: Adjust WORD CLOCK INT to 96 kHz.
Turn on SRC of the channel to be measured and [1] FS (all of 2TR IN DIGITAL 1, 2, 3)
set the frequency to 44.1 kHz. Input frequency Input level Specified frequency Permissible range
1 kHz -20 dBFS 96 kHz 96 kHz±100 Hz
[1] FS (all of 2TR OUT DIGITAL 1, 2, 3)
Input frequency Output level Specified frequency Permissible range [2] Distortion factor (all of 2TR IN DIGITAL 1, 2, 3)
1 kHz -2 dBFS 44.1 kHz 44.1 kHz±100 Hz Input frequency Output level Permissible range
1 kHz -20 dBFS 0.002% or below
[2] Distortion factor (all of 2TR OUT DIGITAL 1, 2, 3)
Input frequency Output level Permissible range 3-3. WORD CLOCK IN, 2TR IN DIGITAL 1, 2, 3
1 kHz -2 dBFS 0.002% orbelow PLL operation range
Parameters: Use System Two.
3-2. 2TR IN DIGITAL 1, 2, 3 Use STEREO A (L, R) for this inspection.
Parameters: Use System Two. Select WORD CLOCK as follows.
Use STEREO A (L, R) for this inspection. When testing WORD CLOCK: WC IN
Select WORD CLOCK as follows. When testing 2TR IN DIGITAL 1: 2TRD1
When testing 2TR IN DIGITAL 1: 2TRD1 When testing 2TR IN DIGITAL 2: 2TRD2
When testing 2TR IN DIGITAL 2: 2TRD2 When testing 2TR IN DIGITAL 3: 2TRD3
When testing 2TR IN DIGITAL 3: 2TRD3 Input from CH1 IN.
Set GAIN to MIN and PAD to ON (PM5D only).
A. 96 kHz
Parameters: Adjust the frequency (Sample Rate) of System A. 96 kHz+6% (101.76 kHz)
Two to 96 kHz. Parameters: When testing WORD CLOCK IN, set the
Turn off 2TR IN DIGITAL SRC. frequency of the oscillator to 96 kHz + 6%.
When testing 2TR IN DIGITAL 1, 2, 3, set the
[1] Gain (all of 2TR IN DIGITAL 1, 2, 3) frequency (Sample rate) of System Two to 96 kHz
Input frequency Input level Specified output level Permissible range + 6%.
1 kHz -20 dBFS +4 dBu +4±2 dBu [1] Distortion factor
(all of WORD CLOCK IN, 2TR IN DIGITAL 1, 2, 3)
[2] f characteristic (2TR IN DIGITAL 1) Input frequency Output level Permissible range
Parameter: 1 kHz is used as reference of the permissible range 1 kHz +22 dBu 0.006% or below
Input frequency Input level Permissible range
20 Hz -20 dBFS -1.0~0.5 dB
40 kHz -20 dBFS -1.0~0.5 dB
200
PM5D/PM5D-RH
201
PM5D/PM5D-RH
Judgment criteria 1:
The EFFECT sounds must be output.
Judgment criteria 2:
The output should be free from noise.
202
PM5D/PM5D-RH
■ 検査
(2) プログラムの書き込み方法
プログラムの書き込み方法は、 「プログラムのアップデー
1. 準備
ト」 の項を参照してください。
(246ページ)
1-1. 条件
◇特に指定しないときは以下の条件とします。
・WORD CLOCK はINT96kHz にします。 1-3. 初期化
内蔵メモリーを初期化すると、それまでメモリー内に保存
・測定CH のみON とします。
されていた内容が失われます。以下の操作は慎重に行なっ
PAN : センター
てください。
GAIN : MIN
PAD SW (PM5D のみ) : ON
INSERT SW (PM5D のみ) : OFF 1 パネル上のSCENE MEMORY [STORE] キーを押し
FADER : NOMINAL (0dB) ながら、パワーサプライPW800W の電源を入れま
す。
MIX MASTER LEVEL : NOMINAL (0dB)
オープニング画面に続いて、 次の初期化メニュー画
MATRIX MASTER LEVEL : NOMINAL (0dB)
面が表示されます。
MONITOR LEVEL : MAX
CUE LEVEL : MAX
PHONES LEVEL : MAX
TALKBACK LEVEL : MAX
+48V MASTER SW (PM5D-RH のみ): ON
PAN NOMINAL POSITION の
MONO : CENTER
PAIR : L⇔R
・0dBu =0.775Vrms
・0dBFS =0 デシベル・フルスケール
・発振器の出力インピーダンスは150 Ωとします。
・オシロスコープ、レベル計等の入力インピーダンスは
100 kΩ以上とします。
・ノイズ測定は12.7kHz 、−6dB /OCT のLPF で補正し
ます。
(実効値ではなく平均値での測定とします。 )
・歪み測定は80kHz 、 −18dB /OCT のLPF で補正します。
2 希望する初期化方法に応じて、 次のいずれかのボタ
ンをクリックします。
・INITIALIZE ALL MEMORIES
◇アナログ出力の検査時は以下の条件を追加、 変更します。
シーンメモリーやライブラリーを含む、 すべてのメ
・最大出力測定時、特に指定のない場合は内蔵オシレー
モリーを工場出荷時の状態に戻します。
ターから0dB を出力します。
・INITIALIZE CURRENT MEMORIES
・アナログ出力の負荷は、
シーンメモリーやライブラリーを除くメモリーを工
STEREO A ,B (L , R) : 600 Ω
場出荷時の状態に戻します。
MONITOR OUT (L ,R , C): 600 Ω
・CANCEL
CUE OUT (L ,R) : 600 Ω
初期化操作を取り消し、 PM5D を通常モードで起動
MATRIX OUT 1−8 : 600 Ω
します。
MIX OUT 1−24 : 600 Ω
INSERT OUT 1−48 : 10k Ω
Note バックアップ用バッテリーの電圧が低いとき、または内蔵
PHONES (x 2) : 8Ω
メモリーにエラーが発生したときは、画面下部に警告の
とします。 メッセージが表示され、強制的に初期化メニューが表示さ
れます。警告メッセージが表示されたときに、CANCEL ボ
1-2. プログラムのアップデート タンをクリックして通常モードで起動した場合、 正常な動
本体のプログラムが最新バージョンになっていない場合、 作は保証しかねますのでご注意ください。
最新のプログラムにバージョンアップする必要がありま
す。 3 初期化を確認するメッセージが表示されるので、 OK
※ 最新のプログラムは、YSISSホームページよりダウンロー ボタンをクリックします。
ドして、メモリーカードに保存します。 内部メモリーの初期化が終了すると、PM5D が通常
モードで起動します。
(1) 本体のプログラムのバージョン確認方法
パネル上の“DISPLAY ACCESS ”の“UTILITY ”ボタンを
押して、LCD 画面内で“PREFERENCE 2 ”のページを選択
すると、 画面の右側に現在のバージョンが表示されます。 203
PM5D/PM5D-RH
8 キャリブレーションが終了して、フェーダー選択ボ
タンがすべてオフになったのを確認したら、OK ボ
タンをクリックします。
内部メモリーにキャリブレーション設定が保存され
ます。
フェーダー選択ボタンがオン(緑色)のままの場合
は、
キャリブレーションに失敗しています。もう一度
キャリブレーションを実行してみてください。
Note 内 部 メ モ リ ー に 書 き 込 み 中 は 、プ ロ グ レ ス バ ー に
“Writing...”
と表示されますので、 その間は電源を切らない
でください。
2-1-1. STEREO A (L ,
R),STEREO B (L ,R)
条件 CH1 のINPUT (XLR)から入力します。
CH1 をSTEREO A ,B にアサインします。
3 フェーダー選択ボタンをクリックしてチェックマー
(1) 利得(STEREO A (L ,R),
STEREO B (L ,
R))
クを付け、キャリブレーションするフェーダーを指
入力周波数 入力レベル 規定出力レベル 許容範囲
定します。
1kHz +10dBu +4dBu +4±2dBu
起動時のチェックで問題が検出されたフェーダー
は、ボタンがオン(緑色)になっていて、あらかじめ
(2) f 特(STEREO A (L ,
R),
STEREO B (L ,
R))
チェックマークも付いています。
条件 許容範囲は1kHz を基準とします。
入力周波数 入力レベル 許容範囲
4 START CALIBRATION ボタンをクリックすると、
自
20Hz +10dBu −1.5 ∼+0.5dB
動的にキャリブレーションが始まります。 40kHz +10dBu −1.5 ∼+0.5dB
プログレスバーには進行状況が表示されます。
(3) 歪率(STEREO A (L ,R),
STEREO B (L ,
R))
5 進行状況が60%になると自動処理が終わるので、指 入力周波数 出力レベル 許容範囲
定したすべてのフェーダーについて、 以下の順番に 1kHz +22dBu 0.007 %以下
フェーダー位置を手作業で合わせます。
(指標からのずれが±0 . 5 m m 以内になるように (4) 残留ノイズ(STEREO A (L ,R),
STEREO B (L ,R))
フェーダーを手動で合わます。 ) 条件 STEREO A ,B をOFF にします。
許容範囲
q −∞ −86dBu 以下
w − 20dB
e 0dB
r + 10dB
204
PM5D/PM5D-RH
206
PM5D/PM5D-RH
207
PM5D/PM5D-RH
208
PM5D/PM5D-RH
消灯
C .ファントム電圧(CH IN 1−48 ,ST IN 1−4 (L ,
R))
LEDレベル 入力周波数 入力レベル 参考出力レベル
XLR の2 ピンと3 ピンをショートし、2−1 ピン間に10k Ω
(STEREO A)
PEAK 1kHz +25dBu +19dBu 負荷を接続してファントムをON したときの電圧は以下の
SIGNAL 1kHz −6dBu −12dBu ように規定します。
許容範囲
DC33∼37V
ファントムをOFF したとき、速やかに放電を開始すること
を確認します。
209
PM5D/PM5D-RH
(2) 残留ノイズ(PHONES L ,
R (x 2)) (1) 歪率(CH IN 1−48 ,ST IN 1−4 (L ,R))
条件 STEREO A をOFF にします。 入力周波数 出力レベル 許容範囲
PHONES LEVEL 許容範囲 1kHz +22dBu 0.015 %以下
MAX −79dBu 以下
(2) ノイズレベル(CH IN 1−48 ,ST IN 1−4 (L ,R))
2-2-7. 2TR IN ANALOG 1 (L ,
R),
2TR IN ANALOG 条件 測定するCH IN , ST IN を150 Ωでショートします。
2 (L ,R) 許容範囲
条件 STEREO A (L)で検査します。 −82dBu 以下
212
PM5D/PM5D-RH
213
PM5D/PM5D-RH
判定基準 2
ノイズが含まれていないこと。
以下同様にシーン6 からシーン36 をリコールし検聴しま
す。
シーンNo. とEFFECT TYPE は次のとおりです。
シーンNo. EFFECT No. EFFECT TYPE
5 1 Reverb
6 1 Symphonic
7 1 HQ Pitch
8 1 Dynamic Filter
9 2 Reverb
10 2 Symphonic
11 2 HQ Pitch
12 2 Dynamic Filter
13 3 Reverb
14 3 Symphonic
15 3 HQ Pitch
16 3 Dynamic Filter
17 4 Reverb
18 4 Symphonic
19 4 HQ Pitch
20 4 Dynamic Filter
214
PM5D/PM5D-RH
215
PM5D/PM5D-RH
NG NG:WCLK
NG:BNC_WCLK_44K
NG
NG:BNC_WCLK_48K_COUNT=1023
Individual judgment result OK
NO When check result is NG, details are displayed.
(NO appears when there is no (output from target CPU)
communication response)
When check marked here, OK and data being transmitted are displayed for
debugging of this PC program (No check mark when program is started.)
Pressing this key will return to Fig. 2 screen.
Checking will stop temporarily when this key is
pressed and forced to stop when it is pressed during temporarily stop.
Used to start and re-start checking
(restarting after [P/STOP] and operation instructions)
● List of check items (Items subject to general check of digital section and each circuit board check)
216
PM5D/PM5D-RH
4) Cable
CANNON (2TRD 1, 2) male ↔ female : 2
COAXIAL (2TRD 3) : 1
BNC (Word clock) : 2
D-SUB 25 pin (GPI) male ↔ male straight all connected : 1
USB : 1
MIDI : 2
CANNON (SMPTE) male ↔ female : 1
D-SUB 68 pin (CASCADE) male ↔ male straight all
connected : 2
5) Others
PCMCIA Card : 1
TIME CODE generator
(It is recommended to play back the TIME CODE recorded 7) How to start PC
CD with the CD player.) Activate PM5DTST_user.EXE through Windows. Set the
PS/2 keyboard PC MIDI Port on the start-up screen to USB MIDI
PS/2 mouse INTERFACE port. (This setting will remain as set initially.)
TRACK PAD Also, when checking USB, start up MidiMoni.exe.
Tester (to measure the voltage of the voltmeter MY SLOT
CHECK Ver.2 check jig)
217
PM5D/PM5D-RH
8) Connection
Connection diagram for general check
PM5D
OPT
PC
SLOT1
JK2 *1
USB USB
SLOT2 USB
Use the MY SLOT CHECK
Ver.2 jig.
D_SUB 68P(P) - D_SUB 68P(P)
SLOT3 CASCADE Straight Cable
IN
SLOT4
CASCADE
OUT
JK1
MIDI
1 CANNON(P) - CANNONR(R) MIDI Cable USB
Cable IN OUT
2TR DIGITAL
2
IN
MIDI Cable
3 MIDI OUT IN
CANNON(P) - CANNONR(R)
Cable
1 THRU UX96 or UX16
2TR DIGITAL
2
OUT
Pin Plug - Pin Plug D_SUB 9P(P) - D_SUB 9P(P)
3 Cable HA REMOTE
*1: Connect this cable only when testing 1-13 USB MIDI.
OK OK OK:DPRAM DataBUS
OK:SRAM DataBUS
OK OK
218
PM5D/PM5D-RH
OK
OK
OK:SDRAM DataBUS
Both checks are executed on SUBL and SUB R respectively.
219
PM5D/PM5D-RH
Explanation about display when DSP6 and DSP7 are common NG:CASCADE OUT Tx ->
CASCADE IN Rx Rx:0x33,0x44
Same NG display for
NG: CASCADE IN as well
or when the check result is NG
The data of poor reception is displayed.
1) CPU Interface (Data Bus) The transmitted data are
"CASCADE OUT" and "CASCADE IN".
NG: IC401 (1) 0000 0000 XXXX 0000 0000 0000 0000 X00X
MSB LSB
IC number DSP number X= Error bit
by slot OK OK OK OK
NG:SLOT1 CON
NG:SLOT1 COMM Preparation : Input the Time code of the frame rate 30 through
NG:FSMY=xxxx
The check result is NG
Auto when unspecified
OK
NG:SYNC=xxxx
NG:64FS=xxxx
because the transmitted the TIME CODE generator.
OK NG:128FS=xxxx
NG:256FS=xxxx /received data differs from
and exclusive OK
NG:SLOT1 ADDR BUS(A10..A1) 000 X000 00X
the displayed xxx section
OK NG:SLOT1 DATA BUS(D15..D0) 0000 0000 0XXX XXXX
when selected OK
(numeric value).
OK
NG
Example of execution screen
Slot number OK
while checking OK
External time display
(hr: min: sec: frame)
Only Slot 1
is valid.
NG SMPTE=01:23:45.29 sts=x
OK
NG:Non-continual TimeCode Data(Frame)
Slot 1 only (no COMM for others) The right end shows LSB,
indicating the bit of 0-OK, X=NG.
OK NG
221
PM5D/PM5D-RH
1-14 WORD CLOCK test 3) RUN bit (0x40 of Reg4) is checked by writing/reading
Contents : Checks WORD CLOCK OUT → IN automatically DIT, DIR, CDIN, CDOUT.
by counting it at PLLP2.
(Fs=44.1/48/88.2/96kHz) 1-16 PC CARD SLOT test
Checks PLL LOCK by reading the UNLOCK signal Contents : Checks the ATA card inserted in the PCMCIA
when the clock has been stabilized after the FS change CARD slot by writing/reading.
(after about 200ms). Also, checks the control line.
Preparation : Connect WORD CLOCK OUT and IN of the
main unit. Example of execution screen
Example of execution screen
When the check result is NG
OK NG:PC CARD SLOT
NG NG:WCLK OK
NG:BNC_WCLK_48K OK:PC CARD SLOT
OK
NG
OK:DIR_PLL_48K_COUNT When the check result is OK
OK
NG:DBL_PLL_48K_COUNT=220
NG NG:DIO IC114-SO62-->IC651-->IC902
-->IC903-->IC604-->IC101-SI30
OK
OK
OK
OK
Date Time
yy mm dd hh mm ss
1) Note on 2TR IN DIGITAL 1, 2, 3
Although 2TR IN DIGITAL 1, 2 and 2TR IN DIGITAL 3
are connected to SI30 and SI31 of ATSC2 → DSP7 Enter PC Clock Set Cancel
NG:Dpram 0003FFFF
When the check result is OK When checking one P.C.B. is completed, a message appears
Upper 16 bits are ADDRESS 15-0 instructing to change the input to the next channel.
Lower 16 bits are DATA 15-0
BIT HIGH for error
When MANUAL is selected for AD AUTO TEST, a message
appears instructing to change the input to the next channel.
However, as such message does not appear when AUTO is
selected, input signals to all of channels 1 to 48 and STIN in
advance.
223
PM5D/PM5D-RH
1) H character display 4) - 8) Have the entire screen covered in white, red, green,
Used to check vertical and horizontal distortion and frame blue and black and check that there is no dot that is
distortion (whether or not Hs are clearly seen in the frame). black or in any other color.
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
OXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXO
OXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXO
OXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXO
OXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXO
OXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXO
OXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXO
OXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXO
OXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXO
OXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXO
OXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXO
OXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXO
OXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXO
3) Color box
The color changes in gradation from the right to left
growing into black.
Check that the color (4 x 4) other than black is displayed
in gradation properly.
224
PM5D/PM5D-RH
■ サービス検査プログラム
● PM5D テストプログラム 起動画面 (Fig.1)
a. 本テストプログラムはPM5D, PM5D-RHの
「サービス検
画面を閉じる(ツールバーに入る)
査」に使用します。 通信ポート(USB-MIDIポート)の選択 このプログラムの終了
※ テストプログラムは、
YSISSホームページよりダウンロードし (無指定は前回の選択)
てください。
c. 検査共通事項
1) 各テストの個別判定で通信の応答の無い場合は 「通
信エラー」 を表示して個別の判定はNG となります。
2) 検査 1 項目でNG が多数の場合は20 個までとして
いる項目があります。
3) このモデルではPM5DとPM5D-RHがありますが
ボタンをクリックすると
PM5Dと書いてある場合、PM5DとPM5D-RHを示 各検査画面(Fig.2)になります このプログラムの終了
し、PM5D-RHと書いてある場合、
PM5D-RHのみを示 (右上のX ボタンと同じ )
します。
総合検査・シート検査画面例 (Fig.2)
自動検査
項目の選択/非選択
検査結果保存ファイルの絶対パス名の表示
Ver.の表示 判定のクリア Fig.1 画面に戻ります
保存した検査結果を読み込みます
総合判定
NG
Fig.1 画面に戻ります
OK OK
ボタンをクリック OK OK
検査結果を保存します
OK NG
すると個別画面が OK
表示されます OK OK
OK OK
判定がNG の場合
OK OK 項目名が赤色文字になります
OK OK
OK
OK
OK
OK
個別検査の判定結果 AUTO で自動、
・人間(目視など)の判定は検査中に
OK MANUAL で半自動検査
「OK/NG」のボタンを表示して
各項目がNG の場合
押してもらいます
「停止する/しない」の指示をします
・非選択の項はOK/NG 表示が無しです
(デフォルトは停止しません)
全部選択
全部非選択 検査一時停止、停止中に押すと強制終了します
検査開始
NG 項目のみ選択 または続行、開始時全ての判定欄が空欄になります
1) 自動モード:[START]で選択有りの項目を左上から下へ連続実行します。
「STOP on NG 」のチェック有り の場合NG 判定で一時停止します。
[STOP]で一時停止、再度[STOP]で中止、[START/CONTINUE]で続行します。
2) マニュアルモード:Fig.2 でOK/NG が表示されているボタンをクリックすると個別テスト画面が表示さ
れます。
3) 全項目の検査内容とシート毎の検査項目は、 後ページの「検査項目一覧」を参照してください。
4) 各検査の画面で 「検査該当無しの項目」 は文字が消えます(グレーアウト)。
5) 検査結果の保存ファイルは、"保存ファイル名.csv"とします。(総合検査の結果のみ保存)
6) 送受信の結果(Fig.3 右側)をファイルとして保存が可能です(最大30KB )。
ファイル名は"保存ファイル名.txt"となります。
7) AD AUTO TEST, AD TRIM はPM5D-RH でのみ実施できます。
PM5Dの場合はグレーアウトします。
225
PM5D/PM5D-RH
NG NG:WCLK
NG:BNC_WCLK_44K
NG
NG:BNC_WCLK_48K_COUNT=1023
個別判定結果 OK
NO NG の場合詳細を表示します
NO は通信応答無しの場合です (ターゲットCPU からの出力です)
TxData 有りの場合
この項目無し
-- COM ACI 2 Loop 送信しているコマンドも表示します
VER NG:AC_CH2 None Rx_data
** or Communication
判定不要項目 OK:AC_CH2
OkData の場合
OK:も表示します
Disconnect WORD CLOCK
IN BNC cable 目視判定の場合、このBOX を表示します。
作業指示や(赤文字) Check ID
処理中の表示(黒文字)をします
OK NG
OK ボタンとEnter キーは連動します
チェック有りはOK や送信のデータを表示します
このPC プログラムのデバッグ用(プログラム起動時はチェック無し)です
Fig.2 画面に戻ります
検査中断、中断中に押すと強制終了します
検査開始と続行
([ P/STOP] 後や作業指示後の続行)
AutoNext の機能
・Fig.2 の「START] ボタンから検査を開始した場合、AutoNext はON となり、自動で検査が進みます。
・Fig.2 のOK/NG ボタンから検査を開始した場合、AutoNext はOFF となり、Fig.3 では「START] ボタンで検査を開始します。
・NG 項目を再テストしたい場合は、[ P/STOP] 後、AutoNext をOFF にし[ START] ボタンでこの画面の検査をします。
● 検査項目一覧 (デジタル部の総合検査、各シート検査の項目)
項目 検査名称 検査項目の概要 判定
1-1 SRAM SRAM のData Bus,Address Bus のチェック 自動
1-2 DPRAM DPRAM のData Bus,Address Bus のチェック 自動
1-3 SDRAM SDRAM のData Bus,Address Bus のチェック 自動
1-4 BATT バックアップ用電池の電圧を判定 自動
1-5 MAIN-SUB Comm MAIN-SUB 通信をLoopBack し、
送受信を判定 自動
1-6 PLLP2 PLLP2(Master,Slave)のレジスタをW/R し判定 自動
1-7 DSP6,SIO 各DSP6 のレジスタをW/R し判定、SIO 接続判定 自動
1-8 DSP7,SIO,ATSC2 各DSP7 のレジスタをW/R し判定、SIO,ATSC2 接続判定 自動
1-9 REMOTE REMOTE-RS422 端子をLoopBack し、
送受信を判定 自動
1-10 CASCADE CASCADE OUT-->IN の送受信を判定 自動
1-11 SLOT SLOT の各信号と電源電圧の判定 自動
1-12 TIME Code SMPTE :TIME Code 入力を判定 自動
1-13 USB MIDI USB 回路の初期化、
外部PC でLoopBack し判定 半自
1-14 WORD CLOCK WCLK OUT のFs をWCLK IN でカウント、
PLL のLOCK 判定 半自
1-15 2TR IN/OUT(DIO) 2TR IN/OUT DIGITAL をLoopBack し判定 半自
1-16 PC CARD SLOT 制御線の検査、ATA CARD をW/R し判定 自動
1-17 RTC LCD CPU のReal Time Clock の取得、
設定 半自
1-18 LCD CHECK result LCD CPU からKBD,MOUSE の検査結果を取得する 自動
1-19 AD 内蔵AD3 シートのAUTO TEST を行う 自動
226
PM5D/PM5D-RH
項目 検査名称 検査項目の概要 判定
1-20 LCD LCDにテストパターンを表示 目視
1-21 KBD,MOUSE I/F KEYBOARD,MOUSE の検査 目視
1-22 全点灯 全てのLED/7seg/NAME の点灯を確認 目視
1-23 色別点灯 色別に分けたLED/7seg/NAME の点灯を確認 目視
1-24 個別点灯 ブロック/ライン/素子ごとに点灯を確認 目視
1-25 操作子入力/駆動 SW/ENCODER/FADER 入力/駆動を確認 目視
1. 総合検査
準備
1) 被検査物 PM5D 本体 6) PM5D 側起動方法
電源ONしてから5秒以内に[FLIP]と[MIX SEND SEL11]
2) パソコン を押し続けるとテストモードが起動します。
DOS/V パソコン1 台
( P - 2 0 0 M H z 以上, W i n d o w s 9 8 , M E , 2 0 0 0 , X P 、
USBx1,COM1またはCOM2)
YAMAHA USB-MIDI ドライバをインストール済のこと
(インストール時にはPC とPM5D が接続されている必
要があります。 また、
ドライバソフトにPM5D.inf ファイ
ルが必要です。 その他インストールの詳細は、 ドライバ
に付属のReadme.txt や既存製品の取説を参照してくだ
さい。) [FLIP] [11]
3) 検査治具
MY SLOT CHECK Ver.2 検査治具 (AAX59920)
:4 枚
USB MIDI INTERFACE (UX96またはUX16):1台
REMOTE↔RS422検査治具ケーブル:1 本
4) ケーブル
CANNON(2TRD 1,2) オス↔メス:2 本
COAXIAL(2TRD 3):1 本
BNC(Word Clock):2 本
D-SUB 25pin(GPI) オス↔オス ストレート全結線:1 本
USB :1 本
MIDI :2 本
CANNON(SMPTE) オス↔メス:1 本
D-SUB 68pin(CASCADE) オス↔オス ストレート全結線:2 本
5) その他
PCMCIA Card :1 枚
TIME CODE generator
(TIME CODE が録音されたCD をCD プレーヤーで再 7) PC 起動方法
生することを推奨します) Windows からPM5DTST_user.EXE を起動します。
PS/2 Keyboard 起動画面のPC MIDI Port をUSB MIDI INTERFACEの
PS/2 Mouse port に設定します。(設定は最初の1回で良いです)
TRACK PAD またUSBチェック時にはMidiMoni.exeを立ち上げます。
テスター (電圧測定器MY SLOT CHECK Ver.2 検査治
具の電圧を測定)
227
PM5D/PM5D-RH
8) 接続
総合検査接続図
PM5D
OPT
PC
SLOT1
JK2 *1
USB USB
SLOT2 USB
MY SLOT CHECK Ver.2
治具を使用します。
D_SUB 68P(P) - D_SUB 68P(P)
SLOT3
CASCADE Straight Cable
IN
SLOT4
CASCADE
OUT
JK1
MIDI
1 CANNON(P) - CANNONR(R) MIDI Cable USB
Cable IN OUT
2TR DIGITAL
2
IN
MIDI Cable
3 MIDI OUT IN
CANNON(P) - CANNONR(R)
Cable
1 THRU UX96 or UX16
2TR DIGITAL
2
OUT D_SUB 9P(P) - D_SUB 9P(P)
Pin Plug - Pin Plug
3 Cable HA REMOTE
実行画面例 実行画面例
OK OK:DPRAM AddressBUS
OK OK:SRAM AddressBUS
OK OK:DPRAM DataBUS
OK
OK:SRAM DataBUS OK
OK
228
PM5D/PM5D-RH
実行画面例
実行画面例
229
PM5D/PM5D-RH
受信したデータが同一であるか、 また、
RS422 端子か
ら出力したデータとHA REMOTE 端子で受信した
データが同一であるか判定を行います。
NG 1:CPU Interface (Data bus)...
NG NG!IC401(1)TxBusy Error
2:CPU Interface (Data bus)...
NG:IC401(1)0000 XXXX 0000 ...
表示の詳細は下記参照 準備 REMOTE 端子とRS422 端子をREMOTE-RS422検査
治具で接続します。
DSP6 のテスト項目と実行中の表示(右のWindow 内)
1:CPU Interface (Data bus) ... OK
2:CPU Interface (Data bus) ... OK
3:CPU Interface (Chip Select, TXB) ... OK
4:CPU Interface (Address bus) ... OK
5:CPU Interface (BUS W/R Reg.) ... OK 1-10 CASCADE Test
6:DRAM Interface (Data Bus) ... OK 内容 1) CASCADE OUT → CASCADE IN に信号を送り
7:DRAM Interface (Address Bus) ... OK 自動判定します。
8:DRAM Interface (Address Bus & MPR)... OK ID0..6 IN 信号とIN_MSB,IN_2CH はGPI のGPO0..8,
9:SIO Connection ... OK DSP6 → DSP6 のSIO test 12 信号を使用して自動判定します。 したがって、 GPI
A:PIO Connection ... OK DSP6 → DSP6 のSIO test の「GPO LED 」 の判定がNG の場合、 この検査もNG
となります。
DSP7 のテスト項目と実行中の表示(右のWindow 内) 2) LINES はDTR,RTS,MSB/nLSB 2ch/n4ch のライ
1:CPU Interface (Data Bus) OK ンのチェックです。
2:CPU Interface (Chip Select) OK
3:CPU Interface (Address Bus) OK 準備 本体のCASCADE INとOUT をD-SUB 68pinケーブル
4:E-RAM Interface (Data Bus) OK で接続します。
5:E-RAM Interface (Address Bus) OK
6:SIO Connection (DSP7 → DSP6) OK 実行画面例
7:SIO Connection (DSP6 → DSP7) OK
8:SIO Connection (DSP7 → DSP7) OK NG
NG
Check CASCADE WCK
NG:CASI_WC COUNT=xxx
NG:CASO_WC COUNT=xxx NG の場合の表示
9:SIO Connection (ATSC → DSP7)
NG
OK NG
OK
Check CASCADE SIO
NG:CAS_SIO MIX1-2
[W:12345678-->R:1234xxxx]
OK OK
NG:CASCADE SIO
NG:CASCADE MUTE
Check CASCADE Communication
NG:CASCADE OUT Tx ->
CASCADE IN Rx Rx:0x33,0x44
NG:CASCADE IN
も同様なNG :表示
230
PM5D/PM5D-RH
電源電圧を検査します。
NG SMPTE=01:23:45.29 sts=x
入します。
実行画面例
POWER 電圧NG の場合の表示例
NG
以下は他のNG 表示項目例
Check SLOT1 POWER SUPPLY
テスト要否 NG:+20V HIGHER (LOWER)
選択は排他
OK NG:64FS=xxxx (数値)が異なるのでNG
OK NG:128FS=xxxx
NG:256FS=xxxx
OK
OK
NG:SLOT1 ADDR BUS(A10..A1) 000 X000 00X
NG:SLOT1 DATA BUS(D15..D0) 0000 0000 0XXX XXXX
SLOT1 のみ(他はCOMM 無)
テスト中のSLOT 番号 OK
OK
NG
SLOT1 のみ有効 OK
OK 右端がLSB で0=OK,X=NG
のビットを示す 1-13 USB MIDI test
内容 USB を初期化後、PC でソフト的にLoopBack して自
動判定します。
準備 本体のUSB コネクタと外部PC とを汎用のUSB ケー
ブルで接続します。
POWER MANUAL の場合の判定BOX
POWER VOLT
実行画面例
OK NG
NG の場合の表示(受信データ
NG NG:USB LoopBack があれば16 進で表示)
Rxdt=xx xx xx ..
OK
NG
受信できない場合約10 秒後
OK:USB LoopBack にNG:の判定になります
1) SLOT の電源電圧の検査について Rxdt=F5 01 F0 55 00 F7
Ver.2 検査治具の各電圧端子をテスターで測定すること
ができます。
2) SIO(IN=all DSP7)の検査について
SLOT1..4 からのIN1∼4、 IN5∼8、IN9∼12、 IN13∼16 は
DSP7 の#1(ICB01)∼#11(ICB11)のSI12..SI27にそれぞれ 1-14 WORD CLOCK Test
接続されているが、ATSC->DSP7(#1∼#11)検査はDSP7 内容 WORD CLOCK OUT → IN をPLLP2 でカウントし
test で実行済みなので、 ここでは#1(ICB01)のみ検査し て自動判定します。
ます。 (Fs=44.1/48/88.2/96kHz)。PLL のLOCK チェック
3) COM のテストは、31.25Kbpsで 0x00,0x55,0xaa,0xff(計 は、FS 変更後クロックが安定するのを待って(約
4Byte の送受信)です。 200ms 後)、 UNLOCK 信号をRead し判定します。
準備 本体のWORD CLOCK OUTとIN を接続します。
1-12 TIME Code test
内容 受信したTIME Code を間引いて画面に表示します。 実行画面例
経過時間が規定フレーム数(1/30Sec.単位)以上不連
NG NG:WCLK
続の時NG となります(自動判定)。 OK
NG
NG:BNC_WCLK_48K
OK:DIR_PLL_48K_COUNT
OK
経過時間の差が規定値を超えた場合、NG となりま
す(自動判定)。
準備 TIME CODE generator からフレームレート30 の
Time Code を入力します。
231
PM5D/PM5D-RH
Date Time
yy mm dd hh mm ss
test で実行済なので、ここでは#1(ICB01)のみ検査しま
す。
OK NG
2) DIR Lock flag はFPGA にてRead します(SIO 送受信開
始後約100mS 待って判定)。
3) DIT,DIR,CDIN,CDOUT のWrite/Read でRUN bit(Reg4
の0x40)を確認します。
1-18 LCD CHECK result Test
内容 LCD のKeyboard, Mouse, Track Pad, DPRAM の検
査の結果を表示します。
1-16 PC CARD SLOT Test
内容 PCMCIA CARD SLOT に装着されたATA カードを 実行画面例
W/R し、判定します。
また、 制御線の検査を行います。 OK NG:Keyboard NG の場合の表示
OK
OK:Mouse
OK
OK
OK の場合の表示
NG:Dpram 0003FFFF
OK の場合の表示
232
PM5D/PM5D-RH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
1-19 AD Test HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
内容 PM5D-RH のみAD3 シートのAUTO TEST, TRIM を HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
実行します。 HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
準備 CH1-8 に同時に1kHz, +8.75dBmの信号を入力しま HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
す。但し、 1ch毎に検査する場合は+6dBmを入力しま HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
す。 HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
実行画面例 HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
NG Check PLL(IC058,IC059)
NG の場合の表示 HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
EXTWC2 NG!
OK
OK
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
OK
Check FLASH(IC013) OK! OK の場合の表示
HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH
OK
OK
OK
OK
OK
OK 2) 色にじみとゆれ表示
OK
OK
OK
OK
周辺をO 、中にX の文字を表示する。文字がゆれていないか、
O が正しく収まっているか、 色ずれないかをチェックしま
OK
す。 文字及び背景は白黒灰の色を微妙に変えて表示されま
す。
またMOUSE カーソルを重ねてみて影などが出ないことも
チェックします。
OXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXO
OXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXO
いたい場合、 TRIM: 10∼TRIM: 16のうち該当するシートの
OXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXO
箇所のチェックをONにしてSTARTします。 OXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXO
TRIMは1シート終わると次のCHに入力を変えるように OXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXO
メッセージが出ます。 AD AUTO TESTをMANUALにした場 OXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXO
合、次のCHに入力を変えるようにメッセージが出ますが、 OXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXO
OXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXO
AUTO にした場合、メッセージは出ないためCH1∼48, ST
OXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXO
IN 全部に信号を入力しておきます。
OXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXO
OXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXO
OXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXO
233
PM5D/PM5D-RH
3) カラーBOX
右から左にかけてグラデーションして黒になります。
黒以外の4x4 の色がグラデーションして正しく出ることを
チェックします。
4) - 8) 白、
赤、緑、
青、黒 のそれぞれ塗りつぶし、
黒くなって
いたり色が着いたりするドットがないかをチェックしま
す。
234
PM5D/PM5D-RH
■ PANEL TEST
Starting procedure on PM5D side Number of patterns
Within 5 seconds after turning on the power, keep pressing (CHANNEL SELECT SECTION)
[FLIP] and [MIX SEND SEL4] in the ENCODER MODE • INPUT and OUTPUT in that order 2
section to start the panel test. • '■' for each figure of NAME, from left to right. 4
A few seconds later, all LEDs/7seg/NAME light up on both • '8.' for each figure of 7seg, from left to right 2
right and left panels. • 2 figures of 7seg simultaneously, by 1 segment sequentially clockwise 8
([MONO] and [USER DEFINE 4] in the MONITOR section
on the right side panel can be used in the same way to start the (SELECTED CHANNEL SECTION: DELAY, GAIN/ATT, GATE,
HPF, STEREO, COMP)
panel test.)
• '8.' for each figure of 7seg of DELAY, HPF from left to right 3
• 3 figures of 7seg at 2 locations, by 1 segment, clockwise 8
The check items of the P.C.B. to be tested are as follows. Press
• EQ ON, UPPER, LOWER, HPF ON, DELAY ON, GAIN/ATT, φ , TOST in that order 8
any 3 switches simultaneously and release them, and the check
• GAIN/ATT encoder, by cluster of 15 surrounding LEDs 1
item changes sequentially.
• STEREO encoder, by cluster of 15 surrounding LEDs 1
• All LEDs lighting check
• Encoders at 2 locations simultaneously, surrounding LEDs sequentially from left 15
• Lighting by color check • Vertical cluster of 6; GATE GR meters and GATE ON 1
• Individual lighting check • Vertical cluster of 4; HOLD sec, m sec, DECAY sec, m sec 1
• Operational element input/drive check • Vertical cluster of 7; COMP GR meters and COMP ON 1
• Vertical cluster of 2; RELEASE sec and m sec 1
• Horizontal cluster of GATE, COMP GR meters from top down 6
1. LED check • Horizontal cluster of 2; GATE HOLD sec, COMP REL sec 1
• Horizontal cluster of 2; GATE HOLD m sec, COMP REL m sec 1
1-1. All LEDs lighting check • Horizontal cluster of 3; GATE DECAY sec, GATE ON, COMP ON 1
Check visually if all LED/7seg/NAME of the P.C.B. to be • GATE DELAY m sec 1
tested are lit. • '8.' for each figure of GATE, 6 COMP 7seg simultaneously, from left to right 3
With 7seg, check that '8' in all digits are lit. • 7 seg at 6 locations, 3 figures simultaneously, by 1 segment sequentially clockwise 8
With NAME, check that all dots are lit as '■■■■'. • GATE: THRE encoder, by clusters of 15 surrounding LEDs 1
• GATE: RANGE encoder, by clusters of 15 surrounding LEDs 1
1-2. Lighting by color check • COMP: THRE encoder, by clusters of 15 surrounding LEDs 1
As LED/7seg/NAME of the P.C.B. to be tested are lit by color, • COMP: GAIN encoder, by clusters of 15 surrounding LEDs 1
check visually that their colors are correct. • Encoders at 4 locations simultaneously, surrounding LEDs sequentially from left 15
Pressing and releasing any one switch causes the lighting color
to change in the order of red -> orange -> yellow -> green. (SELECTED CHANNEL SECTION: EQ-H, HM, LM, L)
• '8.' for each figure of 7seg at 4 locations simultaneously, from left to right 3
• 7 seg at 4 locations, 3 figures simultaneously, by 1 segment sequentially clockwise 8
1-3. Individual lighting check
• Vertical Q encoders of EQ-H, HM, LM, L 1
As LEDs/7seg/NAME of the P.C.B. to be tested light in
• Vertical GAIN encoders of EQ-L, LM, HM, H 1
specified clusters and order, check visually that they light as
• Encoders at 8 locations simultaneously, surrounding LEDs sequentially from left 1
they should. They light automatically in the specified order
• EQ-H HsF, KHz, Hz in that order 3
but while any one switch is being pressed, the order is reversed.
• EQ-HM KHz, Hz in that order 2
When any 2 switches are pressed simultaneously and released, • EQ-LM KHz, Hz in that order 2
lighting starts from the very beginning pattern. • EQ-L LSF, KHz, Hz in that order 3
The lighting clusters and order are specified as follows.
PN1 P.C.B.
SL P.C.B. Number of patterns (ENCODER MODE SECTION)
(METER SECTION) FLIP 1
• Vertical cluster of 12, sequentially from left to right (CH#1~24) 24 '8.' for each figure of 7seg, from left to right 2
• Horizontal cluster for 12, sequentially from top to bottom (OVER~60) 12 2 figures of 7seg, by 1 segment sequentially clockwise 8
• Horizontal cluster of 2; CH1-24 and MIX 1 PAN, GAIN/ATT, ALT in that order 3
• Horizontal cluster of 4; MIX SEND, MIX MASTER, CH25-48 and PEAK HOLD 1 Vertical cluster of 3; MIX SEND SEL, from left to right 8
Horizontal cluster of 8; MIX SEND SEL, from top down 3
(SELECTED CHANNEL SECTION : GROUP
• Vertical cluster of 8; DCA1 ~ 8 1
• Vertical cluster of 8: MUTE 1 ~ 8 1
• Horizontal cluster of 2; DCA and MUTE, sequentially from top down (1 ~ 8) 8
RCL SAFE at the same time as the 1st one and MUTE SAFE at the same time as the 3rd one
• METER sequentially from top down 12
235
PM5D/PM5D-RH
236
PM5D/PM5D-RH
238
PM5D/PM5D-RH
Input fader 13~24ch (FDB P.C.B.) Input fader 13~24ch (FDB P.C.B.)
Press and release the 13ch PRE switch of CH STRIP Press and release the 13ch PRE switch of CH STRIP section.
section. And then press the CH#15 SEL switch. And then press the CH#17 SEL switch.
DCA 1~8CH, STIN 1~4, ST A, B fader (FDC P.C.B.) DCA 1~8CH, STIN 1~4, ST A, B fader (FDC P.C.B.)
Press and release the 24-48ch switch of CH STRIP Press and release the 24-48ch switch of CH STRIP
section. And then press the B MONO switch of section. And then press the #8 MUTE switch of DCA
STEREO STRIP section.. STRIP section.
When the switch is pressed, the following checks are When the switch is pressed, the following checks are
performed by means of the software. performed by means of the software.
Move from the upper limit to the lower limit by one movement Move toward the 0dB index position in one movement. Check
to measure the time required. Check the measured time the difference between the stop position and the index position
displayed on the name indicator visually. visually. For the acceptable value, refer to the description of
* The check uses the same procedure as Fader check B. General check.
• Fader check D
Input fader 1~12ch (FDA P.C.B.)
Press and release the 1ch PRE switch of CH STRIP
section. And then press the CH#4 SEL switch.
239
PM5D/PM5D-RH
■ パネルテスト
PM5D 側起動方法 パターン数
電源ONしてから5秒以内に左パネルのENCODER MODE (CHANNEL SELECT SECTION )
SECTIONの[FLIP] と[MIX SEND SEL 4]を押し続けると ・INPUT,OUTPUT の順に点灯 2
パネルテストが起動します。 ・NAME を1 桁ずつ、左から右へ '■' を順に点灯 4
数秒後に左右パネルとも、 全LED/7seg/NAME が点灯しま ・7seg を1 桁ずつ、左から右へ '8 .' を順に点灯 2
す。 ・7seg を2 桁同時に、1 セグメントずつ右回りで順に点灯 8
(右側パネルのMONITOR SECTIONの[MONO] と[USER
DEFINE 4] スイッチでも同様にパネルテストが起動します。 ) (SELECTED CHANNEL SECTION :DELAY,GAIN/ATT,GATE,
HPF,STEREO,COMP )
・DELAY,HPF の7seg を1 桁ずつ、左から右へ '8 .' を順に点灯 3
なお検査対象シートの検査項目は以下の通りで、 これらは
・2 箇所の7seg を3 桁同時に、1 セグメントずつ右回りで順に点灯 8
いずれかスイッチ3 ヶを同時に押して放すことで順番に切
・EQ ON,UPPER,LOWER,HPF ON,DELAY ON,GAIN/ATT, φ ,TOST の順に点灯 8
り替わります。
・GAIN/ATT エンコーダーの周囲LED 15 ヶの集まりで点灯 1
・全点灯検査
・STEREO エンコーダーの周囲LED 15 ヶの集まりで点灯 1
・色別点灯検査
・2 箇所のエンコーダーを同時に、周囲LED を左から順に点灯 15
・個別点灯検査
・縦にGATE GR メーター6 ヶとGATE ON の集まりで点灯 1
・操作子入力/駆動検査 ・縦にHOLD sec,msec,DECAY sec,msec の4 ヶの集まりで点灯 1
・縦にCOMP GR メーター、COMP ON の7 ヶの集まりで点灯 1
1. LED検査 ・縦にRELEASE sec,msec の2 ヶの集まりで点灯 1
・横の並びでGATE 、COMP GR メーターを上から下へ順に点灯 6
1-1. 全点灯検査 ・横の並びでGATE HOLD sec,COMP REL sec の2 ヶの集まりで点灯 1
検査対象シートの全LED/7seg/NAME が点灯しているか ・横の並びでGATE HOLD m sec,COMP REL m sec の2 ヶの集まりで点灯 1
目視によって確認します。 ・横の並びでGATE DECAY sec,GATE ON,COMP ON の3 ヶの集まりで点灯 1
7seg は ' 8 .' が全桁分点灯しているか確認します。 ・GATE DELAY m sec を点灯 1
NAME は '■■■■' のように全ドットが点灯しているか ・GATE,COMP 7seg 6 ヶ同時に1 桁ずつ、左から右へ '8 .' を順に点灯 3
確認します。 ・6 箇所の7seg を3 桁同時に、1 セグメントずつ右回りで順に点灯 8
・GATE:THRE エンコーダーの周囲LED 15 ヶの集まりで点灯 1
・GATE:RANGE エンコーダーの周囲LED 15 ヶの集まりで点灯 1
1-2. 色別点灯検査 ・COMP:THRE エンコーダーの周囲LED 15 ヶの集まりで点灯 1
検査対象シートのLED/7seg/NAME が色別に点灯するの
・COMP:GAIN エンコーダーの周囲LED 15 ヶの集まりで点灯 1
で、色違いがないか目視によって確認します。 ・4 箇所のエンコーダーを同時に、周囲LED を左から順に点灯 15
点灯色は、いずれかスイッチ1 ヶを押して放すことで、 赤→
橙→黄→緑 の順に切り替わります。 (SELECTED CHANNEL SECTION :EQ-H,HM,LM,L )
・4 箇所の7seg を同時に1 桁ずつ、左から右へ '8 .' を順に点灯 3
1-3. 個別点灯検査 ・4 箇所の7seg を3 桁同時に、1 セグメントずつ右回りで順に点灯 8
検査対象シートのLED/7seg/NAME が、
決められた集まり ・縦にEQ-H,HM,LM,L のQ エンコーダーを点灯 1
・縦にEQ-L,LM,HM,H のGAIN エンコーダーを点灯 1
で順番に点灯するので、その通り点灯するかを目視によっ
・8 箇所のエンコーダーを同時に、周囲LED を左から順に点灯 1
て確認します。点灯は順番通り自動的に行われます。ただ
・EQ-H HSF,KHz,Hz の順に点灯 3
し、いずれかスイッチ1 ヶを押し続ける間は、 その順番が逆
・EQ-HM KHz,Hz の順に点灯 2
になります。またいずれかスイッチ2 ヶを同時に押して放す
・EQ-LM KHz,Hz の順に点灯 2
と先頭パターンから点灯し直します。
・EQ-L LSF,KHz,Hz の順に点灯 3
点灯の集まりと順番は以下の通りです。
240
PM5D/PM5D-RH
パターン数 パターン数
(MATRIX,MIX SECTION) (SCENE MEMORY,CUE,MONITOR,OSC,TB SECTION)
縦にMATRIX 1 Ch 分の集まりで、#1∼8 へ順に点灯 8 DIRECT RCL/MUTE MASTER のLED を上から順に点灯 10
横の並びでMATRIX #1∼8 のON を点灯 1 PREVIEW を点灯 1
横の並びでMATRIX #1∼8 のDCA 7 を点灯 1 7seg を1 桁ずつ、左から右へ '8 .' を順に点灯 3
横の並びでMATRIX #1∼8 のDCA 8 を点灯 1 7seg を3 桁同時に、1 セグメントずつ右回りで順に点灯 8
横の並びでMATRIX #1∼8 のPAIR を点灯 1 縦にACTIVE:INPUT,DCA,OUTPUT, SOLO,2TRIN:A1,D1,D2,D3, MONI ON の集まりで
横の並びでMATRIX エンコーダーの周囲LED を左から順に点灯 15 点灯 1
横の並びでMATRIX #1∼8 のCUE,SEL の集まりで点灯 1 縦にLAST CUE,MONO の集まりで点灯 1
縦にMIX 1 Ch 分の集まりで、#1∼8 へ順に点灯 8 縦にOUTPUT PFL,2TRIN:A2,STEREO:A,B, DEFINE の集まりで点灯 1
横の並びでMIX #1∼8 のON を点灯 1 縦にOSC ON,TB ON の集まりで点灯 1
横の並びでMIX #1∼8 のTOST,DCA 7 の集まりで点灯 1 ACTIVE INPUT を点灯 1
横の並びでMIX #1∼8 のTOMAT,DCA 8 の集まりで点灯 1 ACTIVE DCA を点灯 1
横の並びでMIX #1∼8 のPAIR を点灯 1 ACTIVE OUTPUT を点灯 1
横の並びでMIX #1∼8 エンコーダーの周囲LED を左から順に点灯 15 横の並びでSOLO,LAST CUE,PUTPUT PFL の集まりで点灯 1
横の並びでMIX #1∼8 のCUE,SEL の集まりで点灯 1 横の並びで2TRIN:A1,A2,の集まりで点灯 1
※上記と同様に MIX #9∼16 についても行います。(28 ) 横の並びで2TRIN D1,STEREO A の集まりで点灯 1
※上記と同様に MIX #17∼24 についても行います。(28 ) 横の並びで2TRIN D2,STEREO B の集まりで点灯 1
OSC ON を点灯 1
PN2-1 シート 横の並びで2TRIN D3,DEFINE の集まりで点灯 1
縦にINPUT 1 Ch 分の集まりで、#1∼12 へ順に点灯 12 横の並びでMONI ON,MONO,TB ON の集まりで点灯 1
横の並びでINPUT #1∼12 のON,PRE を点灯 1
横の並びでINPUT #1∼12 エンコーダーの周囲LED を左から順に点灯 15 (STIN STRIP SECTION)
横の並びでINPUT #1∼12 のTOST を点灯 1 縦にSTIN 1 Ch 分の集まりで、#1∼4 へ順に点灯 12
横の並びでINPUT #1∼12 のCOMP を点灯 1 横の並びでSTIN #1∼4 のON,PRE を点灯 1
横の並びでINPUT #1∼12 のGATE を点灯 1 横の並びでSTIN #1∼4 エンコーダーの周囲LED を左から順に点灯 15
横の並びでINPUT #1∼12 のSEL を点灯 1 横の並びでSTIN #1∼4 のTOST を点灯 1
横の並びでINPUT #1∼12 のネームを1 桁ずつ、左から右へ '■' を順に点灯 4 横の並びでSTIN #1∼4 のCOMP を点灯 1
横の並びでSTIN #1∼4 のGATE を点灯 1
PN2-2 シート 横の並びでSTIN #1∼4 のSEL を点灯 1
※PN2-1 シートと同様です。 横の並びでSTIN #1∼4 のネームを1 桁ずつ、左から右へ '■' を順に点灯 4
241
PM5D/PM5D-RH
PN8シート
STIN STRIP SECTION: STIN #1 ネーム表示器
242
PM5D/PM5D-RH
検査結果の表示
なおDCA 1∼8ch、STIN 1∼4、ST A, Bフェーダーの場合の
FDA 、FDB シート検査の場合は、 フェーダーごとのネーム
み8 本と7 本の2 回に分けて検査を行い、 最後に結果を表示
表示器へ結果を表示します。
します。
FDC シート検査の場合は、 フェーダー14 本に対してネーム
※ 異常時はフェーダーの不良またはフェーダー駆動回路の
表示器が不足するため、P N 4 シート: F A D E R M O D E
不良が考えられます。
SECTION:F スイッチを押すごとにDCA #1∼8 ネーム表示
器へ以下のように交互表示します。
● フェーダー検査B
・DCA #1∼8 フェーダーに対応して、DCA #1∼8 ネーム
インプットフェーダー1∼12ch (FDA シート)
表示器へ表示します。
CH STRIP SECTIONの1chのPREスイッチを押し放した
・STO A,B, STIN #1∼4 フェーダーに対応して DCA #1∼
後にCH#2 SEL スイッチを押します。
6 ネーム表示器へ表示します。 残りDCA#7,8 ネーム表示
器へは“■■■■”を表示します。
インプットフェーダー13∼24ch (FDB シート)
CH STRIP SECTIONの13chのPREスイッチを押し放し
検査の内容は以下の通り。
た後にCH#14 SEL スイッチを押します。
● フェーダー検査A
DCA 1∼8ch、STIN 1∼4、ST A, Bフェーダー(FDC シート)
インプットフェーダー1∼12ch (FDA シート)
CH STRIP SECTIONの24-48chスイッチを押し放した後
CH STRIP SECTIONの1chのPREスイッチを押し放した
にSTEREO STRIP SECTIONのB SELスイッチ押します。
後にCH#1 SEL スイッチを押します。
スイッチを押すことにより、ソフトで以下の検査を行いま
インプットフェーダー13∼24ch (FDB シート)
す。
CH STRIP SECTIONの13chのPREスイッチを押し放し
上限から下限へ一気に移動させ、 かかる時間を測定します。
た後にCH#13 SEL スイッチを押します。
測定を終えると、ネーム表示器へ測定時間を表示するので
目視で確認できます。
DCA 1∼8ch、STIN 1∼4、
ST A, Bフェーダー(FDC シート)
表示形式は秒単位で小数点二位を四捨五入し一位までを表
CH STRIP SECTIONの24-48chスイッチを押し放した後
示します。
にSTEREO STRIP SECTIONのA SELスイッチ押します。
例)0.25 秒の場合→“0.3s”
1 秒までの計測を行えるが、 それを超えたものについて
スイッチを押すことにより、
ソフトで以下の検査を行います。
は "XXXX" と表示します。
ビットパターンを網羅しつつ下限から上限へ向かうよう移
合格値は、0.2 ∼0.4 秒です。
動させ、一回の駆動ごとに目標位置に停止しているかどう
かを検査します。
チェックを終えると、ネーム表示器へ結果を表示するので
目視で確認します。
正常時、
" ok " と表示します。
異常時、
"X???" と表示します。
エラーコードは、ビット対応で複数の内容を表せるように
してあります。
左端は 'X' を固定で表示します。
残り3 桁が16 進表記で以下の内容を表します。
243
PM5D/PM5D-RH
● フェーダー検査C ● フェーダー検査E
インプットフェーダー1∼12ch (FDA シート) インプットフェーダー1∼12ch (FDA シート)
CH STRIP SECTIONの1chのPREスイッチを押し放した CH STRIP SECTIONの1chのPREスイッチを押し放した
後にCH#3 SEL スイッチを押します。 後にCH#5 SEL スイッチを押します。
DCA 1∼8ch、STIN 1∼4、ST A, Bフェーダー(FDC シート) DCA 1∼8ch、STIN 1∼4、ST A, Bフェーダー(FDC シート)
CH STRIP SECTIONの24-48chスイッチを押し放した後 CH STRIP SECTIONの24-48chスイッチを押し放した後
にSTEREO STRIP SECTIONのB MONOスイッチ押し にDCA STRIP SECTIONの#8 MUTE スイッチ押します。
ます。
スイッチを押すことにより、ソフトで以下の処理を行いま
スイッチを押すことにより、ソフトで以下の検査を行いま す。
す。 0dB 指標位置へ一気に移動します。
下限から上限へ一気に移動させ、かかる時間を測定します。 移動を終えた後は、その停止位置と指標とのずれを目視で
測定を終えると、ネーム表示器へ測定時間を表示するので 確認します。
目視で確認します。 合格値は、 総合検査を参照してください。
※ フェーダー検査B による検査と同様です。
● フェーダー検査D
インプットフェーダー1∼12ch (FDA シート)
CH STRIP SECTIONの1chのPREスイッチを押し放した
後にCH#4 SEL スイッチを押します。
スイッチを押すことにより、ソフトで以下の処理を行いま
す。
-20dB 指標位置へ一気に移動します。
移動を終えた後は、その停止位置と指標とのずれを目視で
確認します。
合格値は、 総合検査を参照してください。
244
PM5D/PM5D-RH
With PM5D/PM5D-RH, all the CPU data is included in the CF card in LCD CPU, taking into consideration
the case where the version of each CPU is not appropriate.
1 Prepare a CF card and PC SLOT adapter which are commercially available and the environment (note
type computer with a PCMCIA type 2 slot) that enables loading the data into the CF card.
2 Copy all the contents in the Update card folder into the root directory of the CF card.
3 Insert a CF card into the MEMORY CARD slot and turn on the power.
(After the normal start-up title screen, the data copy mode starts without any splash.)
4 When “COPY” appears on the screen, click the button by using the ENTER key, pad or mouse. Then
uploading starts and the PROGRESS indication advances.
5 When 100% is reached and “Take Out Card & Re-start” message appears, turn off the power and
remove the CF card from the slot.
6 With nothing inserted in the MEMORY CARD slot, turn on the power.
* When this screen does not appear (although the version is appropriate)and rewriting needs
to be done, turn on the power while pressing [SHIFT] and [ENTER] to access to this page.
Displayed on this screen are, the current version on the left and the adequate one on the
right for the version check. The inadequate items are indicated in yellow and red.
8 Select only necessary items by the arrow marked SW and press [UPLOAD SW] using the external
mouse or pad.
9 The PROGRESS indication advances and "Please re-start" appears at the end. Then turn off the power.
When the power is turned on after updating the program, the screen with "INITIALIZE" under "CHECK
SUM ERROR" appears. Then execute "ALL INITIALIZE", and the normal screen will appear. Wait
until the [BUSY] indicator turns off and turn off the power.
245
PM5D/PM5D-RH
■ プログラムのアップデート
注意
プログラムのアップデートを行うと、それまでのユーザーデータが失われます。
プログラムのアップデートを行う前には、PM5D/PM5D-RH内部の全ての設定データをメモリーカードにセー
ブ
(保存)してください。
2 UpdateCard フォルダの
「中身」を全てCF カードのルートディレクトリにCOPY します。
4 「COPY」
と画面に表示されたら、 ENTER, PAD, MOUSEのいずれかを使ってボタンをクリックしま
す。UPLOADが始まり、
PROGRESSが進みます。
5 100%になり
「Take Out Card & Re-start」
の表示が出たら電源を切り、挿入したカードを抜きます。
※ もしこの画面が出ず(バージョンは合っている時で)強制的に書き換えたい時は、SHIFT+ENTER を
押しながら電源を入れるとこのPAGE が出てきます。
VERSION が合っているか、
左に現在、
右にふさわしいものが表示され、
おかしいものは黄色や赤で
表示されます。
8 必要なものだけ矢印のSW を選択し、
UPLOAD SW を外部MOUSE かPAD で押します。
246
PM5D/PM5D-RH
Before installing a card, you must check the Yamaha website to make sure that this device is compatible with this card, and
to verify the number of cards that can be installed in conjunction with other Yamaha or thirdparty cards.
Yamaha website: http:www.yamahaproaudio.com
3 Align the edges of the card with the guard rails inside the slot, and insert the card into the slot.
Push the card all the way into the slot so that the connector at the end of the card is correctly mated with the connector
inside the slot.
4 Use the screws included with the card to fasten the card in place.
Malfunctions or incorrect operation may occur if the card is not fastened.
247
PM5D/PM5D-RH
オプションカードの取り付け
カードを取り付ける前に取り付ける機器本体がこのカードに対応しているか、あるいは他のヤマハまたは
サードパーティー製のカードと組み合わせて何枚まで挿入可能かヤマハのホームページで必ずご確認くだ
さい。
Yamaha ウェブサイト:http://proaudio.yamaha.co.jp
オプションのmini‐ YGDAI カードは次のように取り付けます。
1 電源がオフになっていることを確認します。
2 スロットの固定ネジをゆるめ、スロットカバーを取り外します。
取り外したスロットカバーは、安全な場所に保管してください。
3 スロット内のガイドレールにカードの両端を合わせ、カードをスロットに挿入します。
このとき、カードの端子部分がスロット内部の端子に正しくはまるようカードをいっぱいまで押し込んでください。
4 カードに取り付けられているネジでカードを固定します。
カードが固定されていないと、故障や誤動作の原因となることがありますのでご注意ください。
248
PM5D/PM5D-RH
Here’s how to save individual items of data (or all data) from the PM5D onto a memory card.
1 Insert the memory card into the memory card 4 Use the buttons below the MODE area to se-
slot located on the front panel of the PM5D. lect the item you want to save.
You may insert or remove cards while the PM5D is The item whose button is turned on is selected for
powered-on. saving. (You can turn on only one button.) By clicking
the ALL DATA button you can select all items at once.
These buttons correspond to the following items.
3 In the MODE area, click the BASIC button to If you select the SCENE MEMORY, HA, INPUT PATCH,
select BASIC as the save mode.
or OUTPUT PATCH items, you can specify the starting
If BASIC mode is selected, you can choose the desired
number and ending number so that only the desired
item (or all items) and save them to a memory card.
range of scenes or library items will be saved. The
LINKED LIBRARY button is available only if the SCENE
Hint
The other save modes provided are ADVANCED mode which
MEMORY button is on.
lets you save scene memories or libraries under different num-
bers, and CSV EXPORT mode which lets you save the names of Hint
scene memories or libraries as a CSV format file. The TOTAL SIZE field at the bottom of the MODE area indicates
the file size for the selected item(s). The available capacity of the
inserted memory card is shown below the file list.
249
PM5D/PM5D-RH
Note
• The file list can display only up to one hundred items.
• Saving is not possible if the FILE PATH field exceeds 60 char-
acters (including the filename extension).
250
PM5D/PM5D-RH
メモリーカードに任意のファイルをセーブする
PM5D の任意の項目、またはすべての項目の設定データをメモリーカードにセーブします。
を繰り返し押して、SAVE 画面を表示させます。
ボタン 内容
Hint
保存モードには、このほかにシーンメモリー/ライブラリーの番号 Hint
を変えて保存できるADVANCED モードと、シーンメモリー/ライ 選択されている項目のファイルサイズは、MODE 欄の下にある
ブラリーの名称をCSV 形式ファイルで書き出すCSVEXPORT TOTAL SIZE 欄で確認できます。また、挿入されているメモリー
モードがあります。 カードの空き容量は、ファイルリストの下部で確認できます。
251
PM5D/PM5D-RH
1 つ上のディレクトリーに移動するには、ディレクト
5 保存する項目としてシーンまたはライブラリーを リーの行をクリックして選び(その行がリスト中央に移
動して反転表示になります)、FILE NAME欄に表示さ
選んだ場合は、ボタン右側のボックスを使って開
始番号/終了番号を選択します。 れる“..”をクリックします。
Hint
開始番号 終了番号 ・保存先として選択されているディレクトリーの位置は、リスト
上部のFILE PATH 欄で確認できます。
・ファイルリスト下部のMAKE DIR ボタンをクリックすると、
現在の位置に新規ディレクトリーを作成できます。
Note
・ファイルリストには、100 項目までしか表示されません。
・FILE PATH 欄で60 文字(ファイル名の拡張子も含む)を超える
と、セーブできません。
7 保存元の項目と保存先のディレクトリーを指定し
シーン/ライブラリー名
たら、SAVE ボタンをクリックします。
保存されるデータに名前を付けるFILE NAME EDIT
ウィンドウが表示されます。
6 必要に応じて、保存先のディレクトリー(階層)を
ファイルリストで選択します。
ファイルリストに1 つ下のディレクトリーが含まれる
場合、TYPE欄に“[DIR] ”と表示されます。
8 文字パレットを使ってファイル名を入力し、OK
ボタンをクリックします。
1つ下のディレクトリー 保存を確認するウィンドウが表示されます。
Note
1 つ下のディレクトリーに移動するには、ディレクト ・メモリーカード上のファイルに名前を付ける場合、文字パレッ
リーの行をクリックして選び(その行がリスト中央に移 トの一部の記号やアルファベットの小文字は使用できません。
動し、反転表示されます)、FILE NAME欄に表示され ・別の文字パレットからコピーした文字列をファイル名の入力時
るディレクトリー名をクリックします。 にペーストすると、アルファベットの小文字はすべて大文字に変
換されます。
また、ファイルリストに1 つ上のディレクトリーが含
まれる場合は、FILE NAME欄に“..”、TYPE欄に
“[DIR] ”と表示されます。
9 セーブを実行するには、OK ボタンをクリックし
ます。
1つ上のディレクトリー
セーブの実行中は進行状況を表示するウィンドウが表
示されます。セーブが完了すると元の表示に戻りま
す。なお、OK ボタンの代わりにCANCEL ボタンをク
リックすると、セーブを中断して元の画面に戻りま
す。
メモリーカードにアクセスしている間は、カードの抜
き差しはしないでください。アクセス中は、ディレプレイ右
上にBUSY インジケーターが表示されます。
252
PM5D/PM5D-RH
All of the content that had been saved in memory will 2 Click one of the following buttons to select
be lost if you initialize the internal memory. You must use ex- the desired type of initialization.
treme caution when performing this operation. • INITIALIZE ALL MEMORIES
All memories including scene memories and librar-
1 While holding down the SCENE MEMORY ies will return to their factory-set condition.
• INITIALIZE CURRENT MEMORIES
[STORE] key of the panel, turn on the power
Memories other than scene memories and libraries
of the PW800W power supply.
will return to their factory-set condition.
After the opening screen, the following initialization
• CANCEL
menu screen will appear.
The initialization procedure will be aborted, and the
PM5D will start up in normal operating mode.
Note
If the voltage of the backup battery runs low, or if an error occurs
in the internal memory, a warning message will appear at the
bottom of the screen, and the initialization menu will appear “by
force.” Please note that if the warning message is displayed, and
you click the CANCEL button to start in normal operating mode,
we cannot guarantee that the system will operate correctly.
PM5Dの内蔵メモリーを初期化する
PM5D の内蔵メモリーにエラーが起きたとき、またはシステムパスワードを忘れてしまったために通常操作に戻せなくなっ
たときは、次の操作で内蔵メモリーを初期化できます。
内蔵メモリーを初期化すると、それまでメモリー内に 2 希望する初期化方法に応じて、次のいずれかのボ
保存されていた内容が失われます。以下の操作は慎重に行 タンをクリックします。
なってください。 ・INITIALIZE ALL MEMORIES
シーンメモリーやライブラリーを含む、すべてのメ
1 パネル上のSCENE MEMORY [STORE] キーを押 モリーを工場出荷時の状態に戻します。
・INITIALIZE CURRENT MEMORIES
しながら、パワーサプライPW800W の電源を入
れます。 シーンメモリーやライブラリーを除くメモリーを工
オープニング画面に続いて、次の初期化メニュー画面 場出荷時の状態に戻します。
が表示されます。 ・CANCEL
初期化操作を取り消し、PM5D を通常モードで起動
します。
Note
バックアップ用バッテリーの電圧が低いとき、または内蔵メモ
リーにエラーが発生したときは、画面下部に警告のメッセージが
表示され、強制的に初期化メニューが表示されます。警告メッ
セージが表示されたときに、CANCEL ボタンをクリックして通
常モードで起動した場合、正常な動作は保証しかねますのでご注
意ください。
3 初期化を確認するメッセージが表示されるので、
OK ボタンをクリックします。
内部メモリーの初期化が終了すると、PM5D が通常
モードで起動します。
253
PM5D/PM5D-RH
WARNING MASSAGES
These are messages displayed in the lower part of the screen. They will disappear after a certain duration has elapsed.
Message Meaning
No data has been stored in the scene you attempted to recall, or the data has been damaged so that it
#xxx of Scene is Empty!
cannot be recalled.
#xxx of Scene is Read Only! You attempted to overwrite (store) a read-only scene.
#xxx of Scene is Protected! You attempted to overwrite (store) a protected scene.
Cannot Undo! You pressed the SCENE MEMORY [UNDO] key when Undo was not available.
You clicked an unavailable (grayed-out) grid in the patch screen, or pressed an invalid key on the panel
Cannot Assign!
(e.g., a DCA/MUTE assign key that is unavailable due to the selected channel).
Cannot Drop! You attempted to drop a EQ/compressor/gate/EQ/effect mini-graph onto a location of a different type.
Pair Made. You used a panel operation to assign channel pairing.
Pair Broken. You used a panel operation to cancel channel pairing.
CUE was defeated because you switched to another screen from the EQ PARAM or EFFECT ASSIGN
EFFECT CUE: Turned Off.
screen, or because you switched the selected effect.
KEY IN CUE was defeated because you switched from the GATE PRM/COMP PRM screen to a
KEY IN CUE: Turned Off.
different screen.
In the EVENT LIST screen you input an event at the same time as a previously-input event, so the
Overwrite Existing Event.
existing event was overwritten.
In the EVENT LIST screen, the event list is full; the last event in the event list was pushed out and deleted
Event List Full! Last Event cancelled.
when you added a new event.
The event you are attempting to input in the EVENT LIST screen is too close to an existing event earlier
Interval from Previous Event is Too Short!
than that location, so it is possible that it may not be recalled at the time you intend.
The time code that was input in the EVENT LIST screen has experienced a frame jump or is running
TIME CODE: Frame Jump!
backward.
The incoming time code has a frame rate that is different than the time code specified in the EVENT LIST
TIME CODE: Frame Mismatch!
screen.
MIDI: Data Framing Error! Invalid signals are being input to the MIDI IN connector.
MIDI: Data Overrun! Invalid signals are being input to the MIDI IN connector.
MIDI: Rx Buffer Full! Too much data is being received at the MIDI IN connector.
MIDI: Tx Buffer Full! Too much data is being sent from the MIDI OUT connector.
USB: Data Framing Error! Invalid signals are being input from the USB connector input port.
USB: Data Overrun! Invalid signals are being input from the USB connector input port.
USB: Rx Buffer Full! Too much data is being received at the USB connector input port.
USB: Tx Buffer Full! Too much data is being sent from the USB connector output port.
SLOT x: Data Framing Error! Invalid signals are being input from the SLOT x input port.
SLOT x: Data Overrun! Invalid signals are being input from the SLOT x input port.
SLOT x: Rx Buffer Full! Too much data is being received at the SLOT x input port.
SLOT x: Tx Buffer Full! Too much data is being sent from the SLOT x output port.
RS422: Data Framing Error! Invalid signals are being received at the HA REMOTE connector or RS422 REMOTE connector.
RS422: Data Overrun! Invalid signals are being received at the HA REMOTE connector or RS422 REMOTE connector.
RS422: Rx Buffer Full! Too much data is being received at the HA REMOTE connector or RS422 REMOTE connector.
RS422: Tx Buffer Full! Too much data is being transmitted from the HA REMOTE connector or RS422 REMOTE connector.
CASCADE: Data Framing Error! Invalid signals are being input to the CASCADE IN/OUT connector.
CASCADE: Data Overrun! Invalid signals are being input to the CASCADE IN/OUT connector.
CASCADE: Rx Buffer Full! Too much data is being received at the CASCADE IN/OUT connector.
CASCADE: Tx Buffer Full! Too much data is being transmitted from the CASCADE IN/OUT connector.
DME Control: Data Framing Error! Invalid signals are being input during communication with the DME.
DME Control: Data Overrun! Invalid signals are being input during communication with the DME.
DME Control: Rx Buffer Full! Too much data is being received during communication with the DME.
DME Control: Tx Buffer Full! Too much data is being transmitted during communication with the DME.
The PM5D cannot synchronize because the source selected by MASTER CLOCK SELECT in the
Wrong Word Clock!
WORD CLOCK screen is not appropriate.
Sync Error! [xxxx] The xxxx signal is not synchronized with the PM5D.
xxxx No Signal Present! The xxxx signal is not being input.
Data Type Conflict! Canceled. You attempted to execute a library recall or channel copy operation on a different type of channel.
HA Type Conflict! Data Ignored. You attempted to recall a HA library of a different model (PM5D model or PM5D-RH model).
The parameter you assigned to the FADER START function or to a User Defined key is the same as an
Conflicting GPI OUT Cancelled.
existing GPI OUT assignment, so the GPI OUT assignment was cancelled.
Conflicting USER DEFINED KEY The parameter you assigned to GPI OUT is the same as an existing User Defined key assignment,
Cancelled. so the User Defined key assignment was cancelled.
The parameter you assigned to GPI OUT is the same as an existing FADER START function, so the
Conflicting FADER START Cancelled.
FADER START assignment was cancelled.
Wrong Password! The system password or console password you input was incorrect.
System Password Changed. The system password has been changed.
Console Password Changed. The console password has been changed.
254
PM5D/PM5D-RH
Message Meaning
Parameter Locked. Parameter Lock has been enabled.
Parameter Unlocked. Parameter Lock has been defeated.
This Parameter is Locked. The parameter you attempted to control is locked.
Channel Copied. The selected channel settings were copied to the memory buffer.
Channel Pasted. The channel settings in the memory buffer were pasted to the selected channel.
Nothing to Paste! Paste cannot be performed because there is no data in the memory buffer.
Cannot Paste to Different Channel Type. Paste cannot be performed because you are attempting to paste channel settings of a different type.
No Card in Slot! No memory card is inserted in the MEMORY CARD slot.
The memory card already contain a file/directory with the same name as the one you are attempting to
File Already Exist!
save, rename, or create.
Saving Aborted. Saving to memory card was aborted.
Loading Aborted. Loading from memory card was aborted.
No Controllable Gain. You attempted to operate a gain knob that is currently disabled on the panel.
Tap Operation Ignored. Tap operation was ignored because the TAP TEMPO button is not displayed in the screen.
Cascade Unit Disconnected. The connection with a cascade-connected external device was broken.
Additional Cascade Unit Detected. A cascade-connected external device was newly detected.
Incorrect Cascade Connection! The connection is not appropriate for the cascade settings.
The cascade-connected slave console was unable to store the scene because the scene was protected on
Couldn’t Store Scene on Slave Console!
the slave console, or for some other reason.
The cascade-connected slave console was unable to edit the scene because the scene was protected on
Couldn’t Edit Scene on Slave Console!
the slave console, or for some other reason.
DME Disconnected. The connection with an external DME was broken.
No Response from External HA. No response from an external AD8HR or AD824.
Processing Aborted. A process was aborted.
ERROR MASSAGES
These are messages displayed as popup windows in the center of the screen.
After noting the content of the message, click the OK button in the screen to close the popup window.
Message Meaning
Cannot Store! Failed to store a scene memory or library.
Cannot Recall! Failed to recall a scene memory or library.
Memory Card Full! You attempted to save a file that was larger than the available capacity of the memory card.
File Not Found! The file/directory does not exist on the memory card.
Couldn’t Read File. Failed to read the file from the memory card.
Couldn’t Write File. Failed to write the file to the memory card.
Couldn’t Delete File. Failed to delete the memory card file.
Couldn’t Open File. Failed to open the file from the memory card.
Couldn’t Close File. Failed to close the file on the memory card.
Unsupported File Format! The file you attempted to load from the memory card is of an unsupported format.
No Files to Upload! Internal memory does not contain files to upload.
Low Battery! The backup battery voltage is low.
Power Supply has Malfunctioned! A problem has occurred with the PW800W power supply connected to the PM5D.
Total Slot Power Capability Exceeded! The I/O cards installed in the slots exceed the rated power capacity.
255
PM5D/PM5D-RH
ワ−ニングメッセージ
画面下部に表示されるメッセージです。一定時間が経過すると消えます。
メッセージ 概要
256
PM5D/PM5D-RH
メッセージ 概要
エラーメッセージ
画面中央にポップアップ表示されるメッセージです。メッセージ確認後、画面上のOKボタンをクリックすると、ポップアップは閉
じます。
メッセージ 概要
Cannot Store! シーンメモリーやライブラリーのストアに失敗した。
Cannot Recall! シーンメモリーやライブラリーのリコールに失敗した。
Memory Card Full! メモリーカードの空き容量よりも大きなファイルを保存しようとした。
File Not Found! メモリーカードにファイル /ディレクトリーが存在しない。
Couldn’t Read File. メモリーカードからファイルを読み込めなかった。
Couldn’t Write File. メモリーカードにファイルに保存できなかった。
Couldn’t Delete File. メモリーカードのファイルを削除できなかった。
Couldn’t Open File. メモリーカードでファイルを開くことができなかった。
Couldn’t Close File. メモリーカードでファイルを閉じることができなかった。
Unsupported File Format! メモリーカードから対応していないフォーマットのファイルを読み込もうとした。
No Files to Upload! アップローダーが本体内に保存されていない。
Low Battery! バックアップバッテリーの電圧が下がっている。
Power Supply has Malfunctioned! PM5Dに接続されているパワーサプライPW800Wに何らかの異常が発生した。
Total Slot Power Capability Exceeded! スロットに装着されている I/O カードの消費電力が規定値を超えた。
257
PM5D/PM5D-RH
Default X 1, 3
Mode Messages X X Memorized
Altered ************** X
Note X 0–127
:True Voice
Number ************** X
Note On X O
Velocity Effect Control
Note Off X O
After Key’s X X
Touch Ch’s X X
Pitch Bend X X
System Exclusive O *1 O *1
:Song Pos X X
System
:Song Sel X X
Common
:Tune X X
System :Clock X O
Effect Control
Real Time :Commands X X
258
PM5D/PM5D-RH
This section explains the format of the data that the PM5D is able to understand, send, and receive.
In addition to the messages described here, you can use the MIDI REMOTE function or the MIDI EVENT settings of the
SCENE function to transmit any type of command.
259
PM5D/PM5D-RH
Bulk Dumps can be received at any time, and can be transmitted at any time
when a Bulk Dump Request is received.
A Bulk Dump is transmitted on the [Rx CH] channel in response to a Bulk
Dump Request.
In the data portion, seven words of 8-bit data are converted into eight words of
7-bit data.
[Conversion from actual data to bulk data]
d[0. 6]: actual data
b[0. 7]: bulk data
b[0] = 0;
for( I=0; I<7; I++){
if( d[I]&0x80){
b[0] |= 1<<(6-I);
}
b[I+1] = d[I]&0x7F;
}
260
PM5D/PM5D-RH
[Recovery from bulk data to actual data] 4.2 Current Scene, Setup, Backup, Window control,
d[0. 6]: actual data Input Patch, Output Patch, HA Data
b[0. 7]: bulk data
for( I=0; I<7; I++){ – Parameter request –
b[0] <<= 1; 4.2.1 Format
d[I] = b[I+1]+(0x80&b[0]);
Reception
}
This message is received if [Parameter change RX] is ON and [Rx CH] matches
the Device number included in the SUB STATUS.
This message is echoed if [Parameter change ECHO] is ON.
3.3 PARAMTER CHANGE When this is received, the value of the specified parameter is transmitted as a
Reception Parameter Change.
This message is echoed if [Parameter change ECHO] is ON. STATUS 11110000 F0 System exclusive message
This message is received if [Parameter change RX] is ON and [Rx CH] matches Manufacture’s ID number (YAMAHA)
ID No. 01000011 43
the Device number included in the SUB STATUS. When a parameter change is
SUB STATUS 0001nnnn 3n n=0-15 (Device number=MIDI Channel)
received, the specified parameter will be controlled. When a parameter request
is received, the current value of the specified parameter will be transmitted as a GROUP ID 00111110 3E Digital mixer
parameter change with its Device Number as the [Rx CH]. MODEL ID 00001111 0F PM5D
4.6.2 Effect module names 4.8 Time Counter Data – Time Code –
MODULE NAME channel 4.8.1 Format (Parameter change)
Freeze Play button "FRZPLAY_" 0:Effect1 - 7:Effect8 When transmission is enabled by receiving a Remote Time Counter request,
Freeze Record button "FRZREC__" 0:Effect1 - 7:Effect8 Time Counter data is transmitted at 50 ms intervals for a duration of ten
seconds. If you want counter data to be transmitted continuously, you must
Nothing will happen if the Effect Type is different.
transmit a Request at intervals of no longer than ten seconds.
Reception
4.7 Level Meter Data – Parameter change – This message is echoed if [Parameter change ECHO] is ON.
Transmission
4.7.1 Format (Parameter change)
When transmission is enabled by a request, Time Counter data is transmitted
Once a Level Meter Request is received to enable transmission, the specified
for a specific duration.
meter data will be transmitted at 50 msec intervals for a duration of ten seconds.
Transmission is disabled when the power is cycled, or when PORT settings are
If you want meter data to be transmitted continuously, you must transmit a
changed.
Request at intervals of no longer than ten seconds.
If [Parameter change ECHO] is ON, the message is transmitted without change.
Reception
STATUS 11110000 F0 System exclusive message
This message is echoed if [Parameter change ECHO] is ON.
ID No. 01000011 43 Manufacture’s ID number (YAMAHA)
Transmission
SUB STATUS 0001nnnn 1n n=0-15 (Device number=MIDI Channel)
Once transmission is enabled by a Request, the meter data specified in the
GROUP ID 00111110 3E Digital mixer
Address will be transmitted on the [Rx CH] channel at a specific interval for a
specific duration. (The transmission interval and the duration of transmission MODEL ID 00001111 0F PM5D
will differ between models of device.) DATA 00101011 2b Time Counter TC
Transmission is disabled when the power is cycled, or when PORT settings are CATEGORY
changed. DATA 0ddddddd dd Hour
If [Parameter change ECHO] is ON, the message is transmitted without change. 0ddddddd dd Minute
STATUS 11110000 F0 System exclusive message 0ddddddd dd Second
ID No. 01000011 43 Manufacture’s ID number (YAMAHA) 0ddddddd dd Frame
SUB STATUS 0001nnnn 1n n=0-15 (Device number=MIDI Channel) EOX 11110111 F7 End of exclusive
GROUP ID 00111110 3E Digital mixer
MODEL ID 00001111 0F PM5D
4.8.2 Format (Parameter request)
DATA 00100001 21 REMOTE LEVEL METER
CATEGORY Reception
DATA 0mmmmmmm mm ADDRESS UL (See 4.7.3) This message is received if [Parameter change RX] is ON and [Rx CH] matches
0mmmmmmm mm ADDRESS LU the Device number included in the SUB STATUS. This message is echoed if
[Parameter change ECHO] is ON.
0mmmmmmm mm ADDRESS LL
When this message is received, Time Counter data is transmitted on the [Rx
0ddddddd dd Data1 H (See 4.7.5) *1 CH] channel for a specific duration.
0ddddddd dd Data1 L If a message is received with 0x7F as the second byte of the Address, data
: : transmission will be stopped (disabled) immediately.
EOX 11110111 F7 End of exclusive Transmission
*1 Two types of meter data are provided; data that uses the decay value If [Parameter change ECHO] is ON, the message is transmitted without change.
of the DSP as-is, and data that is converted via a table according to
STATUS 11110000 F0 System exclusive message
the number of segments in the meter display.
ID No. 01000011 43 Manufacture’s ID number (YAMAHA)
SUB STATUS 0011nnnn 3n n=0-15 (Device number=MIDI Channel)
4.7.2 Format (Parameter request) GROUP ID 00111110 3E Digital mixer
Reception MODEL ID 00001111 0F PM5D
This message is received if [Parameter change RX] is ON and [Rx CH] matches DATA 00101011 2b Time Counter TC
the Device number included in the SUB STATUS. This message is echoed if CATEGORY
[Parameter change ECHO] is ON. DATA 0ddddddd dd 0: Request transmission
When this is received, the meter data specified in the Address is transmitted on 0x7F: Request stop transmission
the [Rx CH] channel at a specific interval for a specific duration. EOX 11110111 F7 End of exclusive
If this is received with an Address UL = 0x7F, transmission of all meter data will
stop (will be disabled) immediately.
Transmission
If [Parameter change ECHO] is ON, the message is transmitted without change.
STATUS 11110000 F0 System exclusive message
ID No. 01000011 43 Manufacture’s ID number (YAMAHA)
SUB STATUS 0011nnnn 3n n=0-15 (Device number=MIDI Channel)
GROUP ID 00111110 3E Digital mixer
MODEL ID 00001111 0F PM5D
DATA 00100001 21 REMOTE LEVEL METER
CATEGORY
DATA 0mmmmmmm mm ADDRESS UL (See 4.7.3)
0mmmmmmm mm ADDRESS LU
0mmmmmmm mm ADDRESS LL
0ccccccc ch Request Ch Total Number H
0ccccccc cl Request Ch Total Number L
EOX 11110111 F7 End of exclusive
265
DIGITAL MIXING CONSOLE
PM5D/PM5D-RH
PARTS LIST
CONTENTS(目次)
PM5D OVERALL ASSEMBLY(PM5D 総組立)................................................... 2
PM5D-RH OVERALL ASSEMBLY(PM5D-RH 総組立) ..................................... 14
PM5D REAR TOP 1 ASSEMBLY(PM5Dリアトップ1 Ass’y)......................... 26
PM5D-RH REAR TOP 1 ASSEMBLY R(PM5D-RHリアトップ1 Ass’y R) ..... 27
PM5D REAR TOP 2 ASSEMBLY(PM5Dリアトップ2 Ass’y)......................... 28
PM5D-RH REAR TOP 2 ASSEMBLY R(PM5D-RHリアトップ2 Ass’y R)..... 29
PM5D-RH REAR TOP 3 ASSEMBLY R(PM5D-RHリアトップ3 Ass’y R)..... 30
BOTTOM CHASSIS ASSEMBLY 3(ボトムシャーシ Ass’y 3) ......................... 31
PANEL 1 ASSEMBLY(パネル1 Ass’y) ............................................................. 32
PANEL 2 ASSEMBLY(パネル2 Ass’y) ............................................................. 40
PN3 ASSEMBLY(PN3 Ass’y)........................................................................... 48
PN4 ASSEMBLY(PN4 Ass’y)........................................................................... 49
PN6 ASSEMBLY(PN6 Ass’y)........................................................................... 50
LCD ASSEMBLY(LCD Ass’y)........................................................................... 51
ELECTRICAL PARTS(電気部品) .............................................................. 52~192
WARNING
Components having special characteristics are marked and must be replaced with parts having
specification equal to those originally installed.
印の部品は、安全を維持するために重要な部品です。交換する場合は、安全のために必ず指定の部品をご
使用ください。
PM5D/PM5D-RH
1000 300
900 800
890 200
810
430 805
800
275
420 15 810
30 800 275
500 3500 470 18
485 470
490 1040
450 470
210
459 480
470 459 465 190
458
457
454 1035 1030
1060 275
450 456
2120 1050
15
460 2100
440 18
452
2110
PM5D/PM5D-RH
1310
1310
1300
1305
170
150
140
160
1370
1380
(x8)
1290
130 1290
1320 120
2700
50 270
1280
125
1380
45 50
230 250
260
240
1380
1320
1320
40
50 215
1800
220
1810 40b
1800 40a
1810 50
45
3
PM5D/PM5D-RH
1470
Panel 1
assembly:
(パネル1 Ass'y)
See page 32.
1410
1400
1405 1450 2550 X2
1410 1470
1460
1440
1430
1431
1435 1430
1420
Panel 2
1432 assembly:
(パネル2 Ass'y)
See page 40.
1340
1330
Rear top 1
assembly:
(リアトップ1 Ass'y)
See page 26. 1330
1330
1330
1360 Rear top 2
assembly:
(リアトップ2 Ass'y)
See page 28.
1350
1390
4
PM5D/PM5D-RH
1920
390
JK1 - AN13
After mount 365
(マウント後) 344 740
PIC.12 PIC.8
PIC.1 PIC.10 PIC.11 PIC.3 PIC.4 PIC.6 PIC.9 PIC.7
PIC.5 584
PIC.2
PIC.5
Overall view of bottom wiring (before mounting the rear top)
(ボトム配線全体図(リア上マウント前))
354 352 1920
351
504
348
1910
502 350
346
PIC.2
PIC.1
1930 910 970 940 930 920 2300 820 854 852 850
1930
1930
962
1940 830
960
840
2310
1500
950
1510
PIC.6 PIC.7
1920 1920 1940 1920
5
PM5D/PM5D-RH
1920 1940
1920
PIC.8
A view
PIC.5
1920
775 1960
1900
1900
PIC.9-2
PIC.10
PIC.9-1 1990 1500
1910 1510
775 632
1960
1930
1900
PIC.11 PIC.12
1920 1990 1500
6
PM5D/PM5D-RH
1720
410
1500 X4
2280
2290
2270
2260
2250 1510 1520
FR 2240
ON X9
T
Fairing figure for rear top connector
PIC.16
(リア上線材整形図)
2200
2210 2220 2230
2000 2000
PIC.16 PIC.17
PIC.17
1960
1960
PIC.19
1970
PIC.18
7
PM5D/PM5D-RH
B 2600
1500
1500 PIC.20
512
PIC.21
B view
1070 1610 1090
PIC.21 PIC.20
434
506
1500
1500
PIC.28
PIC.22
1670
1080 1500 1500 2000
1960 1970
PIC.22
PIC.24
1970
PIC.29
PIC.23
1510
3500
PIC.23
1920
1960
PIC.29
1670
PIC.28
8 PIC.24
PM5D/PM5D-RH
PIC.26
510
PIC.25
1920
PIC.25
1500
2000
584
1970
PIC.26
PIC.27
1940
9
PM5D/PM5D-RH
10
PM5D/PM5D-RH
11
PM5D/PM5D-RH
12
PM5D/PM5D-RH
ACCESSORIES 付 属 品
V9810000 Lamp 12V 5W JL316A0-18" ラ ン プ 1 2 V 3 16
* a AAX58120 Lamp Shade ラ ン プ シ ェ ー ド 3
* b AAX58130 Bulb 12V/DC 5W 電 球 3
* X4459A00 CD-ROM 650MB 12cm C D − R O M
* WC383900 DC Power Supply Cable UL2464 #16X24 L=3600 電 源 ケ ー ブ ル
TOOLS 工 具
* WB477100 Support JIG 2-R RIGHT サポートJIG 2−R
* WB477200 Support JIG 2-L LEFT サポートJIG 2−L
* WB477300 Support JIG 1-R RIGHT サポートJIG 1−R
* WB477400 Support JIG 1-L LEFT サポートJIG 1−L
L R L R
13
14
PM5D/PM5D-RH
80 1660 400
1260
250 20 440
660 1530
370 1330
1190 1400 1300
380 1520 1230
1285 410 1445
430 1290
70
1280 1270
150
170 965 1250 1445 380
1150
970 920 80
930 1170 1445
1010 1410 140
1170 90 70
930 960
1445 (x10)
2760
1440 370
940 1070
380
1060 980 140
1320 1440
950 110 100
1070 1440
1345
Bottom chassis assembly 3: 1340
(ボトムシャーシAss'y 3) 1320
610 See page 31.
1430
10
1440 1340
1430 270
1350 1345
610
1340
360
15 1350
600
18 1340 360
30
840 3500
810
815 810
830 710 810 1590
820 280
780
810 770 760 805 260
750 1570
730 1580 360
1610
700 18
720
2710
PM5D/PM5D-RH
1690
1690
1670
1680
240
1730 1740
220
210 1730 1740
1730a
230 1730a
1710
1720 1664
(x8) 1730 1740
1664
200 1730a
1700 180
50 350 3000
1662
190
1720
45 50 310 330
340
320
1720
1700
1700
40
50
290
2400 300
40b
2410
2400 40a
2410 50
45
15
PM5D/PM5D-RH
2000
Panel 1
assembly:
(パネル1 Ass'y)
See page 32.
1910
1900
1915
1970
1910
2000
1960
1930 1990
1935 1980
1950 1930
1920
Panel 2
1940 assembly:
(パネル2 Ass'y)
See page 40.
1760
1750
1770
1750
Rear top 1
assembly R:
(リアトップ1 Ass'y R)
See page 27.
37.
1752 Rear top 3
assembly R:
(リアトップ3 Ass'y
Ass'y)R)
See page 30. 1790
Rear top 2
1780 assembly R:
(リアトップ2 Ass'y R)
See page 29.
1800
16
PM5D/PM5D-RH
2760
560
530
1850
PIC.12
PIC.5
PIC.8 1080
PIC.2
Overall view of bottom wiring (before mounting the rear top) PIC.5
(ボトム配線全体図(リア上マウント前)) 510 500 2760
490
860
470
2575
850 480
460
PIC.2
PIC.1
2770 1450 1510 1480 1470 1460 2730 1360 1392 1390
2770 1388
2770
1502
1370
2800
1500
1380
2740
2100
1490
2780
PIC.6 PIC.7
2760 2800 2760
17
PM5D/PM5D-RH
2760 2800
2760
2760
PIC.8
A view
PIC.5
1310
2500
2575
2500
2780
2590
2100 PIC.10
PIC.9
2590 2100
1310 1180
2760 2760
2560
PIC.11 PIC.12
18
PM5D/PM5D-RH
2560
PIC.16 PIC.17
2760
2760
PIC.18
2780
1840 2560
PIC.19
2570 2780
PIC.18
Overall view of bottom wiring (after mounting the rear top)
(ボトム配線全体図(リア上マウント後)) 1860
2760
PIC.19
2920
B
2100
2100
PIC.20
900
PIC.21 B view
1620 2210 1640
2100
PIC.21 PIC.20
630
870
2100
2100
PIC.28
PIC.22
1630 2100 2100 2600 2270
2560
PIC.22
PIC.24
2570
PIC.29
PIC.23
2780
2570
PIC.23
2760
2560
PIC.29 3500
2270
PIC.28
20 PIC.24
PM5D/PM5D-RH
PIC.26
890
PIC.25
2760
PIC.25
2100
2560 2590
2600
1080
2570
PIC.26
PIC.27
2800
21
PM5D/PM5D-RH
22
PM5D/PM5D-RH
23
PM5D/PM5D-RH
24
PM5D/PM5D-RH
ACCESSORIES 付 属 品
V9810000 Lamp 12V 5W JL316A0-18" ラ ン プ 1 2 V 3 16
* a AAX58120 Lamp Shade ラ ン プ シ ェ ー ド 3
* b AAX58130 Bulb 12V/DC 5W 電 球 3
* X4459A00 CD-ROM 650MB 12cm C D − R O M
* WC383900 DC Power Supply Cable UL2464 #16X24 L=3600 電 源 ケ ー ブ ル
TOOLS 工 具
* WB477100 Support JIG 2-R RIGHT サポートJIG 2−R
* WB477200 Support JIG 2-L LEFT サポートJIG 2−L
* WB477300 Support JIG 1-R RIGHT サポートJIG 1−R
* WB477400 Support JIG 1-L LEFT サポートJIG 1−L
L R L R
25
PM5D/PM5D-RH
40
100
110
90
80
90
30
120
40
60
30 60
20
70 50
60
40
Rear view 130
10
26
PM5D/PM5D-RH
110
120
90
40 80 90
40
70
70
20
60
20
40
30
10b
100
50
10a
10
27
PM5D/PM5D-RH
Rear view
150
90
40 45 47
100
47
30
80
45
20
60 40
30
60 140 X4
70
70
120
50 110
130
10
28
PM5D/PM5D-RH
110 100
110
20
140
40
40 130
120
50 x16
10b 80 60
70 170
10a
90
10
29
PM5D/PM5D-RH
70
70
20 60
20
40
30
50 100
10
30
PM5D/PM5D-RH
50
10
20
50
30
40
40
40
31
PM5D/PM5D-RH
PANEL 1 ASSEMBLY(パネル 1 Ass’
y)
10
80
20
50
40
110
120
30
70
90
32
210
230
220
210
210 220
170 220 230 170
220
210 150
220
220
170 220 130 130
210
210 210
220
220
220
230 160 200
220
200
140
180
190
PM5D/PM5D-RH
33
34
PM5D/PM5D-RH
320
340
340
260
320 320
340
340
340
320 340
340 320
320 450
270
340 320
460
320
430
250
270
280
PN3 assembly:
(PN3 Ass'y) 330
See page 48.
690
700
470
540 340
660
320 440
24cH 550 330
670 340
240
310
560
540 340
340
340
550
560
330
510 330
300
24cH
330
1cH
540 520
510 550 530
520
545
560
540
550 290
1cH
560
PM5D/PM5D-RH
350
35
36
PM5D/PM5D-RH
390
370
370
420
410
390
380
390
380
620 570 610 650
580
510
520
660
545
530
670
590 600
630 540
550
560
590 600
540 550 560
PM5D/PM5D-RH
640
640
37
PM5D/PM5D-RH
38
PM5D/PM5D-RH
39
PM5D/PM5D-RH
PANEL 2 ASSEMBLY(パネル 2 Ass’
y)
90
10
70
80
50
50
40
110
60
50
20
30
100
600
650
40
160
190
190
140
190
150
190
130
170
200
PM5D/PM5D-RH
180 180
41
42
PM5D/PM5D-RH
915 915
220 1/2
PN6 assembly:
940 (PN6 Ass'y)
See page 50.
510 240
510
630
230 250
620
520
870
520 800
520
270
280
210 N
N
520
520
A
800
PM5D/PM5D-RH
500
43
44
PM5D/PM5D-RH
LCD assembly: See page 51.
(LCD Ass'y)
570
575 560
550 510
590 560
505
710
710
505 220
330
460 360
470 370
330
905 A
450
905 400
460
480 470
700
905 410
460 400
460 680
700
690
440 420
430
510
330 300
340 310
A
490 350
500 390
700 370 360
380 320
580 880
580
290
905
810
810
850
820 850
830
860
840
800
830 820
850
660
PM5D/PM5D-RH
890
45
PM5D/PM5D-RH
46
PM5D/PM5D-RH
47
PM5D/PM5D-RH
20
20
10
40
30
40
48
PM5D/PM5D-RH
20
20
20
10
40
30
40
49
PM5D/PM5D-RH
20
20
10
40
50
30
30
40
50
PM5D/PM5D-RH
220
170
200 190 160
10
200 20
190 10
110
180
40
30 20
120
90
90
120 30
40 140
100
80 70
100
90
90 60 100
140
130 130
210
130 130 130
51
PM5D/PM5D-RH
ELECTRICAL PARTS(電気部品)
52
PM5D/PM5D-RH
53
PM5D/PM5D-RH
54
PM5D/PM5D-RH
55
PM5D/PM5D-RH
56
PM5D/PM5D-RH
57
PM5D/PM5D-RH
58
PM5D/PM5D-RH
59
PM5D/PM5D-RH
60
PM5D/PM5D-RH
61
PM5D/PM5D-RH
62
PM5D/PM5D-RH
63
PM5D/PM5D-RH
64
PM5D/PM5D-RH
65
PM5D/PM5D-RH
66
PM5D/PM5D-RH
67
PM5D/PM5D-RH
68
PM5D/PM5D-RH
69
PM5D/PM5D-RH
70
PM5D/PM5D-RH
71
PM5D/PM5D-RH
72
PM5D/PM5D-RH
73
PM5D/PM5D-RH
74
PM5D/PM5D-RH
75
PM5D/PM5D-RH
76
PM5D/PM5D-RH
77
PM5D/PM5D-RH
78
PM5D/PM5D-RH
79
PM5D/PM5D-RH
80
PM5D/PM5D-RH
81
PM5D/PM5D-RH
82
PM5D/PM5D-RH
83
PM5D/PM5D-RH
84
PM5D/PM5D-RH
85
PM5D/PM5D-RH
86
PM5D/PM5D-RH
87
PM5D/PM5D-RH
88
PM5D/PM5D-RH
89
PM5D/PM5D-RH
90
PM5D/PM5D-RH
91
PM5D/PM5D-RH
92
PM5D/PM5D-RH
93
PM5D/PM5D-RH
94
PM5D/PM5D-RH
95
PM5D/PM5D-RH
96
PM5D/PM5D-RH
97
PM5D/PM5D-RH
98
PM5D/PM5D-RH
99
PM5D/PM5D-RH
100
PM5D/PM5D-RH
101
PM5D/PM5D-RH
102
PM5D/PM5D-RH
103
PM5D/PM5D-RH
104
PM5D/PM5D-RH
105
PM5D/PM5D-RH
106
PM5D/PM5D-RH
107
PM5D/PM5D-RH
108
PM5D/PM5D-RH
109
PM5D/PM5D-RH
110
PM5D/PM5D-RH
111
PM5D/PM5D-RH
112
PM5D/PM5D-RH
113
PM5D/PM5D-RH
114
PM5D/PM5D-RH
115
PM5D/PM5D-RH
116
PM5D/PM5D-RH
117
PM5D/PM5D-RH
118
PM5D/PM5D-RH
119
PM5D/PM5D-RH
120
PM5D/PM5D-RH
121
PM5D/PM5D-RH
122
PM5D/PM5D-RH
123
PM5D/PM5D-RH
124
PM5D/PM5D-RH
125
PM5D/PM5D-RH
126
PM5D/PM5D-RH
127
PM5D/PM5D-RH
128
PM5D/PM5D-RH
129
PM5D/PM5D-RH
130
PM5D/PM5D-RH
131
PM5D/PM5D-RH
132
PM5D/PM5D-RH
133
PM5D/PM5D-RH
134
PM5D/PM5D-RH
135
PM5D/PM5D-RH
136
PM5D/PM5D-RH
137
PM5D/PM5D-RH
138
PM5D/PM5D-RH
139
PM5D/PM5D-RH
141
PM5D/PM5D-RH
142
PM5D/PM5D-RH
143
PM5D/PM5D-RH
144
PM5D/PM5D-RH
145
PM5D/PM5D-RH
146
PM5D/PM5D-RH
147
PM5D/PM5D-RH
148
PM5D/PM5D-RH
149
PM5D/PM5D-RH
150
PM5D/PM5D-RH
151
PM5D/PM5D-RH
152
PM5D/PM5D-RH
153
PM5D/PM5D-RH
154
PM5D/PM5D-RH
155
PM5D/PM5D-RH
156
PM5D/PM5D-RH
157
PM5D/PM5D-RH
158
PM5D/PM5D-RH
159
PM5D/PM5D-RH
160
PM5D/PM5D-RH
161
PM5D/PM5D-RH
162
PM5D/PM5D-RH
163
PM5D/PM5D-RH
164
PM5D/PM5D-RH
165
PM5D/PM5D-RH
166
PM5D/PM5D-RH
167
PM5D/PM5D-RH
168
PM5D/PM5D-RH
169
PM5D/PM5D-RH
170
PM5D/PM5D-RH
171
PM5D/PM5D-RH
172
PM5D/PM5D-RH
173
PM5D/PM5D-RH
174
PM5D/PM5D-RH
175
PM5D/PM5D-RH
176
PM5D/PM5D-RH
177
PM5D/PM5D-RH
178
PM5D/PM5D-RH
179
PM5D/PM5D-RH
180
PM5D/PM5D-RH
181
PM5D/PM5D-RH
182
PM5D/PM5D-RH
183
PM5D/PM5D-RH
184
PM5D/PM5D-RH
185
PM5D/PM5D-RH
186
PM5D/PM5D-RH
187
PM5D/PM5D-RH
188
PM5D/PM5D-RH
189
PM5D/PM5D-RH
190
PM5D/PM5D-RH
191
PM5D/PM5D-RH
* WB486900 Motor Drive Fader Assembly 3P, RSA0K11V900D B10K フ ェ ー ダ − A s s ' y CH 1-24/CH 25-48 24
* WB486900 Motor Drive Fader Assembly 3P, RSA0K11V900D B10K フ ェ ー ダ − A s s ' y DCA 1-8,STEREO A,B, 14
ST IN 1-4/FX RTN 1-4
192
DIGITAL MIXING CONSOLE
PM5D/PM5D-RH
CIRCUIT DIAGRAM
CONTENTS(目次)
BLOCK DIAGRAM(ブロックダイアグラム) ..........................................................................................3
PM5D OVERALL CONNECTOR CIRCUIT DIAGRAM(PM5D総コネクタ接続回路図).................... 14
PM5D-RH OVERALL CONNECTOR CIRCUIT DIAGRAM(PM5D-RH総コネクタ接続回路図) ........ 22
CIRCUIT DIAGRAM(回路図)
AD1 (PM5D) ............................................... 30 LED (PM5D) ................................................ 42
AD2 (PM5D) ............................................... 31 LD (PM5D-RH) .......................................... 120
AD3 (PM5D-RH) (001~008) ....................... 32 LPVOL (PM5D) ......................................... 121
ANI1 (PM5D) .............................................. 41 LPVOL (PM5D-RH) ................................... 122
ANI2 (PM5D) .............................................. 42 MAIN (002~008) ....................................... 123
ANI3 ............................................................ 43 MNVOL ..................................................... 130
BRG1 (002~007) ......................................... 44 OPT ........................................................... 131
BRG2 ........................................................... 50 PHN1 ......................................................... 132
BRG3 ........................................................... 51 PHN2 ......................................................... 133
BRG4 ........................................................... 52 PN1 (002~010) .......................................... 134
BRG5 ........................................................... 53 PN2 (002~006) .......................................... 143
CN1R (PM5D-RH) ....................................... 54 PN3 (002,003) ........................................... 148
CUVOL ........................................................ 55 PN4 (001,002) ........................................... 150
DA1 ............................................................. 56 PN5 (002,003) ........................................... 152
DA2 ............................................................. 57 PN6 (002,003) ........................................... 154
DA3 ............................................................. 58 PN8 (1/2) (001) ......................................... 156
DR ............................................................... 59 PN8 (2/2) (002) ......................................... 157
DRL ............................................................. 59 SL (002~015) ............................................ 158
DRN ............................................................ 59 SR (1/2) (002~014) ................................... 172
DSP (002~024) ........................................... 60 SR (2/2) (015) ........................................... 185
FDA (002~008) ........................................... 83 STLD (PM5D-RH) ..................................... 186
FDB (002~010) ............................................ 90 SW48 (PM5D-RH) .................................... 187
FDC (002~010) ............................................ 99 TB .............................................................. 188
HIC-HA (PM5D-RH) .................................... 40 TBVOL ...................................................... 189
JK1 (002~007) .......................................... 108 TPSW ........................................................ 190
JK2 (002~007) .......................................... 114
Notation for Circuit Diagrams(回路図表記上の注意)
1. How to identify inter-sheet connectors(シート間コネクタの読み方について)
WR 002:D4
PM5D/PM5D-RH
BLOCK DIAGRAM 001 (PM5D/PM5D-RH)
CN101 CN102
1
CN15 (4P) (8P)
CN201 (4P) (4P)
BRG2 MAIN TPSW Track pad
PN8 PN8
MAIN CPU CN10
CN205 (9P)
CN206 (7P) See Page 10
PN1
(14P)
DC-AC INVERTER LCD SR (2/2) (2/2) (1/2)
See Page 6 CN8
(5P) Encoder SW
CN203 (8P) Matrix
CN204 (6P) LED SW LED SW
Encoder
CN207 Matrix Matrix CN1 (6P) CN2 (7P) Matrix Matrix CN200 CN101
(7P) (4P) (4P)
IC100-IC101 (64P)
BRG3 CN900 (13P) CN100 (11P)
CN101
2
(7P)
CN451 (15P) CN101 (5P) CN600 CN500
CN450 (9P)
SL IC100 (112P)
SR (1/2) IC100 (112P)
(13P) (11P)
CN701 (4P)
CN526 (30P) CN527 (20P) CN702 (6P) CN601 (35P)
PN5
R.Encoder
FDB Motor Driver I/F Counter PN2 (2) FDC Motor Driver I/F 4-Char
IC526 (REC2) CN707 CN400
Encoder (7P) (7P) LED
CN528 (8P)
CN529 (6P)
(64P)
CN525 (24P)
CN100 (24P) 4-Char
LED
PN3 (3) PN3 (4) CN709
(12P)
CN401
(12P)
CN538 (32P) SW
IC522, IC525(16P) SW I/F LED SW LED SW SW I/F Matrix
CN200 (32P) IC501, IC504 (16P) Led
Matrix Matrix Matrix Matrix Matrix
Multiplexer SW Multiplexer
Motor Driver Matrix Motor Driver
(4:1 x 3) CN539 (4:1 x 4)
LED I/F (32P) LED I/F
CN100 (12P) CN100 (12P)
CN500 (32P) Led
Matrix
CN101 (11P)
CN102 (12P)
CN101 (11P)
CN102 (12P) 4
CN501-CN503,CN507-CN509,
CN513-CN515,CN519-CN521 (3P)
CN537
(26P)
CN540
CN504-CN506,
CN510-CN512,
CN516-CN518,
CN531 (12P)
CN534 (11P)
CN536 (12P)
CN530 (12P)
CN533 (11P)
CN535 (12P)
CN101-CN103,
CN107-CN109,
CN104-CN106,
CN110-CN112,
CN708 (17P)
CN706 (15P)
CN705 (15P)
CN714 (12P) PN4
CN201-CN203, CN204-CN206,
(25P) CN522-CN524 CN207-CN209, CN210-CN212, LED
(4P) CN301-CN302 CN303-CN304 Matrix
(3P) (4P) CN201 (15P)
CN101 (12P)
SW
Matrix
CN29
(26P)
CN26
(25P)
IC26 R.Encoder
PN6
FDA Motor Driver I/F
(64P) Counter PN2 (1) LED
(REC2) Matrix
CN100 (17P)
CN27 (9P)
CN25 (24P)
Encoder
CN100 (24P) 4-Char
LED
PN3 (1) PN3 (2) CN101 (15P)
SW
CN28 (7P) SW I/F CN36 (32P) Matrix
IC22, IC25(16P) CN200 (32P) LED SW LED SW
Multiplexer Matrix Matrix Matrix Matrix
SW
Motor Driver Matrix
(4:1 x 3) CN31
LED I/F (32P)
CN500 (32P) CN100 (12P) CN100 (12P)
PM5D/PM5D-RH
BLOCK DIAGRAM 002 (PM5D/PM5D-RH)
1 CN102 (100P), CN101 (80P) CN5 (100P), CN6 (80P) SL
JK1 DSP MAIN
JK101 CN1 CN100
(6P) (6P)
CN901 (36P) CN110 (36P)
CN902 (40P) CN111 (40P)
JK301
SR
CN2 CN100
(44P) (7P) (7P)
(208P)
(80P)
JK1
JK151
CN201
CN110 CN901
(36P) (36P)
2 (48P)
CN111
(40P)
CN902
(40P)
(44P)
CN105 (32P)
CN106 (30P) JK051
CN107 (31P)
CN108 (24P)
CN109 (40P) (28P)
OPT JK052
(208P)
(28P)
3 (28P)
(144P)
CN503
(144P)
CN505 JK2 CN504
CN901
(11P)
(144P) (144P) (144P) (144P) (144P) (144P) CN127 (11P)
(14P)
CN132 (11P) DA1 DA2 DA3
AD3
PHN2 PHN1
AD3 (Rear Top Assembly)
(リア上 Ass'y) (Panel 2 Assembly)
(Bottom Assembly) CN136 CN502 CN503
CN126
(13P)
ANI3
AD3 CN137 (9P)
CN138 (10P) BRG1
CN131
(14P)
PM5D/PM5D-RH
BLOCK DIAGRAM 003 (PM5D/PM5D-RH)
1
XPHONES,XCUE
XMONITOR L,R,C
MONITOR L,R,C
XMX 1-4 SI00
PHONES,CUE
CASCADE IN (CIxx) XMX 5-8 SI01
XMX 9-12 SI02
XMX 13-16 SI03
Input Effect
XMX 17-20
XMX 21-24
SI04
SI05
DSP7 DSP7 Return1-4 INS OUT 1-4
INS OUT 5-8 SI28 GEQ 1-4
XSTEREO A,B
CUEBUS/MONSEL
SI06
SI07
SI29 SO00 TB, OSC MONITOR L,R,C
ICB01-08 ICB09-11 GEQ 5-8
SI43
SO44
SO45
SO46
SI47
SI48
SI49
SI50
SI53 INS OUT 9-12 SO01 SI08
INS OUT 13-16 SI30 GEQ 9-12 XMATRIX1-4 PHONES,CUE
SI54 SO02 SI09
INS OUT 17-20 SI31 MIX 1-4 XMATRIX5-8
KEYMIX21-24 SI55 DSP7 SPECTRUM SO03 SI10
SI52 INS OUT 21-24 SI32 MIX 5-8 XMONCSEL SLOT1OUT 1-4
SI40 SO04 SI43 SO44
TB, OSC SI51 ICB01 INS OUT 25-28 SI33
SO05
MIX2MTX 1-4 DIRECT OUT 1-4 SI11 SO45 SLOT1OUT 5-8
(208P) SI34 MIX2MTX 5-8 DIRECT OUT 5-8 SLOT1OUT 9-12
INS OUT 29-32 SO06 SI12 SO46
SI35 MIX2ST DIRECT OUT 9-12
SO56
SO57
SO58
SO59
SO60
SO61
SO62
SO63
INS OUT 33-36 SO07 SI13 SO47 SLOT1OUT 13-16
INS OUT 37-40 SI36 SPECTRUM DIRECT OUT 13-16 SLOT2OUT 1-4
SI37 SO08 SI14 SO48
INS OUT 41-44 MIX 9-12 DIRECT OUT 17-20 SLOT2OUT 5-8
SO09 SI15 SO49
INS OUT 45-48
INS OUT STI1-2
SI38
SI39
SO10
SO11
MIX 13-16
MIX 17-20
DIRECT OUT 21-24
DIRECT OUT 25-28
SI16
SI17
DSP7 SO50
SO51
SLOT2OUT
SLOT2OUT
9-12
13-16
Input 1-8 SI40 MIX2ST MIX1-4 DIRECT OUT 29-32 SLOT3OUT 1-4
SI43
SI44
SI45
SI46
SI47
SI48
SI49
SI50
INS OUT STI3-4 SI16 SI18 SO52
SI41 MIX2ST MIX5-8 DIRECT OUT 33-36 SLOT3OUT 5-8
INS OUT 1-4 SI17 SI19
KEYMIX21-24
SI40
SI51
DSP7 SO52
SO53 INS OUT 5-8
DIRECT OUT 1-4
INS OUT MIX1-4
INS OUT MIX5-8
SI42 SI18
SI19
MIX2ST MIX9-12
MIX2ST MIX13-16
DIRECT OUT 37-40
DIRECT OUT 41-44
SI20
SI21
ICB14 SO53
SO54 SLOT3OUT
SLOT3OUT
9-12
13-16
ICB02 SO54
DIRECT OUT 5-8 INS OUT MIX9-12
SI43
SI20 MIX2ST MIX17-20 DIRECT OUT 45-48 SI22
SO55
SLOT4OUT 1-4
SI44 MIX2ST MIX21-24 SO56
(208P) SO55 INS OUT MIX13-16
SI45
SI21 DIRECT OUT STI 1-2
SI23 SO57
SLOT4OUT 5-8
XPHONES,XCUE DIRECT OUT STI 3-4 SLOT4OUT 9-12
SO56
SO57
SO58
SO59
SO60
SO61
SO62
SO63
SDRAM INS OUT MIX17-20
INS OUT MIX21-24
SI46
DSP7 SI22
XMATRIX 1-4 SI24 SO58
SLOT4OUT 13-16
SI47 SI23 SO59
INS OUT STA,STB MIX2MTX 1-4 MIX1-12
64Mbit IC197 SI48 SI24
MIX2MTX 1-4 MIX13-24
INS OUT MTX1-4
INS OUT MTX5-8 SI49 SI25
MIX2MTX 5-8 MIX1-12 OUTPUT Patch 2TrDOUT1-2
SI50 ICB12 SI26
MIX2MTX 5-8 MIX13-24
SO60
Input 9-16 XSLOT1OUT 1-4 SO61 2TrDOUT3
2
SI43
SI44
SI45
SI46
SI47
SI48
SI49
SI50
SI27
KEYMIX21-24 SO52
INS OUT 9-12 XMIX 1-4
SI51 SI61
XGEQ 7-10
XGEQ 11-12
XSLOT1OUT 5-8
XSLOT1OUT 9-12
SI25
SI26 MONITOR XMONITOR L,R,C
SI40 DSP7 SO53
INS OUT 13-16 XMIX 5-8 SI52
SI62
XMATRIX 5-8 XSLOT1OUT 13-16
SI27 SO62
SI51
ICB03 SO54
DIRECT OUT 9-12
DIRECT OUT 13-16
XMIX
XMIX
9-12
13-16
SI53 GEQ1 SI63
SO12
MIX 21-24 XSLOT2OUT 1-4
SI28
SI29
DITHER SO63 XPHONES,XCUE
(208P) SO55
XMIX 17-20
SI54
SO13
STEREO A-B XSLOT2OUT 5-8 SI30
SI55 MATRIX 1-5
SO56
SO57
SO58
SO59
SO60
SO61
SO62
SO63
SDRAM XMIX 21-24 SO14 XSLOT2OUT 9-12 SI31
SI56 MATRIX 6-8 XSLOT2OUT 13-16
XSTEREO A,B (208P) SO15 SI32 (208P)
SI57 XSLOT3OUT 1-4
64Mbit IC200 CUEBUS/MONSEL SI58 XSLOT3OUT 5-8
SI33
TB, OSC SI34
SI59 XSLOT3OUT 9-12 SI35
AD IN 1-4 Input 17-24 XMONCSEL SDRAM
SI43
SI44
SI45
SI46
SI47
SI48
SI49
SI50
SI00 SI00 SI60 XSLOT3OUT 13-16
AD IN 5-8 SI36
SI01 SI01 INS OUT 17-20 XSLOT4OUT 1-4 SI37
AD IN 9-12 KEYMIX21-24 SO52 XSLOT4OUT 5-8
SI02 SI02 SI40 DSP7 INS OUT 21-24 SI38
AD IN 13-16 SI03 SI03 SI51
SO53
DIRECT OUT 17-20 XSLOT4OUT 9-12 16Mbit IC222
ICB04 SO54
DIRECT OUT 21-24
INS OUT 1-4
SI28 SO00 XGEQ 7-10 XSLOT4OUT 13-16
SI39
AD IN 17-20 (208P) SO55 INS OUT 5-8 XGEQ 11-12 SI40
SI04 SI04 SI29 SO01
AD IN 21-24 INS OUT 9-12 XPHONES,XCUE
SO56
SO57
SO58
SO59
SO60
SO61
SO62
SO63
SI05 SI05 SDRAM SI30 SI61 X2TrDOUT1-2
AD IN 25-28 INS OUT 13-16 SI41
SI06 SI06 SI31 SI62 X2TrDOUT3,SM OUT SI42
AD IN 29-32 SI07 SI07 INS OUT 17-20 SI63
64Mbit IC201 INS OUT 21-24
SI32
SI33
AD IN 33-36 INS OUT 25-28
SI08 SI08 INS OUT 29-32
SI34
AD IN 37-40 Input 25-32 XSLOT1OUT 1-4
SI43
SI44
SI45
SI46
SI47
SI48
SI49
SI50
SI09 SI09 SI35
AD
AD
IN
IN
41-44
45-48
SI10 SI10 KEYMIX21-24 SO52
INS OUT 25-28
INS OUT 33-36
INS OUT 37-40
SI36 DSP7 SO02
SO03 XSLOT1OUT 5-8
XSLOT1OUT 9-12
SI11 SI11 SI40 DSP7 SO53 INS OUT 29-32 INS OUT 41-44
SI37 SO04
XSLOT1OUT 13-16
SI51 DIRECT OUT 25-28 SI38 SO05
SLOT1IN 1-4 SI12 SI12 ICB05 SO54 INS OUT 45-48
SI39 XSLOT2OUT 1-4 To ATSC2
SLOT1IN 5-8
SLOT1IN 9-12
SI13 SI13 (208P) SO55 DIRECT OUT 29-32 INS OUT STI1-2
INS OUT STI3-4
SI40 ICB13 SO06
SO07 XSLOT2OUT 5-8
XSLOT2OUT 9-12
MIX 1-4
MIX 5-8
SO56
SO57
SO58
SO59
SO60
SO61
SO62
SO63
SLOT1IN 13-16
SI14 SI14 SDRAM SI41 SO08
XSLOT2OUT 13-16 MIX 9-12
SI15 SI15 SO09
INS OUT MIX1-4 XSLOT3OUT 1-4 MIX 13-16
64Mbit IC204 SO10
SLOT2IN 1-4
SLOT2IN 5-8
SI16 SI16 INS OUT MIX5-8
INS OUT MIX9-12
SI42
SI43 GEQ7~12 SO11 XSLOT3OUT 5-8
XSLOT3OUT 9-12
MIX 17-20
MIX 21-24
SI17 SI17 SI44 SO12
SLOT2IN 9-12 Input 33-40 INS OUT MIX13-16 XSLOT3OUT 13-16 STEREO A,B
SI43
SI44
SI45
SI46
SI47
SI48
SI49
SI50
SI18 SI18 SI45 SO13
SLOT2IN 13-16 SI19 SI19 INS OUT 33-36 INS OUT MIX17-20 SO14 XSLOT4OUT 1-4 MATRIX 1-4
SI46
KEYMIX21-24
SI40 DSP7 SO52
INS OUT 37-40 INS OUT MIX21-24 SI47 EFFECT PATCH SO15 XSLOT4OUT 5-8 MATRIX 5-8
SLOT3IN 1-4
SLOT3IN 5-8
SLOT3IN 9-12
SI20
SI21
SI22
SI20
SI21
SI22
SI51
ICB06
(208P)
SO53
SO54
SO55
DIRECT OUT 33-36
DIRECT OUT 37-40
INS OUT STA,STB
INS OUT MTX1-4
INS OUT MTX5-8
SI48
SI49
OUTPUT Patch
SO16
SO17
XSLOT4OUT 9-12
XSLOT4OUT 13-16 3
SI23 SI23 SI50 X2TrDOUT1-2
SLOT3IN 13-16
SO56
SO57
SO58
SO59
SO60
SO61
SO62
SO63
SDRAM XMIX 1-4
SO18
SI51 SO19 X2TrDOUT3,SM OUT
SLOT4IN 1-4 XMIX 5-8
SLOT4IN 5-8
SI24 SI24 64Mbit IC205 XMIX 9-12
SI52 (208P)
SI25 SI25 SI53
SLOT4IN 9-12 XMIX 13-16
SI26 SI26 SI54
SLOT4IN 13-16 Input 41-48 XMIX 17-20
SI43
SI44
SI45
SI46
SI47
SI48
SI49
SI50
SI27 SI27 XMIX 21-24
SI55
KEYMIX21-24 INS OUT 41-44 SI56
STEREO IN 1-2 SO52
STEREO IN 3-4
SI28 SI28 SI40 DSP7 SO53 INS OUT 45-48 XSTEREO A,B
SI57
SI29 SI29 SI51 ICB07 SO54
DIRECT OUT 41-44 CUEBUS/MONSEL
SI58
DIRECT OUT 45-48 TB, OSC
SO20
SO21
SO22
SO23
SO24
SO25
SO26
SO27
(208P) SO55
XMONCSEL
SI59
SI60
SO56
SO57
SO58
SO59
SO60
SO61
SO62
SO63
2TrDIN 1-2 SDRAM
SI30 SI30
FX3/4 SEND1/2
FX5 SEND1/2
FX1 SEND1-4
FX1 SEND5-8
FX6/7 SEND1/2
FX8 SEND1/2
FX2 SEND1-4
FX2 SEND5-8
2TrDIN 3/Talkback
2TrAIN 1-2
SI31 SI31 64Mbit IC208
SI32 SI32
ST Input 1-4 SI43
SI44
SI45
SI46
SI47
SI48
SI49
SI50
FX3/4 RTN1/2
SI33 SI33 KEYMIX21-24 INS OUT STI 1-2
FX5/1 RTN1/2 SO52
FX6/7 RTN1/2
SI34 SI34 SI40 DSP7 SO53 INS OUT STI 3-4
SI35 SI35 SI51 ICB08 DIRECT OUT STI 1-2
FX8/2 RTN1/2 SO54
SI36 SI36 (208P) SO55 DIRECT OUT STI 3-4
Sur1 RTN1-4
SO56
SO57
SO58
SO59
SO60
SO61
SO62
SO63
SI41 SDRAM
Sur1 RTN5-8 SI42
GEQ 1-4 64Mbit IC209
XCOSMA/XCOCUA
XCOSMB/XCOCUB
SI37 SI37
GEQ 5-8 SI38 SI38
XCOMIX13-16
XCOMIX17-20
XCOMIX21-24
GEQ 9-12
XCOMIX9-12
SI39 SI39
XCOMIX1-4
XCOMIX5-8
COMIX21-24
CIMIX13-16
SO56
SO57 MIX13~24 SO62
SO63 MIX2ST MIX 21-24
MIX2MTX 1-4 MIX 13-24
FX1 SEND1/4
FX1 SEND5/8
SI2
SI3
ICA05 SO1
SO3
FX2 SEND1-4
FX2 SEND5-8
SI2
SI3
ICA06 SO1
SO3
FX6/7 RTN1/2
ICB04 INPUT17-24
SI44 (208P) SO48 FX3/4 RTN1/2 EFFECTSO4 FX3/4 RTN1/2 EFFECTSO4
CIMIX17-20
CIMIX21-24 SI45
SI46
SO49
SO50
MIX2MTX 5-8 MIX 13-24
MIX2CUE MIX 13-24 FX5/1 RTN1/2
FX6/7 RTN1/2
SI4
SI5 (FX6) SO5 FX5/1 RTN1/2
FX6/7 RTN1/2
SI4
SI5 (FX7) SO5 ICB05 INPUT25-32
KEYMIX 21-24 SI6 SO6 SI6 SO6
SI47 SO51 FX8/2 RTN1/2 SI7 (176P) SO7
FX8/2 RTN1/2 SI7 (176P) SO7 ICB06 INPUT33-40
4Mbit x2 4Mbit x2
XCOSMA/XCOCUA
SI40
IC241, IC242
DRAM IC243, IC244 DRAM ICB07 INPUT41-48 5
XCOSMB/XCOCUB SDRAM ICB08 ST IN1-4
XSTEREO A,B SI41
XMATRIX1-4
SO52 64Mbit IC216 FX8 SEND1/2 FX2 SEND1/4 Sur2 RTN1-4
XMATRIX5-8
SO53
SO54 DSP7 SO62 DMCOST/DMCOCUE
COSTA/COCUEA
SI0
SI1 DSP6 SO2
SI0
FX8 RTN1-4
SI0
SI1 DSP6 SO2
SI0
Sur2 RTN5-8 ICB09 MIX Master1-12
CUEBUS/MONSEL SO57 FX2 SEND1/4 FX2 SEND1-4 FX8/2 RTN1/2
TB,OSC
SO55
SO56
ICB11 SO58 COSTB/COCUEB
FX2 SEND5/8
SI2
SI3
ICA07 SO1
SO3 FX2 SEND5-8
SI2
SI3
ICA08 SO1
SO3 ICB10 MIX Master13-24
XMONCSEL MIX2ST EFFECTSO4
CIMIX9-12 SO63 ST,A,B, SO59
SI47 INS OUT STMA,B
FX3/4 RTN1/2
FX5/1 RTN1/2
SI4 EFFECTSO4 FX3/4 RTN1/2 SI4
MIX2CUE MIX 1-12
SI46
SI48 MATRIX1~8 SO60 INS OUT MTX1-4 FX6/7 RTN1/2
SI5
SI6
(FX8) SO5
SO6
FX5/1 RTN1/2
FX6/7 RTN1/2
SI5
SI6
(FX2) SO5
SO6
ICB11 ST A/B,Cue,Matrix1-8,TB,OSC
MIX2CUE MIX 13-24 SI49 INS OUT MTX5-8 FX8/2 RTN1/2 (176P) FX8/2 RTN1/2 (176P)
CASCADE OUT (COxx) SO61 SO7 SO7
KEYMIX 21-24 SI51 TB, OSC SI42
SI43
MIX2MTX 1-4
MIX2MTX 5-8
SI7 SI7
ICB12 GEQ1-6
CISTMA/CICUEA XMONITOR L,R,C 4Mbit x2 DRAM 4Mbit x2 DRAM
CISTMB/CICUEB
SI44
SI45
(208P) SI50
IC247, IC248 IC249, IC250 ICB13 GEQ7-12,EFFECT PATCH(SLOT)
ICB14 OutputPatch(SLOT)
PM5D/PM5D-RH
BLOCK DIAGRAM 004 (PM5D/PM5D-RH)
1 CN101
(80P)
CN102
(100P) DSP See Page 4
CN5
CN6
CN7
(7P) 80P 100P
CN1 (6P) CN2 (7P)
DC-AC +5D +3.3D GND
2 INVERTER
(5P)
12V
SCI1, 2, 3, 4
CPU CARD
240P X2
LCD
SW & PCMCIA
3.3V Regulator PS/2Keyboard
40MHz
IC50(3P) PS/2Mouse
LCD Unit IC51 SH-Bus BUFFER
(14P)
CPU BUS
LHSYNC SDRAM
LVSYNC IC41
64Mbit
IC65
CN15 1.9V Regulator
TPSW RXRDY
Flash
(14P)
32MB
CompactFlash
IC56 CS5,6
TRANCEIVER TRANCEIVER CPU
& BUFFER SH7709A
& BUFFER CPU BUS
EOC37120 EOC37120
(100P) (100P)
Companion
Chip IC6 IC17, 20 IC21 IC18
CN13 SCI0, 2
/BUSY
MAIN CPU
SDRAM ROM SDRAM
RTC- 64Mbit 32Mbit 2Mbit
4543 SH7709S x2 x1 x1
172 (54P) (48P) (44P)
CPUA1~CPUA16 44MHz BUS RXD1
DUAL PORT CPUD0~CPUD15
(208P) (FLASH)
/CS4
MEMORY PROGRAM
4 512kbit
132MHz
(Clock x 12)
TXD1
166
/BUSY
IC48 (100P)
CN14 MAIN
(5P)
CN402 (5P)
5
BRG1
/CAUTION
/BRG_MUTE
See Page 10
CN101 CN101
(9P) (9P)
(28P)
CN100 CN100 (28P)
(9P) (9P)
28CA1-8830946-5
CN102 (12P) (12P) CN102 (12P) (12P)
(9P) (9P)
ANI 1 ANI 1
G
CN100
CN003 CN116 (9P) CN003 CN120
(10P) (10P) ANI 1 (10P) (10P)
CN100
(9P) CN201
ANI 1 (9P)
CN100
(9P)
CN201
ANI 1 CN002 CN121
(9P) (12P) (12P)
CN202 (28P)
CN100 (9P)
(9P) CN002 CN117
ANI 1 (12P) (12P) CN100
(9P)
ANI 1
CN202 (28P) CN301
(9P) (9P)
CN100 CN100
(9P) (9P)
ANI 1 ANI 1 CN002 CN121
BLOCK DIAGRAM 005 (PM5D)
(12P) (12P)
CN302 (28P)
CN301 (9P)
(9P) CN100
CN100 (9P)
(9P) CN002 CN117
ANI 1
ANI 1 (12P) (12P)
CN401
(9P)
F
ANI 1
AD 1 -3
CN601
(9P)
CN100 (Rear Top Assembly)
(9P) CN002 CN117 (Rear Top Assembly)
ANI 1 (12P) (12P) (リア上 Ass'y)
(リア上 Ass'y)
CN101
CN602 (9P)
(9P) (28P)
CN002 CN123
CN100 (12P) (12P)
CN100 (9P)
(9P) ANI 1
ANI 1
CN102 (28P)
(9P)
CN100 CN003 CN122
(9P) (10P) (10P)
ANI 1
AD 1 -1
CN201
(9P)
CN100
(9P)
(Rear Top Assembly)
ANI 1 CN002 CN123
(12P) (12P)
(Rear Top Assembly) (リア上 Ass'y) CN202 (28P)
(9P)
(リア上 Ass'y)
CN100
CN101 (9P)
(9P) ANI 1
CN100
(9P) CN002 CN119 CN301
D
CN201 CN401
(9P) (9P)
CN100 CN100
(9P) CN002 CN119 (9P)
ANI 1 (12P) (12P) ANI 1
CN002 CN123
(12P) (12P)
CN402 (28P)
CN202 (28P) (9P)
(9P) CN100
CN100 (9P)
(9P)
ANI 1
ANI 1 CN501
(9P)
CN301 CN100
(9P) ANI 1 (9P)
CN100 CN002 CN123
(9P) CN002 CN119 (12P) (12P)
CN502 (28P)
ANI 1 (12P) (12P) (9P)
CN100
(9P)
CN302 (28P)
ANI 1
C
(9P)
CN100 CN601
(9P) (9P)
ANI 1 CN100
ANI 1 (9P)
CN002 CN123
CN401 (12P) (12P)
(9P) CN602 (28P)
(9P)
CN100
(9P) CN002 CN119 CN100
ANI 1 (12P) (12P) ANI 1 (9P)
CN402 (28P)
(9P)
AD 1 -4
CN100 (Rear Top Assembly)
(9P)
ANI 1 (リア上 Ass'y)
CN501
(9P)
CN100
(9P) CN002 CN119 (Rear Top Assembly)
ANI 1 (12P) (12P) (リア上 Ass'y)
CN502 (28P)
(9P)
CN100
(9P) CN002(8P)
ANI 1 CN100 CN003(9P)
B
(9P) CN301
(9P)
CN601 (28P)
(9P)
CN100
(9P) CN002 CN119
ANI 1 (12P) (12P) LED
CN202(3P)
CN602 (28P)
(9P) CN201 CN100
(3P) (9P)
CN100
(9P) ANI 2
ANI 1
CN401
(9P)
CN100 (28P)
AD 1 -2 ANI 2 (9P)
CN501
(9P)
CN100 (28P)
ANI 2 (9P)
CN601
(9P)
CN125(8P)
CN100 (28P) CN124(9P)
(9P)
BLOCK DIAGRAM 005 (PM5D)
Hard: Analog Input Block
PM5D
Page 4 Page 4
DSP AD 2 DSP
7
6
5
4
3
2
1
6
5
4
3
2
1
8
A
REGULATOR
0dB 38dB 24dB (+5D +2.5D) +2.5D
18dB UPC2925T
-24dB 14dB IC983
28CA1-8830946-6
12dB
6dB IC104
0dB BA
AINL
SDATA
-1
+48V A/D
IC201 IC203 AK5385
INPUT2 Q200 IC204
IC105
BA
AINR
RST
-1
MCLK
SCLK
LRCK
B
+48V
IC304
+48V IC305
INPUT4 Q400 IC401 IC403
IC404
+48V
IC504
BLOCK DIAGRAM 006 (PM5D-RH)
+48V
IC505
INPUT6 Q600 IC601 IC603
IC604
C
+48V
IC704
(ボトムAss'y)
CRYSTAL
OSCILLATOR
60M X901
IC921 SI SO
SI
ATSC2A
SO DSP7
DSP CN1R SYNC SYSTEM RST GAIN (1dB STEP ATT)
256FS MUTE SYNC RST
IC902
128FS
See Page 4
CRYSTAL CRYSTAL
OSCILLATOR OSCILLATOR
49.152M 45.158M
X051 X052
(28P)
CN109
ADIN 1-4 ADIN 1-4 DDA 1-8
AD IN1-4 MUTE Fs
D
Rx_422 Rx_422
Rx_422 CN922
E
Tx_422 Tx_422
LD -2 (INPUT17-32)
(28P)
CN111
CN922
(28P)
Tx_422 Tx_422
/CS_DIT2B /CS_DIT2B
LD -3 (INPUT33-48)
(28P)
CN113
Rx_422 Rx_422
G
(3P)
(3P)
JK101 JK101
(3P)
(3P)
(3P)
(3P)
(28P)
(28P)
JK201 JK201
28CA1-8830946-7
G
JK301 JK301
JK401 JK401
(28P) (28P)
JK501 JK501
JK601 JK601
(28P) (28P)
JK701 JK701
CN133(8P)
CN903(8P)
CN132(11P)
CN901(11P)
CN130(8P)
CN129(8P)
CN128(8P)
CN903(8P)
CN127(11P)
CN901(11P)
DA1 -1 DA1 -4
(Bottom Assembly)
(Bottom Assembly)
(ボトム Ass'y)
(ボトム Ass'y)
BLOCK DIAGRAM 007 (PM5D/PM5D-RH)
F
JK101
(28P) JK601
JK701 CN905(6P)
CN906(3P)
JK801
(28P) CN300
JK301 (9P)
MNVOL
E
CN903(8P)
CN901(11P)
DA1 -2 (Panel 2 Assembly)
(Bottom Assembly) (パネル2 Ass'y)
(ボトム Ass'y)
(28P)
JK401
JK101
JK201
(28P)
JK501
JK301
JK401
(28P)
(28P)
JK501
JK601
CN135(10P)
CN903(10P)
(28P)
D
JK701
DA2
JK801 (Bottom Assembly)
(28P)
(ボトム Ass'y)
CN903(8P)
(3P)
CN901(11P)
DA1 -3 JK101
(Bottom Assembly)
(ボトム Ass'y) (3P)
JK101
JK301
C
JK200
(28P)
JK401
CN134(4P)
CN903(4P)
JK201
ANI3
(Bottom Assembly)
(ボトム Ass'y)
CN600 CN400
(6P) (12P)
CN102
(3P) (28P)
CN100
(14P)
CN101(3P) JK100
B
CN136(13P)
CN502(13P)
CN100(14P)
CN503(13P) PHN2
(Bottom Assembly)
(ボトム Ass'y)
CN501(13P)
CN600
(7P)
TB
See
Page 4 (Panel 2 Assembly)
(パネル2 Ass'y)
DSP JK600
See
Page 4
DSP PHN1
BLOCK DIAGRAM 007 (PM5D/PM5D-RH)
Hard: Analog I/O Block
PM5D/PM5D-RH
A
PM5D/PM5D-RH
BLOCK DIAGRAM 008 (PM5D/PM5D-RH)
1 FROM PW800W
CN808
(7P)
(Panel 1 Assembly) (Bottom Assembly)
(Bottom Assembly)
BRG2 (パネル1 Ass'y) BRG1 (ボトム Ass'y) PM5D-RH only PM5D only
BRG5 (ボトム Ass'y)
CN801
(Panel 1 Assembly)
CN811
CN201
(9P)
(4P)
(4P)
(パネル1 Ass'y) 24V 24V
Line Filter DC-DC Converter +3.3LD_1,2,3,4,5,6 (リア上 Ass'y)
(24V→+3.3V)×6 FDA (+3.3LD_1)
タ
CN201
×4
(7P)
FDB (+3.3LD_2) AD3(INPUT1-48,ST_IN1-4[L-R])
24V (L801∼L805) 24V LM2678S-ADJ (+24V)
SL (+3.3LD_3,+3.3LD_4)
(IC201∼IC206) PN1 (+3.3LD_5,+3.3LD_6)
DC-DC Converter (Bottom Assembly)
(24V→+3.3V)×3 +3.3D_1,2,3 (ボトム Ass'y)
DC-DC Converter (Panel 1 Assembly)
DSP (+3.3D_2.3)
CN813
(24V→+5V)×2 MAIN(+3.3D_1)
2 LM2678S-ADJ FDA,FDB (+5D)
FDA,FDB,SL,PN1 (+5LD)
(IC504∼IC506)
DC-DC Converter
(Bottom Assembly)
(ボトム Ass'y)
(24V→+20V) +20V DA1#1,DA1#4,,PHN2 (+20V)
NJM7820DL1A (Panel 2 Assembly)
CN814
CN815
CN816
(6P)
(8P)
CN205
(Bottom Assembly)
(10P)
4
(7P)
CN807
CN202
CN203
(5P)
(6P)
(8P)
DC-DC Converter
5 (24V→+20V
NJM7820DL1A
+20A
+5D_4
(IC206)(3P)
CN422 (3P)
Linear Regulator
DC-DC Converter
(-7.5V→-5.0V) CN401 (3P)
(24V→-7.5V)×2 ×2
LM2596S-ADJ NJM7905FA
(IC207,IC210)(5P) (IC214,IC215)(3P)
-5A_1.2 SW48
PM5D/PM5D-RH
BLOCK DIAGRAM 009 (PM5D/PM5D-RH)
1
MATRIX1
MATRIX2
MATRIX3
MATRIX4
MATRIX5
MATRIX6
MATRIX7
MATRIX8
4
SELECT
DIM
MONO
5
MONO
DIM
Soft: Mixer Block
28CA1-8830946-9 3 BLOCK DIAGRAM 009 (PM5D/PM5D-RH) 6
11
A B C D E F G H
PM5D
BLOCK DIAGRAM 010 (PM5D)
1
Analog Digital Digital Analog
Analog Digital INPUT MS- EQ INSERT GATE COMP INSERT DELAY LEVEL DCA INSERT ON BUS MASTER DCA MASTER OUTPUT Analog
PAD GAIN AD PATCH PHASE ATT. DECDE HPF INSERT (x4) PAN Adder INSERT EQ INSERT COMP INSERT
(x8) (x8/4) LEVEL BAL (x2) ON INSERT DELAY PATCH DA
[0dBu = 0.775Vrms]
[0dBFS = Full Scale]
Level Diagram
PM5D-RH
BLOCK DIAGRAM 011 (PM5D-RH)
1
Analog Digital Digital Analog
Analog Digital INPUT MS- EQ INSERT GATE COMP INSERT DELAY LEVEL DCA INSERT ON BUS EQ MASTER DCA MASTER OUTPUT Analog
GAIN AD PATCH PHASE ATT. DECDE HPF INSERT (x4) (x8) PAN Adder INSERT (x8/4) INSERT COMP INSERT LEVEL BAL (x2) ON INSERT DELAY PATCH DA
[0dBu = 0.775Vrms]
[0dBFS = Full Scale]
Level Diagram
28CA1-8830946-11 2 BLOCK DIAGRAM 011 (PM5D-RH) 6
13
A B C D E F G H
PM5D
OVERALL CONNECTOR CIRCUIT DIAGRAM 001 (PM5D)
1
CONTROL PANEL 2
CONTROL PANEL 1
ASSEMBLY, RIGHT
ASSEMBLY, LEFT
3
BRG5 DSP BRG1 DRS BRG1
CN801 CN802 CN803 CN116 CN117 CN118 CN119 CN120 CN121 CN122 CN123 CN124 CN125 CN411 CN100 CN424 CN425 CN426 CN427 CN428 CN429 CN430 CN431 CN433
9P 10P 5P 10P 12P 10P 12P 10P 12P 10P 12P 9P 8P 2P 12P 11P 5P 10P 14P 10P 14P 16P 16P 14P
4
24P 10P 12P 10P 12P 10P 12P 10P 12P 10P 12P 4P 16P 16P 16P 16P 15P
CN003 CN002 CN003 CN002 CN003 CN002 CN003 CN002 CN003 CN002 CN100 CN001 CN001 CN001 CN001 CN001
(SEE PAGE 16)
AD1 -1 AD1 -2 AD1 -3 AD1 -4 AD2 LPVOL AD1 -1 AD1 -2 AD1 -3 AD1 -4 AD2
INDEX
PAGE ASSEMBLY SHEET
BOTTOM ASSEMBLY
15 BRG1, BRG4, BRG5, DSP, MAIN, JK1, JK2, OPT, ANI3, DA1, DA2, DA3, PHN2, DR, DRN, DRL
(ボトムAss'y)
PM5D
OVERALL CONNECTOR CIRCUIT DIAGRAM 002 (PM5D)
TO CONTROL PANEL ASSEMBLY LEFT TO CONTROL PANEL ASSEMBLY RIGHT
1
CN815 CN814
CN202 CN201
CN812 CN811 CN813
9P
5P
5P
CN205 CN204
CN807 CN806
7P
7P
10P
6P
6P
BRG5 BRG4 OPT
10P
10P
JK1 JK2
5P
CN816
CN203
(SEE PAGE 20)
8P
8P
CN807 CN808 CN810 CN809 CN801 CN802 CN803 CN804 CN805 CN907 CN902 CN901 CN510 CN506 CN509 CN508 CN507
3P 7P 9P 10P 32P 31P 30P 24P 40P 11P 40P 36P 8P 37P 22P 32P 34P
3P 2P 2P 3P 2P
CN102 CN101 CN101 CN102 CN101
CN137 CN138
CN415 CN414 CN420 CN419 CN406 CN405 CN403 CN404
10P
10P
CN125 CN124 CN123 CN122 CN121 CN120 CN119 CN118 CN117 CN116
10P
CN433 CN431 CN430 CN429 CN428 CN427 CN426 CN425 CN424
11P
9P
9P
12P
5P
11P
10P
10P
8P
12P
14P
BRG1
14P
10P
10P
14P
12P
TO REAR UPPER ASSEMBLY
14P
12P
10P
16P
16P
12P
16P
CN101 CN102
80P 100P
9P
14P
8P
CN127 CN128 CN129 CN130 CN132 CN133 CN135 CN134 CN126 CN136 CN131
11P 8P 8P 8P 11P 8P 10P 4P 13P 13P 14P
13P 4
CN001
5P 7P 14P 5P 11P 8P
CN002
CN14 CN7 CN10 CN8
12P
CN901 CN903
ANI3
100P
CN5
11P 8P
CN901 CN903
CN002 CN001
JK1
6P
DA1 -4
14P 14P
CN6
80P
CN002 CN001
14P 14P
( )
JK2
MIX OUT
6P
CN902
MAIN 1-8 11P
CN15 CN13
CN902 13P
68P
CN001
TO CONTROL PANEL 2
7P
4P
14P
CN500
CN503
ASSEMBLY, RIGHT
16P
13P
(TO CONTROL PANELASSEMBLY RIGHT) 11P 8P PHN2 (TO CONTROL PANEL
CN902 CN903
DA3 ASSEMBLY RIGHT)
CN1
6P
CN002 CN001
CN002
14P
CN9 (TO CONTROL PANEL ASSEMBLY LEFT)
14P
CN600
240P DA1 -2 6P
CN901
( MIX OUT
) 11P
14P
9-16 (SEE PAGE 20)
CN001
14P
*_***_CN***
注1) (図中の▲はFFCコネクタを表し、1PinとnPin、2Pinと(n-2)Pin...nPinと1Pinが接続されます。 11P 8P DA2
尚、nPinはコネクタのPin数の最大数です。 Destination connector No. CN901 CN903
その他のコネクタは1Pinと1Pin、nPinとnPinが接続されます。) (接続先コネクタ番号)
CN001
14P
注2) ∗
(配線に (数字)印がついている部分の接続は19、20、21ページに詳細を示します。
Destination page of the signal
(信号の行き先ページ番号) ( MIX OUT
17-24 ) (SEE PAGE 20)
その他はコネクタ1対1の対応です。)
Note4) indicates the sheet name.
注4) ( 内はシート名称を示します。) TO CONTROL PANEL ASSEMBLY RIGHT (ボトムAss'y)
BOTTOM ASSEMBLY
28CA2-8831131-2 OVERALL CONNECTOR CIRCUIT DIAGRAM 002 (PM5D) 6
15
A B C D E F G H
PM5D
OVERALL CONNECTOR CIRCUIT DIAGRAM 003 (PM5D)
1
TO BOTTOM ASSEMBLY
ANI1 -25
ANI1 -26
ANI1 -27
ANI1 -28
ANI1 -29
ANI1 -30
ANI1 -31
ANI1 -32
ANI1 -33
ANI1 -34
ANI1 -35
ANI1 -36
ANI1 -37
ANI1 -38
ANI1 -39
ANI1 -40
ANI1 -41
ANI1 -42
ANI1 -43
ANI1 -44
ANI1 -45
ANI1 -46
ANI1 -47
ANI1 -48
2_BRG1_CN411
2_DRS_CN100
CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100
9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P
LPVOL
AD1 -3
AD1 -4
CN003 CN002 CN001 CN003 CN002 CN001
10P 12P 16P 10P 12P 16P
LED -1
LED -2
LED -3
LED -4
TO BOTTOM ASSEMBLY
TO BOTTOM ASSEMBLY
1
2_DSP_CN121
2_DSP_CN122
2_DSP_CN123
CN202 CN202 CN202 CN202
3 3P 3P 3P 3P
3P 3P 3P 3P
CN201 CN201 CN201 CN201
ANI1 -1
ANI1 -2
ANI1 -3
ANI1 -4
ANI1 -5
ANI1 -6
ANI1 -7
ANI1 -8
ANI1 -9
ANI2 -1
ANI2 -2
ANI2 -3
ANI2 -4
ANI1 -10
ANI1 -11
ANI1 -12
ANI1 -13
ANI1 -14
ANI1 -15
ANI1 -16
ANI1 -17
ANI1 -18
ANI1 -19
ANI1 -20
ANI1 -21
ANI1 -22
ANI1 -23
ANI1 -24
CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100 CN100
9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P
4
9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P 9P
CN101 CN102 CN201 CN202 CN301 CN302 CN401 CN402 CN501 CN502 CN601 CN602 CN101 CN102 CN201 CN202 CN301 CN302 CN401 CN402 CN501 CN502 CN601 CN602 CN301 CN401 CN501 CN601
AD1 -1
AD1 -2
AD2
CN003 CN002 CN001 CN003 CN002 CN001 CN003 CN002 CN001
10P 12P 16P 10P 12P 16P 9P 8P 15P
TO BOTTOM ASSEMBLY
TO BOTTOM ASSEMBLY
TO BOTTOM ASSEMBLY
1
1
(SEE PAGE 19)
(SEE PAGE 19)
2_DSP_CN117
2_DSP_CN118
2_DSP_CN119
2_DSP_CN124
2_DSP_CN125
Note1) ∗
The connection of the part marked with an (digits) on the wire will be described in detail on pages 19, 20, and 21.
Other part has an one-to-one relation with a connector.
5 注1) ∗
(配線に (数字)印がついている部分の接続は19、20、21ページに詳細を示します。
その他はコネクタ1対1の対応です。)
(リア上Ass'y)
REAR UPPER ASSEMBLY
6 28CA2-8831131-3 OVERALL CONNECTOR CIRCUIT DIAGRAM 003 (PM5D)
16
H G F E D C B A
PM5D
OVERALL CONNECTOR CIRCUIT DIAGRAM 004 (PM5D)
1
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
(TO BOTTOM ASSEMBLY)
CH13
CH14
CH15
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
2_BRG1_CN408
2_MAIN_CN1
3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P
CN501 CN504 CN502 CN505 CN503 CN506 CN507 CN510 CN508 CN511 CN509 CN512 CN513 CN516 CN514 CN517 CN515 CN518 CN519 CN522 CN520 CN523 CN521 CN524
CN539
CN500
CN532
32P
32P
3P
6P
CN100
FDB
CN200
CN538
CN529
32P
32P
PN2 -2
8P
12P
30P
2
CN100
CN525
CN528
24P
11P
PN3 -4
24P
8P
CN800
SL
20P
CN526 CN527 CN537 CN540 CN530 CN533 CN535 CN531 CN534 CN536
12P
30P 20P 26P 25P 12P 11P 12P 12P 11P 12P
11P
PN3 -3
12P
9P 15P
CN102 CN101
3
PN1
11P
5P PN3 -2
12P
5P 7P
CN208 CN207
CN204
6P
11P
CN203
PN3 -1
CN500
CN28
CN31
32P
32P
4
8P
7P
BRG2
12P
CN206
CN200
CN36
CN27
32P
32P
7P
PN2 -1
9P
FDA
CN205
CN100
CN30
CN25
24P
9P
24P
4P
CN201 CN202
4P 10P CN1 CN4 CN2 CN5 CN3 CN6 CN7 CN10 CN8 CN11 CN9 CN12 CN13 CN16 CN14 CN17 CN15 CN18 CN19 CN22 CN20 CN23 CN21 CN24
3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P
2_BRG5_CN811
2_BRG5_CN812
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
(TO BOTTOM ASSEMBLY)
CH10
CH11
CH12
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
TO BOTTOM
2_BRG1_CN407
ASSEMBLY
Note1) In the drawing, the symbol shows an FFC connector by which 1Pin is connected to nPin, 2Pin to (n-2)Pin, ..., and nPin to 1Pin. Note2) Destination name
Where, nPin is the maximum number of pins in the connector. 注2) (行き先名称)
Other connector connects 1Pin to 1Pin and nPin to nPin.
*_***_CN***
注1) (図中の▲はFFCコネクタを表し、1PinとnPin、2Pinと(n-2)Pin...nPinと1Pinが接続されます。
尚、nPinはコネクタのPin数の最大数です。 Destination connector No. (接続先コネクタ番号)
その他のコネクタは1Pinと1Pin、nPinとnPinが接続されます。) Destination sheet name (接続先シート名)
Destination page of the signal (信号の行き先ページ番号)
CONTROL PANEL 1 ASSEMBLY (LEFT)(コンパネ1 Ass'y (LEFT))
Note3) indicates the sheet name. 注3) ( 内はシート名称を示します。)
PM5D
OVERALL CONNECTOR CIRCUIT DIAGRAM 005 (PM5D)
1
2_DA2_CN905
CN300
CN101
CN102
TBVOL
2_MAIN_CN10
9P
4P
8P
TO BOTTOM ASSEMBLY (SEE PAGE 20) MNVOL TO BOTTOM ASSEMBLY 2_MAIN_CN15 TPSW TO TRACK PAD
2_DA2_CN906
CN102
2_PHN2_CN600
3P (TO BOTTOM ASSEMBLY)
3P
CN101 3
2_BRG1_CN421
CN200
15P
CN500
3
14P
CN
2_BRG1_CN432
CN400
14P
12P
CN600
2_MAIN_CN8 (SEE PAGE 20)
7P
TB (TO BOTTOM ASSEMBLY) DC-AC
CN1
5P
INVERTER LCD TO BOTTOM
PHN1 CUVOL
2_DSP_CN131
ASSEMBLY
CN2
CN
CN100
2P
2P
CN401
14P
CN501
7P
2_PHN2_CN503 2_DA2_CN904
13P
(TO BOTTOM ASSEMBLY)
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
ST OUT A
ST OUT B
ST IN 1
ST IN 2
ST IN 3
ST IN 4
DCA1
DCA2
DCA3
DCA4
DCA5
DCA6
DCA7
DCA8
3
3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P
CN101 CN104 CN102 CN105 CN103 CN106 CN107 CN110 CN108 CN111 CN109 CN112 CN201 CN204 CN202 CN205 CN203 CN206 CN207 CN210 CN208 CN211 CN209 CN212 CN301 CN303 CN302 CN304
FDC
CN703 CN701 CN702 CN601 CN714 CN705 CN707 CN709 CN706 CN708
5P 4P 6P 35P 12P 15P 7P 12P 15P 17P
2_BRG1_CN409
4
TO BOTTOM ASSEMBLY
5P
5P
2_BRG5_CN813
CN201
CN500
CN100
11P
11P
CN100
7P
CN600 CN101
13P 4P
2_MAIN_CN2
(TO BOTTOM ASSEMBLY) Note1) In the drawing, the symbol shows an FFC connector by which 1Pin is connected to nPin, 2Pin to (n-2)Pin, ..., and nPin to 1Pin. Note3) Destination name
13P 4P Where, nPin is the maximum number of pins in the connector. 注3) (行き先名称)
5 CN900 CN200 Other connector connects 1Pin to 1Pin and nPin to nPin.
*_***_CN***
注1) (図中の▲はFFCコネクタを表し、1PinとnPin、2Pinと(n-2)Pin...nPinと1Pinが接続されます。
尚、nPinはコネクタのPin数の最大数です。 Destination connector No.
SR (2/2) PN8 2/2 その他のコネクタは1Pinと1Pin、nPinとnPinが接続されます。) (接続先コネクタ番号)
Destination sheet name
Note2) ∗
The connection of the part marked with an (digits) on the wire will be described in detail on pages 19, 20, and 21.
Other part has an one-to-one relation with a connector.
(接続先シート名)
Destination page of the signal
ENCODER 注2) ∗
(配線に (数字)印がついている部分の接続は19、20、21ページに詳細を示します。
その他はコネクタ1対1の対応です。)
(信号の行き先ページ番号)
PM5D
OVERALL CONNECTOR CIRCUIT DIAGRAM 006 (PM5D)
BRG1 AD1 AD2 1
*1 Circuit Board name CN number PIN number Circuit Board name CN number PIN number Circuit Board name CN number PIN number Circuit Board name CN number PIN number
(シート名)(CN番号) (ピン番号) (シート名)(CN番号) (ピン番号) (シート名)(CN番号) (ピン番号) (シート名)(CN番号) (ピン番号)
AD1-1 CN001 15 BRG1 CN424 1 AD1-1 CN001 5 BRG1 CN429 1
AD1-1 CN001 16 2 AD1-1 CN001 6 2
AD1-2 CN001 15 3 AD1-2 CN001 5 3
AD1-2 CN001 16 4 AD1-2 CN001 6 4
5 AD1-3 CN001 5 5
AD1-3 CN001 15 6 AD1-3 CN001 6 6
AD1-3 CN001 16 7 7
AD1-4 CN001 15 8 8
AD1-4 CN001 16 9 AD1-4 CN001 5 9
AD2 CN001 14 10 AD1-4 CN001 6 10
AD2 CN001 15 11 AD2 CN001 4 11
AD2 CN001 5 12
2
AD1-1 CN001 2 BRG1 CN425 1 13
AD1-2 CN001 2 2 14
AD1-3 CN001 2 3
AD1-4 CN001 2 4 AD2 CN001 8 BRG1 CN430 1
AD2 CN001 1 5 AD2 CN001 9 2
3
AD1-1 CN001 3 BRG1 CN426 1 4
AD1-1 CN001 4 2 AD1-3 CN001 9 5
AD1-2 CN001 3 3 AD1-3 CN001 10 6
AD1-2 CN001 4 4 AD1-4 CN001 9 7
AD1-3 CN001 3 5 AD1-4 CN001 10 8
AD1-3 CN001 4 6 9
AD1-4 CN001 3 7 10
AD1-4 CN001 4 8 AD1-1 CN001 9 11
AD2 CN001 2 9 AD1-1 CN001 10 12 3
AD2 CN001 3 10 AD1-2 CN001 9 13
AD1-2 CN001 10 14
AD1-1 CN001 1 BRG1 CN427 1 15
AD1-2 CN001 1 2 16
AD1-3 CN001 1 3
AD1-4 CN001 1 4 AD1-1 CN001 7 BRG1 CN431 1
5 AD1-1 CN001 8 2
6 AD2 CN001 6 3
7 AD2 CN001 7 4
8 AD1-2 CN001 7 5
9 AD1-2 CN001 8 6
10 7
11 8
12 AD1-3 CN001 7 9
13 AD1-3 CN001 8 10 4
14 11
12
AD1-1 CN001 13 BRG1 CN428 1 AD1-4 CN001 7 13
AD1-1 CN001 14 2 AD1-4 CN001 8 14
AD1-2 CN001 13 3 15
AD1-2 CN001 14 4 16
AD1-3 CN001 13 5
AD1-3 CN001 14 6 AD1-1 CN001 11 BRG1 CN433 1
AD1-4 CN001 13 7 AD1-1 CN001 12 2
AD1-4 CN001 14 8 AD1-2 CN001 11 3
AD2 CN001 12 9 AD1-2 CN001 12 4
AD2 CN001 13 10 AD1-3 CN001 11 5
AD1-3 CN001 12 6
TOP ASSEMBLY BOTTOM ASSEMBLY AD1-4 CN001 11 7
AD1-4 CN001 12 8 5
AD2 CN001 10 9
AD2 CN001 11 10
11
Note) The pins in the same in the same line are connected to eath other. 12
A pin having no destination for connection is not used.
13
注) (同一行で同順のピン同士が接続されます。
接続先がないピンは空き端子です。) 14
20
A
*2 DA2 - MNVOL
Circuit Board name CN number PIN number Circuit Board name CN number PIN number
(シート名)(CN番号)(ピン番号) (シート名)(CN番号)(ピン番号)
DA2 CN905 1 MNVOL CN300 1
2 2
3 3
4 4
B
5 5
6 6
CN906 1 7
28CA2-8831131-7
2 8
3 9
Circuit Board name CN number PIN number Circuit Board name CN number PIN number
(シート名)(CN番号)(ピン番号) (シート名) (CN番号)(ピン番号)
CUVOL CN400 1 PHN1 CN600 1
C
2 2
3 3
*3 PHN1, PHN2-CUVOL 4 4
5 5
Circuit Board name CN number PIN number 6 6
(シート名)(CN番号)(ピン番号) 7
PHN2 CN600 1 7
OVERALL CONNECTOR CIRCUIT DIAGRAM 007 (PM5D)
2 8
3 9
4 10
D
5 11
6 12
(シート名)(CN番号)(ピン番号) (シート名)(CN番号)(ピン番号)
DC 1 BRG5 CN801 1
POWER 2 2
INPUT 3 3
(PW800W) 4 4
5 5
6 6
7 7
注)
Note)
8 8
BOTTOM ASSEMBLY
9 9
F
10 CN802 1
11 2
12 3
13 4
接続先がないピンは空き端子です。)
14 5
(同一行で同順のピン同士が接続されます。
15 6
A pin having no destination for connection is not used.
16 7
17 8
The pins in the same in the same line are connected to eath other.
18 9
10
G
19 CN803 1
20 2
21 3
22 4
23 5
24
H
PM5D
OVERALL CONNECTOR CIRCUIT DIAGRAM 008 (PM5D)
1
Circuit Board name CN number PIN number Circuit Board name CN number PIN number
(シート名)(CN番号) (ピン番号) (シート名) (CN番号)(ピン番号) 2
BRG1 CN411 1 LPVOL CN100 1
2 2
3
4
Circuit Board name CN number PIN number Circuit Board name CN number PIN number Circuit Board name CN number PIN number
(シート名)(CN番号) (ピン番号) (シート名)(CN番号) (ピン番号) (シート名)(CN番号) (ピン番号)
DR CN100 1 DRL CN100 1 DRN CN100 1 4
2 2 2
3 3 3
4 4 4
5 5 5
6 6 6
7 7 7
8 8 8
9 9 9
10 10 10
11 11 11 5
12 12 12
Note) The pin numbers which are not connected are terminals which are not used.
注) ( 接続されていないピンは空き端子です。)
PM5D-RH
OVERALL CONNECTOR CIRCUIT DIAGRAM 001 (PM5D-RH)
CONTROL PANEL 2
CONTROL PANEL 1
1
ASSEMBLY, RIGHT
ASSEMBLY, LEFT
*4
*4
*4
*1−1
REAR UPPER ASSEMBLY(SEE PAGE 24)
4
9P 9P 9P 9P 9P 9P 9P
CN981 CN981 CN981 CN981 CN981 CN981 CN981
AD3 -1 AD3 -2 AD3 -3 AD3 -4 AD3 -5 AD3 -6 AD3 -7 SW48 AD3 -1 AD3 -2 AD3 -3 AD3 -4 AD3 -5 AD3 -6 AD3 -7
INDEX
PAGE ASSEMBLY SHEET
BOTTOM ASSEMBLY
23 BRG1, BRG4, BRG5, DSP, MAIN, JK1, JK2, OPT, ANI3, DA1, DA2, DA3, PHN2, DR, DRN, DRL, CN1R
(ボトムAss'y)
5 REAR UPPER ASSEMBLY
24 AD3, LD, STLD, SW48, LPVOL
(リア上Ass'y)
CONTROL PANEL 1 ASSEMBLY, LEFT
∗
Note1) The connection of the part marked with an (digits) on the wire will be described in detail on pages 27, 28, and 29. 25
(コンパネAss'y 1 (LEFT))
BRG2, SL, FDA, FDB, PN1, PN2, PN3
Other part has an one-to-one relation with a connector.
∗
注1) (配線に (数字)印がついている部分の接続は27、28、29ページに詳細を示します。
26
CONTROL PANEL 2 ASSEMBLY, RIGHT
BRG3, SR, FDC, TB, MNVOL, CUVOL, PHN1, PN4, PN5, PN6, PN8, LCD, DC-AC INVERTER, TPSW
その他はコネクタ1対1の対応です。) (コンパネAss'y 2 (RIGHT))
Wiring Diagram of Connector Assembly Wiring diagram of connector assembly for a wire marked with *(digits)
27, 28, 29
(束線結線表) *(数字)印部分の束線結線表
PM5D-RH
OVERALL CONNECTOR CIRCUIT DIAGRAM 002 (PM5D-RH)
TO CONTROL
1
TO CONTROL PANEL PANEL ASSEMBLY
ASSEMBLY LEFT RIGHT TO REAR UPPER ASSEMBLY
CN815 CN814
CN202 CN201
CN803 CN802 CN801
5P
5P
9P
CN205 CN204
CN807 CN806
7P
7P
BRG5
10P
6P
6P
BRG4 OPT
10P
10P
JK1 JK2
5P
CN816
CN203
(SEE PAGE 28)
8P
8P
CN807 CN808 CN810 CN809 CN801 CN802 CN803 CN804 CN805 CN907 CN902 CN901 CN510 CN506 CN509 CN508 CN507
3P 7P 9P 10P 32P 31P 30P 24P 40P 11P 40P 36P 8P 37P 22P 32P 34P
3P
CN102
2P
CN101
2P
CN101
3P
CN102
2P
CN101 2
CN137 CN138
CN415 CN414 CN420 CN419 CN406 CN405 CN403 CN404
CN433 CN431 CN430 CN429 CN427
10P
10P
(SEE PAGE 27) 14P
9P
9P
14P
TO REAR
11P
16P
8P
16P
14P
8P
14P
14P
4P
DSP
12P
12P
12P
16P
12P 12P
CN402 CN401 CN432 CN409 CN421 CN408 CN407 CN422 CN423
5P 7P 14P 5P 15P 3P 4P 3P 6P
CN131
14P
8P
(TO CONTROL PANEL ASSEMBLY RIGHT)
TO CONTROL PANEL ASSEMBLY RIGHT TO CONTROL PANEL TO REAR UPPER CN102 CN101 CN127 CN128 CN129 CN130 CN132 CN133 CN135 CN134 CN126 CN136
ASSEMBLY LEFT ASSEMBLY
TO CONTROL PANEL ASSEMBLY RIGHT 100P 80P 11P 8P 8P 8P 11P 8P 10P 4P 13P 13P
5P 7P 14P 5P
CN14 CN7 CN10 CN8
13P
4
100P
CN5
11P 8P CN001
11P 8P
JK1
CN901 CN903
6P
CN901 CN903
CN002
CN6
80P
12P
CN001
ANI3
14P
CN001
14P
JK2
6P
DA1 -1 DA1 -4
MAIN
(MIX1-8OUT) (MTRX OUT)
CN15 CN13
CN002
68P
14P
CN002
14P
CN902
TO CONTROL PANEL 2 CN902
11P
4P
CN002 CN001
240P 7P 6P
CN002 CN001
14P
DA1 -2
CN500
CN503
14P
16P
13P
Note1) In the drawing, the symbol shows an FFC connector by 6P 8P 4P 12P 12P 12P 12P 8P DA3 PHN2
which 1Pin is connected to nPin, 2Pin to (n-2)Pin, ..., and nPin to 1Pin. (TO CONTROL PANEL
ASSEMBLY LEFT)
CN101 CN108 CN102 CN103 CN104 CN105 CN106 CN107
(MIX9-16OUT) (TO CONTROL PANEL ASSEMBLY RIGHT)
14P
14P
Where, nPin is the maximum number of pins in the connector.
CN901 CN600
Other connector connects 1Pin to 1Pin and nPin to nPin. (TO CONTROL PANEL CN901
ASSEMBLY RIGHT) CN1R 11P
11P 6P
注1) (図中の▲はFFCコネクタを表し、1PinとnPin、2Pinと(n-2)Pin...nPinと1Pinが接続されます。
尚、nPinはコネクタのPin数の最大数です。 10P 11P (SEE PAGE 28)
11P 8P
CN903 CN901
その他のコネクタは1Pinと1Pin、nPinとnPinが接続されます。) CN109 CN110 CN111 CN112 CN113 CN114 CN115 CN901 CN903
∗
(TO CONTROL PANEL ASSEMBLY RIGHT)
5
CN001
28P 28P 28P 28P 28P 28P 28P
14P
CN001
Note2) The connection of the part marked with an (digits) on the wire will be described in detail on pages 27, 28, and 29.
DA1 -3
14P
Other part has an one-to-one relation with a connector. DA2
注2) ∗
(配線に (数字)印がついている部分の接続は27、28、29ページに詳細を示します。
その他はコネクタ1対1の対応です。)
(MIX17-24
OUT
)
TO REAR UPPER ASSEMBLY CN906 CN905 CN904
3P 6P 7P
Note2) Destination name 注2) (行き先名称)
*_***_CN*** (SEE PAGE 28)
PM5D
OVERALL CONNECTOR CIRCUIT DIAGRAM 003 (PM5D-RH)
1
LD -1
LD -2
LD -3
SW48
Note1) In the drawing, the symbol shows an FFC connector by which 1Pin is connected to nPin, 2Pin to (n-2)Pin, ..., and nPin to 1Pin.
Where, nPin is the maximum number of pins in the connector.
Other connector connects 1Pin to 1Pin and nPin to nPin.
注1) (図中の▲はFFCコネクタを表し、1PinとnPin、2Pinと(n-2)Pin...nPinと1Pinが接続されます。
尚、nPinはコネクタのPin数の最大数です。
その他のコネクタは1Pinと1Pin、nPinとnPinが接続されます。)
AD3 -3
AD3 -5
Note4) indicates the sheet name. 注4) ( 内はシート名称を示します。)
STLD
TO BOTTOM ASSEMBLY
TO BOTTOM ASSEMBLY
TO BOTTOM ASSEMBLY
3
(SEE PAGE 27)
32P
CN961
LPVOL
AD3 -7
AD3 -2
AD3 -4
AD3 -6
4
CN501
4P
TO BOTTOM ASSEMBLY
TO BOTTOM ASSEMBLY
TO BOTTOM ASSEMBLY
TO BOTTOM ASSEMBLY
(SEE PAGE 27)
(リア上Ass'y)
REAR UPPER ASSEMBLY
6 28CA2-8831398-3 1 OVERALL CONNECTOR CIRCUIT DIAGRAM 003 (PM5D-RH)
24
H G F E D C B A
PM5D-RH
OVERALL CONNECTOR CIRCUIT DIAGRAM 004 (PM5D-RH)
1
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
2_MAIN_CN1
CH13
CH14
CH15
CH16
CH17
CH18
CH19
CH20
CH21
CH22
CH23
CH24
(TO BOTTOM ASSEMBLY)
6P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P
CN102
12P
CN100 CN501 CN504 CN502 CN505 CN503 CN506 CN507 CN510 CN508 CN511 CN509 CN512 CN513 CN516 CN514 CN517 CN515 CN518 CN519 CN522 CN520 CN523 CN521 CN524
2_BRG1_CN408
(TO BOTTOM ASSEMBLY)
CN532
CN539
CN500
32P
32P
3P
CN101
11P
PN3 -4
FDB
CN538
CN200
CN529
32P
32P
6P
PN2 -2
2
CN100
CN801
SL
12P
30P
CN100
CN528
CN525
24P
24P
8P
CN800
20P
CN526 CN527 CN537 CN540 CN530 CN533 CN535 CN531 CN534 CN536
30P 20P 26P 25P 12P 11P 12P 12P 11P 12P
CN102
12P
9P 15P 7P
CN101
11P
PN3 -3
9P 15P
CN100
CN102 CN101
12P
3
PN1
CN100
12P
CN100
5P
CN101
11P
PN3 -2
CN102
12P
5P 7P
26P
CN29
25P
CN26
12P
CN35
11P
CN37
12P
CN38
12P
CN32
11P
CN33
12P
CN34 4
CN208 CN207
CN500
CN31
CN28
32P
32P
CN204
7P
6P
CN100
12P
CN200
CN36
CN27
32P
32P
CN203
9P
PN2 -1
8P
FDA
CN101
11P
BRG2 PN3 -1
CN100
CN25
CN30
24P
24P
CN206
4P
7P
CN102
12P
CN1 CN4 CN2 CN5 CN3 CN6 CN7 CN10 CN8 CN11 CN9 CN12 CN13 CN16 CN14 CN17 CN15 CN18 CN19 CN22 CN20 CN23 CN21 CN24
3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P
CN205
9P
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
CN201 CN202
4P 10P
CH10
CH11
CH12
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
2_BRG5_CN811 2_BRG5_CN812 2_BRG1_CN407
(TO BOTTOM ASSEMBLY)
5
TO BOTTOM ASSEMBLY
Note1) In the drawing, the symbol shows an FFC connector by which 1Pin is connected to nPin, 2Pin to (n-2)Pin, ..., and nPin to 1Pin. Note2) Destination name
Where, nPin is the maximum number of pins in the connector. 注2) (行き先名称)
Other connector connects 1Pin to 1Pin and nPin to nPin.
*_***_CN***
注1) (図中の▲はFFCコネクタを表し、1PinとnPin、2Pinと(n-2)Pin...nPinと1Pinが接続されます。
尚、nPinはコネクタのPin数の最大数です。 Destination connector No. (接続先コネクタ番号)
その他のコネクタは1Pinと1Pin、nPinとnPinが接続されます。) Destination sheet name (接続先シート名)
Destination page of the signal (信号の行き先ページ番号)
PM5D-RH
OVERALL CONNECTOR CIRCUIT DIAGRAM 005 (PM5D-RH)
1
2_DA2_CN905
TO BOTTOM ASSEMBLY
TO BOTTOM ASS'Y
TO TRACK PAD
2_MAIN_CN15
TBVOL
CN300
(TO BOTTOM ASS'Y)
CN101
CN102
9P
2
4P
8P
MNVOL TPSW
2_DA2_CN906
2_MAIN_CN10
2_PHN2_CN600
CN102
3P
3P
3
(SEE PAGE 28)
CN101
2
2_BRG1_CN421
2_BRG1_CN432
CN200
CN500
TO BOTTOM ASS'Y
15P
14P
CN
14P
CN400
(TO BOTTOM ASS'Y)
TO BOTTOM ASS'Y
3
CN600
12P
2_MAIN_CN8
7P
TB DC-AC
CN1
LCD
5P
PHN1 CUVOL
2_DA2_CN904
CN100
CN2
CN
2P
2P
2_PHN2_CN503
14P
CN401
CN501
7P
13P
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
MOTORIZED FADER
ST OUT A
ST OUT B
3
ST IN 1
ST IN 2
ST IN 3
ST IN 4
DCA1
DCA2
DCA3
DCA4
DCA5
DCA6
DCA7
DCA8
3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P 3P 4P
CN101 CN104 CN102 CN105 CN103 CN106 CN107 CN110 CN108 CN111 CN109 CN112 CN201 CN204 CN202 CN205 CN203 CN206 CN207 CN210 CN208 CN211 CN209 CN212 CN301 CN303 CN302 CN304
CN703 CN701 CN702 CN601 CN714 CN705 CN707 CN709 CN706 CN708
4 5P 4P 6P 35P 12P 15P 7P 12P 15P 17P
2_BRG1_CN409
TO BOTTOM ASS'Y
5P
5P
2_BRG5_CN813
CN201
CN100
CN500
CN600 CN101
(TO BOTTOM ASS'Y)
13P 4P
2_MAIN_CN2
Note1) In the drawing, the symbol shows an FFC connector by which 1Pin is connected to nPin, 2Pin to (n-2)Pin, ..., and nPin to 1Pin. Note3) Destination name
5 13P 4P
Where, nPin is the maximum number of pins in the connector.
Other connector connects 1Pin to 1Pin and nPin to nPin.
注3) (行き先名称)
CN900 CN200 *_***_CN***
注1) (図中の▲はFFCコネクタを表し、1PinとnPin、2Pinと(n-2)Pin...nPinと1Pinが接続されます。
尚、nPinはコネクタのPin数の最大数です。 Destination connector No.
SR (2/2) PN8 2/2 その他のコネクタは1Pinと1Pin、nPinとnPinが接続されます。) (接続先コネクタ番号)
Destination sheet name
ENCODER Note2) ∗
The connection of the part marked with an (digits) on the wire will be described in detail on pages 27, 28, and 29.
Other part has an one-to-one relation with a connector.
(接続先シート名)
Destination page of the signal
注2) ∗
(配線に (数字)印がついている部分の接続は27、28、29ページに詳細を示します。
その他はコネクタ1対1の対応です。)
(信号の行き先ページ番号)
*1-1 *1-2
Power supply cable for digital Power supply cable for digital Power supply cable for analog
28CA2-8831398-6
(DIGITAL用電源束線) (ANALOG用電源束線) (ANALOG用電源束線)
1
G
Circuit Board name CN number PIN number Circuit Board name CN number PIN number Circuit Board name CN number PIN number Circuit Board name CN number PIN number
(シート名)(CN番号)(ピン番号) (シート名)(CN番号)(ピン番号) (シート名)(CN番号)(ピン番号) (シート名)(CN番号)(ピン番号)
AD3_1 CN981 1 BRG1 CN427 1 AD3_1 CN982 1 BRG1 CN429 1
AD3_1 CN981 2 2 AD3_1 CN982 2 2
AD3_2 CN981 1 3 AD3_2 CN982 1 3
AD3_2 CN981 2 4 AD3_2 CN982 2 4
AD3_3 CN981 1 5 AD3_3 CN982 1 5
AD3_3 CN981 2 6 AD3_3 CN982 2 6
AD3_4 CN981 1 7 AD3_4 CN982 1 7
AD3_4 CN981 2 8 AD3_4 CN982 2 8
AD3_5 CN981 1 9 AD3_5 CN982 1 9
AD3_5 CN981 2 10 AD3_5 CN982 2 10
AD3_6 CN981 1 11 AD3_6 CN982 1 11
AD3_6 CN981 2 12 AD3_6 CN982 2 12
F
注)
Note)
AD3_1 CN981 6 BRG5 CN819 1 AD3_3 CN982 6 8
AD3_1 CN981 7 2 AD3_4 CN982 5 9
AD3_1 CN981 8 3 AD3_4 CN982 6 10
E
接続先がないピンは空き端子です。)
AD3_4 CN981 6 10
(同一行で同順のピン同士が接続されます。
AD3_4 CN981 7 11 Circuit Board name CN number PIN number Circuit Board name CN number PIN number
(シート名)(CN番号)(ピン番号) (シート名)(CN番号)(ピン番号)
The pins in the same in the same line are connected to eath other.
AD3_5 CN981 8 4 4
AD3_6 CN981 6 5 AD3_2 CN982 3 5
D
AD3_3 CN981 3 7
AD3_3 CN981 4 8 REAR UPPER ASSEMBLY BOTTOM ASSEMBLY
AD3_3 CN981 5 9
27
6
5
4
3
2
1
6
5
4
3
2
1
28
A
*2 DA2-MNVOL
Circuit Board name CN number PIN number Circuit Board name CN number PIN number
(シート名)(CN番号)(ピン番号) (シート名)(CN番号)(ピン番号)
DA2 CN905 1 MNVOL CN300 1
2 2
3 3
4 4
B
5 5
6 6
28CA2-8831398-7
CN906 1 7
2 8
3 9
Circuit Board name CN number PIN number Circuit Board name CN number PIN number
C
2 8
D
3 9
4 10
5 11
6 12
*4 DC POWER INPUT-BRG5
Circuit Board name CN number PIN number Circuit Board name CN number PIN number
(シート名)(CN番号)(ピン番号) (シート名)(CN番号)(ピン番号)
DC 1 BRG5 CN801 1
POWER 2 2
INPUT 3 3
(PW800W) 4 4
F
5 5
6 6
7 7
8 8
9 9
10 CN802 1
11 2
12 3
13 4
G
14 5
15 6
注)
Note)
16 7
17 8
18 9
10
19 CN803 1
20 2
接続先がないピンは空き端子です。)
21 3
(同一行で同順のピン同士が接続されます。
22 4
H
23 5
A pin having no destination for connection is not used.
24
The pins in the same in the same line are connected to eath other.
PM5D-RH
PM5D-RH
OVERALL CONNECTOR CIRCUIT DIAGRAM 008 (PM5D-RH)
1
Circuit Board name CN number PIN number Circuit Board name CN number PIN number
(シート名) (CN番号)(ピン番号) (シート名) (CN番号)(ピン番号)
BRG1 CN411 1 LPVOL CN501 1
2 2
3
2
4
Circuit Board name CN number PIN number Circuit Board name CN number PIN number Circuit Board name CN number PIN number
(シート名) (CN番号)(ピン番号) (シート名) (CN番号)(ピン番号) (シート名) (CN番号)(ピン番号)
DR CN100 1 DRL CN100 1 DRN CN100 1
2 2 2
3 3 3 4
4 4 4
5 5 5
6 6 6
7 7 7
8 8 8
9 9 9
10 10 10
11 11 11
12 12 12
5
Note) The pin numbers which are not connected are terminals which are not used.
注) ( 接続されていないピンは空き端子です。)
52147-1010
52147-1210
from DSP-CN116,CN118, to DSP-CN117,CN119,CN121,CN123
CN120, CN122
INVERTER to BRG1-CN424,CN425,CN426,CN427,CN428,
CN429,CN430,CN431,CN433
2
PH16P
3
DSS6NF31C223Q93A
DSS6NF31C223Q93A
DSS6NF31C223Q93A
DSS6NF31C223Q93A
DSS6NF31C223Q93A
4 TRANSCEIVER
TRANSCEIVER
10
11
13
14
15
IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 IN10 IN11 IN12
to ANI1-CN100 to ANI1-CN100 to ANI1-CN100 to ANI1-CN100 to ANI1-CN100 to ANI1-CN100 to ANI1-CN100 to ANI1-CN100 to ANI1-CN100 to ANI1-CN100 to ANI1-CN100 to ANI1-CN100
16 XX:not installed(未実装部品)
(F):Metal Film Resistor(金属被膜抵抗)
30 28CC1-8822218-1 5 (マ):Mylar Capacitor(マイラーコンデンサ)
(OS):Organic Semiconductor Aluminum Electrolytic Capacitor(有機半導体アルミ電解コンデンサ)
■ AD1 CIRCUIT DIAGRAM (PM5D)
17
W V U T S R Q P O N M L K J I H G F E D C B A
OP AMP TRANSCEIVER
2
ADC
to DSP-CN124
3
INVERTER
4
to ANI2 (1)-CN100
5
OP AMP
TRANSCEIVER 6
ADC
to DSP-CN125
7
to ANI2 (2)-CN100 8
RB551V-30 (V9634300)
DIODE
OP AMP 9
1
2
ADC
10
1: ANODE
2: CATHODE
11
to ANI2 (3)-CN100
12
OP AMP
13
ADC to BRG1-CN424,CN425,CN426,
CN428,CN429,CN430,
CN431,CN433 14
15
to ANI2 (4)-CN100
16
XX:not installed(未実装部品)
(F):Metal Film Resistor(金属被膜抵抗)
17
28CC1-8831284-1 1 31
(マ):Mylar Capacitor(マイラーコンデンサ)
(OS):Organic Semiconductor Aluminum Electrolytic Capacitor(有機半導体アルミ電解コンデンサ)
■ AD2 CIRCUIT DIAGRAM (PM5D)
W V U T S R Q P O N M L K J I H G F E D C B A
2
OP AMP
3
OP AMP
4 ADC
MULTIPLEXER
5 to HIC-HA-CN101
7
OP AMP
OP AMP
9 MULTIPLEXER
to HIC-HA-CN101
11 1 1
OP AMP
2 2
12 ADC
1: ANODE 1: ANODE
2: CATHODE 2: CATHODE
MULTIPLEXER
13 to HIC-HA-CN101
14
15 OP AMP
OP AMP
XX:not installed(未実装部品)
(F):Metal Film Resistor(金属被膜抵抗)
16 (フ):Flame Proof C. Resistor(不燃化カーボン抵抗)
(M):Mica Capacitor(マイカコン)
(OS):Organic Semiconductor Aluminum Electrolytic Capacitor(有機半導体アルミ電解コンデンサ)
17 32 28CC1-8829580-1 6
■ AD3 CIRCUIT DIAGRAM 001 (PM5D-RH)
W V U T S R Q P O N M L K J I H G F E D C B A
1
MULTIPLEXER
to HIC-HA-CN101 1
2
2
1: ANODE
2: CATHODE
OP AMP
D1F60 (VS201100)
DIODE
3
OP AMP
1
ADC 2
4
1: ANODE
2: CATHODE
MULTIPLEXER 5
to HIC-HA-CN101
7
OP AMP
OP AMP
9
MULTIPLEXER
to HIC-HA-CN101
10
OP AMP
11
OP AMP
ADC 12
MULTIPLEXER
to HIC-HA-CN101 13
14
15
OP AMP
OP AMP XX:not installed(未実装部品)
(F):Metal Film Resistor(金属被膜抵抗)
(フ):Flame Proof C. Resistor(不燃化カーボン抵抗)
(M):Mica Capacitor(マイカコン) 16
(OS):Organic Semiconductor Aluminum Electrolytic Capacitor(有機半導体アルミ電解コンデンサ)
28CC1-8829580-2 6 33
■ AD3 CIRCUIT DIAGRAM 002 (PM5D-RH) 17
P O N M L K J I H G F E D C B A
not installed
4 INVERTER
SRAM 256K
TRANSCEIVER
5 not installed
FLASH ROM
8M
6
OR
INVERTER
SRAM 256K
CPU
7
D-FF
8
DECODER
OR
BUFFER TRANSCEIVER
10 TRANSCEIVER
not installed
11
12 34 28CC1-8829580-3 AND
XX:not installed(未実装部品)
(F):Metal Film Resistor(金属被膜抵抗)
■ AD3 CIRCUIT DIAGRAM 003 (PM5D-RH)
Q P O N M L K J I H G F E D C B A
1
3
2 NAND
1: ANODE
2: CATHODE
PLL
INVERTER 4
SYSTEM
RESET
5
DIR2
PLLP2
(Gate Array)
8
AND
10
INVERTER
11
12
(F):Metal Film Resistor(金属被膜抵抗)
28CC1-8829580-4 35
(マ):Mylar Capacitor(マイラーコンデンサ)
(フ):Film Capacitor(フィルムコンデンサ)
■ AD3 CIRCUIT DIAGRAM 004 (PM5D-RH)
L K J I H G F E D C B A
AND
DSP7
36 28CC1-8829580-5
■ AD3 CIRCUIT DIAGRAM 005 (PM5D-RH)
Q P O N M L K J I H G F E D C B A
not installed
not installed
ATSC2A 6
not installed
TRANSCEIVER
9
MULTIPLEXER
10
to CN1R-CN109,CN110,
CN111,CN112,
CN113,CN114,
CN115
11
INVERTER
12
XX:not installed(未実装部品)
28CC1-8829580-6 37
4 (F):Metal Film Resistor(金属被膜抵抗)
(マ):Mylar Capacitor(マイラーコンデンサ)
■ AD3 CIRCUIT DIAGRAM 006 (PM5D-RH)
P O N M L K J I H G F E D C B
2
D-FF
LED DRIVER
INVERTER
5
6 D-FF
Transistor Array
to LD-CN001
to STLD-CN301
Transistor
Array
8
DECODER
10
11
2
DC-DC CONVERTER
AND
REGULATOR +2.5V
4
1
1
2
3
2
1 2 4 3
1: ANODE to BRG1-CN429, 430, 431, 433
2: CATHODE
7
XX:not installed(未実装部品)
28CC1-8829580-8 7 39
(マ):Mylar Capacitor(マイラーコンデンサ)
(OS):Organic Semiconductor Aluminum Electrolytic Capacitor(有機半導体アルミ電解コンデンサ)
■ AD3 CIRCUIT DIAGRAM 008 (PM5D-RH)
H G F E D C B A
OP AMP
to AD3-IC101, 201, 301, 401, 501, 601, 701, 801
3 OP AMP
DAN217 (VV556300)
DIODE ARRAY 0.3AX2
1
3 2
1: ANODE1
2: CATHODE2
(B):Metal Film Resistor(金属被膜抵抗) Error margin (誤差)± 0.1% 3: CATHODE1,
(D):Metal Film Resistor(金属被膜抵抗) Error margin (誤差)± 0.5% 1 2 ANODE2
40 28CC1-8829594-1 1 (M):Mica Capacitor(マイカコン)
(セ):Ceramic Capacitor(セラコン)
■ HIC-HA CIRCUIT DIAGRAM (PM5D-RH)
H G F E D C B A
INSERT ON/OFF
1
OP AMP
INPUT +48V ON/OFF
DSS6NB32A271Q93A
J100
PAD 26dB
to AD1-CN101,CN102,
J101 CN201,CN202,
CN301,CN302,
CN401,CN402,
CN501,CN502,
GAIN CN601,CN602 2
J102
DSS6NB32A271Q93A
OP AMP
OP AMP 3
DSS6NB32A271Q93A
INSERT OUT
OP AMP
DSS6NB32A271Q93A
4
TLSU126
OP AMP
PEAK
RED
SIGNAL
TLGE50T
GRE
OP AMP
OP AMP
DSS6NB32A271Q93A
5
INSERT IN
OP AMP
DSS6NB32A271Q93A
XX:not installed(未実装部品) 6
(F):Metal Film Resistor(金属被膜抵抗)
(フ):Flame Proof C. Resistor(不燃化カーボン抵抗)
28CC1-8822233-1 6 41
(マ):Mylar Capacitor(マイラーコンデンサ)
(OS):Organic Semiconductor Aluminum Electrolytic Capacitor(有機半導体アルミ電解コンデンサ)
■ ANI1 CIRCUIT DIAGRAM (PM5D)
L K J I H G F E D C B A
OP AMP
1 ANI2 OP AMP
to AD2-CN301,
401, 501, 601
OP AMP
OP AMP
LED
8 XX:not installed(未実装部品)
(F):Metal Film Resistor(金属被膜抵抗)
(フ):Flame Proof C. Resistor(不燃化カーボン抵抗)
42 28CC1-8831304 1 (マ):Mylar Capacitor(マイラーコンデンサ)
(OS):Organic Semiconductor Aluminum Electrolytic Capacitor(有機半導体アルミ電解コンデンサ)
■ ANI2, LED CIRCUIT DIAGRAM (PM5D)
P O N M L K J I H G F E D C B A
OP AMP OP AMP
ADC
TRANSCEIVER 3
INVERTER
to DSP-CN126
4
5
OP AMP OP AMP
ADC 6
9
RB551V-30 (V9634300)
to BRG1-CN414
DIODE
10
1
1: ANODE
2: CATHODE
11
XX:not installed(未実装部品)
(F):Metal Film Resistor(金属被膜抵抗)
28CC1-8831283-1 1 43
(マ):Mylar Capacitor(マイラーコンデンサ)
(OS):Organic Semiconductor Aluminum Electrolytic Capacitor(有機半導体アルミ電解コンデンサ)
■ ANI3 CIRCUIT DIAGRAM (PM5D/PM5D-RH) 12
J I H G F E D C
to BRG5-CN808
to BRG5-CN809
to BRG5-CN810
to BRG5-CN807
(セ):Ceramic Capacitor(セラコン)
INPUT Section
44 28CC1-8830699-2 1
■ BRG1 CIRCUIT DIAGRAM 002 (PM5D/PM5D-RH)
H G F E D C B A
SYSTEM RESET
UDZS22B (WC417200)
ZENER DIODE 22V
1: ANODE
5
2: CATHODE
6
金被:Metal Film Resistor(金属被膜抵抗)
MUTE Section
28CC1-8830699-3 2 45
酸金:Metal Oxide Film Resistor(酸化金属被膜抵抗)
(セ):Ceramic Capacitor(セラコン)
■ BRG1 CIRCUIT DIAGRAM 003 (PM5D/PM5D-RH)
P O N M L K J I H G F E D C B A
1 PM5D:
to AD1-CN001
to AD2-CN001
PM5D-RH: N.C
2 to MAIN-CN7 PM5D:
to AD1-CN001
to DA1-1-CN001
to AD2-CN001
PM5D-RH: N.C
PM-5D: to AD1-CN001
to AD2-CN001
3
to MAIN-CN14 to DR-CN100
PM5D-RH: N.C
to LPVOL-CN100
to DA1-4-CN001
4
to DSP-CN137
CN101
to CN1R-
5
PM5D:
to AD1-CN001
to AD2-CN001
PM5D-RH: N.C
to AD1-CN001
to PHN1-CN500
to DSP-CN138 to AD2-CN001
PM5D-RH:
PM-5D:
to AD3-CN982
6
7 to JK1-CN907
to PHN2-CN500
to AD1-CN001
to AD2-CN002
to AD3-CN982
PM5D:
PM5D-RH:
to AD1-CN001
to AD2-CN001
PM-5D:
8 PM5D-RH:
to AD3-CN982
to JK2-CN510
to TB-CN200
9
PM5D-RH: to AD3-CN981
to FDA-CN30
PM-5D: to AD1-CN001
PM5D-RH: to SW48-CN401
PM5D:
10 to FDB-CN532
to AD1-CN001
to AD2-CN001
PM5D-RH:
PM5D: N.C
to AD3-CN982
to ANI3-CN002
to FDC-CN703
11
OUTPUT Section
12 46 28CC1-8830699-4 4
■ BRG1 CIRCUIT DIAGRAM 004 (PM5D/PM5D-RH)
N M L K J I H G F E D
DC-DC
CONVERTER
3
DC-DC
CONVERTER
LM2678SX-ADJ (X2789A00)
DC-DC CONVERTER
Tab is
Ground
5
1
2
DC-DC
1: SWITCH
3
4 CONVERTER
OUTPUT 5
6
2: INPUT 7
3: C BOOST
4: GROUND
5: NO CONNECTION
6: FEEDBACK
7: ON/OFF 6
DE5S4M (V2330500)
DIODE 40V 5A
4
DC-DC
CONVERTER 7
1
2
3
1 2 4 3
DC-DC
CONVERTER
9
WARNING
Components having special characteristics are marked Z and must be 10
replaced with parts having specification equal to those originally installed. DC-DC
CONVERTER
Z 印の部品は、安全を維持するために重要な部品です。
交換する場合は、安全のために必ず指定の部品をご使用ください。
11
OUTPUT 5 1
6 1: V IN 2 2 2
2: INPUT 7
+15VA (DC-DC CONVERTER: +17.7V) 1: ADJ/GND 3: C BOOST 5 2: V OUT 3
1: INPUT 4: GROUND 3: COM (heat sink)
1 1 2 2: OUTPUT 5: NO CONNECTION 4: O adj 1: ANODE 1: ANODE
2 2: COMMON 3 5: V soft 1 2 4 3 2: CATHODE 2: CATHODE
3 3: INPUT 6: FEEDBACK
3: OUTPUT
2 10EDA40-TA2B5 UDZS16B (VU173100)
7: ON/OFF
1
1
2
2
1: ANODE
3 2: CATHODE 1: ANODE
2: CATHODE
REGULATOR +5V
DC-DC CONVERTER
+5VA (DC-DC CONVERTER: +6.5V)
4
DC-DC CONVERTER REGULATOR
+15VA (DC-DC CONVERTER: +17.7V)
REGULATOR +5V
5
DC-DC CONVERTER
+5VA (DC-DC CONVERTER: +6.5V)
DC-DC CONVERTER
9 DC-DC CONVERTER: +7.5V
DC-DC CONVERTER
DC-DC CONVERTER: +17.2V
10
WARNING
Components having special characteristics are marked Z and must be
replaced with parts having specification equal to those originally installed.
11 Z 印の部品は、安全を維持するために重要な部品です。
交換する場合は、安全のために必ず指定の部品をご使用ください。
DC-DC CONVERTER
3
DC-DC CONVERTER
-15VA (DC-DC CONVERTER: -16.5V)
5
REGULATOR +20V
7
DC-DC CONVERTER
AQZ102 (WC541600)
PHOTO MOS RELAY
4
8
3
2 1: INPUT (DC-)
1
2: INPUT (DC+)
3: OUTPUT (DC-)
4: OUTPUT (DC+)
1 1
金被:Metal Film Resistor(金属被膜抵抗) 1 1 1
1
酸金:Metal Oxide Film Resistor(酸化金属被膜抵抗) 2 2
2 2
(セ):Ceramic Capacitor(セラコン) 2 2
WARNING 1: ANODE
2: CATHODE
1: ANODE
2: CATHODE
1: ANODE
2: CATHODE
1: ANODE
2: CATHODE 1: ANODE 1: ANODE 11
2: CATHODE 2: CATHODE
Components having special characteristics are marked Z and must be
replaced with parts having specification equal to those originally installed.
1 DC-DC CONVERTER
2
to FDB-CN528
3
to FDB-CN529
4
to FDA-CN27
5
to FDA-CN28
to BRG5-CN811
to SL-CN101
7
to BRG5-CN812
to PN1-CN100
8
WARNING
11
Components having special characteristics are marked Z and must be
replaced with parts having specification equal to those originally installed.
金被:Metal Film Resistor(金属被膜抵抗)
(セ):Ceramic Capacitor(セラコン) Z 印の部品は、安全を維持するために重要な部品です。
12 交換する場合は、安全のために必ず指定の部品をご使用ください。
50 28CC1-8830427-1 3
■ BRG2 CIRCUIT DIAGRAM (PM5D/PM5D-RH)
L K J I H G F E D C B
DC-DC CONVERTER
1
to SR-CN101
to BRG5-CN813 DC-DC CONVERTER
to FDC-CN701
4
DC-DC CONVERTER
to FDC-CN702
4
1
2
3
1: SWITCH
OUTPUT
4
5 1 DC-DC CONVERTER
6
6 2
2: INPUT 7 3
3: C BOOST
4: GROUND
5: NO CONNECTION 1 2 4 3
6: FEEDBACK
7: ON/OFF
WARNING
Components having special characteristics are marked Z and must be
replaced with parts having specification equal to those originally installed.
7
金被:Metal Film Resistor(金属被膜抵抗)
(セ):Ceramic Capacitor(セラコン) Z 印の部品は、安全を維持するために重要な部品です。
交換する場合は、安全のために必ず指定の部品をご使用ください。
28CC1-8830428-1 2 51
■ BRG3 CIRCUIT DIAGRAM (PM5D/PM5D-RH)
Q P O N M L K J I H G F E D C B A
2 DC-DC CONVERTER 2
3
2: COMMON
3: OUTPUT
2: INPUT
3: COMMON
NJM7915FA(XD854A00) NJM78M20DL1A(X4368A00)
REGULATOR -15V REGULATOR +20V
2
to BRG5-CN814
3 32
1 1
DC-DC CONVERTER 3
-5VA (DC-DC CONVERTER: -7.5V)
1: OUTPUT 1: INPUT
2: INPUT 2: GND
1
2
3
1: SWITCH 4
to OPT-CN806
5
to BRG5-CN816
OUTPUT 6
5 DC-DC CONVERTER 2: INPUT
3: C BOOST
7
-5VA (DC-DC CONVERTER: -7.5V) 1: ADJ/GND
4: GROUND
1 2 2: OUTPUT 5: NO CONNECTION
3 6: FEEDBACK
DC-DC CONVERTER 3: INPUT
7: ON/OFF
1 1
2 2
3 3
REGULATOR 4
5
4
5
1: VIN 1: VIN
REGULATOR +20V 2: OUTPUT 2: OUTPUT
3: GROUND 3: GROUND
7 DC-DC CONVERTER
4: FEEDBACK
5: ON/OFF
4: FEEDBACK
5: ON/OFF
to OPT-CN807
DC-DC CONVERTER DIODE 40V 5A
8 REGULATOR 1
1
-15V 5
1: V IN
2: V OUT
2
3
3: COM (heat sink)
4: O adj
5: V soft 1 2 4 3
1 1
REGULATOR 2 2
10 -15V
1: ANODE 1: ANODE
2: CATHODE 2: CATHODE
1 1
2
2
12 金被:Metal Film Resistor(金属被膜抵抗) WARNING 1: ANODE
2: CATHODE 1: ANODE
酸金:Metal Oxide Film Resistor(酸化金属被膜抵抗) 2: CATHODE
(セ):Ceramic Capacitor(セラコン) Components having special characteristics are marked Z and must be
replaced with parts having specification equal to those originally installed.
1
to BRG4-CN201
to BRG1-
CN204
to BRG4-CN202
to BRG1-CN201
2
to BRG4-CN203
to BRG1-CN202 3
PM5D: N.C
to BRG1-CN203 PM5D-RH:
to AD3-CN981 4
to DC POWER
INPUT connector
to DC POWER
INPUT connector to BRG2-CN202
PM5D: N.C 6
PM5D-RH:
to AD3-CN981
to DC POWER
INPUT connector
to BRG3-CN201 7
PM5D: N.C
PM5D-RH:
to AD3-CN981
28CC1-8830700-1 1 53
(フ):Film Capacitor(フィルムコンデンサ)
■ BRG5 CIRCUIT DIAGRAM (PM5D/PM5D-RH)
W V U T S R Q P O N M L K J I H G F E D C B A
3
TRANSCEIVER
to AD3-7-CN922
to AD3-1-CN922
-CN922
-CN922
to AD3-2
to AD3-3
-CN922
to AD3-6
-CN922
to AD3-5
-CN922
to AD3-4
6
TRANSCEIVER
10 NOR
TRANSCEIVER
11
13
14
to DSP-CN201
to DSP-CN117
to DSP-CN119
to DSP-CN121
to DSP-CN123
to DSP-CN125
15
to DSP-CN202
to BRG1-CN423
16
54 28CC1-8831180-1 2
■ CN1R CIRCUIT DIAGRAM (PM5D-RH)
D C B A
to PHN1-CN600
to PHN2-CN600
MONITOR PHONES
4
28CC1-8831288-1 55 5
■ CUVOL CIRCUIT DIAGRAM (PM5D/PM5D-RH)
W V U T S R Q P O N M L K J I H G F E D C B A
2
1
2
3
1: OUTPUT
3 2: COMMON
3: INPUT
NJM7805DLA(XW674A00)
REGULATOR +5V
4
OP
2
OP AMP OP AMP OP AMP OP AMP AMP OP AMP OP AMP OP AMP
5 1
3
1: INPUT
2: COMMON
3: OUTPUT
6 LM2940CSX-15 (X4365A00)
REGULATOR +15V
TAB IS
GND
7
1
2
3
1: INPUT
OP AMP OP AMP OP AMP OP AMP OP AMP OP AMP OP AMP OP AMP 2: GND
8 3: OUTPUT
LM2990SX-15 (X3949A00)
REGULATOR -15V
9 TAB IS
INPUT
REGULATOR
REGULATOR REGULATOR REGULATOR
+5V 1
10 DAC +5V DAC +5V DAC +5V DAC
2
3
1: GND
2: INPUT
3: OUTPUT
1FWJ43N (V4607200)
11 DIODE
REGULATOR -15V
12 1
NOTE)
The maximum output level change by service correspondence. (サービス対応による最大出力レベル変更。)
TRANSCEIVER REGULATOR +5V 2
1: ANODE
2: CATHODE
13
10EDA40-TA1B2
(WB880900)
DIODE
14
INVERTER 1
15 REGULATOR +15V 2
1: ANODE
129, 130, 133
2: CATHODE
to DSP-CN128,
16
(F):Metal Film Resistor(金属被膜抵抗)
to BRG1-CN419, 420 to DA1-CN001
(マ):Mylar Capacitor(マイラーコンデンサ)
to DA1-CN002 to DA3-CN001
to DSP-CN127, 132 to DA1-CN902
to DA1-CN901 to DA3-CN902 (OS)
:Organic Semiconductor Aluminum Electrolytic Capacitor(有機半導体アルミ電解コンデンサ)
: A setup at the time of factory shipments. (工場出荷時の設定。)
56 28CC1-8830548-1 2
■ DA1 CIRCUIT DIAGRAM (PM5D/PM5D-RH)
17
X W V U T S R Q P O N M L K J I H G F E D C
TRANSCEIVER 2
1
2 DAC
3
INVERTER
1: OUTPUT
2: COMMON to CUVOL-CN401 3
3: INPUT to DA3-CN901
NJM7805DLA(XW674A00)
REGULATOR +5V
OP AMP OP AMP 4
2 OP AMP
1 TRANSCEIVER
3 5
1: INPUT
2: COMMON
REGULATOR
3: OUTPUT +5V
to DSP-CN135
LM2940CSX-15 (X4365A00)
REGULATOR +15V 6
OP AMP OP AMP
TAB IS OP AMP
GND
DAC 7
1 NOTE)
2
The maximum output level change by service correspondence. (サービス対応による最大出力レベル変更。)
3
1: INPUT
2: GND
to MNVOL-CN300
3: OUTPUT
8
LM2990SX-15 (X3949A00)
REGULATOR -15V
1
2 : A setup at the time of factory shipments. (工場出荷時の設定。)
3
1: GND REGULATOR
10
2: INPUT
3: OUTPUT +5V
1FWJ43N (V4607200)
DIODE OP AMP OP AMP 11
OP AMP
DAC
1 REGULATOR +15V 12
2
1: ANODE
2: CATHODE
to MNVOL-CN300 13
10EDA40-TA1B2
(WB880900)
DIODE
14
REGULATOR -15V
1 to DA3-CN002 REGULATOR
+5V
2
1: ANODE
2: CATHODE
15
REGULATOR +5V
16
1
■ DA3 CIRCUIT DIAGRAM (PM5D/PM5D-RH) PM5D/PM5D-RH
2 NJM78L05UA(XJ598A00) OP AMP
REGULATOR +5V
OP AMP
TRANSCEIVER
DAC
3 1
2
3 INVERTER
1: OUTPUT
2: COMMON
3: INPUT to DA2-CN901
4 NJM7805DLA(XW674A00)
REGULATOR +5V
2 OP AMP
OP AMP
to DA1-CN902
5
1
3
1: INPUT
2: COMMON
3: OUTPUT REGULATOR
6 LM2940CSX-15 (X4365A00) +5V
REGULATOR +15V
to DSP-CN134
TAB IS NOTE) The maximum output level change by service correspondence.
GND (サービス対応による最大出力レベル変更。)
OP AMP
7 OP AMP
1
2
3
1: INPUT
2: GND DAC
3: OUTPUT
8 LM2990SX-15 (X3949A00)
REGULATOR -15V
TAB IS
INPUT : A setup at the time of factory shipments. (工場出荷時の設定。)
9
1
2
3 OP AMP
1: GND
2: INPUT OP AMP
3: OUTPUT
REGULATOR +15V
10 1FWJ43N (V5454500)
DIODE
REGULATOR
+5V
11 1
2
1: ANODE
2: CATHODE
12 REGULATOR -15V
10EDA40-TA2B5
(WB880800) to DA1-CN002
DIODE
13 1 REGULATOR +5V
2
1: ANODE
2: CATHODE
to DA2-CN001
14
to LAMP
DR: to BRG1-CN410
to LPVOL-CN100
to DRL-CN100
3
DRL: to DR-CN100
to DRN-CN100
DRN: to DRL-CN100
to FAN
1
5
2 (1P):Metal Oxide Film Resistor(酸化金属被膜抵抗)
1: ANODE
2: CATHODE
59
KEC-92478-1 7 ■ DR, DRL, DRN CIRCUIT DIAGRAM (PM5D/PM5D-RH)
X W V U T S R Q P O N M L K J I H G F E D C B A
2 to MAIN-CN5
7
BUFFER
9
TRANSCEIVER
10
TRANSCEIVER
11
12
to MAIN-CN6
13
14
15
16
INVERTER
17 60 28CC1-8827233-2
■ DSP CIRCUIT DIAGRAM 002 (PM5D/PM5D-RH)
X W V U T S R Q P O N M L K J I H G F E D C B A
INVERTER
NAND
2
RESET 3
CPLD OR
TRANSCEIVER
PLLP2
(Gate Array) 4
5
PLL
TRANSCEIVER
1SS355 TE-17 (VT332900) 6
TRANSCEIVER
DIODE
NAND INVERTER
RESET N.C. 7
1 INVERTER
2
PLL
8
1: ANODE
2: CATHODE INVERTER
TRANSCEIVER
9
TRANSCEIVER
DIR2
11
12
PLLP2
(Gate Array)
13
14
TRANSCEIVER
15
17
28CC1-8827233-3 61
■ DSP CIRCUIT DIAGRAM 003 (PM5D/PM5D-RH)
K J I H G F E D C B
CPLD
4
8
62 28CC1-8827233-4 1
■ DSP OVERALL CIRCUIT DIAGRAM 004 (PM5D/PM5D-RH)
Q P O N M L K J I H G F E D C B A
1
TRANSCEIVER TRANSCEIVER
ATSC2A ATSC2A
7
10
28CC1-8827233-5 1 63
■ DSP CIRCUIT DIAGRAM 005 (PM5D/PM5D-RH)
Q P O N M L K J I H G F E D C B A
ATSC2A ATSC2A
7
10
64 28CC1-8827233-6 1
■ DSP CIRCUIT DIAGRAM 006 (PM5D/PM5D-RH)
Q P O N M L K J I H G F E D C B A
ATSC2A ATSC2A
7
TRANSCEIVER
MULTIPLEXER TRANSCEIVER
TRANSCEIVER TRANSCEIVER
9
MULTIPLEXER MULTIPLEXER
10
11
12
28CC1-8827233-7 1 65
■ DSP CIRCUIT DIAGRAM 007 (PM5D/PM5D-RH)
X W V U T S R Q P O N M L K J I H G F E D C B A
4
DSP7 DSP7
SDRAM
64M
6 D-FF
8 BUFFER
10
11
12 DSP7 DSP7
13
SDRAM SDRAM
64M 64M
14
15
XX:not installed(未実装部品)
(F):Metal Film Resistor(金属被膜抵抗)
(マ):Mylar Capacitor(マイラーコンデンサ)
16
66 28CC1-8827233-8
■ DSP CIRCUIT DIAGRAM 008 (PM5D/PM5D-RH)
17
X W V U T S R Q P O N M L K J I H G F E D C B A
SDRAM SDRAM 2
64M 64M
DSP7 DSP7
SDRAM SDRAM
64M 64M 10
11
12
DSP7 DSP7
13
14
15
16
XX:not installed(未実装部品)
28CC1-8827233-9 67
(F):Metal Film Resistor(金属被膜抵抗)
(マ):Mylar Capacitor(マイラーコンデンサ)
■ DSP CIRCUIT DIAGRAM 009 (PM5D/PM5D-RH)
X W V U T S R Q P O N M L K J I H G F E D C B
SDRAM SDRAM
2 64M 64M
4
DSP7 DSP7
SDRAM
64M TRANSCEIVER
10
11
12 DSP7
13
14
15
XX:not installed(未実装部品)
(F):Metal Film Resistor(金属被膜抵抗)
(マ):Mylar Capacitor(マイラーコンデンサ)
16
68 28CC1-8827233-10
■ DSP CIRCUIT DIAGRAM 010 (PM5D/PM5D-RH)
X W V U T S R Q P O N M L K J I H G F E D C B A
4
DSP7
SDRAM
16M 10
11
12
DSP7 DSP7
13
14
15
XX:not installed(未実装部品)
(F):Metal Film Resistor(金属被膜抵抗)
(マ):Mylar Capacitor(マイラーコンデンサ)
16
28CC1-8827233-11 69
■ DSP CIRCUIT DIAGRAM 011 (PM5D/PM5D-RH)
W V U T S R Q P O N M L K J I H G F E D C B
DSP6 DSP6
4
DRAM DRAM
6 4M 4M
10
DSP6 DSP6
11
12
DRAM DRAM
4M 4M
13
14
TRANSCEIVER TRANSCEIVER
15
16
17 70 28CC1-8827233-12
■ DSP CIRCUIT DIAGRAM 012 (PM5D/PM5D-RH)
W V U T S R Q P O N M L K J I H G F E D C B
DSP6 DSP6
4
DRAM DRAM
4M 4M 6
10
DSP6 DSP6
11
12
DRAM DRAM
4M 4M
13
14
TRANSCEIVER
15
28CC1-8827233-13 71
■ DSP CIRCUIT DIAGRAM 013 (PM5D/PM5D-RH)
Q P O N M L K J I H G F E D C B
ATSC2A ATSC2A
10
72 28CC1-8827233-14 1
■ DSP CIRCUIT DIAGRAM 014 (PM5D/PM5D-RH)
L K J I H G F E D C B A
ATSC2A
28CC1-8827233-15 1 73
■ DSP CIRCUIT DIAGRAM 015 (PM5D/PM5D-RH) 8
Q P O N M L K J I H G F E D C B A
ATSC2A ATSC2A
MULTIPLEXER MULTIPLEXER
10
11
12 74 28CC1-8827233-16 1
■ DSP CIRCUIT DIAGRAM 016 (PM5D/PM5D-RH)
L K J I H G F E D C B A
1
to OPT-CN801
TRANSCEIVER TRANSCEIVER
to OPT-CN802
3
to OPT-CN803
BUFFER BUFFER
to OPT-CN804
6
TRANSCEIVER
28CC1-8827233-17 75
■ DSP CIRCUIT DIAGRAM 017 (PM5D/PM5D-RH)
H G F E D C B A
BUFFER
to OPT-CN805
3
76 28CC1-8827233-18
■ DSP CIRCUIT DIAGRAM 018 (PM5D/PM5D-RH)
K J I H G F E D C B
BUFFER
to JK1-CN901
3
to JK1-CN902
4
5
TRANSCEIVER
28CC1-8827233-19 77
■ DSP CIRCUIT DIAGRAM 019 (PM5D/PM5D-RH)
L K J I H G F E D C B A
1 BUFFER
to JK2-CN508
to JK2-CN506
3
TRANSCEIVER
to JK2-CN507
to JK2-CN509
6
BUFFER
78 28CC1-8827233-20
■ DSP CIRCUIT DIAGRAM 020 (PM5D/PM5D-RH)
Q P O N M L K J I H G F E D C
BUFFER BUFFER
3
6
BUFFER
PM5D: N.C
PM5D-RH: to CN1R-CN102
PM5D: to AD1-CN002
PM5D-RH: to CN1R-CN104 7
BUFFER
PM5D: to AD2-CN002
PM5D-RH: to CN1R-CN107 8
PM5D: to AD1-CN003
PM5D-RH: N.C 9
to ANI3-CN001
BUFFER
10
PM5D: to AD1-CN002
PM5D-RH: to CN1R-CN105
11
28CC1-8827233-21 79
■ DSP CIRCUIT DIAGRAM 021 (PM5D/PM5D-RH) 12
K J I H G F E D C B A
to DA1-1-CN901 to DA1-4-CN901
to DA1-1 to DA1-4-CN903
3 -CN903
TRANSCEIVER TRANSCEIVER
4 to DA3-CN903
to DA1-2-CN903
TRANSCEIVER
5
to DA2-CN903
to DA1-3-CN903
OR
7 to PHN2-CN502
to TB-CN100
80 28CC1-8827233-22
■ DSP CIRCUIT DIAGRAM 022 (PM5D/PM5D-RH)
H G F E D C B
SYSTEM RESET
1
DC-DC CONVERTER
2 1
1: ANODE
1: ANODE
2: CATHODE
2: CATHODE
4
5
to BRG1-CN403 to BRG1-CN404
XX:not installed(未実装部品)
(F):Metal Film Resistor(金属被膜抵抗)
(セ):Ceramic Capacitor(セラコン)
28CC1-8827233-23 2 81
■ DSP CIRCUIT DIAGRAM 023 (PM5D/PM5D-RH)
6
Q P O N M L K J I H G F E D C B A
CPLD CPLD
6
N. C.
10
11
82 28CC1-8827233-24
■ DSP CIRCUIT DIAGRAM 024 (PM5D/PM5D-RH)
Q P O N M L K J I H G F E D C B A
1 1
1
2
3
2 2
1: OUTPUT
2: COMMON 1: ANODE 1: ANODE
3: INPUT 2: CATHODE 2: CATHODE
2
OP AMP OP AMP
REGULATOR
+6V
CH1 CH4
OP AMP OP AMP 3
OP AMP OP AMP
5
CH2 CH5
OP AMP OP AMP
6
OP AMP OP AMP 8
CH3 CH6
OP AMP OP AMP
10
11
(セ):Ceramic Capacitor(セラコン)
(マ):Mylar Capacitor(マイラーコン)
酸金:Metal Oxide Film Resistor(酸化金属被膜抵抗)
(F):Metal Film Resistor(金属被膜抵抗)
2
OP AMP OP AMP
CH7 CH10
OP AMP OP AMP
3
5 OP AMP OP AMP
CH8 CH11
OP AMP OP AMP
OP AMP OP AMP
8
CH9 CH12
OP AMP OP AMP
10
11
1 1
(セ):Ceramic Capacitor(セラコン) 2 2
(マ):Mylar Capacitor(マイラーコン)
1: ANODE 1: ANODE
酸金:Metal Oxide Film Resistor(酸化金属被膜抵抗) 2: CATHODE 2: CATHODE
OP AMP
MULTIPLEXER
D-FF 5
(セ):Ceramic Capacitor(セラコン)
Fader position select
28CC1-8830183-4 1 85
■ FDA CIRCUIT DIAGRAM 004 (PM5D/PM5D-RH)
K J I H G F E D C B A
2
MULTIPLEXER MULTIPLEXER
D-FF
6
1SS355 TE-17 (VT332900)
DIODE
2
7
1: ANODE
2: CATHODE
(セ):Ceramic Capacitor(セラコン)
8
Fader motor enable
Fader position scan
86 28CC1-8830183-5 1
■ FDA CIRCUIT DIAGRAM 005 (PM5D/PM5D-RH)
O N M L K J I H G F E D C B
1
■ FDA CIRCUIT DIAGRAM 006 (PM5D/PM5D-RH) PM5D/PM5D-RH
GATE ARRAY 4
to PN2-CN100
7
10
to PN2-CN200
to PN2-CN500
TRANSCEIVER
4
AND
AND
6 to FDB-CN537
to FDB-CN540
to PN3-1-CN100
to PN3-2-CN100
7
to PN3-1-CN101
to PN3-2-CN101
8
to PN3-1-CN102
to PN3-2-CN102
9
to BRG2-CN205
10 to BRG1-CN407
to BRG2-CN206
11
10
11
LED current drive (Source/sink)
28CC1-8830183-8 1 89
(セ):Ceramic Capacitor(セラコン)
■ FDA CIRCUIT DIAGRAM 008 (PM5D/PM5D-RH)
Q P O N M L K J I H G F E D C B A
1 1
1
2
3
2 2
1: OUTPUT
2 2: COMMON 1: ANODE 1: ANODE
3: INPUT 2: CATHODE 2: CATHODE
3 OP AMP OP AMP
5
OP AMP OP AMP
CH14 CH17
OP AMP OP AMP
6
8
OP AMP OP AMP
CH15 CH18
OP AMP OP AMP
9
10
11
12
(セ):Ceramic Capacitor(セラコン)
(マ):Mylar Capacitor(マイラーコン)
Fader motor drive
90 28CC1-8830202-2 1 酸金:Metal Oxide Film Resistor(酸化金属被膜抵抗)
(F):Metal Film Resistor(金属被膜抵抗)
■ FDB CIRCUIT DIAGRAM 002 (PM5D/PM5D-RH)
P O N M L K J I H G F E D C B A
OP AMP OP AMP
CH19 CH22
OP AMP OP AMP 3
5
OP AMP OP AMP
CH20 CH23
OP AMP OP AMP
6
OP AMP OP AMP 8
CH21 CH24
OP AMP OP AMP
10
1SS355 TE-17 (VT332900) UDZ 5.6B (VU172000)
DIODE ZENER DIODE 5.6V
1 1
11
2 2
1: ANODE 1: ANODE
2: CATHODE 2: CATHODE
(セ):Ceramic Capacitor(セラコン)
(マ):Mylar Capacitor(マイラーコン)
酸金:Metal Oxide Film Resistor(酸化金属被膜抵抗) Fader motor drive 12
(F):Metal Film Resistor(金属被膜抵抗)
28CC1-8830202-3 1 91
■ FDB CIRCUIT DIAGRAM 003 (PM5D/PM5D-RH)
P O N M L K J I H G F E D C B
OP AMP
MULTIPLEXER
D-FF
4
OP AMP
6
D-FF
MULTIPLEXER
10
(セ):Ceramic Capacitor(セラコン)
11
2
MULTIPLEXER MULTIPLEXER
D-FF
6
1SS355 TE-17 (VT332900)
DIODE
7
1: ANODE
2: CATHODE
(セ):Ceramic Capacitor(セラコン)
GATE ARRAY
4
to PN2-2-CN100
7
10
TRANSCEIVER
to SL-CN801
6
AND
TRANSCEIVER
9
to SL-CN800
10
11
SL I/F
28CC1-8830202-7 2 95
(セ):Ceramic Capacitor(セラコン)
■ FDB CIRCUIT DIAGRAM 007 (PM5D/PM5D-RH)
P O N M L K J I H G F E D C B A
TRANSCEIVER
to PN3-3-CN100
2
to PN3-3-CN101
3
to PN3-3-CN102
to PN3-4-CN100
to PN2-2-CN200 to PN2-2-CN500
6
to PN3-4-CN101
7
to PN3-4-CN102
9
to FDA-CN29 to FDA-CN26
to BRG2-CN203
to BRG1-CN408
10
to BRG2-CN204
Switch scan data input (Channel Module CH13–24)
11 LED data output (Channel Module CH13–24)
FDB I/F
Power input
96 28CC1-8830202-8 1
12
■ FDB CIRCUIT DIAGRAM 008 (PM5D/PM5D-RH)
O N M L K J I H G F E D C B
1
10
11
(セ):Ceramic Capacitor(セラコン)
LED current drive (Source/sink)
28CC1-8830202-9 1 97
■ FDB CIRCUIT DIAGRAM 009 (PM5D/PM5D-RH)
K J I H G F E D C B
NAND
4
TRANSCEIVER TRANSISTOR
REGISTER ARRAY
NAND
NAND
D-FF
8
LED DATA serial/parallel conversion
98 28CC1-8830202-10
■ FDB CIRCUIT DIAGRAM 010 (PM5D/PM5D-RH)
Q P O N M L K J I H G F E D C B A
OP AMP OP AMP 3
5
OP AMP OP AMP
DCA2 DCA5
OP AMP OP AMP
6
8
OP AMP OP AMP
DCA3 DCA6
OP AMP OP AMP
9
10
NJM78L06UA(X3620A00) 1SS355 TE-17 (VT332900) UDZ 5.6B (VU172000)
REGULATOR +6V DIODE ZENER DIODE 5.6V
1 1 1 11
2
3
2 2
1: OUTPUT
(セ):Ceramic Capacitor(セラコン) 2: COMMON 1: ANODE 1: ANODE
3: INPUT 2: CATHODE 2: CATHODE
(マ):Mylar Capacitor(マイラーコン)
酸金:Metal Oxide Film Resistor(酸化金属被膜抵抗)
(F):Metal Film Resistor(金属被膜抵抗) Fader motor drive 12
28CC1-8830203-2 1 99
■ FDC CIRCUIT DIAGRAM 002 (PM5D/PM5D-RH)
P O N M L K J I H G F E D C B A
OP AMP OP AMP
DCA7 ST OUT B
3 OP AMP OP AMP
5
OP AMP OP AMP
DCA8 ST IN 1
OP AMP OP AMP
6
8
OP AMP OP AMP
ST OUT A ST IN 2
OP AMP OP AMP
9
10
1SS355 TE-17 (VT332900) UDZ 5.6B (VU172000)
DIODE ZENER DIODE 5.6V
11 1 1
2 2
OP AMP
ST IN 3
2
OP AMP
OP AMP
ST IN 4
OP AMP
7
1
1: ANODE
2: CATHODE
8
(セ):Ceramic Capacitor(セラコン)
(マ):Mylar Capacitor(マイラーコン) Fader motor drive
28CC1-8830203-4 1 酸金:Metal Oxide Film Resistor(酸化金属被膜抵抗) 101
(F):Metal Film Resistor(金属被膜抵抗) ■ FDC CIRCUIT DIAGRAM 004 (PM5D/PM5D-RH)
O N M L K J I H G F E D C B
3
OP AMP
MULTIPLEXER
D-FF
OP AMP
4
MULTIPLEXER
D-FF
10
MULTIPLEXER MULTIPLEXER
2
1: ANODE
2: CATHODE
(セ):Ceramic Capacitor(セラコン)
TRANSCEIVER
3
to SR-CN800
AND
6 TRANSCEIVER
(セ):Ceramic Capacitor(セラコン)
SR I/F
104 28CC1-8830203-7
8 ■ FDC CIRCUIT DIAGRAM 007 (PM5D/PM5D-RH)
K J I H G F E D C B A
TRANSCEIVER
to PN4-CN101
to PN6-CN101
to BRG3-CN203
to PN4-CN201 5
to BRG3-CN204
to PN6-CN100
to PN5-CN400
to BRG1-CN409
7
to PN5-CN401
10
11
(セ):Ceramic Capacitor(セラコン)
LED current drive circuit (Source/sink)
106 28CC1-8830203-9 1
■ FDC CIRCUIT DIAGRAM 009 (PM5D/PM5D-RH)
K J I H G F E D C
NAND
NAND
5
NAND
D-FF 6
SRC
SRC
INVERTER
SRC
LINE RECEIVER
7 DAN217 (VV556300)
DIODE ARRAY 0.3AX2
1
3 2
1: ANODE1
2: CATHODE2
8 3: CATHODE1,
1 2 ANODE2
1
SRC
3
SRC
LINE DRIVER
not installed
SRC 5
6
D-FF
not installed
DAN217 (VV556300)
DIODE ARRAY 0.3AX2
7
1
3 2
1: ANODE1
2: CATHODE2
3: CATHODE1, 8
1 2 ANODE2
MULTIPLEXER
28CC1-8830385-3 109
■ JK1 CIRCUIT DIAGRAM 003 (PM5D/PM5D-RH)
L K J I H G F E D C
not installed
1SS372 (V9424900)
DIODE ARRAY
FLASH ROM
4M 3
5 1
3 2
1: ANODE1
2: CATHODE2
3: CATHODE1,
1 2 ANODE2
CPU
(USB 32K)
6
110 28CC1-8830385-4
■ JK1 CIRCUIT DIAGRAM 004 (PM5D/PM5D-RH)
L K J I H G F E D C B A
1
BUFFER
COMPARATOR
OP AMP
not installed
XX:not installed(未実装部品)
28CC1-8830385-5 1 111
■ JK1 CIRCUIT DIAGRAM 005 (PM5D/PM5D-RH)
L K J I H G F E D C B A
1 DECODER
DECODER
D-FF
3
INVERTER
TRANSCEIVER
6 INVERTER
112 28CC1-8830385-6 1
■ JK1 CIRCUIT DIAGRAM 006 (PM5D/PM5D-RH)
L K J I H G F E D C B A
TRANSCEIVER 1
INVERTER
TRANSCEIVER
3
to DSP-CN110
to DSP-CN111
4
5
INVERTER
BUFFER
to BRG1-CN405
7
not installed
not installed
8
28CC1-8830385-7 113
■ JK1 CIRCUIT DIAGRAM 007 (PM5D/PM5D-RH)
L K J I H G F E D C B A
1 3
1
3 2
1: ANODE1
2: CATHODE2
3: CATHODE1,
1 2 ANODE2 LINE RECEIVER
LINE RECEIVER
5 LINE RECEIVER
LINE RECEIVER
LINE RECEIVER
LINE DRIVER
114 28CC1-8827235-2
■ JK2 CIRCUIT DIAGRAM 002 (PM5D/PM5D-RH)
L K J I H G F E D C B A
DAN217 (VV556300)
■ JK2 CIRCUIT DIAGRAM 003 (PM5D/PM5D-RH) DIODE ARRAY 0.3AX2 PM5D/PM5D-RH
1
1
3 2
1: ANODE1
2: CATHODE2
3: CATHODE1,
1 2 ANODE2
LINE DRIVER
LINE DRIVER
LINE DRIVER
LINE DRIVER
7
LINE
RECEIVER 8
28CC1-8827235-3 115
LINE DRIVER ■ JK2 CIRCUIT DIAGRAM 003 (PM5D/PM5D-RH)
H G F E D C B A
1
1
INVERTER 1: ANODE
Photo Coupler 2: CATHODE
INVERTER
LINE
DRIVER/RECEIVER
116 28CC1-8827235-4
■ JK2 CIRCUIT DIAGRAM 004 (PM5D/PM5D-RH)
L K J I H G F E D C B A
D-FF 1
DAN217 (VV556300) TRANSISTOR
DIODE ARRAY 0.3AX2 ARRAY
1
3 2
1: ANODE1
2: CATHODE2
3: CATHODE1, 2
1 2 ANODE2
GPI
OP AMP
not installed
OP AMP
not installed
8
XX:not installed(未実装部品)
28CC1-8827235-5 117
(F):Metal Film Resistor(金属被膜抵抗)
(フ):Flame Proof C. Resistor(不燃化カーボン抵抗)
■ JK2 CIRCUIT DIAGRAM 005 (PM5D/PM5D-RH)
L K J I H G F E D
TRANSCEIVER
1
to DSP-CN112
DECODER
TRANSCEIVER
TRANSCEIVER
7 D-FF
118 28CC1-8827235-6
■ JK2 CIRCUIT DIAGRAM 006 (PM5D/PM5D-RH)
K J I H G F E D C B A
to DSP-CN113
to DSP-CN115
TRANSCEIVER 5
to BRG1-CN406
6
to DSP-CN114
8
28CC1-8827235-7 119
■ JK2 CIRCUIT DIAGRAM 007 (PM5D/PM5D-RH)
K J I H G F E D C
to AD3-1-CN961
to AD3-3-CN961
to AD3-5-CN961
3
8
120 28CC1-8831282-1 RED:Red (赤)
GRE:Green (緑)
■ LD CIRCUIT DIAGRAM (PM5D-RH)
D C B A
LAMP DIMMER
to DR-CN100
to BRG1-CN411
28CC1-8831285-1 121
■ LPVOL CIRCUIT DIAGRAM (PM5D)
D C B A
LAMP DIMMER
to DR-CN100
to BRG1-CN411
122 28CC1-8831282-4
■ LPVOL CIRCUIT DIAGRAM (PM5D-RH)
X W V U T S R Q P O N M L K J I H G F E D C B A
1
4
2 1 2
CLOCK BUFFER 1
2
3 1: INPUT 2
2: GND
3: OUTPUT 1: ANODE
2: CATHODE 1: ANODE
REGULATOR 4: GND 2: CATHODE 3
+1.8V
CPU
6
OR
10
11
OP AMP RESET OR
INVERTER AND
AND 12
CR2032 socket
Battery AND
Z
Detection
Voltage: 2.7V
RESET
TRANSCEIVER 13
SRAM 2M
Detection Detection
RESET
Voltage: 3.0V Voltage: 4.2V
to SL-CN100
14
WARNING
Components having special characteristics are marked Z and must be
Lithium Battery (リチウム電池) replaced with parts having specification equal to those originally installed. 15
OR
Battery VN103500 Battery
VN103600(Battery holder for VN103500) Z 印の部品は、安全を維持するために重要な部品です。
to SR-CN100
Notice for back-up battery removal. Push the battery 交換する場合は、安全のために必ず指定の部品をご使用ください。
as shown in figure, then the battery will pop up.
:not installed(未実装部品)
Druk de batterij naar beneden zoals aangeven in de
MULTIPLEXER tekening, de batterij springt dan naar voren. Battery holder (F):Metal Film Resistor(金属被膜抵抗)
MAIN CPU I/F 16
28CC1-8830308-2 4 123
■ MAIN CIRCUIT DIAGRAM 002 (PM5D/PM5D-RH)
V U T S R Q P O N M L K J I H G F E D C
5 TRANSCEIVER
TRANSCEIVER
BUFFER
TRANSCEIVER
9
to DSP-CN101
10
TRANSCEIVER
11
AND
TRANSCEIVER
12
13
14 BUFFER
to DSP-CN102
15
to BRG1-CN401
2
REGULATOR
+1.25V
to LCD (INVERTER)-CN1
AND 4
LT1117CST (XW818A00)
REGULATOR +1.25V
0V: Brightness MAX
4V: Brightness MIN
TAB IS
VOUT
1
5
2
3
1: ADJ/GND
2: OUT
to BRG1-CN402 3: IN
RESET
POWER 6
CONTROLLER
Detection
Voltage: 3.0V
NAND
8
BUFFER
9
NAND
REGISTER
AND 10
NAND
11
:not installed(未実装部品)
CPU CARD I/F
28CC1-8830308-4 5 125
(F):Metal Film Resistor(金属被膜抵抗)
■ MAIN CIRCUIT DIAGRAM 004 (PM5D/PM5D-RH)
O N M L K J I H G F E D
2
INVERTER
TRANSCEIVER
AND
5
MULTI FUNCTION
AND BUFFER
7
10
11
SRAM 512K
7
AND
OR 8
BUFFER
9
10
11
3
to LCD
LT1117CST (XW818A00)
REGULATOR +1.25V
5 TAB IS
VOUT
INVERTER
1
2
3
1: ADJ/GND
2: OUT
3: IN
6
1SS355 TE-17 (VT332900)
DIODE
REGULATOR
+1.25V 1
7
2
1: ANODE
USART 2: CATHODE
8 BUFFER
9 to TPSW-CN101
INVERTER
10
11 BUFFER
BUFFER
:not installed(未実装部品)
CONNECTOR (VIDEO, LCD, MOUSE, KEYBOARD, TRACK PAD)
128 28CC1-8830308-7 (F):Metal Film Resistor(金属被膜抵抗)
■ MAIN CIRCUIT DIAGRAM 007 (PM5D/PM5D-RH)
O N M L K J I H G F E D C B
TRANSCEIVER
4
MULTI FUNCTION
BUFFER
10
11
MONITOR
LEVEL
to DA2-CN905, 906
130 28CC1-8831289-1
■ MNVOL CIRCUIT DIAGRAM (PM5D/PM5D-RH)
V U T S R Q P O N M L K J I H G F E D C B
7
to DSP-CN109
10
11
12
13
14
POWER AMP
3 0.65W 2CH
OP AMP
4 TRANSCEIVER DAC
INVERTER
to PHN2-CN503
5
POWER AMP
to CUVOL-
0.65W 2CH
OP AMP CN400
7 REGULATOR
+5V
10
to BRG1-CN432
REGULATOR
11 +12V
12
1 1 1
2 32
3
1
1: OUTPUT 1: OUTPUT 2 2
2: COMMON 1: ANODE 1: ANODE
2: COMMON
2: CATHODE 2: CATHODE
3: INPUT 3: INPUT
POWER AMP
OP AMP
0.65W 2CH 3
TRANSCEIVER
DAC 4
INVERTER
to DSP-CN136
to CUVOL-CN400
5
POWER AMP
0.65W 2CH
OP AMP
to PHN1-CN501
REGULATOR 7
+5V
10
to BRG1-CN415
REGULATOR 11
+12V
12
1 1 1
2 32
3
1
1: OUTPUT 1: OUTPUT 2 2
2: COMMON 2: COMMON 1: ANODE 1: ANODE
2: CATHODE 2: CATHODE
3: INPUT 3: INPUT
to BRG2-
CN208
4
GATE ARRAY
5
to SL-CN451
to SL-CN450
GATE ARRAY
10
11
10
TRANSCEIVER
TRANSCEIVER
1: ANODE
2: CATHODE SW (MATRIX 1–8, MIX 1–24, ENCODER MODE/FADER)
28CC1-8830178-5 137
■ PN1 CIRCUIT DIAGRAM 005 (PM5D/PM5D-RH)
H G F E D C B A
3 NOR
4
INVERTER
D-FF
8
SOURCE DRIVER SOURCE DRIVER SOURCE DRIVER SOURCE DRIVER SOURCE DRIVER
10
11
6
140 28CC1-8830178-8
■ PN1 CIRCUIT DIAGRAM 008 (PM5D/PM5D-RH)
P O N M L K J I H G F E D C B A
10
11
10
11
to FDA-CN25
to FDB-CN525
Encoder 8
28CC1-8830167-2 143
■ PN2 CIRCUIT DIAGRAM 002 (PM5D/PM5D-RH)
H G F E D C B A
to FDA-CN36
to FDB-CN538
5
1
1: ANODE
2: CATHODE
6 SW (Channel Module)
144 28CC1-8830167-3 1
■ PN2 CIRCUIT DIAGRAM 003 (PM5D/PM5D-RH)
H G F E D C B
to FDA-CN31
to FDB-CN539
10
11
148 28CC1-8830165-2
■ PN3 CIRCUIT DIAGRAM 002 (PM5D/PM5D-RH)
H G F E D C B A
1: ANODE
2: CATHODE
5
28CC1-8830165-3 149
■ PN3 CIRCUIT DIAGRAM 003 (PM5D/PM5D-RH)
O N M L K J I H G F E D C B
3
to FDC-
CN714
8
1
1: ANODE
2: CATHODE
10
150 28CC1-8830149-1
■ PN4 CIRCUIT DIAGRAM 001 (PM5D/PM5D-RH)
K J I H G F E D C B
to FDC-CN705
28CC1-8830149-2 1 151
■ PN4 CIRCUIT DIAGRAM 002 (PM5D/PM5D-RH)
K J I H G F E D C B A
152 28CC1-8830164-2 1
■ PN5 CIRCUIT DIAGRAM 002 (PM5D/PM5D-RH)
F E D C B A
1
to FDC-CN709
to FDC-CN707
2
1
1: ANODE
2: CATHODE
28CC1-8830164-3 1 153
■ PN5 CIRCUIT DIAGRAM 003 (PM5D/PM5D-RH)
L K J I H G F E D C B A
2
to FDC-CN708
3
to FDC-CN706
154 28CC1-8830173-2
■ PN6 CIRCUIT DIAGRAM 002 (PM5D/PM5D-RH)
G F E D C B
4
1SS355 TE-17 (VT332900)
DIODE
1: ANODE
2: CATHODE
28CC1-8830173-3 155
■ PN6 CIRCUIT DIAGRAM 003 (PM5D/PM5D-RH)
G F E D C B
PN8 1/2
2 to PN8 (2/2)-CN200
CANCEL OK
(DEC) (INC) ENTER
to SR-CN500
SHIFT
1SS355 TE-17 (VT332900)
DIODE
1: ANODE
2: CATHODE
156 28CC1-8830137-1
■ PN8 CIRCUIT DIAGRAM 001 (PM5D/PM5D-RH)
D C B A
PN8 2/2
2
DATA
ENCODER
to PN8 (1/2)-CN101
28CC1-8830137-2 157
■ PN8 CIRCUIT DIAGRAM 002 (PM5D/PM5D-RH)
P O N M L K J I H G F E D C B
2
to BRG2-CN207
FLASH ROM
5 4M
CPU
8 INVERTER
BUFFER
9
to MAIN-CN1
DECODER
10
11
RESET AND
158 28CC1-8830206-2 5
■ SL CIRCUIT DIAGRAM 002 (PM5D/PM5D-RH)
P O N M L K J I H G F E D C B A
2
TRANSISTOR
ARRAY
OR
REGISTER
TRANSCEIVER
TRANSISTOR
ARRAY
4
5
LCD
CONTROLLER INVERTER
INVERTER
INVERTER 6
D-FF
7
INVERTER
INVERTER 8
9
D-FF
10
11
10
11
SOURCE DRIVER SOURCE DRIVER SOURCE DRIVER SOURCE DRIVER SOURCE DRIVER
8
10
11
10
11
10
11
12
LED (SELECTED CHANNEL/METER)
28CC1-8830206-7 1 163
■ SL CIRCUIT DIAGRAM 007 (PM5D/PM5D-RH)
Q P O N M L K J I H G F E D C B A
10
11
12
LED (METER)
164 28CC1-8830206-8
■ SL CIRCUIT DIAGRAM 008 (PM5D/PM5D-RH)
P O N M L K J I H G F E D C B A
TRANSCEIVER 2
4
to FDB-CN527
7
TRANSCEIVER
8
to FDB-CN526
µPC2933AT-E1 (X0638A00)
REGULATOR +3.3V
AND
2
9
AND 1
3
DECODER 1: V in
2: GND
3: V out
2
REGULATOR 11
+3.3V 1: ANODE
2: CATHODE
GATE ARRAY
5
8
DECODER
10
11
GATE ARRAY
10
11
10
11
ENCODER (SELECTED CHANNEL)
168 28CC1-8830206-12
■ SL CIRCUIT DIAGRAM 012 (PM5D/PM5D-RH)
H G F E D C B
DECODER
TRANSCEIVER
1
5
2
1: ANODE
2: CATHODE
8
SW (SELECTED CHANNEL)
170 28CC1-8830206-14 1
■ SL CIRCUIT DIAGRAM 014 (PM5D/PM5D-RH)
J I H G F E D C B A
1
■ SL CIRCUIT DIAGRAM 015 (PM5D/PM5D-RH) PM5D/PM5D-RH
TRANSCEIVER
to PN1-CN102
TRANSCEIVER
5
AND
TRANSCEIVER
to PN1-CN101
PN1 I/F
28CC1-8830206-15 1 171
■ SL CIRCUIT DIAGRAM 015 (PM5D/PM5D-RH)
8
Q P O N M L K J I H G F E D C B
2
to BRG3-CN202
5 FLASH ROM
4M
CPU
8
INVERTER
9 BUFFER
DECODER
to MAIN-CN2
10
11
RESET AND
172 28CC1-8830218-2
12
3
■ SR CIRCUIT DIAGRAM 002 (PM5D/PM5D-RH)
P O N M L K J I H G F E D C B A
REGISTER
TRANSCEIVER
3
INVERTER
5
LCD
CONTROLLER INVERTER
D-FF
INVERTER 6
NAND
ST IN 1 ST IN 2
8
INVERTER
D-FF NAND 9
10
ST IN 3 ST IN 4
11
2
LED DRIVER LED DRIVER
SOURCE DRIVER
8
LED Driver (Current source)
28CC1-8830218-5 175
■ SR CIRCUIT DIAGRAM 005 (PM5D/PM5D-RH)
D C B A
SCENE
NUMBER
LED 7seg
176 28CC1-8830218-6
■ SR CIRCUIT DIAGRAM 006 (PM5D/PM5D-RH)
K J I H G F E D C B A
to SR (2/2)-CN900 7
10
11
LED (METER, SCENE MEMORY)
178
28CC1-8830218-8 ■ SR CIRCUIT DIAGRAM 008 (PM5D/PM5D-RH)
K J I H G F E D C B A
2
TRANSCEIVER
AND TRANSCEIVER 4
to FDC-CN601
DECODER
6
µPC2933AT-E1 (X0638A00)
REGULATOR +3.3V
1
3 7
1: V in
2: GND
3: V out
REGULATOR
+3.3V 1SS355 TE-17 (VT332900)
DIODE
2
8
1: ANODE
2: CATHODE
GATE ARRAY
7
ENCODER SCAN (ST IN 1–4)
180 28CC1-8830218-10 1
■ SR CIRCUIT DIAGRAM 010 (PM5D/PM5D-RH)
D C B A
ENCODER ENCODER
(ST IN 3) (ST IN 4)
1 DECODER
TRANSCEIVER
TRANSCEIVER
SW SCAN (ST IN 1–4, DISPLAY ACCESS, USER DEFINE, CUE, MONITOR, OSC, TALKBACK, SCENE MEMORY)
182 28CC1-8830218-12
6 ■ SR CIRCUIT DIAGRAM 012 (PM5D/PM5D-RH)
L K J I H G F E D C B A
to PN8(1/2)-CN100
3
1: ANODE
2: CATHODE
7
1: ANODE
2: CATHODE
SR (2/2) 2
1
1: ANODE
2: CATHODE
3
to SR (1/2)-CN600
6
28CC1-8830218-15 185
■ SR CIRCUIT DIAGRAM 015 (PM5D/PM5D-RH)
K J I H G F E D C B
1
■ STLD CIRCUIT DIAGRAM (PM5D-RH) PM5D-RH
3
to AD3-CN961
RED:Red (赤)
GRE:Green (緑)
186 28CC1-8831282-2
■ STLD CIRCUIT DIAGRAM (PM5D-RH)
D C B A
to BRG1-CN422
+48V MASTER
28CC1-8831282-3 187
2
■ SW48 CIRCUIT DIAGRAM (PM5D-RH)
W V U T S R Q P O N M L K J I H G F E D C B A
5
ADC
to TBVOL-CN102
TRANSCEIVER
6 OP AMP
OP AMP
INVERTER
to DSP-CN131
7
TALKBACK
10
11
RB551V-30 (V9634300)
DIODE
12
1
13
1: ANODE
2: CATHODE
14 D1F60 (VS201100)
DIODE
1 to BRG1-CN421
15 2
1: ANODE
16 2: CATHODE
17 XX:not installed(未実装部品)
(F):Metal Film Resistor(金属被膜抵抗)
(フ):Flame Proof C. Resistor(不燃化カーボン抵抗)
(マ):Mylar Capacitor(マイラーコンデンサ)
188 28CC1-8831287-1 2
■ TB CIRCUIT DIAGRAM (PM5D/PM5D-RH)
D C B A
3
TALKBACK
LEVEL
to TB-CN101
28CC1-8831290-1 189
■ TBVOL CIRCUIT DIAGRAM (PM5D/PM5D-RH)
H G F E D C B
to MAIN-CN15
to TRACK PAD
3
LEFT RIGHT
TRACK PAD