EC T45 / DIGITAL CIRCUITS UNIT 3

DEPARTMENT OF ECE
EC T45 – DIGITAL CIRCUITS
UNIT - 3
Combinational Logic Design: Half adder - Full adder– Parallel Adder- Carry Look Ahead
Adder – BCD Adder – Magnitude Comparator – Encoders and Decoders – Multiplexers – Code
converters – Parity generator, Parity checker- Combinational circuit implementation using
multiplexers and decoders.
Programmable Logic Devices: PROM – EPROM – EEPROM- Programmable Logic Array
(PLA) – Programmable Array Logic (PAL) -Realization of combinational circuits using PROM,
PLA and PAL.

Introduction
 A digital systems consists of two types of circuits namely
 Combinational Logic Circuit
 Sequential Logic Circuit
 If any logic circuit output depends only the present input, that type of logic circuit called
as a combinational logic circuit e.g., arithmetic circuits, code converter, multiplexer,
encoder/decoder, etc.

 On the other hand, if the output of the logic circuit depends not only the present input and
also on the past outputs, this type of logic circuit is called as sequential logic circuit e.g.,
counters, shift registers etc,.

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Half Adder
 A half-adder is an arithmetic circuit block that can be used to add two bits. Such a
circuit thus has two inputs (A and B) that represent the two bits to be added and two
outputs, with one producing the Sum output and the other producing the Carry.
 The truth table shows all possible input combinations and the corresponding outputs.
The Boolean expressions for the Sum and Carry outputs are given by the equations
below.
Sum (S) = A (XOR) B = AB‟ + A‟B
Carry (C) = AB
 The figure below shows the logic diagram for half circuit

A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

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Limitations of Half Adder

 The reason these simple binary adders are called Half Adders is that there is no scope
for them to add the carry bit from previous bit.
 This is a major limitation of half adders when used as binary adders especially in real
time scenarios which involves addition of multiple bits. To overcome this limitation,
full adders are developed.
Full Adder
 A full adder circuit is an arithmetic circuit block that can be used to add three bits to
produce a Sum and a Carry output. Such a building block becomes a necessity when it
comes to adding binary numbers with a large number of bits.
 The full adder circuit overcomes the limitation of the half-adder, which can be used to
add two bits only. Let us recall the procedure for adding larger binary numbers. We
begin with the addition of LSBs of the two numbers.
 We record the sum under the LSB column and take the carry, if any, forward to the next
higher column bits. As a result, when we add the next adjacent higher column bits, we
would be required to add three bits if there were a carry from the previous addition.
 We have a similar situation for the other higher column bits. Also until we reach the
MSB. A full adder is therefore essential for the hardware implementation of an adder
circuit capable of adding larger binary numbers. A half-adder can be used for addition
of LSBs only.

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A B C or Cin Sum Carry or Cout

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Parallel Adder
 A full binary adder performs addition of any single bit of one binary number, same
significant or same position bit of another binary numbers and carry comes from result
of addition of previous right side bits of both binary numbers.
 But a single full adder cannot add more than one bits binary number instantly. This can
be done only by connecting as many full adders as the number of bits of the binary
numbers whose addition is to be performed.
 This parallel combination of full adders which performs addition of specific bits binary
numbers is called binary parallel adder. For adding two 4 bit binary numbers we have to

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connect 4 full adders to make 4 bit parallel adder. The inter connection of 4 full adder in
4bit parallel adder is shown below.

Carry Look ahead Adder

 The carry look ahead adder is based on the principle of looking at the lower order
bits of the augend and addend if a high order carry is generated.
 This adder reduces the carry delay by reducing the number of gates through which carry
signal must propagate. It uses two functions carry generate and carry propagate.
 The structure of one stage of a carry look ahead adder is shown
below. Carry generate, Gi = AiBi
Carry propagate, Pi = Ai ⊕ Bi
Sum, S= Pi ⊕ Ci = Ai ⊕ Bi ⊕ Ci
Carry, Ci+1 = Gi + Pi Ci

 Gi (carry generate) generates is carry if both Ai and Bi are 1 regardless of the

input carry.

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 Pi (carry propagate) propagates carries if atleast one of its addened bits is 1.

 The carry output of a stage can now be written in terms of the generate and propagate
signals.
Ci+1 = Gi + PiCi.
 The implementations of carry equations using AND – OR logic is given by

BCD Adder
 A BCD 1-digit adder is a circuit that adds two BCD digits in parallel and also produces
the Sum digit in BCD along with the necessary correction logic.
 The conventional implementation of addition as mentioned above is shown in Figure
below.

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 It can be seen that a 4-bit binary adder is used initially to add two BCD digits (each
digit expressed using 4 bits) with a carry-input.
 An overflow detection circuit is used (to check if the „Sum‟ of the BCD digit has
exceeded 9) which is designed using two 2-input AND gates and a 3-input OR gate.
 Finally, another 4-bit binary adder is used as a correction stage, which comes in the path
of final Sum computation. Thus, the critical path in this circuit consists of a 4-bit binary
adder, overflow logic and one more 4-bit binary adder.
 Assuming, in the best case, that the 4-bit binary adder is a carry look-ahead adder, a
gate level analysis would indicate that it consists of 4-gates in the critical path.
 It can be observed from figure above that the overflow detection circuit comes into
picture only after the topmost 4-bit binary adder performs its operation and it consists of
2 gates in the critical path.
 Thus, a minimum of a 10-gate delay can be expected in conventional implementation.
The above design can however be optimized by removing those gates that are
completely redundant in their operation.
 Such a modification is shown in Figure below which results in a smaller critical path.

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  A faster carry prediction for this implementation is proposed in, which uses carry look-
ahead logic to predict the carry in advance.
 These 1-digit full adders can be cascaded to realize higher digit BCD adders.

Magnitude Comparator
 A magnitude digital Comparator is a combinational circuit that compares two digital
or binary numbers in order to find out whether one binary number is equal, less than
or greater than the other binary number.
 We logically design a circuit for which we will have two inputs one for A and other for
B and have three output terminals,
 one for A > B condition,
 one for A = B condition and
 one for A < B condition.

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One Bit Magnitude Comparator
 A comparator used to compare two bits is called a single bit comparator. It consists of
two inputs each for two single bit numbers and three outputs to generate less than, equal
to and greater than between two binary numbers.
 The truth table for a 1-bit comparator is given below

A B A<B A=B A>B

0 0 0 1 0

0 1 1 0 0

1 0 0 0 1

1 1 0 1 0

Two Bit Magnitude Comparator

 A comparator used to compare two binary numbers each of two bits is called a 2-
bit Magnitude comparator.
 It consists of four inputs and three outputs to generate less than, equal to and greater
than between two binary numbers.

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 The truth table for a 2-bit comparator is given below.

A1 A0 B1 B0 A<B A=B A>B

0 0 0 0 0 1 0
0 0 0 1 1 0 0
0 0 1 0 1 0 0
0 0 1 1 1 0 0
0 1 0 0 0 0 1
0 1 0 1 0 1 0
0 1 1 0 1 0 0
0 1 1 1 1 0 0
1 0 0 0 0 0 1
1 0 0 1 0 0 1
1 0 1 0 0 1 0
1 0 1 1 1 0 0
1 1 0 0 0 0 1
1 1 0 1 0 0 1
1 1 1 0 0 0 1
1 1 1 1 0 1 0
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Decoder
 The process of taking some type of code and determining what it represents in terms of
a recognizable number or character is called decoding.
 A decoder is a combinational logic circuit that performs the decoding function, and
produce an output that indicates the (meaning) of the input code.
 The decoder is an important part of the system which selects the cells to be read from
and write into.
 This particular circuit is called a decoder matrix, or simply a decoder, and has a
characteristic that for each of the possible 2n binary input number which can be taken
by the n input cells, the matrix will have a unique one of its 2n output lines selected.

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 The decoder is called n to m where m < 2n for example two to four line decoder, figure
shows a two to four line decoder and its truth table.

X2 X1
0 0
0 1
1 0
1 1
W0 W1
1 0
0 1
0 0
0 0
W2 W3
0 0
0 0
1 0
0 1

Encoder
 An encoder is a combinational logic circuit that generate n output lines from 2n (or less)
inputs. It has the reverse function of the decoder.

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 An encoder accepts digit on its inputs, such as a decimal or octal digit, and converts it to
a coded output, such as a binary or BCD. Encoder can also be devised to encode various
symbol and alphabetic characters.
 This process of converting from familiar symbols or numbers to a coded format is
called encoding. Figure below shown a four to two line encoder and its truth table.
A3 A2 A1 A0 F1 F0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1

Multiplexers
 Multiplex means “Many into One”. A multiplexer is a combinational
circuit with many inputs but only one output. By applying control signals,
we can steer any input to the output.
 It has 2n input lines and n selection lines, Multiplexer are called as data
selector or because the output bit depends on the input data bit that is
selected.

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Logic symbol

Truth Table

Logic Diagram

Applications of Multiplexer:
 They are used as a data selector to select “one to many” data inputs.
 They can be used to implement combinational circuit
 They are used in time multiplexing systems.
 They are used in frequency multiplexing systems.
 They are used in A/D and D/A convertor.

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Demultiplexer
 Demultiplexer means “one into many”. A demultiplexer is a combinational
logic circuit with “one input and many outputs”. It is also called as data
distributor or serial-to-parallel converter.
Logic Symbol

Truth Table

Enable S1 S0 Din Y0 Y1 Y2 Y3

0 X X X 0 0 0 0

1 0 0 0 0 0 0 0

1 0 0 1 1 0 0 0

1 0 1 0 0 0 0 0

1 0 1 1 0 1 0 0

1 1 0 0 0 0 0 0

1 1 0 1 0 0 1 0

1 1 1 0 0 0 0 0

1 1 1 1 0 0 0 1

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Logic Diagram

Applications of Multiplexer:
 It can be used as a decoder.
 It can be used as a data distributer.
 It is used in time division multiplexing at the receiving end as a data separator.
 It can be used to implement Boolean expressions.

Code Converters

 A code converter is a logic circuit that changes data presented in one type of binary
code to another type of binary code. The following are some of most commonly used
code converters.
 Binary to Gray Code
 Gray to Binary code
 BCD to Excess – 3 Codes
 Excess – 3 to BCD code

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Binary to Gray Code
The truth table for binary to gray code converter is given below.
B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0

G3 = B3

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G2 = B3 XOR B2

G1 = B1 XOR B2

G0 = B1 XOR B0

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Gray to Binary code

The truth table, K – map, and logic diagram for Gray to binary code is given below.
G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 1 0 0 1 0

0 0 1 0 0 0 1 1

0 1 1 0 0 1 0 0

0 1 1 1 0 1 0 1

0 1 0 1 0 1 1 0

0 1 0 0 0 1 1 1

1 1 0 0 1 0 0 0

1 1 0 1 1 0 0 1

1 1 1 1 1 0 1 0

1 1 1 0 1 0 1 1

1 0 1 0 1 1 0 0

1 0 1 1 1 1 0 1

1 0 0 1 1 1 1 0

1 0 0 0 1 1 1 1

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BCD to Excess – 3 code

The truth table, K – map, and logic diagram for BCD to Excess - 3 code is given below.
B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0

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Excess – 3 to BCD code
The truth table, K – map, and logic diagram for Excess – 3 to BCD code is given below.

E3 E2 E1 E0 B3 B2 B1 B0
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1
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Parity Generator and Checker

 A parity bit is used for the purpose of detecting errors during transmission of binary
information. A parity bit is an extra single bit included with a message.
 An error is detected if the checker parity does not correspond with the one transmitted.
The parity which is transmitted along with the message is called parity generator.
 The parity, which is received, is called as parity checker. The parity bit, P= X xor Y xor
ZThe three message bits together with the parity bit are transmitted to the destination
where they are applied to parity checker to check possible errors in transmission.
 The output of the parity checker should have even number of ones for accurate
transmission. If an error is encountered, then it will have odd number of ones.
 The parity checker can be implemented with XOR-gate. C= (X xor Y) (Z xor P).
Even Parity Generator

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X Y Z P

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 1

Even Parity Generator

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X Y Z P C

0 0 0 0 0

0 0 0 1 1

0 0 1 0 1

0 0 1 1 0

0 1 0 0 1

0 1 0 1 0

0 1 1 0 0

0 1 1 1 1

1 0 0 0 1

1 0 0 1 0

1 0 1 0 0

1 0 1 1 1

1 1 0 0 0

1 1 0 1 1

1 1 1 0 1

1 1 1 1 0

Implementation using Multiplexers and Decoders

 The following is the procedure for implementation.
1. List the input of the multiplexer.
2. List under them all the given minterms in two rows. the first half of the minterms
associated with A‟ and the second half with A.
3. The given function is implemented by circling the minterms of the function and
applying the following rules to find the various values for the input of the multiplexer.
 If the two minterms in a column are not circled, apply 0 to the corresponding
multiplexer input.
 If the two minterms in a column are circled, apply 1 to the corresponding
multiplexer input.

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 If the bottom minterm is circled and top is not circled, apply A to the corresponding
multiplexer input.
 If the top minterm is circled and bottom is not circled, apply A‟ to the
corresponding multiplexer input.
4. Draw the multiplexer implementation diagram.
Example: Implement the following function using a multiplexer.
F (A, B, C) = ∑(1, 3, 5, 6)
Solution
Variables, n = 3 (A, B, C)
Selection lines = n -1 = 2 (S0, S1)
2n to 1 MUX (i.e) 22 to 1 MUX = 4 to 1 MUX
Input lines = 2n – 1 = 22 = 4 (I0, I1, I2, I3)
Implementation Table

I0 I1 I2 I3

A’ 1 3
0 2

A 5 6
4 7

0 1 A A‟

I0= 0, I1=1 I2 = A I3 = A‟

Multiplexer Implementation

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Example: Implement the following function with a multiplexer.

F(A,B,C,D) = ∑(0,1,3,4,8,9,15).
Solution
Implementation Table
D0 D1 D2 D3 D4 D5 D6 D7
0 1 2 3 4 5 6 7
A 8 9 10 11 12 13 14 15
1 1 0 0 0 A

Multiplexer Implementation

3. 15 Programmable Logic Devices

 As number of components rise, nodes interconnection complexity grow exponentially
Growth in interconnection will cause increase in interference, PCB size, PCB design
cost, and manufacturing time.
 The purpose of a PLD device is to permit elaborate digital logic designs to be
implemented by the user in a single device.
 It can be erased electrically and reprogrammed with a new design, making them very
well suited for academic and prototyping
Types of Programmable Logic Devices
 SPLDs (Simple Programmable Logic Devices)
 ROM (Read-Only Memory)
 PLA (Programmable Logic Array)
 PAL (Programmable Array Logic)
 GAL (Generic Array Logic)

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 CPLD (Complex Programmable Logic Device)

 FPGA (Field-Programmable Gate Array)
 The first three varieties are quite similar to each other: They all have an input
connection matrix, which connects the inputs of the device to an array of AND-gates.
 They all have an output connection matrix, which connect the outputs of the AND-gates
to the inputs of OR-gates which drive the outputs of the device.
 The gate array is significantly different and will be described later. The differences
between the first three categories are these:
1. In a ROM, the input connection matrix is hardwired. The user can modify the output
connection matrix.
2. In a PAL/GAL the output connection matrix is hardwired. The user can modify the
input connection matrix.
3. In a PLA the user can modify both the input connection matrix and the output
connection matrix.

General structure of PLD

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Buffer/Invertor Symbol and Circuit

 A programmable logic device (PLD) is an integrated circuit with internal
logic gates that are connected through electronic fuses.
 Programming the device involves the blowing of internal fuses to achieve
a desired logic function. The initial stateof PLD has all the fuses intact.

Programming by blowing fuses (a) Before Programming (b) After Programming

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 All PLD consists of programmable arrays. A programmable array is

essentially a grid of conductors that form rows and columns with a fusible
link at each cross point. Arrays can be either fixed or programmable.
 The gates in a PLD are divided into an AND array and an OR array that are
connected together to provide an AND-OR implementation.
 An OR array consists of OR gates connected to a programmable matrix with
fusible links at each cross point of a row and column.
 The array can be programmed by blowing fuses to eliminate selected
variables from the output functions.
 An AND array consists of AND gates connected to a programmable matrix
with fusible links at each cross point of a row and column.
 The array can be programmed by blowing fuses to eliminate variables from
the output function.

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PROM (Programmable Read Only Memory)

 PROMS are programmed by user. To provide the programming facility, each
address select and data line intersection has its own fused MOSFET or
transistor.
 When the fuse is intact, the memory cell is configured as a logic1 and
when fuse is blown (open circuit), the memory cell is logical 0.
 Logical 0s are programmed by selecting the appropriate select line and
then driving the vertical data line with a pulse of high current.

 It has diodes in every bit position; therefore, the output is initially all 0s.
Each diode however has a fusible link in series with it.

 By addressing bit and applying proper current pulse at the corresponding

output, we can blow out the fuse, storing logic 1 at that bit position.

 The fuse uses material like nichrome and polycrystalline. For blowing the
fuse it is necessary to pass around 20 to 50 mA of current for period 5 to
20ps.

 The blowing of fuses according to the truth table is called programming of

ROM. The user can program PROMs with special PROM programmer.

 The PROM programmer selectively burns the fuses according to the bit
pattern to be stored. This process is also known as burning of PROM.

 The PROMs are one time programmable. Once programmed, the information
stored is permanent.

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EPROM (Erasable Programmable Read Only Memory)

 Erasable programmable ROMs use MOS circuitry. They store 1s and 0sas
a packet of charge in a buried layer of the IC chip.
 EPROMs can be programmed by' the user with a special EPROM
programmer.
 The important point is that we can erase the stored data in the EPROMs by
exposing the chip to ultraviolet light through its quartz window for 15 to
20 minutes.

 It is not possible to erase selective information, when erased the entire

information is lost. The chip can be reprogrammed.
 This memory is ideally suitable for product development, experimental
projects, and college laboratories, since this chip can be reused many
times, over.

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3.17. 1 EPROM Programming:

 When erased each cell in the EPROM contains I. Data is introduced by
selectively programming 0s into the desired bit locations.
 Although only 0s will be programmed, both1s and 0s can be presented in
the data.
 During programming address and data are applied to address and data pins
of the EPROM.
 When the address and data are stable, program pulse is applied to the
program input of the EPROM.
 The program pulse duration is around50 ms and its amplitude depends on
EPROM IC. It is typically 11.5 V to25 V.
 In EPROM, it is possible to program any location at any time - either
individually, sequentially.
EEPROM (Electrically Erasable Programmable Read Only Memory)
/EAPROM (Electrically Alterable Programmable Read Only Memory)
 Electrically erasable programmable ROMs also use MOS circuitry very
similar to that of EPROM.
 Data is stored as charge or no charge on an insulated layer or an insulated
floating gate in the device.
 The insulating layer is made very thin (<200 A). Therefore, a voltage as low
as 20 to 25V can be used to move charges across the thin barrier in either
direction for programming or erasing.
 EEPROM allows selective erasing at the register level rather than
erasing all the information since the information can be changed by using
electrical signals.
 The EEPROM memory also has a special chip erase mode by which entire
chip can be erased in 10 ms. this time is quite small as compared to time
required to erase EPROM.
 It can be erased and reprogrammed with device right in the circuit. However,
EEPROMs are most expensive and the least dense ROMs.

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Programmable Logic Arrays (PLAs).

 The combinational circuit does not use all the minterms every time.
Occasionally, they have don't care conditions.
 Don‟t care condition when implemented with a PROM become an address
input that will never occur.
 The result is that not all the bit patterns available in the PROM are used, which
may be considered a waste of available equipment.
 For cases where the number of don't care conditions is excessive, it is more
economical to use a second type of LSI component called a Programmable
Logic Array (PLA).
 A PLA is similar to a PROM in concept; however it does not provide full
decoding of the variables and does not generates all the minterms as in the
PROM.
 The PLA replaces decoder by group of AND gates, each of which can be
programmed to generate a product term of the input variables.
 In PLA, both AND and OR gates have fuses at the inputs, therefore in PLA
both AND and OR gates are programmable.
 It consists of n inputs, output buffer with m outputs, m product terms, m
sum terms, Input and output buffers.
 The product terms constitute a group of in AND gates and the sum terms
constitute a group of m OR gates, called OR matrix.
 Fuses are inserted between all n inputs and their complement values to each
of the AND gates. Fuses are also provided between the outputs of the AND
gates and the inputs of the OR gates.

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 The third set of fuses in the output inverters allows the output function to be
generated either in the AND-OR form or in the AND-OR-INVERT form.
 When inverter is bypassed by link we get AND-OR implementation. To get
AND-OR-INVERTER implementationinverter link has to be
disconnected.
Input Buffer
 Input buffers are provided in the PLA to limit loading of the sources that
drive the inputs. They also provide inverted and non-inverted form of inputs
at its output.

Output Buffer
 The driving capacity of PLA is increased by providing buffers at the output.
They are usually TTL compatible.
 The tri-state, TTL compatible output buffer. The output buffer may provide
totem-pole, open collector or tri-state output.

Example: A combinational circuit is defined by the functions;

F1=∑m(3,5,7)
F2=∑m(4,5,7)
Let us determine the truth table for the given Boolean functions.

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Truth table

K-Map Simplification

Program Table for PLA

PRODUCT INPUTS OUTPUTS

TERM
A B C F1 F2
AC 1 - 1 1 1

BC - 1 1 1 -

A 1 0 - - 1

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 Circuit Diagram:

Programmable Array Logic

 Programmable array logic (PAL) has a programmable AND array at the input and a
fixed OR array at the output.
 The programmable AND array of a PAL architecture is same as that of the PLA
architecture.
 The number of programmable AND gates in PAL architecture are smaller than the
number of minterms.
 The OR array is fixed and the AND outputs are divided between OR gates.

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Realization of PROM PAL and PLA.

PROM PAL and PLA are various forms of PLD. These are mask or programmable devices.
Within these a user must submit a PLA program table to user.

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 EC T45 / DIGITAL CIRCUITS UNIT 3

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