DC Unit 4

EC T45 / DIGITAL CIRCUITS UNIT 4
DEPARTMENT OF ECE
EC T45 – DIGITAL
CIRCUITS UNIT - 4
Sequential Circuits: General model of sequential circuits –latches – Master-slave
Configuration- Flip-Flops - Concept of State – State diagram – State Table.
Synchronous Sequential Circuits – Binary ripple counters-Design of Synchronous counters-
binary counters- Arbitrary sequence counter - BCD counter – Shift Registers – Ring Counter
– Johnson Counter – Timing diagram – Serial Adder – PN sequence generator.
Sequential PLDs – Block diagrams of CPLD and Field programmable Gate Array (FPGA).
Introduction
 The analysis and design of combinational circuits, shows that the outputs dependent
upon the present inputs. It consists of logic gates only.
 There are many applications in which digital outputs are required to be generated in
accordance with the present inputs and previous states of the circuit.
 This requirement cannot be satisfied using combinational logic system. These
application require outputs to be generated depend upon the past outputs of these
inputs.
 The past output is provided by feedback from the outputs back to the input. These
circuits include the memory elements and are called as sequential circuits.
General Model of Sequential Circuits
 A block diagram of a sequential circuit is shown in Figure below.
Block Diagram of Sequential Circuits
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 It consists of a combinational circuit to which storage elements are connected to form

a feedback path. The storage elements are devices capable of storing binary
information.
 This binary information stored in these elements at any given time defines the state of
the sequential circuit at the time. The sequential circuit receives the binary
information from external inputs.
 These inputs and the present state of memory elements determine the binary value of
the output of the circuit. They also determine the condition for changing the state in
memory elements.
 Thus, the next state of the memory elements is also a function of the external inputs
and the present state.
Types of Sequential Circuits
 A sequential circuit is specified by a time sequence of inputs, outputs and internal
states. The sequential circuits can be classified in two ways depending on the timing
of their signals. They are:
 Synchronous sequential circuits.
 Asynchronous sequential circuits.
 A synchronous sequential circuit is a system whose behavior can be defined from the
knowledge of its signals at discrete instants of time, i.e., signals can affect the
memory elements only at discrete instants of time.
 These are also called as clocked sequential circuits. Figure below shows the block
diagram of synchronous clocked sequential circuit.
Synchronous clock sequential circuit

 In asynchronous sequential circuit, change in input signals can affect memory element
at any instant of time.
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 The behaviour of an asynchronous sequential circuit depends upon the order in which
its input signals change and can be affect at any instant of time. These are also called
as unclocked sequential circuits.
 The memory elements used in both cases are flip-flops which are capable of storing 1-
bit binary information. A flip-flop circuit has two outputs one for the normal value
and other for the complement value of the bit stored in it.
Comparison between Combinational Circuits and Sequential Circuits
Combinational Circuits Sequential Circuits
A circuit whose output is dependent only A circuit whose output depends not only on
on the inputs at that instant (or) The circuit the present inputs, but also on the past history
that does not contain any memory of the inputs (or) A circuit that contains at
elements. least one memory element.
Combinational circuits are easy to design Sequential circuits are comparatively harder
but require more hardware. to design but require less hardware.
More expensive circuit. Cheaper circuit.
Combinational circuits are faster in speed, Sequential circuits are slower than the
because delay between input and output is combinational circuits because of memory
due to propagation delay of gates. elements or delay elements.
The behaviour is defined by the set of The behaviour is defined by the set of output
output functions only functions and next state functions
Designer has less flexibility since the Designer has more flexibility because, the
output depends only on the present inputs. output depends on both present input and
Example: Parallel Adder past history of input.
Comparison between Synchronous and Asynchronous Sequential Circuits

Synchronous Sequential Circuits Asynchronous Sequential Circuits
Synchronous sequential circuit is a system The behaviour of asynchronous sequential
whose behaviour is defined from the circuit depends upon the order in which the
knowledge of its signals at discrete instants input change, and the state of the circuits can
of time, i.e., the input signals can affect the be affected at any instant of time, i.e., the
memory elements upon the activation of the change in the input signals can affect
clock pulse. memory element at any instant of time.
Easier to design More difficult to design
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Here the memory elements are clocked flip- The memory elements are either unclocked
flops flip-flops or time delay elements.
The maximum operating speed of clock Because of absence of clock, asynchronous
depends on time delays involved circuits can operate faster than synchronous
circuits.
Synchronization is employed by the help of Here no synchronization, hence it is a
clock pulses. combinational circuit with feedback.
Latches
 A flip-flop can maintain a binary state (either 0 or 1) as long as power is delivered to
the flip-flop. The most basic types of flip-flops operate with signal levels and are
referred to as latches.
 The latches are the basic circuits from which all flip-flops are constructed. Also
latches are useful for storing binary information and for the design of asynchronous
sequential circuits, they are not practical for use in synchronous sequential circuits.
 The basic difference between latches and flip-flops.
Latches Flip-flops
A latch checks all its inputs continuously Flip-flops samples its inputs and changes its
and change its output accordingly at any outputs only at a time as determined by a
time clock signal
No clock is used A clock is used.
It is used in asynchronous sequential logic It is used in synchronous sequential circuit
circuit
RS Latch
 The simplest latch is the Reset-Set latch (RS - latch). It can be constructed from either
two NOR gates or two NAND gates.
 Figure below shows the RS latch using two NOR gates. The two NOR gates are cross
coupled so that output of NOR gate 1 is connected to one of the inputs of NOR gate 2
and vice-versa.
 The latch has two outputs Q and Q’ and two inputs, set (S) and Reset (R).
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RS Latch using NOR Gates

Operation of RS latch
Let us see the operation of this circuit for various input possibilities
Case (i) R = 0 and S = 1
 In this case, S input of NOR gate 2 is at logic 1, hence its output Q’ is at logic 0 which
indicates that both inputs of NOR gate 1 are at logic 0. So that its output, Q is at logic
1 as shown in Figure below.
Case (ii) R = 1 and S = 0

 In this case, R input of the NOR gate 1 is at logic 1, hence its output Q is at logic 0.
This indicates that both inputs of NOR gate 2 are now at logic 0, so its output Q’ at
logic 1 as shown below.
Case (iii) R = 0 and S = 0

 Let us assume that initially Q = 1 and Q’ = 0. With Q’ = 0, both inputs to NOR gate 1
are at logic 0. So its output, Q is at logic 1.
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 With Q = 1, NOR gate 2 output Q’ is at logic 0. Thus the output is same as initial
value. This same for Q = 0 and Q’ = 1 also. The diagram is shown in figure.
Case (iv) R = 1 and S = 1

 When both inputs are at logic 1, they force the outputs of both NOR gates to logic 0
i.e., Q = 0 and Q’ = 0. Since we know that Q is a logic binary variable and Q’ is its
complement, then Q ≠ Q’ for any condition.
 So we call this condition or state as an .indeterminate state or prohibited state. Thus in
normal operation, this condition must be avoided. This is shown in below figure.
 The symbol of RS latch and its truth table is given below.
Symbol of RS Latch
Input Output
State
R S Q Q’
0 0 NC NC No Change
0 1 1 0 Set
1 0 0 1 Reset
1 1 X X Indeterminate
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RS latch using NAND gates or R S Latch

 The active-LOW RS latch can be constructed using two cross-coupled NAND gates.
Figure shows the logic diagram of RS latch using NAND gates.
Logic Diagram and Symbol of RS Latch

Operation
Case (i) If S’ = 1; R’ = 0; it will reset the R S latch i.e., Q = 0 and Q’ = 1
Case (ii) If S’ = 0; R’ = 1, it will set the R S latch i.e., Q = 1 and Q’ = 0
Case (iii) If S’ = R’ = 1, the latch will remain in its previous state
Case (iv) If S’ = R’ = 0, the latch is unpredictable
Input Output
State
R’ S’ Q Q’
1 1 NC NC No Change
1 0 1 0 Set
0 1 0 1 Reset
0 0 X X Indeterminate
Flip-Flops
 The latch is an asynchronous transparent sequential circuit. This meant that any
change in the input of latch is transmitted immediately to the output at Q and Q.
 The operation of the latch can be modified by providing an additional control input
that determines when the state of the circuit is to be changed. This additional control
input is called clock or clock pulse.
 With this clock, the latch is called flip-flops which is also working in synchronous
mode. The term synchronous indicates that the output changes its state only at
specified point according to the input of the latch circuit.
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 There are many types of flip-flops. The major differences among various types of flip-
flops are in the number of inputs they process and the manner in which the inputs
affect their output state. The types of flip-flops s are:
 RS flip-flops
 JK flip-flops
 D flip-flops
 T flip-flops
Clocked RS Flip-flop
 An RS flip-flops is shown below. It consists of basic NOR latch circuit and two AND
gates at the input.
 AND gates remain `0' as long as the clock pulse CLK is `0' regardless of the R and S
inputs. When the clock pulse goes to 1, information from R and S inputs is allowed to
reach the basic RS latch. The basic symbol is also shown below.
Logic Diagram and Symbol of Clocked RS Flip-flop

Operation
 When clock is absent or CLK =0, the circuit will retain same state.
 When clock is present or CLK =1, the RS flip-flop work as basic RS Latch.
Case (i) If R = 0 and S = 0 and assume that Q = 1
 The output of both AND gates are `0' which are given as one of inputs to the NOR
gate. If Q =1 and Q’ =0, the output of NOR gate 1 =1 and NOR gate 2 =0 i.e., same as
the previous values. This state is called .no change state.
Case (ii) If R = 1 and S = 0
 The output of AND gate 1 = 1 and AND gate 2 is `0'. With these inputs, the NOR gate
1 output = 0 and NOR gate 2 output is 1. The state is called reset state.
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Case (iii) If R = 0 and S = 1

 The output of AND gate 1 = 0 and AND gate 2 is 1. With these inputs the NOR gate 1
output =1 and NOR gate 2 output is 0. This state is called set state.
Case (iv) If R = 1 and S = 1
 The output of both AND gates is 1. With these inputs, irrespective of other input, the
output of both NOR gates is `0' i.e., Q=0 and Q’=0 which is an invalid output. This
state is called indeterminate state. The truth table of RS Flip flop is given below.
Input Output
State
CLK R’ S’ Q Q’
0 X X NC NC No Change
1 0 0 NC NC No Change
1 0 1 1 1 Set
1 1 0 0 1 Reset
1 1 1 X X Indeterminate
D Flip-Flop
 A flip-flop whose output follows it data input when the clock is active. As shown
below, D input goes directly to the S input, and its complement is applied to the R
input, through NOT.
 Therefore, only two input conditions exist, either S = 0 and R = 1 or S = 1 and R = 0.
When D = 1; S = 1 and R = 0 and when D = 0; S = 0 and R = 1.
 Therefore, during the occurrence of clock pulse if D = 1, the Q output is set and if D =
0, the output is reset. The table below shows the truth table of D flip-flop.
CLK D Qn+1
0 X Qn
1 0 0
1 1 1
 Here Qn is present state and Qn+1 is Next state.
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Clocked D Flip flop

JK Flip-flop
 A JK Flip-flop is a refinement of the RS flip-flop. In JK flip-flop the unpredictable
state in the RS flip-flop is defined inputs J and K behave like inputs S and R to set and
reset the flip-flop respectively as shown below.
Case (i): J = K =0
 When J and K are both low, both AND gates are disabled. Therefore, clock pulses
have no effect and, Q and Q retain their last values. The truth table of JK FF as shown
in Table below.
Case (ii): J = 0, K =1
 When J is low and K is high. The lower AND gate is disabled. So there is no way to
set the flip-flop. The only possibility is reset.
 When K is high the upper gate passes a RESET trigger as the next possible clock
pulse arrives. This forces Q to become low.
 Therefore J = 0 and K = 1 means that the next positive clock pulse resets the flip-flop
unless Q is already reset.
Clocked JK Flip-flop
Case (iii): J = 1, K =0
 When J is high and K is low, the upper gate is disabled, so there is no way to reset the
flip-flop.
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 The only possibility is to set the flip-flop if it is not previously set with Q = 0; J is
high and hence the lower gate passes a SET trigger on the next positive clock pulse.
 This drives Q into the high state. Therefore, J = 1 and K = 0 means that the next
positive clock pulse set the flip-flop unless Q is already set.
Case (iv): J = K =1
 When J and K are both high (Recall that this is an indeterminate condition with an RS
flip-flop) it's possible to set or reset the flip-flop.
 If Q is high, the upper gate passes a RESET trigger on the next positive clock edge.
On the otherhand, when Q is low, the lower gate passes a SET trigger on the next
positive clock edge.
 Either way, Q changes to the complement of the last state. Therefore, J = K = 1 means
output of the flip-flop will toggle on the next positive clock edge. When the inputs J
and K are short circuited, the JK flip-flop is act as a T flip-flop.
 When input T = 1, it complement the present input. When input T = 0, it maintain the
present state.
FF Inputs Present State Next State
J K Qn Qn+1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
T Flip-flop
 The T flip-flop is also known as .toggle flip-flop. It is a modification of JK flip-flop.
 The T flip-flop is made from a JK flip-flop merly by connecting its J and K terminals
together. This means that at all times J = K. The clocked T flip-flop is shown below.
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Logic Diagram of T Flip-flop

Operation
i) When CLK = 0
The outputs of both AND gates are 0 irrespective of the value of T. The output of the circuit
is same as the previous output.
ii) When CLK = 1
 Case (a) If T = 0. Both AND gates are disabled and hence there is no change in
output.
 Case (b) It T =1(i:e J =K =1) The outputs of both AND gates depend on the previous
output and finally the output toggles (output is complement the present state).
 The logic symbol is given below and the truth table of T flip-flop is shown in table.
Logic Symbol of T flip-flop

Input Present State Next state
T Qn Qn+1
0 0 0
0 1 1
1 0 1
1 1 0
Truth Table of T Flip-flop
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Master Slave Configuration

 This flip-flop has two clocked NAND gate SR flip-flops. One of them is known as
master and the other one slave.
 The figure below shows the JK Master Slave flip-flop. The master is positively
clocked. Due to the presence of inverter, the slave is negatively clocked.
Master Slave Flip-flop

 When the clock is high, the master is active and the slave is inactive. When the clock
is low, the master is inactive and the slave is active. This is a local clocked flip-flop.
 When clock is high any changes in J and K inputs can affect S and R outputs.
Therefore, J and K are kept constant during positive half of clock.
 When clock is low, the master is inactive and J and K inputs can be allowed to be
changed. The different conditions are set, reset and toggle.
 The race condition is avoided because of feedback from slave to the master and the
slave being inactive during positive half of clock.
 To understand the set state, assume that Q’ is low and Q is high. For high J, low K
and high CLK, the master forces to set state giving high J and low K.
 Since slave is inactive, Q’ and Q do not change. When CLK becomes low, the slave
goes to set state giving high Q and low Q’.
 Next is the reset condition. At the end of set state Q is high and Q’ is low. Now if J is
low, K is high and CLK is high, the master resets giving low Q and high Q’.
 Q and Q’ do not change because slave is inactive. When CLK becomes low, the slave
becomes active and resets giving low Q.
 If both J and K are high, the slave copies the master. When CLK is high, the master
toggles once. Then the slave toggles once when CLK is low. If the master toggles into
set state, the slave copies the master and toggles into set state.
 If the master toggles into reset state, the slave again copies the master and toggles into
reset state. The Table below is the truth table of JK master and slave flip-flop.
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Flip Flop Conversions

 There are many types of flip-flops are available, the one type of flip-flop is converted
to another type flip-flop by using the following steps. The figure below shows the
block diagram to realize a required flip-flop using the given flip-flop.
 Draw the block diagram of the desired flip-flop from the given problem.
 Write the truth table of required flip-flop and excitation table of given flip-flop.
 Combine the above truth table and excitation table to form conversion table.
 Using K-Maps, simplify the logic expression for excitation inputs of given FF.
 Draw a circuit for the desired flip-flop using flip-flop conversion logic and the
given flip-flop as shown in the block diagram.
Triggering of Flip-flop
 Flip-flops are synchronous bistable devices. The term synchronous mean that changes
in the output occurred at a specified point on a triggering input called the clock; that
is, changes in the output occurred in synchronization with the clock.
 Based on the specific internal or point in the clock during which triggering the flip-
flop to change the output states. The triggering method can be classified into two
different types.
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 Level triggering
 Edge triggering
Level Triggering in Flip-flop
 Flip-flop circuits are constructed in such a way as to make them operate properly
when they are part of a sequential circuit that employs a common clock. For proper
operation of flip-flop is to trigger it only during a signal transition.
 A clock pulse goes through two transitions from 0 to 1 (positive level triggering) and
the returns from 1 to 0. (Negative level trigger).
 A flip-flop that triggers only during a signal transition (from 0 to 1 or from 1 to 0) and
is disabled during the rest of the clock pulse duration.
 The flip-flop changes its states when clock is positive level, it is termed as positive
level triggering flip-flop. The flip-flop changes its states when the clock is negative, it
is termed as negative level triggering flip-flop.
Edge Triggering Flip-flop
 Edge: The HIGH to LOW (negative edge) or LOW to HIGH (positive edge)
transition of a pulse wave form.
 Edge detector: A circuit in an edge triggered flip-flop that converts active edge of a
CLOCK into an active-level pulse at the internal latch's SET and RESET inputs.
 Edge RC circuit: Depends upon a charging time, the clock is converted to spike by
using RC combination circuit.
 Clock pulse goes through two signal transitions from 0 to 1 and returns from 1 to 0,
as shown in Figure (a). Figure (b) shows the spike wave forms.
 A positive transition is defined as the positive edge and a negative transition as the
negative edge.
RC Equivalent Circuit
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Wave form at output of Edge triggered circuit

 The term edge-triggered means that the flip-flop changes its state either at the positive
edge (rising or leading edge) or at the negative edge (falling or trailing edge) of the
clock. Usually a capacitor in series with a resistor is used for this purpose.
 The positive (or) negative voltage across the resistor appears only during the positive
transition or negative transition of the clock. The positive voltage spike occurring, in
case of positive edge triggered flip-flop if proper signal are available at input
terminals during this short positive spike period.
 Negative edge triggered flip-flop differs from the positive edge triggered only that in
to setting or resetting of the flip-flop takes place only during the negative edge of the
clock.
Concept of State
 A flip-flop is a device that stores either 0 or 1. The state of the flip flop is the value
that it currently stores.
 The stored value can be changed only at a certain times by a clock input and the new
value may further depend on the flip-flops current state and its control input.
 The state of a sequential circuit is a collection of state variables whose values at any
one time contain all the information about the past necessary to account for the
circuit’s behaviour.
Present State
 The status of all state variables, at some time t, before the next clock edge, represents
condition called present state.
 The information stored in the memory elements at any given time defines the present
state of the sequential circuit.
Next State
 The status of all state variables, at some time t+1, represents condition called next
state.
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 The present state and the external inputs determine the outputs and the next state of
sequential circuit.
State Diagram
 State diagram is the pictorial representation of behaviour of a sequential circuit.
 The state represented by a circle, and the transition between different states for
different input conditions are indicated by directed lines connecting the circles.
State Table
 The table which represents the relationship between present states and next states is
called state table.
 State table is the translation of state diagram into a tabular form; representing
relationships among input, output and flip-flop states.
State Assignment
 The state assignment is an one step in the design of sequential circuit which assigns
binary values to states in such a way that it reduces the cost of combinational circuit
that drives the flip-flop.
State Reduction
 The State Reduction is a technique that reduces the number of states in the sequential
circuit by keeping only one state for two or more redundant/equivalent states.
 This reduces the number of required flip-flops and logic gates reducing the cost of
final circuit.
Ripple Counter
 To design the ripple counter, the number of flip-flops required depends on the number
of states. The number of the output states of the counter is called `Modules' (MOD) of
the counter.
 The maximum number of states of a counter is 2n, where n is the number of flip-flops
in the counter.
 If we have two flip-flops, then the maximum possible number of output states of the
counter is 22 i.e. 4. Now we can name that counter as MOD-4 or Modulus -4 counter.
MOD -4 or 2 - bit Asynchronous counter
 MOD - 4 counter is a 2-bit asynchronous counter which consists of four states due to
its two number of flip-flops.
 The state diagram and logic diagram of 2-bit ripple counter is shown in Figure a and
b. The clock is connected to the clock input of first flip-flop.
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 The clock input of the second stage flip-flop is triggered by the QA output of the first
stage.
 Note that the flip-flop changes it's state only when triggered by negative edge of the
each clock pulse, but the second flip-flop changes its state only when triggered by the
negative going transition of the QA output.
 Therefore, the two flip-flops are never simultaneously trigged which results in
asynchronous counter operation.
a) State Diagram
b) Logic Diagram
 The figure below shows the timing diagram for 2-bit asynchronous counter. It
illustrates the changes in the state of the flip-flop outputs in response to the clock.
Timing Diagram
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MOD-8 or 3-bit Ripple counter

 It is a 3-bit asynchronous counter, the count sequence starts from 000 to 111 and uses
three flip-flops. Figure below shows the state diagram of the 3-bit ripple counter.
State Diagram
 In this diagram, each binary states are indicated inside the circles and the directed line
between the circles are indicated by the state transitions.
Logic Diagram
 Figure above shows the 3-bit ripple counter with 3 JK flip-flops named as A,B and C,
where C output represents the most significant bit of the count and the A flip-flop
output indicates the least significant bit of the count.
 Here, first flip-flop (A) is triggered by the CLK which is holding the least significant
bit. The second flip-flop (B) is triggered by QA output of first flip-flop.
 The third flip-flop (C) is triggered by the QB output of the second flip-flop. Figure
below shows the timing diagram of 3-bit ripple counter.
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Timing Diagram
Design procedure of Synchronous counter
To design a synchronous counter, the following steps are followed
Step 1 Obtain the state diagram from the given circuit information
Step 2 Determine the number of required flip-flops
Step 3 Write the excitation table of above obtained flip-flop.
Step 4 Develop the circuit state table by using excitation table.
Step 5 Use K-map to find the expression for corresponding input function of counters
Step 6 Draw the counter circuit by using flip-flop and required gates, from the above
obtained boolean expression.
Example: Design Mod 4 synchronous counter using JK flip-flops and implement it.
Step 1 Here 4 indicates total number of states (0,1,2 and 3)
Step 2 The required flip-flop
2n >N
2n <4
n=2
Two flip-flops are required to design MOD 3 counter. The flip-flops are labelled as A and B.
Step 3 Excitation table for JK flip-flop
Present State Next state Flip-flop Inputs

Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
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Step 4 State table
Present State Next state Flip-flop Inputs

QA QB QA+1 QB+1 JA KA JB KB
0 0 0 1 0 X 1 X
0 1 1 0 1 X X 1
1 0 1 1 X 0 1 X
1 1 0 0 X 1 X 1
Step5 K-map simplification to find expression for corresponding flip-flop inputs

(Present state only is considered for K-map simplification)
Step 6 From above expression, the MOD 4 counter is constructed as follows
Binary Counter
 The following are the types of binary counters. They are
 2-bit synchronous binary counter
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2-bit synchronous binary counter

 Two bit synchronous counter is shown below. It has two JK flip-flops. These flip-
flops are negative edge triggered flip-flops.

 Here, the clock signal is connected in parallel to clock inputs of both the flip-flops.
But the QA output of the first stage is used to derive the J and K inputs of the second
stage.
Operation
 Initially assume that QA =QB =0. For the first clock pulse negative edge, the flip-flops.
A will toggle, because JA = KA = 1 whereas flip-flop B output will remain 0, because
JB = KB = 0 (upto this first clock pulse the QA = 0) and QA = 1 at the end of the pulse
i.e., negative edge of the pulse. So after the first clock pulse QA = 1 and QB = 1.
 At the negative edge of the second clock pulse, both flip-flop will toggle because they
both have a toggle condition on their J and K inputs (i.e. JA = KA = JB = KB = 1). Thus
after second clock pulse QA = 0 and QB = 1.
 At the negative edge of the third clock pulse, flip-flop A toggles making QA = 1, but
flip-flop B remains set (QB = 1). Hence, at the end of third clock pulse QA = QB = 1.
 Finally, at the negative edge of the fourth clock pulse, both flip-flops toggle as their
JK inputs are at logic 1.
 This results in QA = QB = 0 and the counter is recycled back to its original state. The
timing diagram of 2-bit synchronous counter is shown below.
Timing Diagram of 2-bit synchronous binary counter
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The figure shows 3-bit synchronous binary counter and its timing diagram.
Timing Diagram of 3-bit synchronous binary counter

CLK QC QB QA
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
 From the table above, we can notice that flip-flop C has to change its state only when
QB and QA both are at logic 1.
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 This condition is detected by AND gate and applied to the JC and KC inputs of flip-
flop C. Whenever both QA and QB are HIGH, the output of the AND gate makes the J
and K inputs of the flip-flop C HIGH and flip-flop C toggles on the clock pulse.
 At other times (i.e. other than QA = QB = 1), the J and K inputs of flip-flop C are held
Low by the AND gate output and the flip-flop does not change its state.

 The figure below shows the 4-bit synchronous binary counter. This counter contains
four JK flip-flops, namely A,B,C and D where flip-flop A for LSB count and flip-flop
D is for MSB count of the counter.
 All the flip-flops are negative edge triggered flip-flops. The CLK input terminals of
all flip-flops are connected to the common clock pulse.
Logic diagram of 4-bit synchronous binary counter

 The basic operation of the 4-bit synchronous counter can be illustrated as shown
below. The output of the counter is given by Q = QD QC QB QA. Assume initially, all
the flip-flops are in reset condition and the count Q = 0000.
Timing diagram of 4-bit synchronous binary counter

 From table below, the output of flip-flop A must change for every clock pulse. So, the
inputs JA and KA are connected to HIGH, so that the output QA toggles on each clock
pulse. After the first clock pulse, the count Q = 0001.
108
 The flip-flop B output must change whenever the QA = 1 and a clock pulse occurs
and when QA = 0, the output QB remains same. After the second clock pulse, the
count Q = 0010.
CLK QD QC QB QA
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
 When QA and QB are at HIGH, then the third flip-flop output QC is made to change its
state. This condition is detected by the AND gate 1 and it's output is applied to the J
and K inputs of the third flip-flop.
 Whenever both QA and QB are HIGH, the output of the gate 1 makes as the JC and KC
of flip-flop C and it toggles on the following clock pulse. At all other conditions, the
gate output is 0 and QC does not change its state.
 We can also observe that whenever QA;QB and QC are at HIGH, the fourth flip-flop D
changes its output. This condition is detected by AND gate 2, so that when a clock
109
pulse occurs, the D flip-flop will change the state. Note that for all other times, the JD
and KD inputs are LOW and it is no change condition.
Arbitrary Sequence Generator

Design an arbitrary counter using the following sequence
02457024
 It goes from 0 to 2 then 4 this way. After reaching 7 it goes back to beginning of the
sequence and repeats the sequence.
 The figure below shows the arbitrary sequence counter state diagram
Arbitrary sequence counter state diagram
Arbitrary sequence counter binary state diagram

Arbitrary Counter State Table
 When simplifying input equations, unused states can be used as don’t care conditions
or it may also be assigned specific next states. Here unused or unreachable states are
1, 3, and 6 so these states can have any assigned next state of designer’s choice.
110
 The reason or advantage of using don’t care is easier state diagram, smaller state
table, easier k-map equations as well as less connections in the logic diagram etc.
 There is also a good reason to use specific next states from unreachable states instead
of using don’t care conditions. Such as during operation due to outside interference
the may reach an unused state and break the intended sequence. Also it may keep
circulating in unused states and never come back to original sequence.
BCD Counter
 To design a BCD or Decade (MOD-10) counter that has ten states i.e., 0 to 9 the
number of flip flops required is four. Let us assume that the MOD-10 counter has ten
states, viz.
Step 1 – State diagram:
 Now the state diagram for the MOD-10 counter can be drawn. Here, it is assumed that
the state transition from one state to another takes place when the clock pulse is
asserted. When the clock is unasserted, the counter remains in the present state.
Step 2 – State Table:
 From the above state diagram, one can draw the Present state – Next state table as
shown below,
Present State (PS) Next State (NS)
a b
b c
c d
d e
e f
f g
g h
h i
i j
j a
 The above state table does not have any redundant state because no two are
equivalent. So, there is no modification required in the above state table.
111
Step 3 – State Assignment:

Let us assign four state variables to these states a,b,c,d,e,f,g,h,i and j as follows:a = 0000, b=
0001, c =0010, d=0011, e=0100, f=0101, g=0110, h=0111, i=1000, j=1001. Then, the above
PS – NS table can be modified as shown below.
Present State (PS) Next State (NS)
q3q2q1q0 Q3Q2Q1Q0
0000 0001
0001 0010
0010 0011
0011 0100
0100 0101
0101 0110
0110 0111
0111 1000
1000 1001
1001 0000
1010 dddd
1011 dddd
1100 dddd
1101 dddd
1110 dddd
1111 dddd
State diagram of BCD counter
112
Step 4 – Excitation Table:

The excitation table having entries for flip-flop inputs can be drawn, from the PS–NS table
using the application table of JK flip-flop given earlier, as shown below,
Present State Next State Excitation Inputs

q3 q2 q1 q0 Q3 Q2 Q1 Q0 J3 K3 J2 K2 J1 K1 J0 K0
0000 0001 0 d 0 d 0 d 1 d
0001 0010 0 d 0 d 1 d d 1
0010 0011 0 d 0 d d 0 1 d
0011 0100 0 d 1 d d 1 d 1
0100 0101 0 d d 0 0 d 1 d
0101 0110 0 d d 0 1 d d 1
0110 0111 0 d d 0 d 0 1 d
0111 1000 1 d d 1 d 1 d 1
1000 1001 d 0 0 d 0 d 1 d
1001 0000 d 1 0 d 0 d d 1
1010 dddd d d d d d d d d
Step 5 – Excitation Maps:

The excitation maps for inputs of the counter can be drawn below
113
Schematic Diagram
Schematic Diagram of BCD or Mod 10 counter
114
Timing Diagram of BCD or Mod 10 counter

Shift Registers
 A register that is capable of shifting data one bit at a time is called a shift register.
 The logical configuration of a serial shift register consists of a chain of flip-flops
connected in cascade, with the output of one flip flop being connected to the input of
its neighbor.
 The operation of the shift register is synchronous; thus each flip-flop is connected to a
common clock. Using D flip-flops forms the simplest type of shift-registers. The basic
data movement possible within a four-bit shift registers.
Data movement diagram
115
Assume that the register is initially clear.
Four-bit serial in-serial out shift register

Shift left register:
 The entry of the four bit binary number1111 into the register beginning with the right
most.
Case 1: Initially, register is cleared. So QD QC QB QA = 0 0 0 0. When the data 1 1 1 1 is

applied serially. The left most 1 is applied to Din. Din = 1, QD QC QB QA = 0 0 0 0.
The arrival of the first falling clock edges sets the right most (D flip flop) and the stored
information as follows QD QC QB QA = 0 0 0 1.
Case 2: When the next negative clock edges hits, the flip flop sets and the register
contents QD QC QB QA = 0 0 1 1
Case 3: The third negative clock edges, the register contents QD QC QB QA = 0 1 1 1
Case 4: The fourth negative clock edges, the register contents QD QC QB QA = 1 1 1 1
Shift right register:
 The entry (consider the binary data 1 1 1 1) of the four bit binary number into the
register, beginning with left most bit, the register is cleared QD QC QB QA = 0 0 0 0
116
 When the data 1 1 1 1 is applied serially the left most 1 is applied to Din So, Din = 1
QD QC QB QA = 0 0 0 0
Case 1: The arrival of the first falling clock edge sets the left most flip flop, and stored
contents as follows QD QC QB QA = 1 0 0 0
Case 2: After second falling clock edge, the register contents QD QC QB QA = 1 1 0 0
Case 3: The third falling clock edge, the register contents QD QC QB QA = 1 1 1 0
Case 4: The fourth falling clock edge, the register contents QD QC QB QA = 1 1 1 1
Ring Counter
 In the Shift Register, if we apply a serial data signal to the input of a Serial-in to
Serial-out Shift Register, the same sequence of data will exit from the last flip flop in
the register chain after a preset number of clock cycles thereby acting as a sort of time
delay circuit to the original input data signal.
 But what if to connect the output of this Shift Register back to its input so that the
output from the last flip-flop, QD becomes the input of the first flip-flop, DA.
 The closed loop circuit that “re-circulates” the same bit of data around a continuous
loop for every state of its sequence, and this is the principal operation of a Ring
Counter.
 Then by looping the output back to the input, (feedback) we can convert a standard
shift register circuit into a ring counter. Consider the circuit below.
117
4- bit Ring Counter:

 The synchronous Ring Counter is preset so that exactly one data bit in the register is
set to logic “1” with all the other bits reset to “0”.
 To achieve this, a “CLEAR” signal is firstly applied to all the flip-flops together in
order to “RESET” their outputs to a logic “0” level and then a “PRESET” pulse is
applied to the input of the first flip-flop (FFA) before the clock pulses are applied.
This then places a single logic “1” value into the circuit of the ring counter.
 So on each successive clock pulse, the counter circulates the same data bit between
the four flip-flops over and over again around the “ring” every fourth clock cycle.
 In order to cycle the data correctly around the counter we must first “load” the counter
with a suitable data pattern as all logic “0‟s” or all logic “1‟s” outputted at each clock
cycle would make the ring counter invalid.
 This type of data movement is called “rotation”, and like the previous shift register,
the effect of the movement of the data bit from left to right through a ring counter can
be presented graphically as follows along with its timing diagram:
Rotational Movement of a Ring Counter
118
 Since the ring counter has four distinct states, it is also known as a “modulo-4″ or
“mod-4″ counter with each flip-flop output having a frequency value equal to one-
fourth or a quarter (1/4) that of the main clock frequency.
 The “MODULO” or “MODULUS” of a counter is the number of states the counter
counts or sequences through before repeating itself and a ring counter can be made to
output any modulo number.
 A “mod-n” ring counter will require “n” number of flip-flops connected together to
circulate a single data bit providing “n” different output states.
 For example, a mod-8 ring counter requires eight flip-flops and a mod-16 ring counter
would require sixteen flip-flops.
 However, as in our example above, only four of the possible sixteen states are used,
making ring counters very inefficient in terms of their output state usage.
Johnson Counter
 The Johnson Ring Counter or “Twisted Ring Counters”, is another shift register with
feedback exactly the same as the standard Ring Counter above, except that this time
the inverted output Q of the last flip-flop is now connected back to the input D of the
first flip-flop as shown below.
 The main advantage of this type of ring counter is that it only needs half the number
of flip-flops compared to the standard ring counter then its modulo number is halved.
 So a “n stage” Johnson counter will circulate a single data bit giving sequence of 2n
different states and can therefore be considered as a “mod-2n counter”.
4- bit Johnson Ring Counter
 This inversion of Q before it is fed back to input D causes the counter to “count” in a
different way. Instead of counting through a fixed set of patterns like the normal ring
counter such as for a 4-bit counter.
 For a 4-bit counter, “0001”(1), “0010”(2), “0100”(4), “1000”(8) and repeat, the
Johnson counter counts up and then down as the initial logic “1” passes through it to
the right replacing the preceding logic “0”.
 A 4-bit Johnson ring counter passes blocks of four logic “0” and then four logic “1”
thereby producing an 8-bit pattern. As the inverted output Q is connected to the input
D this 8-bit pattern continually repeats.
 For example, “1000”, “1100”, “1110”, “1111”, “0111”, “0011”, “0001”, “0000” and
this is demonstrated in the following table below.
119
Clock Pulse A-FF B-FF C-FF D-FF

0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1
Truth Table for 4-bit Johnson counter
 As well as counting or rotating data around a continuous loop, ring counters can also
be used to detect or recognize various patterns or number values within a set of data.
 By connecting simple logic gates such as the AND or the OR gates to the outputs of
the flipflops the circuit can be made to detect a set number or value.
Serial Adder
 Sequential serial adders are economically efficient and simple to build. A serial adder
consists of a 1-bit full-adder and several shift registers. In serial adders, pairs of bits
are added simultaneously during each clock cycle.
 Two right-shift registers are used to hold the numbers (A and B) to be added, while
one left-shift register is used to hold the sum (S). A block diagram of a serial adder is
shown below.
A finite-state machine adder performs the addition operation on the values stored in the input
shift registers and stores the sum in a separate shift register during several clockcycles.
During each clock cycle, two input bits ai and bi are shifted from the two input right-shift
registers into the 1-bit full-adder, which adds the two bits and evaluates the sum bit si and the
carryout bit ci+1. The sum bit si, is shifted out to the left-shift register and the carryout
120
bit ci+1 is stored in the state memory of the serial adder for the next two bits. The time
sequence of the operation of a 4-bit serial adder is illustrated in table below.
A B S Si Ci+1
1011 0011 0000 0 1
0101 0001 1000 1 1
0010 0000 1100 1 0
0001 0000 1110 1 0
Time sequence operation of 4-bit serial adder
PN Sequence Generator
 Pseudo noise sequence is a binary sequence used in spread spectrum communication
for spreading the message signal.
 These coded sequences are generated independently at two or more sites, and this
sequence must be deterministic, even though it should appear random to unauthorized
listeners. Such random appearing deterministic signals are called pseudo noise or
pseudo random signals.
 A pseudo noise sequence is a periodic binary sequence with a noise like waveform
that is usually generated by means of a feedback shift register, a general block
diagram of which is shown below.
 The flip flops in the shift register are regulated by a single timing clock. At each clock
pulse, the state of the flip flop is shifted to the next one down the line.
PN Sequence Generator using Flip-flops

 The PN Sequence Generator block generates a sequence of pseudo random binary
numbers. A pseudo noise sequence can be used in a pseudorandom scrambler and
descrambler. It can also be used in a direct-sequence spread-spectrum system.
121
 The PN Sequence Generator block uses a shift register to generate sequences, as

shown below.
PN Sequence Generator using Shift Registers

Block Diagram of FPGA
 Field Programmable Gate Arrays (FPGA) provide the
next generation in the programmable logic devices.
General FPGA Architecture

 The word array is used to indicate a series of columns and rows of
gates that can be programmed by the end user.
122
 As compared to standard gate arrays, the field programmable gate arrays

are larger devices. The basic cell structure for FPGA is somewhat
complicated than the basic cell structure of standard gate array.
 The programmable logic blocks of FPGAs are called configurable logic
blocks (CLBs). The FPGA architecture consists of three types of
configurable elements –
 A perimeter of input/output blocks (IOBs),
 A core array of configurable logic blocks (CLBs) and
 Resources for interconnection.
 The IOBs provide a programmable interface between the internal array
of logic blocks (CLBs) and the device's external package pins.
 CLBs perform user-specified logic functions, and the interconnect
resources carry signals among the blocks.
 A configuration program stored in internal static memory cells
determines the logic functions and the interconnections.
 The configuration data is loaded into the device during power-up
reprogramming functions.
 FPGA devices are customized by loading configuration data into internal
memory cells.
 The FPGA device can either actively read its configuration data out of
an external serial or byte-wide parallel PROM (master modes), or the
configuration data can be written to the FPGA device (slave and
peripheral modes).
Architecture of FPGA
 The general structure of FPGA chip consists of a large number of
programmable logic blocks surrounded by programmable I/O block.
 The programmable logic blocks of FPGA are smaller and less capable
than a PLD, but an FPGA chip contains a lot more logic blocks to
make it more capable.
 The logic blocks are distributed across the entire chip. These logic blocks
can be interconnected with programmable interconnections.
 The programmable logic blocks in the Xilinx family of FPGAs are
called configurable logic blocks (CLBs).
123
 The Xilinx architecture uses CLBs, I/O blocks switch matrix and an
external memory chip to realize a logic function. It uses external
memory to store the interconnection information.
 Therefore, the device can be reprogrammed by simply changing the
configuration data stored in the memory.
Configurable Logic Block:
 The CLB consists of a combinational logic array, program controlled
data multiplexers, and flip-flops.
 The program controlled multiplexers are used to route data internally
in the CLB.
 The two outputs of the combinational logic function F and G can be
routed through multiplexers to either of the two output pins or to the
D inputs of the two flip-flops.
CLB used to generate 5 variable function

 The other possible input for D flip-flops is data input, which is
independent of the combinational array.
 A clock enables and reset inputs are common to both flip-flops. Both
inputs are active high. Two output multiplexers are used.
 They can select either a flip-flop (Q1and Q2) or a combinational (F
and G) logic output.
124
General Architecture of FPGA chip
Block Diagram of CPLD

 PLAs and PALs are useful for implementing a wide variety of small digital circuits.
 Each device can be used to implement circuits that do not require more than the
number of inputs, product terms, and outputs that are provided in the particular chip.
 These chips are limited to fairly modest sizes, typically supporting a combined
number of inputs plus outputs of not more than 32.
 For implementation of circuits that require more inputs and outputs, either multiple
PLAs or PALs can be employed or else a more sophisticated type of chip, called a
complex programmable logic device (CPLD), can be used.
 A CPLD comprises multiple circuit blocks on a single chip, with internal wiring
resources to connect the circuit blocks. Each circuit block is similar to a PLA or a
PAL; we will refer to the circuit blocks as PAL-like blocks.
 An example of a CPLD is shown below. It includes four PAL-like blocks that are
connected to a set of interconnection wires.
125
Structure of CPLD
 Each PAL-like block is also connected to a subcircuit labeled I/O block, which is
attached to a number of the chip's input and output pins.
 The figure below shows an example of the wiring structure and the connections to a
PAL-like block in a CPLD.
 The PAL-like block includes 3 macrocells (real CPLDs typically have about 16
macrocells in a PAL-like block), each consisting of a four-input OR gate (real
CPLDs usually provide between 5 and 20 inputs to each OR gate).
 The OR-gate output is connected to another type of logic gate that we have not yet
introduced. It is called an Exclusive-OR (XOR) gate. The behavior of an XOR gate
is the same as for an OR gate except that if both of the inputs are 1, the XOR gate
produces a 0.
 One input to the XOR gate in figure above can be programmably connected to 1 or
0; if 1, then the XOR gate complements the OR-gate output, and if 0, then the XOR
output value produced by the OR gate.
 Each tri-state buffer (see section 3.8.8) is connected to a pin on the CPLD package.
The tri-state buffer acts as a switch that allows each pin to be used either as an
output from the CPLD or as an input.
 To use a pin as an output, the corresponding tri-state buffer is enabled, acting as a
switch that is turned on. If the pin is to be used as an input, then the tri-state buffer is
disabled, acting as a switch that is turned off.
126
 In this case an external source can drive a signal onto the pin, which can be
connected to other macrocells using the interconnection wiring. The interconnection
wiring contains programmable switches that are used to connect the PAL-like
blocks.
 Each of the horizontal wires can be connected to some of the vertical wires that it
crosses, but not to all of them. Extensive research has -been done to decide how
many switches should be provided for connections between the wires.
 The number of switches is chosen to provide sufficient flexibility for typical circuits
without wasting many switches in practice.
 Some CPLDs include additional connections between the macrocells and the
interconnection wiring that avoids wasting macrocells in such situations.
Commercial CPLDs range in size from only 2 PAL-like blocks to more than 100
PAL like blocks.
A Section of CPLD
127

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EC T45 / DIGITAL CIRCUITS UNIT 4

Block Diagram of Sequential Circuits

 It consists of a combinational circuit to which storage elements are connected to form

Synchronous clock sequential circuit

Comparison between Synchronous and Asynchronous Sequential Circuits

RS Latch using NOR Gates

Case (ii) R = 1 and S = 0

Case (iii) R = 0 and S = 0

Case (iv) R = 1 and S = 1

 The symbol of RS latch and its truth table is given below.

RS latch using NAND gates or R S Latch

Logic Diagram and Symbol of RS Latch

Logic Diagram and Symbol of Clocked RS Flip-flop

Case (iii) If R = 0 and S = 1

 Here Qn is present state and Qn+1 is Next state.

Clocked D Flip flop

Logic Diagram of T Flip-flop

Logic Symbol of T flip-flop

Master Slave Configuration

Master Slave Flip-flop

Flip Flop Conversions

Wave form at output of Edge triggered circuit

MOD-8 or 3-bit Ripple counter

Present State Next state Flip-flop Inputs

Step 4 State table

Present State Next state Flip-flop Inputs

Step5 K-map simplification to find expression for corresponding flip-flop inputs

Step 6 From above expression, the MOD 4 counter is constructed as follows

105 DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING - RAAKCET

2-bit synchronous binary counter

2-bit synchronous binary counter

Timing Diagram of 2-bit synchronous binary counter

3-bit synchronous binary counter

3-bit synchronous binary counter

Timing Diagram of 3-bit synchronous binary counter

3-bit synchronous binary counter

Logic diagram of 4-bit synchronous binary counter

Timing diagram of 4-bit synchronous binary counter

Arbitrary Sequence Generator

Arbitrary sequence counter state diagram

Arbitrary sequence counter binary state diagram

Step 3 – State Assignment:

State diagram of BCD counter

Step 4 – Excitation Table:

Present State Next State Excitation Inputs

Step 5 – Excitation Maps:

Schematic Diagram of BCD or Mod 10 counter

Timing Diagram of BCD or Mod 10 counter

Data movement diagram

Assume that the register is initially clear.

Four-bit serial in-serial out shift register

Case 1: Initially, register is cleared. So QD QC QB QA = 0 0 0 0. When the data 1 1 1 1 is

4- bit Ring Counter:

Clock Pulse A-FF B-FF C-FF D-FF

Truth Table for 4-bit Johnson counter

Time sequence operation of 4-bit serial adder

PN Sequence Generator using Flip-flops

 The PN Sequence Generator block uses a shift register to generate sequences, as

PN Sequence Generator using Shift Registers

General FPGA Architecture

 As compared to standard gate arrays, the field programmable gate arrays

CLB used to generate 5 variable function

General Architecture of FPGA chip