WORLD'S #1 ACADEMIC OUTLINE

ELE
PART 2 of FUNDAMENTALS OF ELECTRONIC DEVICES & BASIC ELECTRONIC CIRCUITS

OPERATIONAL AMPLIFIERS -SLEW RATE: Maximum rate at which the output ~------------------------~
LINEAR VOLTAGE-TO-CURRENT
voltage can change (volts/microsecond). In ideal OP­
CONVERTERS
DEFINITIONS AMPs, slew-rate ~ 00.

Fi~ ~ ,.~
- A basic ditlerential amplifier (see Electronics I Part -OTHER PARAMETERS: (I) Bandwidth; (2)
One) enables mathematical ditlerence operation and Maximum output current available when the output

~:,- ~; j :.:- ~; j
can be modified to perform addition, integration and terminal is set to ground; (3) PSRR: Power supply
differentiation. Hence, the differential amplitier is also
designated as an Operational Amplifier (Op-Amp).
rejection ratio: Change in input offset voltage to
corresponding change in one of the power supply
voltages (±V). Ideally, PSRR = 0; in practice, it is of
.
-An Op-Amp represents, v ~ V Fig
111 essence, a hIgh-gam "" ­ the order of a few 11VIV. Source Circuit Sink Circuit
electrol1lc cIrcuIt mtended A
to amphfy the dlflerence 111 + Vo ~ vom FREQUENCY ROLL-OFF LOGARITHMIC AMPLIFIER
the sIgnal voltages apphed v,,,, v It is the fall-off of the voltage gain at high frequencies. This
to its two input terminals, namely, inverting (- ) and is indicated by gain-bandwidth product. Roll-off to higher V k. T
=-I-In _'_n_ (V. )
non-inverting (+) inputs (Fig. 1). frequencies is achieved by frequency compensation. out q alllR
-In simple form (Fig. 2), Fig. 2 V OU!

an Op-Amp constitutes a Differential Pair R~vcrsc saturation current or E8 Juncti on

differential amplifier made output
INVERTING AMPLIFIER : Tran sislOr a
kl3 : l30hzmann Constant
Up of, for example, a pair of +~­ (VIRTUAL GROUND AMPLIFIER)
BJTs driven by a constant Non­ Fig. 3
a: Virtual R, CHARGE AMPLIFIER
current source (I). JFETs inverting I Fig. 10
and MOSFETs can also be IOput Input (from a
used as differential pairs. VOU(
capac iti ve transducer); Vin

input Cr: Nominal capaci tan ce

IDEAL OP-AMP CHARACTERISTICS R, ~ R

J
of the transducer

charged by a voltage V.

- Nominal voltage gain, A ~ ~

-Input impedance (at both inputs), Zln ~

00
-Output impedance with feedback ='
V
out
= v.In (1+~)
R,
-Output impedance, Zo ~ 0
Output impedance of the OP-AMPxClosed-loop gain
- Both transistors are idcntical.
·Vo = -AVint = AVin2; or, if Vinl = Vin2, Vo = 0 (Open-loop gain)
- Bandwidth (BW) ~ ~ - Node a is almost at ground potential.
PRECISION RECTIFIER &
- With bipolar transistors, it may be difficult to -Closed-loop voltage gain Vout / Vin = -R2/RI Fig. 11 PEAK DETECTOR
achieve a very high-input impedance. -Input impedance = RI
-JFET and MOSFET provide high-input impedance
capabilities.
- Output impedance = Ro
~ VOO.'~ V","

'" ~v,"~
NON-INVERTING AMPLIFIER
OP-AMP OPERATIONAL PARAMETERS Fig. 4
v
J,
In reference to typical inverting (Fig. 3, above right) andnon­
Precision Recti fier Peak Detector
inverting (Fig. 4) modes ofoperational characteristics: R2
-INPUT BIAS CURRENT: This is the emitter current Av=l + ­
in the differential amplifier for active region operation
Non-inverting Zln = R3 R. VOLTAGE FOLLOWER
input
of the pair of BJTs (e.g. 0.0511A for 741 OP-AMP) Zout ~ Low (UNITY GAIN AMPLIFIER)

F,g ~ ._
which comes through R2 so that Vou' = (0.05 X 10-6
x R 2)volts. This could be large enough to saturate the
output. Saturation is overcome by introducing R, =
INTEGRATOR (LOW-PASS FILTER) Zill =A X (Rill (Device)(
RdlR2 and made adjustable to compensate for input
Vi" ~ Z,,,,,
[Ro (Device)]
offset current due to any dissimilarities in the differ­ Fig. 5 c - R 2: Provides negative
feedback for low­ A
ential pair configuration (Fig. 3). output impedance
-INPUT OFFSET VOLTAGE (= ± 60mV): It is needs, but it also Unity Gain Amplifier
required at the input as a counter voltage to offset the distorts the output. The output voltage "follows" the input voltage. Used
tinite unbalance voltage due to unequal current flowing
through the differential pair devices in the OP-AMP, so _
dv o
dt
=-~
R.C
V
0
=_(_I_)Xf
R.C
V.
,n
dt
as a buffer amplifier with high-input/low-output
impedance reali zation.
that this balancing gives zero output voltage.
-CMRR: When the OP-AMP is ideally balanced at
REGULATED POWER SUPPLY
DIFFERENTIATOR (HIGH-PASS FILTER) The Zener diode offers a constant reference voltage
the input, the output voltage = 0, i.e. Vlnt = Vin2, and (V z). Bias derived from the unregulated voltage (VII),
this circuit can reject common-mode signals due to its
common-mode gain (Ae) = O. For differential mode
Fig. 6 p
~ via potential division by RI and Rl and the Zener

signals (Vln' - Vin2), the gain (Ad) ~~. The ratio Ad/Ae
Vin ...-.t"·1~
RR.,' +A
I- v
""
.
-Inverse operatIOn 0
f
reference voltage, are compared by an inverting
amplifier to provide a stable output Voltage.
common-mode rejection ratio (CMRR). In practical the integrator circuit. Vou' = V, (t + R./ R 2) and I, = (vou,- V,) / R3
OP-AMPs, Ae > 0 and Ad < 00; or, CMRR is finite Fig. 13
and indicates the extent of balance in the OP-AMP (A
Igure of merit parameter).
-OUTPUT VOLTAGE SWING: This is the peak LEVEL CLAMPING

: g~>L".'
output swing with reference to zero at the output.
It is limited by power supply voltages used (= 80
percent of power supply voltage ±V). - The output is
-INPUT VOLTAGE SWING: Input common-mode A out
clamped to Zener
voltage swing is limited by the saturation of the differ­ voltage V, .
ential amplifier at the input: (= 30 percent of power
supply voltage ±V).
1fJffifb.::
R, +

1

DEFINITIONS
• The device current is decided by one type of current
carrier only (unipolar).
• The device interior current is controlled by an electric
field applicd in the path of the current carriers.
FET TYPES
·JFET (Junction Field Effect Transistor): In the
JFET, the resistance of the current path is modulated
by the application of bias voltages to PN junctions
adjacent to it.
• MOSFET (Metal-Oxide Semiconductor FET): In
MOSFET, there arc no junctions. The controlling
electric field is applied via an insulating layer to
regulate the resistance of' a main conducting path.
MOSFET
• When V G is applied: This provides additional DEFINITIONS
reverse-bias. Therefore , pinch-off will occur at ~ Induced channel devicel lnsulated Gate FET (IG
lower VI) and the corresponding VI)(s.') will also FET)
be smaller. Hence, application of V G modulates ·The gate is totally insulatcd rrom the semiconductor by
the channel dimension and reduces In. This is a a thin layer or Si0 2 .
depletion mode operation. Channel current decreases • The voltage applied at the gate induces a
as the gate voltage is increased. conducting channel within the semiconductor and
modulates its conductivity.
LINEAR OPERATION OF JFET
ENHANCEMENT TYPE MOSFET
Fig. 15 Pinch-off locus
Fig. 16

FET OPERATION MODES Si0 2 layer

N+ source N+ drain
• Depletion mode operation: The controlling electric field
reduces the number of carriers available for conduction. Polysili con P-typc cpitaxi a l substrate
• Enhancement mode operation: Application of electric
field causes an increase in the majority-carrier density Si02~ 100 to 300 A' (Thermally grown insulation layer)
in the conducting regions of the transistor.
. Slope: Go MOSFET OPERATION
JFET: DEVICE OPERATION
Fig. 17
Fig. 14a r---....,........
Source Gate 1
GI
No gate bias
G +VJ)
x-direction
----------. ~ I ~

~ )
VI) N+ N+
c- = Electron s
P-('pi

Slope: Go
G +VJ)
~ -+1 + VG

++ +++ ~
N+ 4 .. ~~.-,
Suppose channel is lightly doped relative to the gates, Induced
negat ive
Due to the appl ication of the voltage across source i. e. Na(ga'e) » Nd(ch.nnel)' : . Thickness of depletion P-c pi charges
(S)-to-drain (D), electrons flow from S to 0 (majority
carrier flow). Thc path between S-to-O has an ohmic . . [(Vo+VG)]}
layer 111 the N-channells d n == 2E eN . ..
resistance. Therefore, flow of electron current would Suppose no gate voltagc is applied. Then, N+P junction
As V G changes, d n changes. D
cause a voltage drop and the potential at any point at the source, as well as PN+ junction at the drain ,
along this path (x-direction) increases from the source
[Yo: Contact potential, Na and Nd are acceptor and
are reverse-biased . Thererore, no drain current flows.
donor concentrations; €: Permittivity of the channel].
to drain (becoming more positive towards the drain Suppose a small +V G is applied at the gate. T he
end). Since the gates (tied together) are connected to Let V PO be the value of V G at which pinch-off occurs.
positive voltage at the top of the Si0 2 dielectric
the source, the N-region ofthe channel and the regions The corresponding change in In = O. For V G < V po,
would induce negativc charges below this layer. These
of the gate would form a reverse-biased PN junction. negative charges will deplete the holes of the P­
The extent of reverse bias increases progressively from the epilaycr, exposing ncgatively charged acceptor ions.
source side to drain side. Correspondingly, the depletion i.e. a depletion layer will be tormed just below the
layers formcd will be wider near the drain side as shown. gate as shown in Fig. 17. A further increase in +V G
Normally, the P-type gates (G I and G z) are heavily where Go = channel conductance with zero bias will induce more and more negative charges below the
doped relativc to the N-channel region. Therefore, (VG=O) condition: gate, with the result being a copious accumulation of
channel has (relatively) high resistance. Hence, the Go = (eNd~.) x negative charges below the gate forming an induced­
depletion laycr widens predominantly into the channel
IArea of cross-section of the channell Length of the layer of negative charges constituting a " channel"
region. Suppose Vo is increased. Consequently, the
channell (induced channel) between the source and thc drain as
depletion layer into the channel widens more. As a
e: electronic charge; ~c: electron mobility. shown in Fig. 18.
result, eventually the two (top and bottom) depletion
layers meet each other. Therefore, the channel is Fig. 18
closed , not permitting the flow of electrons through it. JFET OPERATION
This condition is known as pinch-off. Upon pinch-off: ~
OUTPUT CHARACTERISTICS OF JFET I
os
=1
0"
l] - 3VG+2(VG)~1
Vp Vp
\ -Nt ::: ~ :=::::: "N+" /'
• N-tYPL'in(\ucccll:han1)c l
Transfer Characteristics:
( \ •••• - Dep!ction laye r r',cpi

g -_dlnsl
-- -_ -I 3VJ)l
- - 1- (VG)il
- ­ N-type Induced Channel
m dV 0" VZ V
C Vi) P P
Once the channcl is induced between the Sand
Suppose an additional bias V G is applied between the gm ~ Mutual/transfer conductance 0 , the electrons flow through thi s channel, with
-31 the result bcing a drain current. Therefi.)re, the
gates and the source terminals (Fig. 14b): = Max g =g
m
I
m vG ~ o
=g
mil -
_ _ _ Il,_, - - G
Vp - 0 induced channcl constitutes an ohmic path. The
• Suppose, V G = O. In the absence of drain current, the
conductivity of this channel is dependcnt on the
depletion layer is uniform along the channel. As VI)
= Conductance of the channel with zero bias magnitUde of Ve. In other words, the channel conduc­
increases, II) increases. Corresponding voltage drop
tivity is modulated by VG. Thcreforc, the morc the
along the channel causes a wedge-shaped path due to
VG , the more will be Il). Thus, the device operates in
reasons discussed before. Upon pinch-ofl~ the drain g m == g mil ll - (VG
current remains constant at a saturated value. Vp )}l enhancement lllode.

2
MOSFET OUTPUT CHARACTERISTICS COMMON-GATE AMPLIFIER
Fig. 19 Common-gate (CG) FET amplifier circuit and its
Saturation
G ? VG
Pinch-otT +++1+++ equivalent circuits Fig. 25
10 locus region
Vo (1l+ I )R L •
A v = '- ",gmRLfor

~
lOS vin rd +RL
DifTuscd N-typc layer: Chanllel ~ = gmrd» I, r d » RL
IV d : Increasing P-cpitaxial substrate
Rj V.
=_1_11 =
RI +rd
~ _ _ "' _
__
1 for rd»
R L;
il 11+1 gm
Vos Vo
Ro = -:- = rd + (~+ I)Re '" rtl + ~RG
0 Vp VG - VT '2
Fig. 25 Common-Gate Amplifier
Analysis: Let voltage at x along the channel be Vex).
S c ~- D

I[)= ( V
~cCg) Ve- VT - Vo/2) .
Vo=>ThlsIoversus

VI) is valid as long as Vc; - Vex) > V T . Note: L: Channel

length. At some gate voltage VC;I with Vex) = VI), the Depletion mode (;
channel is turned open and the flow of charges along the - When a positive bias is applied, more electrons are drawn
channel becomes constant, i.e. at Vo = VC;I - V T , (~ : Amplitication factor)
into the channel causing more carrier population, i.e.

I
~cCg
=-'-----"'O_L-_ __
VC;-VT
)2 channel conductance is increased. Hence, more current
would now; or, an increase in +Ve would increase
S
t+ +
i······
I
.o

ds 2 [0 => enhancement mode operation. V-I character­

_u_1I)_I => - C _V_o istics indicate that circuit operations of diffused-channel i
G O---'--t:::::::i=~---<:; c
uVe v gm -~. g L2 MOSFET are similar to thosc of JFET.
1>
Note: For CG configuration, the output resistance is
~ Transconductance of the MOSFET
very large and can be considered as infinite; the input
I ~cCg( )2 Vo resistance is relatively low. Voltage gain is dependent on
Il)s=Illv =V - v = - - VC;-VT =gm­
1> G T 20 2 R L , and its maximum value is about~. CG configuration
in FET is the counterpart orCB configuration in BJTs.
V-I CHARACTERISTICS OF

ENHANCEMENT-TYPE MOSFET

Fig. 20 COMMON-SOURCE AMPLIFIER

, VGs= V T Normal symbolic representations of the JFETs and the
Ohmic Saturation
A common-source (CS) FET amplilier (with the dc
Region Region MOSFETs are shown in Fig. 22. biasing circuitry) and its small signal equivalent circuit
VG

\ Fig. 22
N-channel
JFET
P-channel
JFET
NMOS
FET
D
PMOS
FET
D
are shown in Fig. 26.

Fig. 26 , - _ , -+" VI) D +

. ,.- .+--o

G~ G~ J J
V DS
NMOS output
characteristics
Go19 Go19
-Ohmic Region (Triode Region)
S D s S
Here VOS S; V GS - V T and the V -I characteristic is Fig. 23
10 = Kn'2(VGS - V'r)V IlS - V20s), where Approximate Low Frequency Equivalent Circuits

~/'oEox
W = ~.Cox (W) and II = surface
K =
n 2tL 2 L ....
ox
mobility of electrons: ~c = 800cm 2 I volt-sec (in Silo
Eo = permittivity of free space ( = 8.85 x 10 -14 F/cm)
Eox = dielectric constant of Si0 2 ('" 4);
tox = thickness of the oxide; Cox = EoEoxLW/tox
Co,: Capacitance of SiOz layer
Dividing locus between saturation and ohmic regions is
given by substituting Vos = (Ves - V T):
_ ' 2 _ ~cCoxW
10 - Kn V os - - - - V os'
2
2L
This locus is shown by the dotted line in Fig. 20.
-SATURATION REGION: Here, VI)S ;?: Ves - V T ,
and the current II) is approximately constant as shown
in Fig. 20. The transfer characteristic is obtained by
replacing Vos by Ves - V T ; 10 = Kn (Ves - V T)2. A
plot of the transfer characteristic is shown in Fig. 20.
-CUTOFF REGION: Here, Vc;s < V T, and thus 10
= O. The device is OFF in this region and is used in
switching applications in this mode.
DIFFUSED-CHANNEL
(DEPLETION-TYPE) MOSFET
-Diffused-channel MOSFET can be operated both as
depletion mode or as enhancement mode device.
-The device has a thin N-type layer of the same
conductivity as source or drain and is diffused
below the gate.
- When the gate has a small negative bias, the resulting
positive charges in this diffused region cause the depletion
layer (channel conductance) to be reduced. Thus, negative
bias on gate enables depletion mode operation.
1, {,~l
1,
JFET
s~s
MOSFET
Fig. 24
High Frequency Equivalent Circuit of a JFET
G COMMON-DRAIN AMPLIFIER
t
~' c" Cd:t+
g",v,
f ds
A common-drain (CD) FET amplifier (with the bi asing
circuitry) and its small-signal equivalent circuit are
shown in Fig. 27.
Current in an FET is carried by majority carriers
drifting under the influence of an electric field, whereas
in the bipolar transistor, current is transported by means
of diffusing minority carriers. Since drift velocities in
semiconductors are usually very much higher than
diffusion velocities, carrier transit times are much
shorter in FETs than in bipolar transistors. For this
reason, one might expect FETs to have a much more
extended high-frequency range than bipolar devices.
A limitation to the high-frequency performance or the Ro=
switching speed of a FET is the gate-channel capacitance,
which must be charged via the channel resistance. The _VO ~RL _ g mRL
resulting time constant determines the upper limit of the Av=
(I+~)RL +rd l+gmR L
frequency response. The gain x bandwidth product, which
can be derived from the equivalent circuit and equals For gmRL » I, the voltage gain is close to unity.
gm/21tCg, is normally taken as afigure ofmerit to indicate The CD configuration is thererore called the source
the high-frequency response of a particular device. follower (SF), since the source voltage follows the
g V-V input gate signal. The CS conl1guration in FET is the
-.!!!..=Il ~; C g: Total gate capacitance
Cg e L2 counterpart of the CC configuration in 8.IT.

3
 COMPARISON OF FET AMPLIFIERS
CG CS CD(SF)*
N-CHANNEL JFET N-CHANNEL ENHANCEMENT MOSFET
~ Fig 28 Fig 31
Rin

RO
XIII
rd
~m
Z Common-Source
Amplifier
Parameters Common-Source Parameters Vo g mRI.

[JI
V'I - Amplifier V, + A\, = Vin gmRL - gmRL gm Ra. + I
c=o
W ID V,,'"
K in;\;,
. ~?
VDD
Olher N-~~l~~~el *SF=Sourcc Follower
~ Yin RD ,t :!: YV A +
Parameters DepIction
MOSFET
IVy:, .="-------t--1 H>--_-oV"lLt
OP-AMPS REVISITED
o Is i V OD

Vos
'II
+
I" Symbol -INSTRUMENTATION AMPLIFIER - a high-perfor­

~
JO mance differential amplifier with high-input impedance.
V;II = VGS - IsRs G o----j .. <>8
- Vo = - (R4/ R3) (\ + R 2/R I) (VI - V 2)
Vllut = -VU - II)RU = Vns - IsRs
Symbol V;n = V GS (a) '1s -Input impedance presented at both inputs tends to be
Vout = Vou -loRD = Vos
G o----j ~
o
tl(V l _-_
A = __O_"t_= R O_
infinity.
G O-
A = tl(Vou,l =-g R
, i1(V l R +~
S gm

v ~(Vin) - m I)
(b) S -Output impedance of the differential amplifier tends
In to be zero.
-Application: To amplify ditferential signal(s) from
- On-Slate: VGS> VT (a) Conventional
- Satration Region: Vus ~ VGS - VT tran sducers / sensors.
(b) When substratelbody " 8 "
- RI can be adjusted to achieve null-offset.
io = K(vGS - VT)2(1 + AVoS) connected to source

-Triode Region: Vns ~ VGS - VT Note: Different states and regions of operation: Fig 34 Common Source Amplifier

,...... -----------------_._-----------.
iu = K[2(vGS - VT)vos - v2nsl
- VA: A FET Parameter

=> Same as for N-channel JFET

i Differential Amplifier i
: 1

P-CHANNEL DEPLETION MOSFET

P-CHANNEL JFET
Fig 29 Fig 32
Common-Source Parameters
Common-Source Parameters Amplifier
Amplifier V, +
~pC,,~ W
K - 2-L-

Symbol
'0 JS L=O
Vns
Go---,l'--0 8
j.1p: Hole mobility (a) D
V;n = V GS
Go--I ~

Symbol Vou' = -VI)O - InRo = Vos

(b) 0
A = tl(Voutl =-g R
v i1(V;nl - m I)
-AC-COUPLED NON-INVERTING AMPLIFIE R:
(a) Conventional -Capacitivcly coupling an OP-AMP reduces the
(b) When substratelbody " 8" dc offset considerably.
-On-State: VGS ~ VT
connected to source - Provision of R3 is mandated to facilitate continuous
-Satration Region: VOS ~ VGS - VT
Note: Different states and regions of operation: dc path for each of the input terminals.
io = K(VGS - VT)2(l + AVos)
=> Same as for P-channel JFET
-Triode Region : Vos ~ VGS - VT Fig. 35

iu = K/2(vGs- VT)VOS - V2os/

C,
P-CHANNEL ENHANCEMENT MOSFET
>-+--o VQ
N-CHANNEL DEPLETION MOSFET Fig. 33

Fig 30 Common-Source Parameters

Amplifier VT ­
Common-Source Parameters -v DU
Amplifier As for - A SUMMARY ON OP-AMPS

V,
P-Channel
Other -OP-AMPS in practical circuits o ffer performance
Iln Co~ W RD Parameters Dep iction
V OUl
K 2L r='-----H ~_--ov OUI MOSFET matching theoretical estimations.
As for -An OP-AMP consists of:
Others N-C hanncl
JFET Symbol (a) An inverting input terminal;
(b) A non-inverting input terminal;
Symbol
JS (e) An output terminal;
G ~' -oB
V;n = VGS
(a) 10 (d) Two power supply terminals + and -, with a
~
o
Yin = VGS Go---J _ ~B
Vout = VOl) - InRI) = VOS common circuit ground.
Vout = - Vno - loRo = VOS .J'S -Ideally, an OP-AMP responds to the two inputs
~O
(a) S
A = tl(Voutl = -g R A = i1(Vout l "'-g R (+v;nd and (-V;n2) to yield an output V" = A(v;n l
~
o (b)
v tl(V;nl - m 0 G<>-l v ~(Vin) - m 0
- V;n2) ; A is known as open-loop gain, which is very
(b) S
large (Ideally A ~ ~; in practice, A - 104 to 10 6 ) .
(a) Conventional
~ (a) Conventional - An ideal OP-AMP has an infinite input impedance (at
(b) When substratelbody "B"
~ (b) When substrate/body " 8 " both input terminals) and a zero output impedance.
connected to source
connected to source - With a negative feedback, the closed-loop gains are :
Note: Different states and regions of operation:

Z Note: Different states and regions of operation: => Same as for P-channel JFET - For inverting input, V,,IV;III = R2/ RI

=> Same as for N-channel JFET - For non-inverting input, VJV;n2 = (I + R 2/R I)
W
------------------~
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