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A Practical Implementation of Silicon Microchannel Coolers for High Power

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218 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 30, NO. 2, JUNE 2007
A Practical Implementation of Silicon Microchannel
Coolers for High Power Chips
Evan G. Colgan, Senior Member, IEEE, Bruce Furman, Michael Gaynes, Willian S. Graham, Nancy C. LaBianca,
John H. Magerlein, Senior Member, IEEE, Robert J. Polastre, Mary Beth Rothwell, R. J. Bezama, Member, IEEE,
Rehan Choudhary, Kenneth C. Marston, Hilton Toy, Jamil Wakil, Jeffrey A. Zitz, and Roger R. Schmidt
Abstract—This paper describes a practical implementation of
a single-phase Si microchannel cooler designed for cooling very
high power chips such as microprocessors. Through the use of
multiple heat exchanger zones and optimized cooler fin designs, a
unit thermal resistance 10.5 C-mm2 W from the cooler surface
to the inlet water was demonstrated with a fluid pressure drop of
35 kPa. Further, cooling of a thermal test chip with a micro-
channel cooler bonded to it packaged in a single chip module
was also demonstrated for a chip power density greater than
300 W/cm2 . Coolers of this design should be able to cool chips
with average power densities of 400 W/cm2 or more.
Index Terms—High power density, liquid cooling, microchannel
cooling.
I. INTRODUCTION
M ORE than 20 years ago, Tuckerman and Pease first de-
scribed the use of microchannel cooling for very high
power densities [1]. They demonstrated cooling of 790 W/cm
with a temperature increase of 71 C for a flow rate of 0.52 lpm
with a pressure drop of 214 kPa where the 0.3-mm deep chan-
nels were fabricated on the opposite side of an 0.4-mm thick
wafer from a 1 cm 1 cm thin film resistor. However, the
coolers could not be fabricated easily and pressure drops were
very high. As chip power densities are now increasing beyond
air cooling limits, it is necessary to address a number of practical
issues for implementing microchannel cooling. Recent progress
in high-rate reactive ion etching (DRIE) of Si [2] has greatly
simplified the fabrication of microchannel coolers from silicon.
Also a number of methods of reducing the pressure drop have
been reported including subdividing the flow into multiple heat
exchanger zones with shorter channel lengths [3] and mani-
fold designs with large cross-sectional area (i.e., equal, or larger
than, the channel cross-sectional area) [4]. In addition, staggered
fins in microchannel coolers have been found to increase the
heat transfer coefficient compared to continuous fins [5]. This
Manuscript received July 18, 2005; revised November 22, 2005. This work
was recommended for publication by Associate Editor J. Parry upon evaluation
of the reviewers comments.
E. G. Colgan, B. Furman, M. Gaynes, W. S. Graham, N. C. LaBianca,
J. H. Magerlein, R. J. Polastre, and M. B. Rothwell are with the IBM
T. J. Watson Research Center, Yorktown Heights, NY 10598 USA (e-mail:
ecolgan@us.ibm.com).
R. J. Bezama, K. C. Marston, H. Toy, J. Wakil, and J. A. Zitz are with IBM
East Fishkill, Hopewell Junction, NY 12533 USA.
R. Choudhary is with the Business Performance Services Team, IBM Corpo-
rate Headquarters, Somers, NY 10589 USA.
R. R. Schmidt is with IBM, Poughkeepsie, NY 12601 USA.
Digital Object Identifier 10.1109/TCAPT.2007.897977
1521-3331/$25.00 © 2007 IEEE
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is one of a number of thermal enhancement techniques which
have been proposed for microchannel coolers [6].
To use microchannel coolers in an application such as a server
rack, it is desirable to have the pressure drop in the microchan-
nels be 35 kPa ( 5 psi). This number is based on the pressure
available from compact and reliable pumps reduced by the pres-
sure drops in other system components such as heat exchangers,
connectors, filters, and distribution piping. It is also necessary to
minimize the flow through the microchannel cooler. If water is
used as the coolant, corrosion inhibiters, biocide/algaecide etc,
are required in addition to appropriate filtration.
For a practical implementation of microchannel cooling, it is
critical that the cooler be easy to integrate with the chip pack-
aging. High performance chips are typically mounted active side
down on a first-level package substrate using an area array of
solder balls. The assembly is subsequently attached to a printed
circuit board or second level package by a solder ball grid array
(BGA). With chips mounted active side down, the back sides of
the chips are available for the cooling solution. Given the cost
of high-performance processor chips, it is not practical to form
the microchannels directly on the back surface of the chip. In-
stead, a separate microchannel cooler is bonded to the back of
the chip with materials having as low a thermal resistance as
possible. If the microchannel cooler is fabricated from silicon, a
rigid bonding means such as silver-filled epoxy or solder can be
used. If a copper microchannel cooler were used [7], accommo-
dating the different thermal expansion coefficients of Si and Cu
would require a compliant thermal interface material, possibly
limiting the thermal performance.
This paper first describes the design, fabrication, and testing
of individual Si microchannel coolers and presents measure-
ment results for coolers with both staggered and continuous
fins. A practical integration method for packaging microchannel
coolers into single chip modules (SCMs) is then described along
with measurement results for these packaged coolers.
II. MICROCHANNEL DESIGN, FABRICATION, AND TESTING
The design and assembly of the silicon microchannel coolers
can be understood with reference to Figs. 1–3. The cooler con-
sists of a manifold chip shown in Fig. 1(a) and a channel chip
shown in Fig. 1(b) bonded together. Each chip is 20 20 mm in
size and there is a 0.7-mm wide seal region around the perimeter
with no microchannels. Magnified images of the two chips are
shown in Fig. 2. Fig. 2(a) shows the side of the manifold chip
which faces the channel chip, while Fig. 1(a) shows the other
side. The view in Fig. 2(a) shows distribution channels which
are etched 0.25 mm deep into the Si to help redistribute the
COLGAN et al.: PRACTICAL IMPLEMENTATION OF SILICON MICROCHANNEL COOLERS
Fig. 1. Image of manifold chip from (a) gasket side and (b) channel chip.
2
Each is 20 mm 20 mm in size. The etched microchannels in (b), which are
not visible in the photograph, run vertically.
Fig. 2. Magnified images of manifold chip from (a) side facing the channels
and (b) channel chip.
Fig. 3. 3-D rendering of assembled microchannel cooler.
flow from or to the fluid vias. As shown in Fig. 2(b), the mi-
crochannel fin segments are removed from the regions under the
fluid vias and the manifold redistribution channels to aid further
in the redistribution of the flow at the fluid vias.
A 3-D rendering of the assembled microchannel cooler is
shown in Fig. 3, where the manifold chip is on top and shown
semi-transparent. In operation, alternate lines of fluid vias are
used as inlets and outlets (see Fig. 1), so the microchannel cooler
is divided into six parallel-fed heat exchanger zones and the flow
length between the inlets and outlets is 3 mm. The fluid vias in
the manifold chip were formed as zigzagged arrays of circular
openings instead of elongated slots to reduce the likelihood of
the manifold chips breaking during fabrication and assembly.
The microchannel coolers described in Section III were fab-
ricated on 200-mm wafers 0.725-mm thick using photolithog-
raphy and deep Si reactive ion etching. For the channel chips,
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219
Fig. 4. Heater and sensor resistor pattern for (a) thermal testing and (b) mi-
crochannel thermal test station.
the channels were about 180 m deep and the regions which
aligned to the fluid vias were about 230 m deep. Several dif-
ferent staggered fin configurations were fabricated. The pitch
was kept constant at 100 m, but the channel width was ei-
ther 65 or 75 m, referred to as “narrow” or “wide.” The
fin length was either 210 or 250 m where there was a 40 m
gap between rows of fins when the length was 210 m. The
sharpness of the ends of the fins was also varied. The image in
Fig. 2(b) is from a sample with a 65 m channel, no gap between
the rows of fins, and a blunt end. For the manifold chips, the
fluid vias were formed first and etched to a depth of 0.5 mm;
the manifold channels were than etched on the opposite side of
the wafer to a depth of 0.25 mm. The manifold and channel
chips were joined together using a very thin (5–15 m) adhesive
layer applied to the manifold chip.
For thermal testing of these microchannel coolers, a heater
and a temperature sensor resistor shown in Fig. 4(a) were
formed by etching a 0.5–1.5 m thick copper film on a thin
insulator layer on the back surface of the channel chip. The
two large pads in the upper corners were used for powering
the heater resistor and the two small pads in the lower corners
were used for connecting to the sensor resistor. The heater
resistor was designed to cover as much of the 20 20 mm
channel chip area as possible. The sensor resistor was located
within the 0.2-mm wide gaps between the serpentines of the
heater resistor, which were open towards the bottom edge of
the chip. The sensor resistor was 22-mm long and 15 m
wide. The samples were measured using the test station shown
in Fig. 4(b), where the water flow could be varied while mea-
suring the differential pressure across the microchannel cooler,
the inlet and outlet water temperatures, the sensor resistor
value, and the power applied to the heater resistor. The sensor
resistor was calibrated by varying the water temperature while
measuring the sensor resistor value.
III. MICROCHANNEL COOLER RESULTS AND DISCUSSION
Fig. 5 shows test results for a microchannel cooler with 250
25 m staggered blunt fins and 75 m wide 195 m deep
channels for various flow conditions with more than 1.1 kW
applied to the heater resistor (275 W/cm ). The power (line
without symbols and right axis) was turned off while stabilizing
different flow conditions. The temperature difference between
the average chip temperature measured by the sensor resistor
and the inlet water is plotted with square symbols and the water
temperature rise between outlet and inlet is plotted with cir-
cular symbols and indicated on the left axis. Note that there will
220
2
Fig. 5. Microchannel cooler with staggered 250 25 m fins and 75-m wide,
195-m deep channels for various flows and >1.1-kW power.
Fig. 6. Friction coefficient for microchannels with different fin geometry.
be a systematic variation in the chip temperature between the
inlet and outlet regions, so the maximum chip temperature will
be approximately equal to the average chip temperature plus
half of the total increase in the fluid temperature, or
2. In an actual application, it is desirable
to align the microchannel inlet regions with the highest power
density regions on the chip to minimize the maximum junction
temperature. The differential pressure, flow, and unit thermal re-
sistance values are indicated on Fig. 5. As expected, the tem-
perature differences, and unit thermal resistances, decreased as
the flow rate was increased. Note that the flow rate was not in-
creased, or decreased, monotonically. The unit thermal resis-
tance values (C-mm W) were calculated as
where the chip area was the full area of the 20 20 mm
chip, not just the active area of the microchannels. Note that
this is an average value and the 0.5-mm thick silicon sub-
strate of the channel chip contributes 4 C-mm /W to the
measured unit thermal resistance. This compares favorable to
the 9.0 C-mm W thermal resistance reported in the work of
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IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 30, NO. 2, JUNE 2007
Fig. 7. Nusselt number for microchannels with different fin geometry.
Tuckerman and Pease [1] where the silicon substrate below
the channels was only 0.1-mm thick and the pressure drop was
much higher. Thermal conduction of the complete structure
was simulated numerically using a commercially available
CFD code and found that a unit resistance of 10.5 C-mm W
corresponds to an average heat transfer coefficient for the
microchannels of 130 000 W/m -C and 12.0 C-mm W corre-
sponds to 105 000 W/m -C.
Figs. 6 and 7 show flow and thermal performance for a va-
riety of microchannel configurations as indicated by the symbol
type. Blunt and sharp ended fin results were similar and are not
distinguished. The number of samples of each type is also indi-
cated. The channel chips were all from three wafers with similar
etch depths in the regions which aligned to the fluid vias.
To display all the flow results on the single graph shown in
Fig. 6, the differential pressure was converted into an apparent
friction factor, -app, using an effective wetted fin length ,
fluid density , channel average fluid velocity , and channel
hydraulic diameter using the expression
(2)
where the effective fin length of a continuous channel was set
equal to the 3000- m nominal channel length, . Since the av-
erage hydraulic diameter for the channels is about 100 m and
the Reynolds number ranges between 26 and 282, the flow in
a continuous channel is expected to become fully developed
after Re/20 diameters [8], or within the first 1000 m along the
channel. However, the flow with the staggered fins cannot be
fully developed because of the significantly shorter length (210
or 250 m). Therefore, the pressure drop data analysis is done
using the channel dimensionless hydrodynamic entry-length
(1) as a metric of the fluid flow characteristics for a given
channel flow and geometry where is the nominal channel
length. The value of (f-app ) for a fully developed flow in a
rectangular channel with aspect ratio (height/width) of 3 is ap-
proximately 17, and increases to 24 for very large aspect ratios
[8]. Fig. 6 shows the pressure data collected for both continuous
and staggered fins, and the data analysis suggests an asymp-
totic value for (f-app ) of 32. This somewhat higher than
COLGAN et al.: PRACTICAL IMPLEMENTATION OF SILICON MICROCHANNEL COOLERS
expected value is probably due to the fact that the experimen-
tally measured differential pressure values include contributions
from both the microchannels and the inlet and outlet manifolds.
Thus the contribution of the microchannels alone cannot easily
be determined.
Since the thermal data was collected using water (Prandtl
number, 7), we do not expect fully developed thermal pro-
files in any of the samples since fully developed thermal profiles
require approximately /20 diameters of channel length
[8]. The calculated average convective heat transfer coefficient
(based on the effective fin length, ) was used to calcu-
late an average Nusselt number using the channel hydraulic di-
ameter . Similar to the pressure drop evaluation above, the
thermal data analysis was done using a dimensionless thermal
entry-length as a metric of a given experi-
mental test condition. For a channel with aspect ratio of 3 and
fully developed laminar flow, the Nusselt number is expected to
asymptotically approach 4. The expected value is 9 for
80.
The experimental thermal data in Fig. 7 shows a higher
average Nusselt number than expected from laminar flow
theory [8]. This deviation is expected because the microchannel
entrance hydrodynamics does not correspond directly to the as-
sumptions used to develop the theoretical values. Furthermore,
3-D computational fluid dynamics simulations of a typical
microchannel geometry assuming laminar flow conditions
support a higher heat transfer coefficient than expected from
theory. Since the theory for turbulent heat convection inside
a tube and laminar heat convection over an external surface
supports a direct relationship between the Stanton number
and the friction coefficient f-app, usually in
the form
(3)
a plot of versus f-app should result in a linear relationship.
Fig. 8 shows that the data departs somewhat from the expected
linear relationship. The model proportionality constant of
0.08 is lower, as expected, than the value predicted from (3)
for 7, mainly because the pressure data includes both
microchannel and flow manifolds effects as stated above. The
systematic deviation from linearity at higher friction factor
values can be attributed to the expected different dependency
of pressure drop and water velocity in these two flow zones,
where a quadratic dependency is expected only in the inlet and
outlet manifolds while the channel section will show a variable
dependency between linear and quadratic depending on the
channel Reynolds number and channel length.
The thermal data also shows that continuous and staggered
fins with different channel width and fin geometry will follow
the given semi-empirical relationship with a deviation below
7% (see Fig. 7). Within the range studied, the Nusselt number
follows a square root dependency on the Reynolds number,
hence providing higher heat transfer with increasing fluid
velocity or decreasing microchannel hydraulic diameter. For
samples with equivalent geometries, the presence of the 40 m
gap (i.e., shorter ) between rows of staggered fins was found
to reduce the thermal performance for both the narrow and wide
channel cases. Note that in this section, there are no samples
which allow a direct comparison of continuous and staggered
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221
Fig. 8. Stanton number and friction coefficient relationship for microchannels
with different fin geometries.
fin with the same channel geometry. The next section provides
such direct comparisons and staggered fins provide improved
performance, mainly because the staggered fins effectively
reduce the thermal diffusion distance between the wall and the
flow centerline.
IV. SINGLE CHIP MODULE ASSEMBLY AND RESULTS
The microchannel coolers which were integrated into single
chip modules were very similar to those described above, but
were fabricated on 150-mm wafers 0.675-mm thick. The
manifold and channel chips were fusion bonded together rather
than joined with adhesive. Four cooler designs similar to those
described above were used. Both continuous and staggered
fins with a 75- m pitch and 45- m channel width as well
as a 100- m pitch and 60- m channel width were used. The
channel depths were about 254 m and 262 m for the two
pitches. For the staggered fins, there was no gap between rows
of fins.
A test station similar to that described above for individual
microchannel coolers was used for testing the single chip mod-
ules. The differential pressure measurements were not corrected
for the 4 kPa pressure drop measured in the test station when
the SCM was replaced with a short hose segment. The thermal
test chip in the SCM was 18.5 18.6 mm in size and the pow-
ered area was 3 cm . The uncertainty in the measured thermal
performance is 5%, due mainly to the uncertainty in the sensor
calibration and the small amount of heat which does not flow
through the microchannel cooler.
When packaging a chip with a microchannel cooler in a
practical module configuration, there are many constraints
which must be considered. Since a first level package may
contain more than one chip and frequently contains passive
components such as capacitors around the chip, the external
fluid manifold for the microchannel cooler must not interfere
with such passive components. The fluid connection should
provide mechanical decoupling between the cooler and the
fluid inlet/outlet manifold to prevent excessive stress on the
solder balls which attach the chip to the package substrate. For
a normal BGA assembly processes, the microchannel cooler
and associated manifold should be compatible with a eutectic
( 225 C) or Pb-free ( 245–260 C) reflow and the total
222 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 30, NO. 2, JUNE 2007
Fig. 9. Schematic cross-section of microchannel cooler integrated in a single
chip module.
Fig. 10. Components for assembly of microchannel SCM.
weight low enough to enable self alignment during reflow. We
have designed a microchannel cooled SCM assembly shown in
Fig. 9 to meet these requirements.
The components used in a microchannel cooled SCM are
shown in Fig. 10. A two piece manifold block, Fig. 10(a)–(c),
which was molded from a high-temperature plastic, transformed
a single inlet and outlet into alternating inlet and outlet zones.
A 18.5 18.6 mm thermal test chip was mounted with solder
balls onto a ceramic module and underfilled, Fig. 10(d). The mi-
crochannel cooler, Fig. 10(e), was bonded to the thermal chip
using a Ag epoxy or In solder. A flexible gasket, Fig. 10(e), was
placed between the microchannel cooler and the manifold block.
The bottom perimeter of the manifold block was bonded to the
ceramic package. A completed microchannel SCM is shown in
Fig. 10(f).
Fig. 11 shows results for a microchannel SCM with 30 m
fins and 45 m channels for various flow conditions when more
than 900 W was applied to the heater resistors. The powered
area was 3 cm , so the power density was 300 W/cm . The
power (line without symbols and right hand axis) was turned
off while stabilizing different flow conditions. The temperature
difference between the chip (determined from the average of
the two chip center sensors) and the inlet water is plotted with
square symbols and between the outlet and inlet water is plotted
with circular symbols and indicated on the left axis. For the con-
ditions used, the increase in the water temperature was around
10 C, so there is no possibility of boiling, even at substantially
higher power levels. The thermal conduction in the test mod-
ules was simulated numerically using a commercially available
CFD code to relate the measured thermal resistance ( C/W) to
the unit thermal resistance (C-mm W) indicated on Fig. 11.
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Fig. 11. Microchannel SCM with 30-m fins and 45-m channels for various
flows and >0.9-kW power.
Fig. 12. Thermal resistance for a large group of SCM microchannel coolers
with four different microchannel designs at a water flow rate of 1.25 lpm.
Note that the unit thermal resistance values in Fig. 11 are larger
than those in Fig. 5 because the measurement includes a thermal
chip (0.725-mm thick) and the Ag epoxy layer used to join the
microchannel cooler to the chip.
The results for a number of microchannel SCMs with the four
different microchannel configurations are shown in Fig. 12. The
total unit thermal resistance includes the thermal chip, the Ag
epoxy, and the microchannel cooler. The unit thermal resistance
is indicated by the squares and the left axis and the differential
pressure by the circles and the right axis. These measurements
were made with four inlets and three outlets where the chip
center sensors were closer to the fluid inlet than to the outlet.
With a flow of 1.25 lpm, reversing the flow direction causes
the measured thermal resistance to increase by 3%. Therefore,
the average thermal resistance, (i.e., midway between the inlet
and outlet) is about 1.5% larger than the values plotted. The mi-
crochannel cooler was bonded to the back side of the thermal
chip using an Ag epoxy. All the SCMs, except for three which
are indicated by “X” on the plots, used the same material. Use of
an alternate Ag epoxy reduced the total unit thermal resistance
by about 1.6 C-mm W. From the above measurements, it is
not possible to determine the contribution from the individual
components to the total unit thermal resistance.
The results of 3-D computational fluid dynamic simulations
for the 100 m pitch staggered (a,b) and continuous (c,d) mi-
crochannels with 60 m channels 260 m deep are shown in
COLGAN et al.: PRACTICAL IMPLEMENTATION OF SILICON MICROCHANNEL COOLERS
Fig. 13. Calculated temperature and velocity for 100-m pitch staggered and
continuous fins with 1.0 lpm flow.
Fig. 13. The calculated temperature profiles Fig. 13(a), (c) and
velocity profiles, Fig. 13(b), (d) shown are for a plane midway
between the top and bottom of the channels. The lowest temper-
ature is 22 C (black) and the maximum is 37 C (white), and
the maximum velocity is 1.7 m/s (white). Note that the contin-
uous fin is hotter than the staggered fins at equivalent distances
along the channel, indicating the improved heat transfer with the
staggered fins, Fig. 13(a), (c). The apparent heat transfer coef-
ficient, , midway between the inlet and outlet, with a flow
of 1.25 lpm, was calculated to be 150 000 W/m -K for 100- m
pitch continuous fins and 190 000 W/m -K for 100- m pitch
staggered fins as described above. From these value and the
thickness of the thermal chip (0.725 mm, 5.6 C-mm /W) and
the microchannel cooler base (0.425 mm, 3.3 C-mm /W), the
unit thermal resistance of the Ag epoxy used can be estimated
as 7.5 C-mm W. The thermal resistance of the alternate Ag
epoxy is about 5.9 C-mm W.
For the 75- m pitch staggered fin results shown in Fig. 12,
the average total unit resistance was 20.7 C-mm W. If we
assume that the Ag epoxy unit thermal resistance is about
7.5 C-mm W, and allowing for the thermal resistance of
the chip and the microchannel cooler base, then the average
apparent heat transfer coefficient is about 210 000 W/m -K.
Fig. 14 shows graphically the approximate contributions
of the various components to the total unit thermal resis-
tance which was measured for the 75 m pitch staggered fins
(Fig. 12). The total thermal resistance can be further reduced
to permit operation at higher power densities by using the
alternate Ag epoxy (reduction of 1.6 C-mm /W), by thin-
ning the chip from 725 m to 400 m and the base of the
microchannel cooler from 425 m to 250 m (additional re-
duction of 3.8 C-mm /W), and by using a thin In solder bond
instead of Ag epoxy (additional reduction of 3.4 C-mm /W).
We have found that such an In solder joint between two silicon
chips has a unit resistance of about 2.5 C-mm W.
The maximum power density which can be cooled with this
technology may be estimated from the values in Fig. 14 by as-
suming a of 63 C, i.e., 22 C and 85 C,
and increasing the values by 1.5% so they correspond to the unit
thermal resistance from the inlet water to a point midway be-
tween the inlet and outlet manifolds. A total unit resistance of
21.0 C-mm W would correspond to 300 W/cm , as demon-
strated in Fig. 11. For the thin Si case with the alternate Ag
epoxy, having a thermal resistance of 15.7 C-mm W, a power
density of 400 W/cm could be cooled midway between the inlet
and outlet. As an approximation, for a 2 2 cm chip with a flow
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223
Fig. 14. Estimated thermal resistance with 75-m pitch staggered fins and ex-
tensions to higher powers.
of 1.25 lpm, would be about 19 C at 400 W/cm , so
in the regions aligned to the inlet and outlet, power densities of
460 W/cm and 340 W/cm , respectively, could be cooled
while maintaining 85 C. The temperature gradient be-
tween the inlet and outlet can be reduced by increasing the flow,
but if there is a chip hot spot which is smaller in one direction
than the channel length, the increased cooling capacity near the
inlet can be taken advantage of by aligning the microchannel
inlet regions to the chip hot spot. This approach might be ex-
tended to even higher power densities by using a solder layer to
join the microchannel cooler to the chip and by using finer pitch
staggered fins.
V. CONCLUSION
A practical implementation of a single-phase silicon mi-
crochannel cooler bonded to a high power chip and extendable
to power densities of 400 W/cm or more has been described,
and cooling of 300 W/cm in an SCM demonstrated. A 2
2 cm microchannel cooler with a resistive heater on the back of
the channel chip with six heat exchanger zones demonstrated
a thermal resistance of 10.5 C-mm W with a reasonable flow
rate and a pressure drop in the microchannel cooler of 35 kPa.
The performance of 75- or 100- m pitch silicon microchannel
coolers with staggered fins was shown to be superior to con-
tinuous fin designs with equivalent geometries. This work has
shown that a silicon microchannel cooler can be integrated with
a single chip module in a simple and practical manner while
providing excellent thermal performance at very high power
levels.
ACKNOWLEDGMENT
The authors wish to thank: B. Kane, W. Lam, D. Lisounenko,
K. McCollough, R. Meyer, J. Newbury, A. Niera, R. Nunes,
R. Owen, D. Patsy, D. Posillico, C. Scerbo, M. Steen, C. Tsang,
J. Vichiconti, and B. White, IBM Yorktown Microelectronics
Research Laboratory, for fabrication of the silicon wafers;
S. Bradley and F. Pompeo, for chip joining; and B. Humphrey,
RC Molding, and L. Mabbott, Micralyne, for technical support
in the fabrication of the plastic manifold blocks and the fusion
bonded microchannel coolers.
224 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 30, NO. 2, JUNE 2007
REFERENCES
[1] D. B. Tuckerman and R. F. W. Pease, “High performance heat sink for
VLSI,” IEEE Electron Dev. Lett., vol. EDL-2, no. 5, pp. 126–129, May
1981.
[2] F. Laermer and A. Urban, “Challenges, developments and applications
of silicon deep reactive ion etching,” Microelectron. Eng., vol. 67–68,
pp. 349–55, 2003.
[3] G. M. Harpole and J. E. Eninger, “Micro-channel heat exchanger opti-
mization,” in Proc. 7th IEEE Semi-Therm Symp., 1991, pp. 59–63.
[4] R. L. Webb, “Effect of manifold design on flow distribution in parallel
micro-channels,” presented at the International Electronic Packaging
Technology Conference (IPACK’03), 2003, unpublished.
[5] T. Kishimoto and S. Sasaki, “Cooling characteristics of dia-
mond-shaped interrupted cooling fins for high power LSI devices,”
Electron. Lett., vol. 23, no. 9, pp. 456–457, 1987.
[6] M. E. Steinke and S. G. Kandlikar, “Single-phase heat transfer en-
hancement techniques in microchannel and minichannel flows,” in
Proc. 2nd Int. Conf. Microch. Minich., 2004, pp. 141–148.
[7] P. Prechtl and O. Kurtz, “Efficient liquid cooling technologies for
computer systems,” in Proc. Adv. Technol. Workshop Thermal Manag.
(IMAPS ATW) Conf., Palo Alto, CA, Oct. 25–27, 2004, [CD ROM].
[8] W. M. Kays, Convective Heat and Mass Transfer. New York: Mc-
Graw-Hill, 1966, ch. 6, 8, and 9.
Evan G. Colgan (M’87–SM’06) received the B.S.
degree in applied physics from the California Insti-
tute of Technology (Caltech), Pasadena, in 1982 and
the Ph.D. degree in materials science from Cornell
University, Ithaca, NY, in 1987.
He joined IBM, Hopewell Junction, NY, in 1987
and worked on silicides, selective CVD-W, diffusion
barriers, and both Cu- and Al-based chip wiring.
He transferred to IBM Research as a Research Staff
Member in 1995 to manage the TFT Processing
Department, and subsequently worked on a number
of display related projects. He joined the Packaging Area in 2001 to work on
optical packaging and is currently working on high performance liquid cooling.
He has 100 technical publications and 65 issued U.S. patents.
Dr. Colgan and is a member of APS and MRS.
Bruce Furman received the Ph.D. degree in chem-
istry from Cornell University, Ithaca, NY, in 1980.
He then joined Charles Evans and Associates
doing materials characterization of semiconductors.
In 1982, he joined IBM GTD (Technology Division),
Poughkeepsie, NY. In 1985, he moved to the Re-
search Division of IBM to work in thin film material
development for packaging applications. During his
20 plus years at IBM, he has worked on numerous
packaging and silicon programs. Currently, he is
working in an Optoelectronic and MEMs Packaging
Group. Projects include bonding applications for silicon, optoelectronic, and
MEMS fabrication and integration.
Michael Gaynes received the B.S. degree in chem-
ical engineering from Brigham Young University,
Provo, UT.
He joined IBM in 1979. He has held technical
leadership positions that cover a wide spectrum
of electronic packaging in manufacturing and
development. These include ceramic chip carrier
circuitization, failure analysis, reliability test and
model development, flip chip organic packaging
design and process development, adhesive develop-
ment, and adhesion science. From 1990 to 2003, he
directed materials and process development efforts for applications that require
thermally and electrically conductive adhesives, die attach adhesives, and flip
chip underfills. Since 2003, he has been with IBM Research, Yorktown Heights,
NY, where he is providing leadership in developing advanced adhesives and
adhesion improvements that are needed for next generation flip chip structures.
He is a Senior Engineer with 30 technical publications and 87 U.S. patents
issued.
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William S. Graham is a Staff Engineer at the
IBM Thomas J. Watson Research Center, Yorktown
Heights, NY. He joined IBM in 1982. Presently, he is
working on the development of FEOL RIE processes
for advanced CMOS technologies. Previously, he
had worked on thin-film transistor processing for flat
panel displays, mainframe packaging, contamination
control, and superconductor technology.
Nancy C. LaBianca is an Advisory Engineer in
the Applied Polymer Technology Group, Thomas
J. Watson Research Center, Yorktown Heights,
NY. She joined IBM in 1988, working to develop
gate metal processes for GaAs technology. Her
projects have included a broad range of lithographic
and packaging activities, including high-resolution
photosensitive polyimides for advanced multichip
modules, CGR negative resist, used in manufacturing
IBM logic chips, and thermal cooling strategies and
materials for advanced packaging. She is currently
involved in the application and development of wafer level underfill for flip
chip processing.
John H. Magerlein (M’93–SM’06) received the
B.A. degree in physics from Kalamazoo College,
Kalamazoo, MI, and the M.S. and Ph.D. degrees
in physics from the University of Michigan, Ann
Arbor, in 1973 and 1975, respectively.
He is a Research Staff Member and Manager
of the Chip Cooling and RF Passives Department,
IBM Thomas J. Watson Research Center, Yorktown
Heights, NY. He worked at Bell Laboratories
prior to joining IBM in 1977. While there he has
carried out research on experimental Josephson
junction circuits, GaAs MESFET processing, and electromagnetic modeling
of high-performance interconnects prior to assuming his current position in
2001. His present research interests include liquid cooling of high power chips,
RF MEMS devices, and electrical and optical packaging for high-performance
computer systems.
Dr. Magerlein is a member of the American Physical Society.
Robert J Polastre received the Associates degree
in electronic technology and the B.S. degree from
LaSalle University, Philadelphia, PA.
He is an Advisory Engineer working in the System
on A Package Group, IBM, Yorktown Heights, NY.
He joined the IBM Research Division in 1983. He
is the author or co-author of several papers on au-
tomated and thermal testing and is a co-inventor of
patents in these areas.
Mr. Polastre received Outstanding Technical
Achievement Awards in 1990 and 1999 and an IBM
Corporate Award in 1993 for his work on array testing of thin film transistors.
Mary Beth Rothwell received the B.S. degree in
chemistry from Pace University, Pleasantville, NY.
She joined the IBM Research Division, Yorktown
Heights, NY, in 1985. She first worked in an Electron-
Beam Lithography Group and then in 1991, joined
the TFT Processing Group. In 2001, she was an In-
tegration Engineer for the offline packaging facility.
She is currently an Advisory Integration Engineer for
the Microelectronics Research Laboratory (MRL) of
the Research Division.
COLGAN et al.: PRACTICAL IMPLEMENTATION OF SILICON MICROCHANNEL COOLERS
R. J. Bezama (M’01) received the B.S. degree in
chemical engineering from the University of Chile,
Santiago, in 1978 and the M.E. and Ph.D. degrees in
chemical engineering from University of Utah, Salt
Lake City, in 1980 and 1983, respectively.
In 1983, he joined IBM, East Fishkill, NY, as a
Staff Engineer to work on the development of glass
ceramic MLC products. At IBM, he specialized in
process simulation and optimization of production
tools for different development and manufacturing
sectors like ceramic processing, thin films pro-
cessing, C4 plating, and chip processing. He is currently a Distinguished
Engineer in the Package Development Group, Hopewell Junction, NY. He
holds 38 U.S. patents and has authored and co-authored 15 technical papers.
His current activities include SCM and MCM microelectronic packaging
research and development, research and development of high performance
cooling devices, and providing CFD modeling support to both development
and manufacturing engineering groups.
Dr. Bezama is a member of AIChE and Tau Beta Pi.
Rehan Choudhary received the B.S. degree in
chemical engineering and the B.A. degree in eco-
nomics from the University of Maryland at College
Park and is currently pursuing the MBA from the
State University of New York at New Paltz.
He has held positions as a Manufacturing Engineer
and a Technology Development Engineer at IBM
Systems and Technology Group, Hopewell Junction,
NY. He is currently part of the Business Perfor-
mance Services Team, IBM Corporate Headquarters,
Somers, NY. His present Assignment is focused on
Identifying and developing initiatives aimed at Strengthening IBM’s revenue
growth.
Kenneth C Marston received the B.E. degree in
mechanical engineering from the State University
of New York (SUNY), Stony Brook and the M.S.
degree in mechanical engineering (with a focus on
thermal sciences) from the University of Minnesota,
Minneapolis, in 1991.
He is an Advisory Engineer with IBM Micro-
electronics, East Fishkill, NY. He has been with
IBM since 1991 and has 15 years of experience
in product development and advanced module
manufacturing, including thermal/mechanical pack-
aging development for organic and ceramic packages; project management
for several high-end products manufactured in the IBM Poughkeepsie BAT
line; development of temperature control systems in module test and burn in
equipment; and manufacturing process responsibilities for temperature-related
stress, solder reflow operations, and encapsulation.
Hilton Toy received the B.S. degree in mechanical
engineering from the Polytechnic Institute of New
York, Brooklyn, NY.
He joined IBM in 1982 and is currently working
in Thermal and Mechanical Design Group, IBM,
East Fishkill, NY. Since 1990, he has been working
in product development on module encapsulation
and cooling solutions for electronic packaging. He
has co-authored several technical papers and holds
28 patents.
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225
Jamil Wakil received the B.S. degree in mechanical
engineering from Texas A&M University, College
Station, the B.S. degree in electrical engineering
from the University of Texas at Dallas, and the
M.S. degree in mechanical engineering from The
University of Texas at Austin.
He is currently working on package thermal devel-
opment for IBM microelectronics, focusing on first
level thermal enhancement for organic packages.
He has been with IBM for six years and has several
patents and publications.
Jeffrey A. Zitz received the B.S.M.E. and M.S.M.E.
degrees from Rensselaer Polytechnic Institute, Troy,
NY.
He is a Senior Packaging Engineer with IBM,
East Fishkill, NY. During his 20 years with IBM, he
has applied his diverse engineering expertise in the
areas of materials, mechanical, thermal, statistical
modeling, reliability, and manufacturing to IBM’s
ceramic and organic chip carriers, and computer
systems. He lead the development of both bare-die
flip-chip ceramic carriers and the direct lid attach
(DLA) package utilized by IBM and other flip-chip package manufacturers. His
innovations appear across IBM’s ASIC and PowerPC die product offerings, and
have been key drivers to higher package performance at lower cost. Recently,
he lead the first-level packaging of IBM i/p series POWER4 and POWER5
server generations, driving thermal, mechanical and cost performance to meet
product and market requirements.
Mr. Zitz is a Registered Professional Engineer in the State of New York.
Roger R. Schmidt has over 25 years experience
in engineering and engineering management in the
thermal design of IBM’s large scale computers. He
has led development teams in cooling mainframes,
client/servers, parallel processors and test equipment
utilizing such cooling mediums as air, water, and
refrigerants. He has published more than 75 technical
papers and holds 51 patents in the area of electronic
cooling. He is a member of ASME’s Heat Transfer
Division and an active member of the K-16 Elec-
tronic Cooling Committee. He has been an Associate
Editor of the Journal of Electronic Packaging and is now Associate Editor of
the ASHRAE Research Journal and the ASME Journal of Heat Transfer. He
has taught extensively over the past 20 years mechanical engineering courses
for prospective professional engineers and has given seminars on electronic
cooling at a number of universities.
Dr. Schmidt is a Fellow of the ASME and a member of the National Academy
of Engineering and the IBM Academy of Technology. He is Vice Chair of the
ASHRAE TC9.9 Committee on Mission Critical Facilities, Technology Spaces,
and Electronic Equipment.