Encoders

The combinational circuits that change the binary information into N output lines are
known as Encoders. The binary information is passed in the form of 2N input lines. The
output lines define the N-bit code for the binary information. In simple words,
the Encoder performs the reverse operation of the Decoder. At a time, only one input
line is activated for simplicity. The produced N-bit output code is equivalent to the
binary information.

There are various types of encoders which are as follows:

4 to 2 line Encoder:
In 4 to 2 line encoder, there are total of four inputs, i.e., Y0, Y1, Y2, and Y3, and two
outputs, i.e., A0 and A1. In 4-input lines, one input-line is set to true at a time to get the
respective binary code in the output side. Below are the block diagram and the truth
table of the 4 to 2 line encoder.

Block Diagram:
Truth Table:

The logical expression of the term A0 and A1 is as follows:

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A1=Y3+Y2
A0=Y3+Y1

Logical circuit of the above expressions is given below:

8 to 3 line Encoder:
The 8 to 3 line Encoder is also known as Octal to Binary Encoder. In 8 to 3 line
encoder, there is a total of eight inputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and three
outputs, i.e., A0, A1, and A2. In 8-input lines, one input-line is set to true at a time to
get the respective binary code in the output side. Below are the block diagram and the
truth table of the 8 to 3 line encoder.

Block Diagram:

Truth Table:

The logical expression of the term A0, A1, and A2 are as follows:

A2=Y4+Y5+Y6+Y7
A1=Y2+Y3+Y6+Y7
A0=Y7+Y5+Y3+Y1

Logical circuit of the above expressions is given below:

Decimal to BCD Encoder
The Octal to Binary Encoder is also known as 10 to 4 line Encoder. In 10 to 4 line
encoder, there are total of ten inputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, and Y9 and four
outputs, i.e., A0, A1, A2, and A3. In 10-input lines, one input-line is set to true at a time
to get the respective BCD code in the output side. The block diagram and the truth
table of the decimal to BCD encoder are given below.

Block Diagram:
Truth Table:

The logical expression of the term A0, A1, A2, and A3 is as follows:

A3 = Y9 + Y8
A2 = Y7 + Y6 + Y5 +Y4
A1 = Y7 + Y6 + Y3 +Y2
A0 = Y9 + Y7 +Y5 +Y3 + Y1

Logical circuit of the above expressions is given below:

Priority Encoder:
4 to 2 line Priority Encoder:
In this priority encoder, there are total of 4 inputs, i.e., Y0, Y1, Y2, and Y3, and two
outputs, i.e., A0 and A1. The Y3 has high and Y0 has low priority inputs. When more than
one input is '1' at the same time, the output will be the (binary) code corresponding
to the higher priority input. Below is the truth table of the 4 to 2 line priority encoder.

Truth Table:

The logical expression of the term A0 and A1 can be found using K-map as:
A1=Y3+Y2
A0=Y3+Y2'.Y1

Logical circuit of the above expressions is given below:

Uses of Encoders:
1. These systems are very easy to use in all digital systems.
2. Encoders are used to convert a decimal number into the binary number. The objective
is to perform a binary operation such as addition, subtraction, multiplication, etc.

Decoder
The combinational circuit that change the binary information into 2N output lines is
known as Decoders. The binary information is passed in the form of N input lines. The
output lines define the 2N-bit code for the binary information. In simple words,
the Decoder performs the reverse operation of the Encoder. At a time, only one input
line is activated for simplicity. The produced 2N-bit output code is equivalent to the
binary information.
There are various types of decoders which are as follows:

2 to 4 line decoder:
In the 2 to 4 line decoder, there is a total of three inputs, i.e., A0, and A1 and E and four
outputs, i.e., Y0, Y1, Y2, and Y3. For each combination of inputs, when the enable 'E' is
set to 1, one of these four outputs will be 1. The block diagram and the truth table of
the 2 to 4 line decoder are given below.

Block Diagram:

Truth Table:

The logical expression of the term Y0, Y0, Y2, and Y3 is as follows:

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Y3=E.A1.A0
Y2=E.A1.A0'
Y1=E.A1'.A0
Y0=E.A1'.A0'

Logical circuit of the above expressions is given below:

3 to 8 line decoder:
The 3 to 8 line decoder is also known as Binary to Octal Decoder. In a 3 to 8 line
decoder, there is a total of eight outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and three
outputs, i.e., A0, A1, and A2. This circuit has an enable input 'E'. Just like 2 to 4 line
decoder, when enable 'E' is set to 1, one of these four outputs will be 1. The block
diagram and the truth table of the 3 to 8 line encoder are given below.
Block Diagram:

Truth Table:

The logical expression of the term Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 is as follows:

Y0=A0'.A1'.A2'
Y1=A0.A1'.A2'
Y2=A0'.A1.A2'
Y3=A0.A1.A2'
Y4=A0'.A1'.A2
Y5=A0.A1'.A2
Y6=A0'.A1.A2
Y7=A0.A1.A2

Logical circuit of the above expressions is given below:

4 to 16 line Decoder
In the 4 to 16 line decoder, there is a total of 16 outputs, i.e., Y0, Y1, Y2,……, Y16 and four
inputs, i.e., A0, A1, A2, and A3. The 3 to 16 line decoder can be constructed using either
2 to 4 decoder or 3 to 8 decoder. There is the following formula used to find the
required number of lower-order decoders.

Required number of lower order decoders=m2/m1

m1 = 8
m2 = 16
Required number of 3 to 8 decoders= =2

Block Diagram:
Truth Table:

The logical expression of the term A0, A1, A2,…, A15 are as follows:

Y0=A0'.A1'.A2'.A3'
Y1=A0'.A1'.A2'.A3
Y2=A0'.A1'.A2.A3'
Y3=A0'.A1'.A2.A3
Y4=A0'.A1.A2'.A3'
Y5=A0'.A1.A2'.A3
Y6=A0'.A1.A2.A3'
Y7=A0'.A1.A2.A3
Y8=A0.A1'.A2'.A3'
Y9=A0.A1'.A2'.A3
Y10=A0.A1'.A2.A3'
Y11=A0.A1'.A2.A3
Y12=A0.A1.A2'.A3'
Y13=A0.A1.A2'.A3
Y14=A0.A1.A2.A3'
Y15=A0.A1.A2'.A3

Logical circuit of the above expressions is given below:

Half Adder
The Half-Adder is a basic building block of adding two numbers as two inputs and
produce out two outputs. The adder is used to perform OR operation of two single bit
binary numbers. The augent and addent bits are two input states, and 'carry'
and 'sum 'are two output states of the half adder.

Block diagram

Truth Table

In the above table,

1. 'A' and' B' are the input states, and 'sum' and 'carry' are the output states.
2. The carry output is 0 in case where both the inputs are not 1.
3. The least significant bit of the sum is defined by the 'sum' bit.

The SOP form of the sum and carry are as follows:

Sum=x'y+xy'
Carry = xy

Half-Adder logical circuit:

So, the Half Adder is designed by combining the 'XOR' and 'AND' gates and provide
the sum and carry.
There is the following Boolean expression of Half Adder circuit:

Sum= A XOR B (A+B)

Carry= A AND B (A.B)

Full Adder
The half adder is used to add only two numbers. To overcome this problem, the full
adder was developed. The full adder is used to add three 1-bit binary numbers A, B,
and carry C. The full adder has three input states and two output states i.e., sum and
carry.

Block diagram
Truth Table

In the above table,

1. 'A' and' B' are the input variables. These variables represent the two significant bits
which are going to be added
2. 'Cin' is the third input which represents the carry. From the previous lower significant
position, the carry bit is fetched.
3. The 'Sum' and 'Carry' are the output variables that define the output values.
4. The eight rows under the input variable designate all possible combinations of 0 and
1 that can occur in these variables.

Construction of Half Adder Circuit:

The full adder logic circuit can be constructed using the 'AND' and the 'XOR'
gate with an OR gate.
The actual logic circuit of the full adder is shown in the above diagram. The full adder
circuit construction can also be represented in a Boolean expression.

Sum:
o Perform the XOR operation of input A and B.
o Perform the XOR operation of the outcome with carry. So, the sum is (A XOR B) XOR
Cin which is also represented as:
(A ⊕ B) ⊕ Cin

Carry:
1. Perform the 'AND' operation of input A and B.
2. Perform the 'XOR' operation of input A and B.
3. Perform the 'OR' operations of both the outputs that come from the previous two
steps. So the 'Carry' can be represented as:
A.B + (A ⊕ B)

Unit 4

Memory mapped I/O

As a CPU needs to communicate with the various memory and input-output

devices (I/O) as we know data between the processor and these devices flow
with the help of the system bus. There are three ways in which system bus
can be allotted to them:
 1. Separate set of address, control and data bus to I/O and memory.
2. Have common bus (data and address) for I/O and memory but
separate control lines.
3. Have common bus (data, address, and control) for I/O and memory.
In first case it is simple because both have different set of address space and
instruction but require more buses.

Memory Mapped I/O –

In this case every bus in common due to which the same set of instructions
work for memory and I/O. Hence we manipulate I/O same as memory and
both have same address space, due to which addressing capability of memory
become less because some part is occupied by the I/O.
Direct Memory Access

Removing the CPU from the path and letting the peripheral device manage the
memory buses directly would improve the speed of transfer.

This technique is known as DMA.

In this, the interface transfer data to and from the memory through memory
bus. A DMA controller manages to transfer data between peripherals and
memory unit.

Many hardware systems use DMA such as disk drive controllers, graphic cards,
network cards and sound cards etc.

It is also used for intra chip data transfer in multicore processors.

In DMA, CPU would initiate the transfer, do other operations while the transfer
is in progress and receive an interrupt from the DMA controller when the
transfer has been completed.

Explain the use of buses in DMA controllers in a computer:

Extensively used method to capture buses is through special control signals:

Bus Request (BR): used by DMA controller to request the CPU for buses. When
this input is active, CPU terminates the execution of the current instruction and
places the address bus; data bus and read & write lines into high impedance
state.

Bus Grant (BG): CPU activates BG output to inform DMA that buses are
available (in high impedance state). DMA now take control over buses to
conduct memory transfers without processor intervention. When DMA
terminates the transfer, it disables the BR line and CPU disables BG and returns
to normal operation.

– BBSY (bus busy) line - open collector line - the current bus master i di n cates
d i ev ces that it is currently using the bus by signaling this line
Hardware Interrupts

When the signal for the processor is from an external device or hardware then
this interrupts is known as hardware interrupt.

Let us consider an example: when we press any key on our keyboard to do

some action, then this pressing of the key will generate an interrupt signal for
the processor to perform certain action. Such an interrupt can be of two types:

 Maskable Interrupt

The hardware interrupts which can be delayed when a much high

priority interrupt has occurred at the same time.

 Non Maskable Interrupt

The hardware interrupts which cannot be delayed and should be

processed by the processor immediately.

Asynchronous Data Transfer Methods

The asynchronous data transfer between two independent units requires that
control signals be transmitted between the communicating units to indicate
when they send the data. Thus, the two methods can achieve the asynchronous
way of data transfer.

1. Strobe Control Method

The Strobe Control method of asynchronous data transfer employs a single

control line to time each transfer. This control line is also known as a strobe, and
it may be achieved either by source or destination, depending on which initiate
the transfer.
a. Source initiated strobe: In the below block diagram, you can see that
strobe is initiated by source, and as shown in the timing diagram, the source unit
first places the data on the
data bus.

b. Destination initiated strobe: In the below block diagram, you see that the
strobe initiated by destination, and in the timing diagram, the destination
unit first activates the strobe pulse, informing the source to provide the
data.

INTERRUPT - Interrupt Service Routine

• When I/O Device is ready, it sends the INTERRUPT signal to processor via a
dedicated controller line
• Using interrupt interrupt we are ideally eliminating eliminating WAIT period
• In response to the interrupt, the processor executes the Interrupt Service
Routine (ISR)
Interrupt Service Routine (ISR)
• All the registers registers, flags, program program counter counter values are
saved by the processor before running ISR
• The time required to save status & restore contribute to execution overhead
 “Interrupt Latency”

Enabling and Disabling Interrupts

Enabling
• Device activates interrupt signal line and waits with this signal activated until
processors attends
• The interrupt signal line is active during execution of ISR and till the device
caused interrupt is serviced
• Necessary to ensure that the active signal does not lead to successive
interruptions (level -triggered input) causing the system to fall in infinite loop.
Disabling Interrupts
– Processor automatically disables interrupts before starting the execution of
the ISR
– The processor processor saves the contents contents of PC and PS (status
(status register) before performing interrupt disabling.
– The interrupt-enable is set to 0 – no further interrupts allowed
– When return from interrupt instruction is executed the contents contents of
the PS are restored restored from the stack, and the interrupt enable is set to 1
Define the concept of polling in DMA
The IRQ (interrupt request) bit in the status register is set when a device is
requesting requesting an interrupt interrupt.
• The Interrupt Interrupt service service routine routine polls the I/O devices
devices connected to the bus.
• The first device encountered with the IRQ bit set is serviced and the
subroutine is invoked.
• Easy to implement, but too much time spent on checking the IRQ bits of all
devices, though some devices may not be requesting service.
Explain the concept of Vectored Interrupts
• Device requesting an interrupt identifies itself directly to the processor
• The device sends a special code to the processor over the bus.
• The code contains the – identification of the device ,
– starting address for the ISR,
– address of the branch to the ISR
• PC finds the IS R address from the code.
• To add flexibility for multiple devices - corresponding ISR is executed
executed by the processor processor using a branch address address to the
appropriate routine - device specified Interrupt Vector.
An interrupt vector is the memory address of an interrupt handler, or an index
into an array called an interrupt vector table or dispatch table - a table of
interrupt vectors (pointers to routines that handle interrupts).

7)(A) The synchronous bus

The synchronous bus is a bus used to interconnect devices that comprise a

computer system where the timing of transactions between devices is under
the control of a synchronizing clock signal.
A device connected to a synchronous bus must guarantee to respond to a
command within a period set by the frequency of the clock signal or a
transmission error will occur. Such buses are usually employed in closely
controlled processor backplane environments where device characteristics and
inter-device signal delays are known.
It includes a clock in the control line.
It has a fixed protocol for communication relative to its clock.
Every device on the bus must run at the same speed.

UNIT 3
Machine Instructions: -
Machine Instructions are commands or programs written in machine code of a machine
(computer) that it can recognize and execute.
A machine instruction consists of several bytes in memory that tells the processor to
perform one machine operation.
The processor looks at machine instructions in main memory one after another, and
performs one machine operation for each machine instruction.
The collection of machine instructions in main memory is called a machine language
program.
Machine code or machine language is a set of instructions executed directly by a computer’s
central processing unit (CPU). Each instruction performs a very specific task, such as a load,
a jump, or an ALU operation on a unit of data in a CPU register or memory. Every program
directly executed by a CPU is made up of a series of such instructions.
The general format of a machine instruction is

[Label:] Mnemonic [Operand, Operand] [; Comments]

 Brackets indicate that a field is optional

 Label is an identifier that is assigned the address of the first byte of the instruction in
which it appears. It must be followed by “:”
 Inclusion of spaces is arbitrary, except that at least one space must be inserted; no
space would lead to an ambiguity.
 Comment field begins with a semicolon “ ; ”
Example:
 Here: MOV R5,#25H;load 25H into R5

Machine instructions used in 8086 microprocessor

1. Data transfer instructions– move, load exchange, input, output.
 MOV: Move byte or word to register or memory .
 IN, OUT: Input byte or word from port, output word to port.
 LEA: Load effective address
 LDS, LES Load pointer using data segment, extra segment .
 PUSH, POP: Push word onto stack, pop word off stack.
 XCHG: Exchange byte or word.
 XLAT: Translate byte using look-up table.
2. Arithmetic instructions – add, subtract, increment, decrement,
convert byte/word and compare.
ADD, SUB: Add, subtract byte or word
ADC, SBB: Add, subtract byte or word and carry (borrow).
INC, DEC: Increment, decrement byte or word.
NEG: Negate byte or word (two’s complement).
CMP: Compare byte or word (subtract without storing).
MUL, DIV: Multiply, divide byte or word (unsigned).
IMUL, IDIV: Integer multiply, divide byte or word (signed)
CBW, CWD: Convert byte to word, word to double word
AAA, AAS, AAM ,AAD: ASCII adjust for add, sub, mul, div .
DAA, DAS: Decimal adjust for addition, subtraction (BCD numbers).
3. Logic instructions – AND, OR, exclusive OR, shift/rotate and test
 NOT: Logical NOT of byte or word (one’s complement)
 AND: Logical AND of byte or word
 OR: Logical OR of byte or word.
 XOR: Logical exclusive-OR of byte or word
 TEST: Test byte or word (AND without storing).
 SHL, SHR: Logical Shift rotate instruction shift left, right byte or
word? by 1or CL
 SAL, SAR: Arithmetic shift left, right byte or word? by 1 or CL
 ROL, ROR: Rotate left, right byte or word? by 1 or CL.
 RCL, RCR: Rotate left, right through carry byte or word? by 1 or
CL.
4.String manipulation instruction – load, store, move, compare
and scan for byte/word
 MOVS: Move byte or word string
 MOVSB, MOVSW: Move byte, word string.
 CMPS: Compare byte or word string.
 SCAS S: can byte or word string (comparing to A or AX)
 LODS, STOS: Load, store byte or word string to AL.
5. Control transfer instructions – conditional, unconditional, call
subroutine and return from subroutine.
 JMP: Unconditional jump .it includes loop transfer and
subroutine and interrupt instructions.
 JNZ: jump till the counter value decreases to zero. It runs the
loop till the value stored in CX becomes zero
6. Loop control instructions-
 LOOP: Loop unconditional, count in CX, short jump to target
address.
 LOOPE (LOOPZ): Loop if equal (zero), count in CX, short jump to
target address.
 LOOPNE (LOOPNZ): Loop if not equal (not zero), count in CX,
short jump to target address.
 JCXZ: Jump if CX equals zero (used to skip code in loop).
 Subroutine and Interrupt instructions-
 CALL, RET: Call, return from procedure (inside or outside
current segment).
 INT, INTO: Software interrupt, interrupt if overflow.IRET:
Return from interrupt.
7. Processor control instructions-
Flag manipulation:
STC, CLC, CMC: Set, clear, complement carry flag.
STD, CLD: Set, clear direction flag.STI, CLI: Set, clear interrupt enable
flag.
PUSHF, POPF: Push flags onto stack, pop flags off stack.

I/O
● The data on which the instruc ons operate are not necessarily already stored in memory.

● Data need to be transferred between processor and outside world (disk, keyboard, etc.)

● I/O opera ons are essen al, the way they are performed can have a significant effect on the
performance of the computer.

Program-Controlled I/O Example

● Read in character input from a keyboard and produce character output on a display screen.

Rate of data transfer (keyboard, display, processor)

Difference in speed between processor and I/O device creates the need for mechanisms to
synchronize the transfer of data.

A solution: on output, the processor sends the first character and then waits for a signal from the
display that the character has been received. It then sends the second character. Input is sent from
the keyboard in a similar way.

A stack is a data structure where we can store a group of items.

Elements are added and removed from the top of the stack. i.e., the
element to be removed is top of the stack. Stack follows Last In First
Out(LIFO) order in adding and deleting the elements. Adding an
element is called push operation and removing the element is
called pop operation.
Consider a scenario like:
Main memory capacity is 2048 MB. Stack occupies memory location
from 2000 to 1500 location. Initially the stack is empty . Lets have a
stack pointer whose name is SP to point the elements in the stack.
Note: When we are adding elements to a stack the stack moves
towards lower memory locations i.e., stack moves form location
2000 to 1500.
push operation:
Adding an element to a stack is called push operation. When adding
an element to a stack we need to decrement the stack pointer SP.
Then after decrementing the stack the element to be pushed on to
the new location pointer to by stack pointer SP.
For example we want to place a data item A on to stack.
SP=SP-1
MOVE A,[SP]
Note: [SP] stands for value at address pointed to by SP
The above assembly language instructions can be written in a single
instruction like
MOVE A,-[SP]
Now SP is pointing to new data item A
POP Operation:
Removing an element from the stack is called pop operation.
Removing an element means we are not physically removing the
item from the stack but we just incrementing the stack pointer to
show the next top element. To implement pop operation first we
need to copy the item and then just increment the stack pointer.
MOVE [SP],TEMP
SP=SP+1
The above assembly language instruction can be written in a single
instruction as
MOVE [SP]+,TEMP
Now the Stack pointer SP is pointing to next top element and
removed element is in TEMP variable.
Addressing modes
We have the list below showing the various kind of addressing modes:
Types of Addressing Modes
1. Register Addressing Mode
2. Direct Addressing Mode
3. Immediate Addressing Mode
4. Register Indirect Addressing Mode
5. Index Addressing Mode
6. Auto Increment Mode
7. Auto Decrement Mode
8. Relative Addressing Mode
1. Register Addressing Mode
Every instruction includes operands; the operands can be a memory location, a
processor register or an I/O device. The instruction which uses
processor registers to represent operands is the instruction in register
addressing mode.
Here, the effective address is a register where the value of the operand is
present.
EA=R
Below we have two instructions as our examples for register addressing mode.
Add R4, R3
Load R3, R2
In the examples above, the Add instruction uses registers to represent both of
its operands. Similarly, the Load instruction also uses registers to represent
both of its operands. So, the instruction above uses register addressing mode
to describe the address of the operand. Below, we have a figure showing the
Add instruction in the example above.

Advantage: In the register addressing mode there are no memory references

as the value to be operated is present in the register.
Disadvantage: Registers have limited address space. So, it has a limit on the
size of value that can be stored.
2. Direct Addressing Mode
The direct addressing mode is also known as Absolute Addressing mode. Here,
the instruction contains the address of the location in memory where the
value of the operand is stored.
Here, the effective address is the address of memory location.
EA = A
For example, observe the examples below:
Add R2, A
Store R2, B
The Add instruction includes the memory location A which has the value to be
added to the content of register R2. Similarly, the Store instruction has the
address of memory location B where the content of register R2 will be stored.
Below we have a figure showing the direct addressing of the operand A in the
Add instruction of the example above.

Advantage: Direct addressing mode is the simplest of all addressing mode.

Disadvantage: Direct addressing mode provides a limited address space.
3. Immediate Addressing Mode
In immediate addressing mode, the value of the operand is explicitly
mentioned in the instruction. Here, effective address is not required as the
operand is explicitly defined in instruction.
Let us see the example of immediate addressing mode:
Add R2, #100
Store R2, 100H
The Add instruction, adds 100 to R2’s content . The # sign in front of the value
indicates the immediate value to be operated. If a value does not have # sign in
front of it then it is the address of a memory location.
The next instruction Store considers the immediate value 100H as address as it
does not have # sign in front of it. The Store instruction stores the content of
R2 at memory location 100H. In the figure below we have shown the Store
instruction of the above examples.
Advantage: In the immediate addressing mode the memory reference is not
required as the value is explicitly present in the instruction
Disadvantage: The instruction format provides a limited size for the operand.
So, the immediate addressing mode has limited space for immediate value.
4. Register Indirect Addressing mode
A processor register is used to hold the address of a memory location where
the operand is placed. This addressing mode allows executing the same set of
instructions for the different memory location. This can be done by
incrementing the content of register thereby pointing the new location each
time.
In higher-level language, it is referred to as pointers. The indirect mode is
denoted by placing the register inside the parenthesis.
Here the effective address is the content of memory location present in the
register.
EA=(R)
Now, for example:
Load R3, (R2) // Load R2, A
The Load instruction above will load the value present at the memory location
contained by register R2 in the register R3. The figure below shows how the
register R3 gets loaded with the value stored in the memory location held by
register R2.
Advantage: In the register indirect addressing mode the same set of
instructions can be used multiple times.
Disadvantage: In the register indirect addressing mode the number of memory
reference is more.
5. Index Addressing Mode
Index addressing mode is helpful when the instructions in the program are
accessing the array or the large range of memory addresses. In this mode, the
effective address is generated by adding a constant to the register’s content.
The content of the register does not change.
The symbolic representation of index addressing mode is denoted as:
X(R)
And the effective address is denoted by
EA = X + (R)
For example, consider the instruction below:
Load R2, A
Load R3, (R2)
Load R4, 4(R2)
Load R5, 8(R2)
Load R6, 12(R2)
The above instructions will load the register R3, R4, R5, R6 with the contents,
present at the successive memory addresses from memory location A
correspondingly.

Advantage: The index addressing mode provides flexibility to specify memory

locations.
Disadvantage: The index addressing mode is complex to implement.
6. Auto Increment Addressing Mode
In auto-increment addressing mode once the content of the register
is accessed by the instruction the register’s content is incremented to refer the
next operand.
Symbolically it is represented as below:
(R)+
Here, the effective address is content of the register as it is enclosed by
parenthesis. The content of register which is referring to a memory location is
incremented so that it could point the next memory location where the next
operand is stored.

7. Auto Decrement Addressing Mode

It is just opposite of auto-increment mode. In auto decrement mode the
content of the register is decremented initially and then the decremented
content of the register is used as effective address.
Symbolically it is presented as:
-(R)
The auto-increment and decrement mode help to implement the stack
structure.
8. Relative Addressing Mode
In the content above we have discussed the index addressing mode. There we
were adding a constant to the register content to refer the next operand
address. In some computer instead of a register, the program counter is used.
The symbolic representation of relative address mode is
X(PC)
The effective address for it would be:
EA = X + (PC)
As here the operand addresses are found relative to the program counter.
That’s why it is referred to as relative address mode.
Advantage: Relative addressing mode doesn’t require memory references.
Disadvantage: Relative addressing mode doesn’t have any disadvantage as
such.
This is all about addressing modes in computer architecture. It provides us with
a flexible method to specify the address of the operands used in instruction.

ARM
Advanced RISC Machine (ARM) Processor is considered to be family of Central
Processing Units that is used in music players, smartphones, wearables, tablets
and other consumer electronic devices.
The architecture of ARM processor is created by Advanced RISC Machines,
hence name ARM. This needs very few instruction sets and transistors. It has
very small size. This is reason that it is perfect fit for small size devices. It has
less power consumption along with reduced complexity in its circuits.
They can be applied to various designs such as 32-bit devices and embedded
systems. They can even be upgraded according to user needs.
RISC
RISC stands for Reduced Instruction Set Computer Processor, a microprocessor
architecture with a simple collection and highly customized set of instructions. It is
built to minimize the instruction execution time by optimizing and limiting the number
of instructions. It means each instruction cycle requires only one clock cycle, and each
cycle contains three parameters: fetch, decode and execute. The RISC processor is also
used to perform various complex instructions by combining them into simpler ones.
RISC chips require several transistors, making it cheaper to design and reduce the
execution time for instruction.

Examples of RISC processors are SUN's SPARC, PowerPC, Microchip PIC processors,
RISC-V.

OPCODE
An Opcode is also known as Operation code. In computer architecture and
microprocessor instruction, the Opcode is the task to be performed by the
computer on the operand.

Example: SUB D The above instruction will subtract the content of register D
with the accumulator. The SUB is the Opcode while the D and accumulator
are operands.

LDR

Generally, LDR is used to load something from memory into a register, and STR is used
to store something from a register to a memory address.

LDR r2,[r1]

This instruction will take the address in r1, and then load a 4 byte value from the
memory pointed to by it into register r2.

Note: r1 is called the base register.