Module 5.

Basic
Processing Unit
(upto 7.5 except 7.5.1 to 7.5.6 of Chap
7 of Text)

Padma Prasada
Sr. Assistant Prof. E&C Dept.
MITE
Outline
 Some Fundamental Concepts
 Execution of a Complete Instruction
 Multiple Bus Organization
 Hardwired Control
 Microprogrammed Control

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 Course Plan
Sl. Content Planned Engaged
No Date Date
1 Some Fundamental Concepts
2 Some Fundamental Concepts contd...
3 Execution of a Complete Instruction
4 Execution of a Complete Instruction contd...
5 Multiple Bus Organization
6 Multiple Bus Organization contd...
7 Hardwired Control
8 Microprogrammed Control

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Overview
 Instruction Set Processor (ISP)
 Central Processing Unit (CPU)
 A typical computing task consists of a series of steps
specified by a sequence of machine instructions that
constitute a program.
 An instruction is executed by carrying out a sequence of
more rudimentary operations.

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Some Fundamental
Concepts
Fundamental Concepts
 Processor fetches one instruction at a time and
perform the operation specified.
 Instructions are fetched from successive memory
locations until a branch or a jump instruction is
encountered.
 Processor keeps track of the address of the memory
location containing the next instruction to be fetched
using Program Counter (PC).
 Instruction Register (IR)

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Executing an Instruction
 Fetch the contents of the memory location pointed
to by the PC. The contents of this location are
loaded into the IR (fetch phase).
IR ← [[PC]]
 Assuming that the memory is byte addressable,
increment the contents of the PC by 4 (fetch phase).
PC ← [PC] + 4
 Carry out the actions specified by the instruction in
the IR (execution phase).

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Processor Organization – Single Bus Structure

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Executing an Instruction
 Transfer a word of data from one processor
register to another or to the ALU.
 Perform an arithmetic or a logic operation and
store the result in a processor register.
 Fetch the contents of a given memory location
and load them into a processor register.
 Store a word of data from a processor register
into a given memory location.

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Register Transfers
Internal processor
bus
R iin

Ri

R iout

Y in

Constant 4

Select MUX

A B
ALU

Z in

Z out

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Figure 7.2. Input andMITE
output gating for the registers in Figure 7.1. 10
Performing an Arithmetic or
Logic Operation
 The ALU is a combinational circuit that has no
internal storage.
 ALU gets the two operands from MUX and bus.
The result is temporarily stored in register Z.
 What is the sequence of operations to add the
contents of register R1 to those of R2 and store the
result in R3?
1. R1out, Yin
2. R2out, SelectY, Add, Zin
3. Zout, R3in

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Fetching a Word from Memory
 Address into MAR; issue Read operation; data into MDR.

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Assignment 5
1. Describe multiple bus organization with neat
diagram, mention its advantages
2. With a neat figure explain the single bus
organization of data path inside a processor
3. Explain hardwired control unit organization
in a processing unit
Due date 21/11/2019

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Fetching a Word from Memory
 The response time of each memory access varies
(cache miss, memory-mapped I/O,…).
 To accommodate this, the processor waits until it
receives an indication that the requested operation
has been completed (Memory-Function-Completed,
MFC).
 Move (R1), R2

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Timing Diagram – Memory Read Operation

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Execution of a Complete
Instruction
 Add (R3), R1
 Fetch the instruction
 Fetch the first operand (the contents of the
memory location pointed to by R3)
 Perform the addition
 Load the result into R1

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Execution of a Complete
Instruction
Add (R3), R1

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Execution of Branch
Instructions
 A branch instruction replaces the contents of
PC with the branch target address, which is
usually obtained by adding an offset X given in
the branch instruction.
 The offset X is usually the difference between
the branch target address and the address
immediately following the branch instruction.
 Conditional branch

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Execution of Branch Instructions

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Multiple-Bus Organization

While the steps still have to be performed by sequentially

changing from one step to another, the number of
independent steps can be clubbed into single step in a
multiple bus organization.
Improvement in performance in a multiple bus organization

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Multiple-Bus Organization

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Multiple-Bus Organization
 Add R4, R5, R6

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Hardwired Control
Overview
 To execute instructions, the processor must
have some means of generating the control
signals needed in the proper sequence.
 Two categories: hardwired control and micro
programmed control
 Hardwired system can operate at high speed;
but with little flexibility.

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Control Unit Organization

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Control Unit Organization

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Generating Zin
 Zin = T1 + T6 • ADD + T4 • BR + …
Branch Add

T4 T6

T1

Figure 7.12. Generation of the Z in control signal for the processor in Figure 7.1.
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Generating End T7
Add

T5
N
Branch<0

T4
Branch

T5

End

Figure 7.13. Generation of the End control signal.

 End = T7 • ADD + T5 • BR + (T5 • N + T4 • N) • BRN +…

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Microprogrammed
Control
Micro programmed Control
 Control signals are generated by a program
similar to machine language programs.
 Control word cw: individual bits represent the
various control signals
 Sequence of CWs corresponding to the control
sequence of a machine instructions constitutes
the ‘micro routine’
 Individual words in micro routine are referred to
as ‘micro instructions’
 Control Store special memory for instruction
storage
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Overview
MDRout

WMFC
MAR in

Select
Read
PCout

R1out

R3out
Micro -

End
PCin

R1in
Add

Z out
IRin
Yin

Zin
instruction

1 0 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0
2 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0
3 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0

 Control signals are generated by a program similar to machine

4 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0
5 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0
6 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0
7 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1

language programs.
Figure 7.15 An example of microinstructions for Figure 7.6.

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Overview
 Control store
Starting
IR address
generator

Clock mP C

Control
store CW

Figure 7.16.Basic organization of a microprogrammed control unit.

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Overview
 The previous organization cannot handle the situation when the control
unit is required to check the status of the condition codes or external
inputs to choose between alternative courses of action.
 Use conditional branch microinstruction.
Address Microinstruction

0 PC out ,MAR in ,Read, Select4,Add, Z in

1 Z out ,PC in ,Y in ,WMF C
2 MDR out ,IR in
3 Branch to Starting address of appropriate microroutine
..................................................................
25 IfN=0,then branch to microinstruction 0
26 Offset-field-of-IR
, SelectY, Add, Z
out in
27 Z out ,PC in ,End

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Figure 7.17. Microroutine for the instruction Branch<0.
Overview

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 Model Questions
1. With a diagram, explain typical single bus processor data path.
2. List out the actions needed to execute the instruction ADD (R3), R1. Write
and explain sequence of control steps for the execution of the same.
3. Write the control sequence for an un – conditional branch instruction.
4. Write down the control sequence for the instruction ADD R4,R5,R6 for three
bus organization.
5. Explain the process of fetching a word from memory along with a timing
diagram.
6. With a neat block diagram, explain hardwired control unit. Show the
generation Zin and END control signals.
7. With the neat diagram, the basic organization of a micro programmed control
unit. Write the micro routine for the instruction branch<0.
8. Differentiate hardwired and micro programmed control unit.
9. Describe the multiple bus organization with neat figure

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