This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TTE.2019.2957635, IEEE
Transactions on Transportation Electrification

Design Methodology of A Three-Phase Four-Wire EV

Charger Operated at the Autonomous Mode
Yongsheng Fu, Yu Li, Yang Huang, Hua Bai, Member, IEEE, Ke Zou, Xi Lu and Chingchi Chen

ABSTRACT: Compared with G2V and V2G modes,
EV battery chargers are more vulnerable to power
quality problems at the autonomous mode, i.e.,
creating its own electric grid during the grid blackout
while facing unbalanced and nonlinear loads. Active
damping is another common challenge given most
charger equip LC filters at grid-end voltage-source
inverters (VSIs). In this paper, an output voltage
control with harmonic compensation plus virtual
impedance term is proposed to achieve high power
quality and necessary damping, respectively. The
physical meaning of the virtual impedance is further
explained, and the voltage loop with PI plus
multi-resonant terms is analyzed in depth. More
importantly, the analytical solutions and procedures
to design such controllers considering the time delays
are proposed. Finally, simulation results and
experimental data on an EV battery charger
prototype using SiC devices, which is made of one
VSI and one isolated DC/DC converter, validate the
effectiveness of the proposed design methodology.
Index Term-Battery Charger, DC-AC inverter,
Electric Vehicle, Silicon Carbide.
I. INTRODUCTION
Three-phase grid-tied voltage source inverters (VSIs)
are very commonly used devices in energy storage
systems, with the DC side as solar panels, fuel cells,
battery pack, etc. Recently years witnessed the surge of
the decentralized grid, where a grid-tied inverter is
usually employed to create its own grid when the grid
capacitors [6], [7],[8]. In this case, the fourth leg cannot
be independently controlled to maintain a stable neutral
point and the corresponding control design (including the
PWM waveform generating scheme) becomes much
more complicated. Meanwhile the fourth leg is
high-frequency operated, leading to common-mode
voltage with respect to the ground and electromagnetic
interference (EMI) arising [9]. The control of the fourth
leg is also coupled with the control of other three-phase
output voltage, complicating the design of controller
parameters [10][11]. The other solution is to add an
additional leg with split DC-link capacitors, as shown in
Fig.1 where DC link capacitors are not necessarily as
large as those in the conventional split DC link topology
[9]. This feature is preferred for high power-density
designs. Furthermore, the controller design for this
topology is relatively straightforward since the control of
the neutral point and phase voltage can be decoupled. As
a summary, this topology has the following advantages:
1) The capacitance of the split dc-link capacitor can be
greatly reduced;
2) The common-mode current from the neutral point
to the ground is eliminated;
3) The control of the independently controlled neutral
module is decoupled with that of the three-phase output
voltage so that the charger can be operated at either
three-phase mode or single-phase mode. If this charger is
an off-board fast charger with large enough battery
capacity, each of the created three separate single phases
can take care of individual houses/communities.
V

blackout happens, i.e., the autonomous mode [1]–[5]. A + CN1

S n1
typical example is the vehicle-to-home (V2H) or uN 1
-
S a1 S b1 S c1
Lf RLA
vehicle-to-load (V2L) mode, i.e., using the on-board uN
iLN iCN
N
uphA iA
u phB iB
Lf RLB
LN
battery to create the power grid once the house uphC Lf RLC
iC

Sn 2 iN u + CN 2
encounters the power outage. The vehicle control unit N2

-
Sa 2 Sb 2 Sc 2
Cf Cf Cf
(VCU) sends the discharging current reference to the N
on-board charger (OBC). The DC/DC part of the OBC V

then delivers the power, while its grid-side power factor
controller (PFC), which is also an AC/DC converter
manages to build the grid voltage. Such grid recovered
by the OBC can be single-phase AC for the residential
application, or three-phase for the commercial or
industrial applications, which usually requires much
higher power. With the battery capacity large enough, the
recovered three-phase voltage can even be split to power
different community with different phases. Such V2L
feature goes beyond the V2G and G2V and will greatly
increase EV adoptions, especially when dealing with
power outage. Despite its growing importance, there
exist several essential control problems associated. First,
a neutral point needs to be provided by the inverter
because of potential unbalanced loads. One solution is to
add an additional fourth leg without split DC-link
Fig.1. Three-phase four-wire inverter with an extra neutral leg
Therefore this topology is the study of this paper.
In [9], a simplified linear model is built with a
classical control applied. However, for the simplicity
of analysis, the time delay caused by the
analog-to-digital conversion (ADC), computation and
signal transportation in a digital control system is
usually neglected [12], which needs be addressed. On
the other hand, according to IEEE standards [13], the
voltage unbalance factor (VUF) and the total voltage
harmonic distortion (THD) should be maintained
below 2% and 5%, respectively. Therefore providing
effective elimination of the output voltage distortion
caused by nonlinear and unbalanced loads is critical.
The article [14] presented the voltage outer loop and
current inner loop based on the proportional-resonant

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(PR) control under the stationary reference frame. A respectively. Section Ⅵ is the simulation and
simplified first-order inertial part is used to quantify experimental validation, where such an inverter acts as
the effect of the signal sampling, calculation and the AC/DC part of a bidirectional EV OBC. Section
transportation in digital control systems. In [15], a Ⅶ is the conclusion. Our goal is to provide the design
similar controller is proposed in the stationary framework for the neutral-point and
reference frame with the consideration of the sampling phase-voltage/current controllers thereby providing
effect, and a lead-lag compensator is also introduced the comprehensive design guidance of a three-phase
to enhance the system stability. Essentially the PR four-wire system. The success of such an attempt
controller is to introduce an infinite gain at specific helps comprehend the essence of such inverter control
resonant frequency to eliminate the steady state error. strategy, promotes the EV adoption and could be
Another challenge of grid-tied VSIs is caused by easily extended to other multi-phase VSIs.
the filter. Though LC or LCL output filters are
II. MODELING A THREE-PHASE FOUR-WIRE
commonly used to mitigate VSIs switching ripples,
INVERTER
without being properly controlled inherent resonances
of the filter can introduce serious stability problems A. Modeling the Neutral leg
[18]. Active damping through the virtual impedance is
The neutral leg is made of S n1 and Sn2 in Fig.1.
becoming a promising technique to address this issue
Decoupled from the other three phases, the neutral
without introducing additional losses. An internal
point can be steadily regulated by a simple controller
virtual resistance (VR) based technique to damp the
using the voltage and current feedback, even when the
resonance in a standalone VSI with LC filters is
three-phase load is extremely unbalanced. Assume the
analyzed in [16]. To compensate the voltage harmonic
voltage across capacitors CN1 and CN2 are uN1 and uN2,
distortion and produce sinusoidal voltage, the article
respectively. The DC link voltage is
[17] proposes a selective voltage harmonic
compensation strategy for standalone inverters with 𝑢𝐷𝐶 = 𝑢𝑁1 + 𝑢𝑁2 (1)
the appropriate virtual impedance design. In [18], a Define the shift of the neutral point as
generalized closed-loop control scheme is proposed 𝜀 = 𝑢𝑁2 − 𝑢𝑁1 (2)
for VSIs, which provides a clear physical meaning of Based on Kirchhoff voltage and current laws (KVL
each control term. In [22], upon a virtual RC damper, and KCL), we have:
the effective harmonic compensation range of 𝜀 𝑑𝑖
LCL-filtered converters is extended. (𝑢𝑖𝑛𝑣 − ) = 𝐿𝑁 𝐿𝑁 + 𝑅𝑁 𝑖𝐿𝑁
2 𝑑𝑡
In this paper, a stable neutral point is supported
by the fourth leg of the power converter. The 𝑖𝐿𝑁 = 𝑖𝑁 + 𝑖𝐶𝑁
output-voltage control loop and virtual impedance are 𝑑𝑢𝑁2 𝑑𝑢𝑁1
employed to achieve high power quality and necessary { 𝑖𝐶𝑁 = 𝐶𝑁2 − 𝐶𝑁1
𝑑𝑡 𝑑𝑡
damping, respectively. To maximize the hardware (3)
potential to achieve rapid dynamic response, the time where 𝑢𝑖𝑛𝑣 = (𝑑 − 1⁄2)𝑢𝐷𝐶 is the fourth-leg
delay effect of the digital control system has been output voltage referring to the neutral point N when
taken into account. Different from previous literature, 𝜀 = 0 holds. The objective of the control loop is to
major contributions of this paper include: maintain the balance of the neutral-point voltage, i.e.,
1) The computational and transport delay has 𝜀 ≈ 0. The control block diagram of the neutral leg is
been analyzed. With the time delay effect taken into shown as Fig. 2, according to (1) ~ (3).
account, the three-phase four-wire VSI model has
uDC/2
been re-formulated, which can be easily extended to
other power electronics systems with different time (CN 1  CN 2 )
(CN 1  CN 2 )
delay; iN
2) The virtual impedance damping effects are uinv + 1 iLN + - iCN 1 +
-

investigated in depth, particularly its physical meaning. LN s  RN (CN 1  CN 2 ) s 2
-
To further enhance the power quality, this paper
utilizes the voltage loop with PI plus multi-resonant
terms, instead of the conventional PI controller. Fig.2. Control block diagram of the neutral leg
Detailed comparison will be made in this paper.
3) Detailed analysis and design methodology of The topology of the three-phase four-wire four-leg
controllers with optimized dynamic response have inverter is shown in Fig.1. At the AC side, the
been proposed, which provides the analytical solutions conventional three-phase two-level inverter is
of PI controllers and evaluates the performance of composed of MOSFETs Sa1~Sc2. At the DC-bus side,
controllers with both simulation and experimental there are split DC-link capacitors CN1 and CN2, where
data. the midpoint of split DC-link capacitors serves as the
This paper is structured as follows: Section Ⅱ neutral point. The fourth leg formed by S n1, Sn2 and LN
presents the analytical model of the VSI. Section Ⅲ is to regulate the neutral-point voltage caused by the
analyzes the computational and transportation delay in load imbalance. Lf and Cf are the grid-side filtering
the digital control system. Section Ⅳ & Ⅴ propose the inductor and capacitor, respectively.
control of the neutral point and phase voltage,

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B. Modeling three-phase Legs Assume the duty cycle is updated once every N
switching periods, where N is an integer. This
Specific common mode voltage, such as the introduces a computational delay equal to N switching
third-order harmonics, may be added to the PWM periods to the control loop. Shown in Fig.5 is the
reference to increase the DC-bus voltage utilization. PWM for a single-phase leg. The duty cycle command
However, it also causes the phase cross talking, i.e., is frozen for N carrier periods (NTs) and then
phase current is determined not only by the related compares against a triangular carrier. Such a delay is
phase voltage, but also by other phases [23]. Thanks to equivalent to a zero-order holder (ZOH), and this
the intrinsic feature of the topology shown in Fig.1, intrinsic feature introduces another half switching
the neutral-point voltage and the phase voltage can be period transport delay into the control loop [24]. Thus,
regulated independently. Thus, all the analysis can be an overall time delay of (N+1/2)Ts is introduced to the
simplified into a completely decoupled single-phase control loop, and can be incorporated into the model
system, with its equivalent circuit shown in Fig. 3. by adding an e -s(N+1/2)Ts term in the forward path. To
V
further investigate the time delay effect, bode plots
with different N showing the effect of these delays on
+ CN1
the forward path open loop are depicted in Fig. 6.
uN 1 S1 Note that the ideal forward path phase response does
- iLf Rf Lf iO not cross −180° , which ensure a stable system.
u ph
N
iCf
However, when considering time delay effect, phase
+ CN 2 + response falls to −∞° as the frequency increases.
u N2
S2 uCf Cf
Local Load
Such time delay effect makes it possible to produce an
- - unstable system since the open-loop phase shift goes
V
beyond −180°. Moving forward, all control loops in
this paper will take the time delay effect into account.
Fig.3. The equivalent single-phase system
PWM Computation Delay

According to KCL and KVL, we have 1st

Ts
2nd Nth

Duty Cycle
Command
𝑑𝑖𝐿𝑓 Duty Cycle
𝑢𝑝ℎ − 𝑢𝐶𝑓 = 𝐿𝑓 + 𝑅𝑓 𝑖𝐿𝑓 Command Updates
𝑑𝑡 Duty Cycle
Updates
Duty Cycle

𝑖𝐿𝑓 = 𝑖𝑜 + 𝑖𝐶𝑓
𝑑𝑢𝐶𝑓 1 t
= 𝑖
{ 𝑑𝑡 𝐶𝑓 𝐶𝑓 ADC Time CPU Calculation Time... CPU Calculation Time
t
PWM
t
(4)
O

Fig.5. Time Delays Caused by PWM and Digital Implementation

The control diagram of each single phase is then

iO
- ucf
uph + 1 iLf + iCf 1
Lf s  Rf Cf s
-

Fig. 4. Control block diagram of a single-phase system

III. EFFECT OF COMPUTATION AND TRANSPORT

DELAYS
A commonly used strategy to simplify the power
electronics model is to replace various switching
modes with a linear amplifier, which assumes the
control system is a function of the duty cycle.
However, most of modern control systems utilize Fig. 6. Bode plot of the open-loop forward path loop gain vs time delay
digital signal processors to implement the closed-loop effect
calculation and modulation, which to save the IV. THE NEUTRAL-POINT CONTROLLER DESIGN
computation resources does not update the duty cycle
every switching period. In addition, a sampling time The existence of the neutral inductor and DC-link
delay from ADC to the PWM generation exists, which capacitors causes potential resonance. A feasible
affects the system stability margin. In some cases, the method to damp such resonance is to introduce a
duty cycle command might be updated in a much virtual resistor. Given the shift of the neutral-point
lower rate compared to the switching period, voltage is also affected by the neutral current iN, an
especially in high switching frequency applications intuitive idea is to eliminate its influence through
such as SiC MOSFETs based converters. the feed-forward control. Therefore, the capacitor

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current iCN is selected as the internal impedance iLN RN LN

feedback variable since it contains both iN and iLN.
A. Virtual impedance analysis

LN iCN
Take the time delay into consideration, as shown in uN Z N ,VI  iN
K iN Cequ Cequ
Fig.7(a). By tentatively ignoring KiN term (red line),
the relationship among iN, iCN and iLN can be expressed 
as
𝐼𝑁 (𝑠) = 𝐼𝐿𝑁 (𝑠) −
Fig. 8. Block diagram of the neutral leg
𝐼𝐶𝑁 (𝑠)
1
The neutral current contains harmonics with
−(𝑁+ )𝑇𝑠 𝑠
𝑈𝑁 (𝑠)𝑒 2 𝜀(𝑠) frequency much higher than the fundamental
= 𝐿𝑁 𝑠+𝑅𝑁
− 𝑠(𝐶𝑁1 + 𝐶𝑁2 ) 2
(5) frequency. Optimizing the virtual impedance term then
With the KiN term, we can further modify the neutral needs to widen the control bandwidth thereby
including useful current information as much as
current as possible. Firstly, move the feedback node of 𝜀/2
𝐼𝑁,𝑉𝐼 (𝑠) back to the node of disturbance term 𝑖𝑁 . Secondly,
according to the superposition ignore the disturbance
= 𝐼𝐿𝑁,𝑉𝐼 (𝑠)
term 𝑖𝑁 and voltage feedback term, as shown in Fig.
− 𝐼𝐶𝑁 (𝑠) 7(b). After such manipulation, the open-loop transfer
1 function of the inner current loop is shown as below:
(𝑈𝑁 (𝑠) − 𝐾𝑖𝑁 𝐼𝐶𝑁 (𝑠))𝑒 −(𝑁+2)𝑇𝑠𝑠 𝜀(𝑠)
= − 𝑠(𝐶𝑁1 + 𝐶𝑁2 ) 𝐾𝑖𝑁 ∙𝑒 −(𝑁+0.5)𝑇𝑠 ∙𝑠
𝐿𝑁 𝑠 + 𝑅𝑁 2 𝐺𝐹𝑊𝑖𝑁 (𝑠) = (8)
𝐿𝑁 𝑠+𝑅𝑁

𝑈𝑁 (𝑠)𝑒
1
−(𝑁+2)𝑇𝑠 𝑠
𝜀(𝑠) 𝐾𝑖𝑁 𝐼𝐶𝑁 (𝑠)𝑒
1
−(𝑁+2)𝑇𝑠 𝑠 where RN is the neutral-inductor internal resistance.
=
𝐿𝑁 𝑠+𝑅𝑁
− 𝑠(𝐶𝑁1 + 𝐶𝑁2 )
2
−
𝐿𝑁 𝑠+𝑅𝑁
(6) To enhance the dynamic performance and secure the
system stability, the phase angle of this open loop
uDC/2 (CN 1  CN 2 )
transfer function at the cross-over frequency ωcN is
(CN 1  CN 2 ) depicted as
iN
- - -
uN 
𝐾𝑖𝑁 ∙𝑒 −(𝑁+0.5)𝑇𝑠 ∙(𝑗𝜔𝑐𝑁 )
uN + 1 uinv + 1 iLN + iCN 1 +
 ( N  )Ts s

-
e 2
LN s  RN (CN 1  CN 2 ) s 2 ∠𝐺𝐹𝑊𝑖𝑁 (𝑗𝜔𝑐𝑁 ) = ∠
𝐿𝑁 (𝑗𝜔𝑐_𝑖𝑁 )+𝑅𝑁
KiN

(a) Before Manipulat ion = −(𝑁 + 0.5

LN s  RN 𝐿𝑁 𝜔𝑐𝑁
)𝑇𝑠 𝜔𝑐𝑁 − 𝑎𝑟𝑐𝑡𝑎𝑛 ( ) = −𝜋 + ∅𝑚𝑁
+ 𝑅𝑁
iN + uDC/2 (CN 1  CN 2 )
(CN 1  CN 2 )

uN + uN iLN +
×
- iCN -

(9)
1
 ( N  )Ts s
1 1 +
-
e 2
LN s  RN (CN 1  CN 2 ) s 2 where 𝜙𝑚𝑁 is defined as the required stability
KiN phase margin. Almost invariably, the system crossover
(b) Aft er Manipulat ion frequency will be well above the plant pole frequency
𝐿 𝜔
in practical scenarios. Hence 𝑎𝑟𝑐𝑡𝑎𝑛 ( 𝑁 𝑐𝑁 ) is
Fig.7. Block diagram of the neutral leg 𝑅𝑁
approximately π/2. The possible maximum control
The last item of (6) can be equivalent to a virtual bandwidth then can be found as
impedance in parallel with the equivalent capacitor
𝜋⁄2−∅𝑚𝑁
(𝐶𝑒𝑞𝑢 = 𝐶𝑁1 + 𝐶𝑁2 ), where 𝜔𝑐𝑁_𝑚𝑎𝑥 = (10)
(𝑁+0.5)𝑇𝑠
𝐿𝑁 𝑠+𝑅𝑁 𝐿𝑁
𝑍𝑁,𝑉𝐼 (𝑠) = 1 ≈ (7) The maximum value of 𝐾𝑖𝑁 can be derived by
−(𝑁+2)𝑇𝑠 𝑠 𝐾𝑖𝑁 𝐶𝑒𝑞𝑢
𝐾𝑖𝑁 𝐶𝑒𝑞𝑢 𝑠𝑒
setting the open-loop gain at ωcN to be unity, i.e.,
So the equivalent circuit can be found in Fig.8. The
𝐾𝑖𝑁_𝑚𝑎𝑥
physical meaning of the virtual impedance can be =1 (11)
described as an equivalent internal impedance in 2
√(𝐿𝑁 𝜔𝑐𝑁_𝑚𝑎𝑥 )2 +𝑅𝑁
parallel with the filter capacitor. Considering (7), the
Therefore,
virtual impedance equals to a virtual resistor to
provide enough damping for the system. Furthermore,
the control parameter 𝐾𝑖𝑁 gives the freedom to 𝐾𝑖𝑁_𝑚𝑎𝑥 = √(𝐿𝑁 𝜔𝑐𝑁_𝑚𝑎𝑥 )2 + 𝑅𝑁2 ≈ 𝐿𝑁 𝜔𝑐𝑁_𝑚𝑎𝑥 (12)
balance the bandwidth of the control loop and
damping coefficient. B. Analysis of voltage loop controller

With the virtual impedance properly designed,

the control block diagram of the voltage loop can be
modified as Fig. 9. Firstly, the capacitor difference

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term is ignored. Secondly, the virtual impedance {

𝜁 = 𝜁𝑟
(16)
term is equivalently transformed. Here the transfer 𝜔𝑟 ≈ 𝜔𝑛
function of the voltage-open-loop gain is As mentioned above, the bandwidth of the system
𝐺𝑣𝑁 (𝑠) ∙ 𝑒 −(𝑁+0.5)𝑇𝑠∙𝑠 𝐾𝑖𝑁 𝐶𝑒𝑞𝑢 𝑠 𝜔𝑐𝑁 should be high enough to reject unpredictable
𝐺𝐹𝑊𝑣𝑁 (𝑠) = 2
∙ (1 + ) disturbance and secure the fast dynamic response.
𝐶𝑒𝑞𝑢 𝐿𝑁 𝑠 + 𝐶𝑒𝑞𝑢 𝑅𝑁 𝑠 + 1 𝐺𝑣𝑁 (𝑠)
Here a similar manner is applied as [16]. Two factors
𝜔 𝜔𝑐𝑁
=
(𝐾𝑖𝑁 𝐶𝑒𝑞𝑢 𝑠+𝐺𝑣𝑁 (𝑠))
𝑒 −(𝑁+0.5)𝑇𝑠∙𝑠 (13) 𝑘𝑟𝑛 ≜ 𝑟 > 1 and 𝑘𝑏𝑤 ≜ ≤ 1 are defined and
𝜔𝑛 𝜔𝑐𝑁_𝑚𝑎𝑥
𝐶𝑒𝑞𝑢 𝐿𝑁 𝑠 2 +𝐶𝑒𝑞𝑢 𝑅𝑁 𝑠+1
initial values will be selected (e.g. 𝑘𝑟𝑛 = 1.1, 𝑘𝑏𝑤 =
1) based on the analysis above. It is now clear that all
uDC/2 (CN 1  CN 2 )
(CN 1  CN 2 ) control parameters can be calculated through
iN
× equations above once inverter parameters are given, as
O + GvN ( s )
+
e
1
 ( N  )Ts s
2
+
- uN 1
LN s  RN
iLN + -
iCN 1
Cequ s
+
- 
2
shown in Table 1 of Section Ⅵ. A flow chart of the
neutral-point control-loop design process is shown in
- -
×
×
Fig.11. The more detailed explanation is as follows:
+ 1
KiN Cequ s
GvN ( s )
+
Step-1: Based on system parameters and
specifications, the maximum bandwidth of the
Fig. 9. Control diagram of the simplified neutral voltage loop
control loop 𝜔𝑐𝑁_𝑚𝑎𝑥 and the corresponding
The aim of controlling the fourth leg is to balance maximum gain 𝐾𝑖𝑁_𝑚𝑎𝑥 could be obtained using
the voltage on the two series-connected DC link (10) and (12).
capacitors, i.e. regulating the voltage difference on the Step-2: Select 𝑘𝑏𝑤 = 1 as the initial value to
two capacitors to be zero. As depicted in Section II, enhance the dynamic performance of the system.
the voltage difference between the two capacitors can Step-3: Based on system parameters and
be modeled in equation (3). Accordingly, the voltage specifications, calculate 𝜔𝑟 and 𝜁𝑟 , select 𝑘𝑟𝑛 > 1,
difference is able to be regulated by switching the e.g. 𝑘𝑟𝑛 = 1.1, and then calculate 𝜔𝑛 and ζ.
fourth leg. Therefore, the control diagram of the Step-4: Parameters of the voltage-loop PI controller
neutral point loop is obtained in Fig. 9. In reality, we can be found according to 𝜔𝑛 and ζ.
used two voltage sensors to sample the upper and Step-5: Draw the bode plot of the open-loop
lower capacitor voltage. Physically, when capacitor transfer function. If the phase margin is sufficient, the
voltage is above the threshold, its related switch will design process is done; Otherwise, 𝑘𝑟𝑛 should be
increase the duty cycle to absorb its energy then decreased and the design process from Step-2 to
transfer to another capacitor. Step-5 need to be repeated until the phase margin
A PI controller, with the transfer function as (14), is meets the requirement.
selected in this paper. In Fig.10, bode plots with different 𝑘𝑏𝑤 are
𝐾𝑣𝑁 (1+𝑠𝑇𝑣𝑁 ) pictured, based upon parameters in Table 1. The plots
𝐺𝑣𝑁 (𝑠) = (14)
𝑠𝑇𝑣𝑁 show that (i) the phase plot remains nearly the same
with different 𝑘𝑏𝑤 ; (ii) bigger 𝑘𝑏𝑤 yields higher gain,
where 𝐾𝑣𝑁 is the proportional gain, 𝑇𝑣𝑁 is the
reciprocal of the integral gain expressed as a time however, lower phase margin. The selection of 𝑘𝑏𝑤 is
constant in accordance with normal convention. To a trade-off between the system bandwidth and the
ease the design process, the voltage-open-loop gain is stability margin.
written in a standard form as below
𝐾𝑖𝑁 𝐶𝑒𝑞𝑢 𝑇𝑣𝑁 𝑠 2 + 𝐾𝑣𝑁 𝑇𝑣𝑁 𝑠 + 𝐾𝑣𝑁 −(𝑁+0.5)𝑇 ∙𝑠
𝐺𝐹𝑊𝑣𝑁 (𝑠) = ∙𝑒 𝑠
𝑇𝑣𝑁 𝑠(𝐿𝑁 𝐶𝑒𝑞𝑢 𝑠 2 + 𝑅𝑁 𝐶𝑒𝑞𝑢 𝑠 + 1)

𝑠2 𝑠
( 2 +2𝜁 +1)
𝜔 𝜔𝑛
= 𝐾𝐹𝑃 𝑛
𝑠2 𝑠
∙ 𝑒 −(𝑁+0.5)𝑇𝑠∙𝑠 (15)
𝑠( 2 +2𝜁𝑟 +1)
𝜔𝑟 𝜔𝑟

𝐾𝑣𝑁 𝐾𝑣𝑁
where 𝐾𝐹𝑃 = , 𝜔𝑛 = √ ,𝜁 =
𝑇𝑣𝑁 𝐾𝑖𝑁 𝐶𝑒𝑞𝑢 𝑇𝑣𝑁

1 𝐾𝑣𝑁 𝑇𝑣𝑁 1 1 𝐶𝑒𝑞𝑢

√𝐾 , 𝜔𝑟 = , and 𝜁𝑟 = 𝑅𝑁 √ .
2 𝑖𝑁 𝐶𝑒𝑞𝑢 √𝐿𝑁 𝐶𝑒𝑞𝑢 2 𝐿𝑁
The resonant pole of 𝐿𝑁 and 𝐶𝑒𝑞𝑢 introduces a
phase shift of −𝜋 at the resonant frequency 𝜔𝑟 . On
Fig. 10. Bode plot of the open-loop transfer function
the premise that 2𝜋𝑓𝑠𝑤 is much higher than 𝜔𝑟 , the
closed loop system will be stable if the un-damped
natural frequency 𝜔𝑛 is lower than 𝜔𝑟 [25]. 𝜔𝑛 <
𝜔𝑟 with sufficient damping is necessary to ensure the
system stability. Two prerequisites then need to be
satisfied:

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Transactions on Transportation Electrification

Start controller. For simplicity, only equations and

conclusion are given here. Again the capacitor current
is selected as the feeding term. The maximum control
STEP-1
Calculate the maximum
System Parameters:
RN, LN, CN1, CN2, Ts, N
bandwidth can be written as
bandwidth of control loop ωcN_max
Design Specification: 𝜋⁄2−∅𝑚𝑝ℎ
(18)
using Equ. (10) and the maximum
gain of KiN_max using Equ. (12). ϕmN, ϕrN 𝜔𝑐𝑝ℎ_𝑚𝑎𝑥 =
(𝑁+0.5)𝑇𝑠

where ∅𝑚𝑝ℎ is defined as the required stability

STEP-2
phase margin. Then the maximum value of 𝐾𝑖𝑝ℎ is
Select kbw =1 as the initial
value, calculate ωcN and KiN.

𝐾𝑖𝑝ℎ_𝑚𝑎𝑥 = √(𝐿𝑓 𝜔𝑐𝑝ℎ_𝑚𝑎𝑥 )2 + 𝑅𝑓2 ≈ 𝐿𝑓 𝜔𝑐𝑝ℎ_𝑚𝑎𝑥 (19)

STEP-3

Calculate ωr and  r ,
System Parameters:
RN, LN, CN1, CN2, Ts, N
The related term is observed as virtual impedance in
Select krn >1 (e.g. krn = 1.2),
Design Specification: parallel to the filter capacitor, where the virtual
calculate ωn and  .
ϕmN, ϕrN impedance is defined as
𝐿𝑓 𝑠+𝑅𝑓 𝐿𝑝ℎ
Back to STEP-2 STEP-4 𝑍𝑝ℎ,𝑉𝐼 (𝑠) = 1 ≈ (20)
−(𝑁+2)𝑇𝑠 𝑠 𝐾𝑖𝑝ℎ 𝐶𝑓
Decrease kbw with Calculate the parameters 𝐾𝑖𝑝ℎ 𝐶𝑓 𝑠𝑒
predefined kbw. of PI controller.

The equivalent circuit can be found in Fig.13.

STEP-5
Draw bode plots of iLf R f Lf
forward path loop transfer


function.

Lf iCf
no Meet phase margin
u ph Z ph ,VI  i ph
specification? K iph C f Cf
yes 
Stop

Fig. 13. Block diagram of the phase leg

Fig. 11. Design process of the neutral-point control loop
To accurately track or suppress a periodic
V. PHASE CONTROLLER DESIGN disturbance, its internal model must be established
[27]. Mathematically, a periodic signal could be
Each phase is able to be regulated independently decomposed into the sum of a set trigonometric series
once a stable neutral point is provided. In fact, the using Fourier Series. Therefore in this paper, the PIR
analysis and design process of the phase controller is controller is used for output voltage loop as below.
quite similar to the neutral-voltage control design
𝐾𝑣𝑝ℎ (1+𝑠𝑇𝑣𝑝ℎ ) 𝐾𝑟ℎ_𝑣𝑝ℎ 𝑠
since the control plant can be abstracted into the 𝐺𝑣𝑝ℎ (𝑠) = + ∑ℎ (21)
𝑠𝑇𝑣𝑝ℎ 𝑠 2 +2𝜔𝑐ℎ 𝑠+(ℎ𝜔𝑓 )2
identical mathematical model. Meanwhile, two
noteworthy features of the phase voltage controller where 𝐾𝑣𝑝ℎ is the proportional gain, 𝑇𝑣𝑝ℎ is the
should be emphasized: (i) the resonant frequency of reciprocal of the integral gain, h is the order of
the LC filter is quite high, especially when SiC selected harmonics, 𝐾𝑟ℎ_𝑣𝑝ℎ is the gain of the
devices are deployed; (ii) nonlinear and imbalanced resonant term at fundamental and selected harmonic
loads need more attention. frequencies, 𝜔𝑐ℎ is the cutoff bandwidth and 𝜔𝑓 is
Similar to the neutral point controller, a virtual
the fundamental frequency. It is worth pointing out
resistor emulation-based technique is adopted to damp
that the proportional term provides a high gain in the
the resonance of the LC filter. Again, the
low frequency range, securing the fast dynamic
computational and transport time delay is considered,
response. Meanwhile, a PIR controller has better
as shown in Fig. 12.
capability of suppressing low frequency disturbance.
To tune parameters, the asymptotic bode plot of the
iph
- -
PIR controller is analyzed here. As the frequency is far
uref + + uph iLf + iCf 1 uo
away from the resonant frequency ℎ𝜔𝑓 ,
1 + 1
Gvph ( s )  ( N  )Ts s
e 2
Lf s  Rf Cf s
- -
×
+ 1 × 𝐾𝑣𝑝ℎ (1+𝑠𝑇𝑣𝑝ℎ )
+
Gvph ( s )
Kiph Cf s
𝐺𝑣𝑝ℎ (𝑗𝜔) ≈ (22)
𝑠𝑇𝑣𝑝ℎ

The resonant term dominant with very high gain at

Fig. 12. The block diagram of phase-voltage-loop controllers the specific selected resonant frequency 𝑘𝜔𝑓 then is
In Section IV, a comprehensive illustration of the 𝐾𝑟𝑘_𝑣𝑝ℎ
𝐺𝑣𝑝ℎ (𝑠) ≈ (23)
physical meaning and design method of the virtual 2𝜔𝑐ℎ
impedance term has been proposed. The same
The bode plot of a PIR controller and PI controller
methodology is employed for the phase voltage
is then compared in Fig.14. It shows a drastic change

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Transactions on Transportation Electrification

of both the magnitude and phase at selected resonant multi-resonant term at the corresponding resonant
frequencies. For the magnitude, each resonant term frequency. Multi-resonant gains are chosen by setting
generates a very high gain at specific resonant the open-voltage-loop gain equal to specified dB at
frequency, which allows the controller to reject the multi-resonant frequencies so that steady-state errors
disturbance caused by nonlinear loads. It only has a at these frequencies comply with THD requirements.
strong effect in the vicinity of the specific resonance In this paper,
frequency, and could be ignored when the frequency is
away from the resonance frequency. 20𝑙𝑔|𝐺𝐹𝑊𝑣𝑝ℎ (𝑗3𝜔𝑓 )| = 60𝑑𝐵 = 𝑀3
20𝑙𝑔|𝐺𝐹𝑊𝑣𝑝ℎ (𝑗5𝜔𝑓 )| = 40𝑑𝐵 = 𝑀5 (28)
20𝑙𝑔|𝐺𝐹𝑊𝑣𝑝ℎ (𝑗7𝜔𝑓 )| = 40𝑑𝐵 = 𝑀7
{ …

Therefore
𝑀ℎ
𝐾𝑟ℎ_𝑣𝑝ℎ = 2 ∙ 10 20 ∙ 𝜔𝑐ℎ (30)
Lastly, the voltage-open-loop bode plot is redrawn
as the red curve in Fig.15, indicating the phase margin
requirement is met without sacrificing the dynamic
performance.

Fig. 14. Block plots of PI and PIR controllers

Based on the analysis above, the PIR controller can

be first observed as a PI controller. Thereafter, the
coefficients of the resonant term will be investigated.
The method of designing the PI controller is already
proposed with details in Section IV and will not be
repeated here. The voltage open-loop transfer function
is shown as below.
𝐾𝑖𝑝ℎ 𝐶𝑓 𝑇𝑣𝑝ℎ 𝑠 2 + 𝐾𝑣𝑝ℎ 𝑇𝑣𝑝ℎ 𝑠 + 𝐾𝑣𝑝ℎ −(𝑁+0.5)𝑇 ∙𝑠
𝐺𝐹𝑊𝑣𝑝ℎ (𝑠) = ∙𝑒 𝑠
𝑇𝑣𝑝ℎ 𝑠(𝐿𝑓 𝐶𝑓 𝑠 2 + 𝑅𝑓 𝐶𝑓 𝑠 + 1)

𝑠2 ′ 𝑠
( 2+2𝜁 𝜔′ +1)
𝜔′𝑛 𝑛
= ′
𝐾𝐹𝑃 𝑠2 𝑠
∙ 𝑒 −(𝑁+0.5)𝑇𝑠 ∙𝑠 (24)
𝑠( 2+2𝜁𝑟′ ′ +1)
𝜔𝑟′ 𝜔 𝑟 Fig. 15. Bode plot of the open voltage-loop transfer function

𝐾𝑣𝑝ℎ 𝐾𝑣𝑝ℎ
′
Where 𝐾𝐹𝑃 = , 𝜔𝑛′ = √ , The flow chart of the design process is shown in
𝑇𝑣𝑝ℎ 𝐾𝑖𝑝ℎ 𝐶𝑓 𝑇𝑣𝑝ℎ Fig.16.
1 𝐾𝑣𝑝ℎ 𝑇𝑣𝑝ℎ 1 1 𝐶
𝜁′ = √ , 𝜔𝑟′ = , and 𝜁𝑟′ = 𝑅𝑓 √ 𝑓 .
2 𝐾𝑖𝑝ℎ 𝐶𝑓 √𝐿𝑓 𝐶𝑓 2 𝐿𝑓
Two factors are defined as
′ 𝜔𝑟′ ′ 𝜔𝑐𝑝ℎ
𝑘𝑟𝑛 ≜ ′ > 1, 𝑘𝑏𝑤 ≜ ≤1 (25)
𝜔𝑛 𝜔𝑐𝑝ℎ_𝑚𝑎𝑥

The damping ratio is

𝜁 ′ = 𝜁𝑟′ (26)
Before the gain of the multi-resonant term is chosen,
at a specific resonant frequency 𝑘𝜔0 we have
𝐾𝑣𝑝ℎ (1 + 𝑗𝑘𝜔0 𝑇𝑣𝑝ℎ )
𝐺𝑣𝑝ℎ (𝑗𝑘𝜔0 ) =
𝑗𝑘𝜔0 𝑇𝑣𝑝ℎ
𝑗𝑘𝜔0 𝐾𝑟ℎ_𝑣𝑝ℎ
+∑
(𝑗𝑘𝜔0 )2 + 2𝜔𝑐ℎ (𝑗𝑘𝜔0 ) + (ℎ𝜔𝑓 )2
ℎ

𝐾𝑣𝑝ℎ (1 + 𝑗𝑘𝜔0 𝑇𝑣𝑝ℎ ) 𝐾𝑟ℎ_𝑣𝑝ℎ 𝐾𝑟ℎ_𝑣𝑝ℎ

≈ + ≈
𝑗𝑘𝜔0 𝑇𝑣𝑝ℎ 2𝜔𝑐ℎ 2𝜔𝑐ℎ
(27)
Namely the kth-order resonant gain dominates the

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Start
Tab.1 PARAMETER OF INVERTER
STEP-1 System Parameters:
Calculate the maximum control Rph, Lph, Cph, Ts, N Item Quantity
loop bandwidth ωcph_max using
Equ. (18) and the maximum gain Design Specification:
of Kiph_max using Equ. (19). ϕmph, ϕrph Phase filter inductance: Lf 120µH

Phase inductor resistance: Rf 50mΩ

STEP-2

Select k'bw =1 as the initial Phase filter capacitance: Cf 30μF

value, calculate ωcph and Kiph.

DC link capacitance: CN1 220μF

STEP-3 System Parameters: DC link capacitance:CN2 220μF
Rph, Lph, Cph, Ts, N
Calculate ω'r and  r ,
'

select k'rn >1 (e.g. k'rn = 1.2), Design Specification:

calculate ω'n and  .
'
ϕmph, ϕrph Neutral point filter inductance: Ln 120μH

Neutral inductor resistance: Rn 50mΩ

Back to STEP-2 STEP-4
Decrease k'bw with Calculate the parameters Maximum phase current: Iph_rms 30A
predefined k'bw. of PI controller.
DC-bus voltage: Udc 500V
STEP-5
Output line-line voltage: Ug 208Vrms
Calculate the coefficients of
resonant term.
Output frequency: fo 60Hz

STEP-6 Switching frequency: fsw 50kHz

Draw bode plots of
forward path loop transfer
function. The overall voltage oscillation across the whole DC
link is then
4𝜋
2𝑈𝑚 |∆𝐼𝑏 𝑠𝑖 𝑛(2𝜃− 3 )+∆𝐼𝑐 𝑠𝑖𝑛(2𝜃+4𝜋/3)|
no Meet phase margin ∆𝑈 = (33)
specification? 𝐶𝑈𝐷𝐶
𝜋 1 ∆𝐼𝑏 +∆𝐼𝑐
yes
Here 𝜃 = + 𝑡𝑎𝑛−1 ( ). (33) can be used
2 2 √3(∆𝐼𝑐 −∆𝐼𝑏 )
Stop
as the reference in the test of the load imbalance to
restrain the overall voltage ripple to a reasonable
Fig. 16. Flow chart of phase-voltage control-loop design process range.
VI. SIMULATION AND EXPERIMENTAL RESULTS A. Comparison Study of dynamic performance
Inverter parameters are listed in Table 1. The To confirm the validity and optimality of the
studied VSI under unbalanced and nonlinear loads is proposed controller design, a comparison study
simulated to verify the proposed design methodology, focusing on the dynamic response of the neutral-point
based on which control parameters were analytically control is implemented. Two cases below are
derived. The performance of the inverter in steady and investigated in this paper.
transient states then is simulated and tested. The Case I: 𝑘𝑏𝑤 = 1, meaning the maximum bandwidth
overall capacitance of the DC link is 110µF, to save limited by the control system is adopted;
the size and the weight. Such small capacitance faces Case II: 𝑘𝑏𝑤 = 0.6 , meaning less aggressive
the challenges once the three-phase load is imbalanced. coefficient is selected.
Assume the load is the resistive type, with imbalance The bode plot of the open-loop transfer function has
happening on phase-B and phase-C. The load current been illustrated in Fig.10, from which one can see
is increased by ∆𝐼𝑏 , and ∆𝐼𝑐 respectively, i.e., both cases obtain sufficient phase margin. Meanwhile,
Case I has higher magnitude compared to Case II.
𝐼𝑎 = √2 ∗ 𝐼𝑚 ∗ 𝑐𝑜𝑠 𝜔𝑡 Theoretical, Case I is projected to achieve better
𝐼𝑏 = √2 ∗ (𝐼𝑚 + ∆𝐼𝑏 ) ∗ 𝑐𝑜𝑠 (𝜔𝑡 − 𝜋)
2 performance in both steady states and dynamic
3
processes. Simulation results are shown in Fig.17. The
2
𝐼𝑐 = √2 ∗ (𝐼𝑚 + ∆𝐼𝑐 ) ∗ 𝑐𝑜𝑠 (𝜔𝑡 + 𝜋) neutral-point current has the step change at t=0.05s
{ 3
(31) from 𝐼𝑁 to 0.1𝐼𝑁 , respectively. Case I obtains smaller
errors at the steady state and faster convergence rate
The neutral-point is balanced well with three-phase than Case II.
voltage regulated as

𝑈𝑎 = √2 ∗ 𝑈𝑚 ∗ 𝑐𝑜𝑠 𝜔𝑡
2
𝑈𝑏 = √2 ∗ 𝑈𝑚 ∗ 𝑐𝑜𝑠 (𝜔𝑡 − 𝜋)
3
2
𝑈𝑐 = √2 ∗ 𝑈𝑚 ∗ 𝑐𝑜𝑠 (𝜔𝑡 + 𝜋)
{ 3
(32)

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Transactions on Transportation Electrification
Fig. 17. Dynamic response of the neutral point control in time domain
Similar comparison is carried out on the phase
output voltage. Two cases are illustrated as follows.
Case I’: 𝑘𝑏𝑤 = 1 , meaning the maximum
bandwidth limited by the control system is adopted;
Case II’: 𝑘𝑏𝑤 = 0.8 , meaning less aggressive
coefficient is selected.
Simulation results are shown in Fig.18, where the
phase load current has a step change from 0.5𝐼𝑁 to
𝐼𝑁 at t=0.05s. In both cases, the output voltage
converges to the reference value, although the
comparison confirms that Case I’ achieves a better
dynamic response compared to Case II’, i.e., faster
converging speed. This validates the effectiveness of
the proposed controller design methodology for both
the neutral point and the phase voltage.
Fig. 18. Output voltage and load current of Phase A (overall-left,
zoomed-right)
B．Steady-State Analysis
The simulation result in steady states is as shown in
Fig.19. The inverter works at the autonomous mode,
generating a three-phase 208VAC grid for an
extremely nonlinear load, a diode rectifier. At the
same time, a 10A 5 th-order harmonic current is added
on Phase A, causing the imbalance of the load current.
Simulation results show three phase output voltages
are still well balanced with high power quality. Each
phase is controlled independently, thanks to the solid
neutral point provided by the fourth leg. Fourier Series
analysis on the output voltage of Phase A shows the
voltage THD is 2.48% and the voltage unbalanced
factor is less than 1% in steady states.
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Fig. 19. Simulation of phase voltage and load current under the diode
rectifier with the load imbalance.
Based on all theoretical analysis and simulation
results performed in previous sections, a three-phase
four-wire bi-directional on-board charger is
successfully prototyped to verify the control strategy.
The initial system setup is as shown in Fig. 20(a). The
whole charger contains two stages. In addition to the
three-phase four-wire inverter used as the AC/DC
stage, the other stage is a bidirectional DC/DC
converter. To realize the high-efficiency and
high-power density, SiC MOSFETs SCT3030KL and
SCT3022AL are applied for AC/DC and DC/DC
stages, respectively. A Digital Signal Processor
TMS320F28335 is used for each stage. The switching
frequency of the DC/DC stage is 100k~200kHz and
that of the PFC stage is 50kHz. The on-board battery
pack has the voltage range of 250~400VDC and the
expected output voltage is three-phase 208~480VAC.
The DC/DC stage employs the voltage control to keep
the DC-bus voltage of ~500V. Since the focus of this
paper is on the inverter stage, the DC/DC part will not
be detailed and can be referred to [25]. Shown in Fig.
20(b) is the charger equipped with the water-cooling
system. The overall test bench is shown in Fig. 20(c).
The maximum operation power is 8.8kW, as shown in
Fig. 20(d)~(f). When the three-phase load is balanced,
the three-phase 208VAC (line-line voltage) is obtained
even when the load is the three-phase motor, as shown
in Fig.20(g). The voltage distortion of the output
voltage can be further enhanced by adding more
filtering capacitor at the grid side.
The dynamic performance is tested by stepping up
1.2kW more in one phase while keeping the other two
phases unchanged, as shown in Fig. 21. Without any
neutral-point control, the three-phase voltage lost
symmetry, as shown in Fig.21(a). Besides, a
neutral-point voltage oscillation as high as 40V is
observed, as shown in Fig. 21(b). Once the
neutral-point balancing control is applied, it shows a
strong impact on the three-phase output, as shown in
Fig. 21(c). Three-phase voltage gets little affected by
the sudden load change. The DC bus voltage is shown
in Fig. 21(d), where the DC-bus oscillation is
drastically suppressed down to 5V. Such experiments
validated the effectiveness of the neutral-point control.
More importantly, all parameters of the controller
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TTE.2019.2957635, IEEE
Transactions on Transportation Electrification

were directly calculated by analytical equations. No

extra engineering debugging effort was consumed.

Fig. 20(e). V2G waveforms

Fig. 20(a). Component layout inside the enclosure

Fig. 20(f). Three-phase output voltage and current with the resistor
load

Fig. 20(b). The prototyped EV charger (AC/DC + DC/DC) with the

water-cooling system

Fig. 20(g). Three-phase output voltage and current when driving a

motor

Fig. 20(c). The overall test bench

Fig. 21(a). Three-phase voltage and current during the load step-up,
without the neutral-point balancing control

Fig. 20(d). G2V PFC waveforms

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TTE.2019.2957635, IEEE
Transactions on Transportation Electrification

Fig. 22(a). Output waveforms without virtual resistor at 5kW

Fig. 21(b). Voltage of split DC-link capacitors, without the
neutral-point balancing control

Fig. 22(b). Output waveforms with virtual resistor at 5kW

Fig. 21(c). Three-phase voltage and current during the load step-up,
with the neutral-point balancing control

Fig. 22(c). Increase output power from 1kW to 1.33kW

120
Fig. 21(d). Voltage of split DC-link capacitors, with the Without Virtual Resistor
neutral-point balancing control 100
Fundamental frequency
Mag(% of Fundamental)

Fig.22(a) shows the output voltage without the

80

virtual resistor, yielding tremendous grid-voltage 60

Resonant frequency Switching frequency
harmonics. Fig.22(b) shows the output voltage with 40

the virtual resistor, where the output-voltage quality is 20

much improved. Fig.22(c) shows power-stepping
waveforms based on the simulation parameters (𝑘𝑏𝑤 = 0
0 5 10 15 20 25 30 35 40 45 50
Frequency (kHz)
1, 𝑘𝑖𝑝ℎ = 1.57). The output voltage remains relatively
stable. Fig.22(d) and (e) compared inverter PWM Fig. 22(d). FFT analysis of Phase-A voltage, without virtual
voltage without and with the virtual resistance. With resistance
the virtual resistance, most of harmonics have been
120 With Virtual Resistor
pushed to the high-frequency zone, much easier to be Fundamental frequency
filtered out. 100
Mag(% of Fundamental)

All the coefficients were obtained based on the 80 Switching frequency

calculation according to the analytic expressions 60

above. When implemented in the real time controller, 40

the bilinear transformation below is used to transform
the derived coefficients from the continuous to
20

discrete systems. 0
0 5 10 15 20 25 30 35 40 45 50

2 𝑧−1 Fig. 22(e). FFT analysis of Phase-A voltage, with virtual resistance
𝑠= (34)
𝑇𝑠 𝑧+1

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TTE.2019.2957635, IEEE
Transactions on Transportation Electrification
VII. CONCLUSION
This paper has provided a design methodology of
controllers in a three-phase four-wire voltage-source
inverter. A neutral leg with split DC-link capacitors
provides a stable neutral point, even with extremely
unbalanced loads. As the output voltage quality is
vulnerable under the autonomous mode with nonlinear
load, a voltage controller with a harmonics
compensator and virtual resistance is presented to
address this problem. The optimized design method of
controller is comprehensively analyzed in the
frequency domain, and analytical formulas were given
with the time delay considered. Thanks to the
stabilized neutral point, three-phase legs could be
controlled independently. At last, the simulation and
experiment are carried out on a bidirectional EV
battery charger, which is capable of G2V, V2G and
V2L to investigate the performance of designed
controllers in both steady states and transient states.
Given a lot of controller design in previous
literatures are highly empirical, or based upon
time-consuming numerical analysis, the main purpose
of this paper is to provide an overall design framework,
based upon which electrical engineers could
analytically derive all controller parameters for
specific inverter systems. This will save tremendous
debugging effort. So far the system was tested up to
8.8kW, with the maximum efficiency of ~97%. The
future work will emphasize more on the higher power
with various types of other loads, and optimize this
prototype layout to enhance its power density.
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Yongsheng Fu Received the B.S.
and M.S. Degrees from Xi’an
Technological University
ShannXi, China in 2010 and
2013, respectively. He was a
research scholar in Department
of Electrical and Computer
Engineering, Kettering
University, MI, in 2013~2014,
and a research fellow in ECE
Department, University of
Michigan Dearborn, in 2017~2018. He is currently a
lecturer at Xi’an Technological University, ShaanXi,
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TTE.2019.2957635, IEEE
Transactions on Transportation Electrification

China. His research interests include weak signal Ke Zou got his BS and MS
detection and processing, wireless power transfer and degrees from Xi`an Jiaotong
power electronics for electric vehicles. University, China in 2005 and
2008, respectively. He
Yu Li (S'18) was born in
received his Ph.D degree from
Shandong, China. He received the
M.S. degree in school of
the Ohio State University in
automation in Northwestern 2012. He is currently with
Polytechnical University, Xian, Ford Motor Company in
China in 2012. From 2012 to 2013, Dearborn, MI. His research
he worked in Bosch Rexroth interests include the design of
company as a hardware engineer. traction drive inverters in hybrid electric vehicles
From 2013 to 2015, he worked as (HEV), on-board and off-board chargers and the
a research engineer in Department characterization of power semiconductor devices.
of Electrical and Computer Engineering, Kettering
University, MI, USA. He is currently a Ph.D. candidate Xi Lu received the B.S.
at the School of Electrical Engineering, Shandong degree from Huazhong
University, Jinan, China. His research interests include University of Science and
power electronics, renewable energy, distributed
Technology, Wuhan, China,
generation, power quality, and microgrids.
in 2007, and M.S. and Ph.D.
Yang Huang received his BS degree from Michigan State
degree in Department of University, East Lansing,
Electrical Engineering of MI, USA, in 2012 and 2014
Southeast University, Nanjing, respectively. Since 2013,
China in 2016 and the Master she has been with Ford Motor Company as a Power
degree in Electrical Engineering Electronics Research Engineer. Her current research
from the University of interests include traction inverter and
Michigan-Dearborn, MI, USA in on-board/off-board charger.
2018. He is currently pursuing a
Power Electronics Ph. D degree in Chingchi CHEN received
the Department of Electrical and a Ph.D. degree in 1994
Computer Engineering, University of from the University of
Tennessee-Knoxville, TN, USA. His research interests Wisconsin-Madison, in
include on-board/off-board EV charger design, FPGA Electrical Engineering.
based motor drive, common-mode voltage reduction and Since then, he has been
magnetic simulation and design. with the Ford Research &
Advanced Engineering,
Hua Bai (M-10’, SM-19’) leading power electronics
received B S and PHD
research for on-vehicle applications. He has been
degree in Department of
working on various areas in power electronics for
Electrical Engineering of
automotive applications, including topology
Tsinghua University, Beijing,
China in 2002 and 2007, evaluation, dynamic analysis, reliability assessment,
respectively. He was a WBG technology evaluation, and package design.
postdoctoral fellow and
research scientist in Univ of
Michigan-Dearborn, USA,
in 2007 and 2009,
respectively. He was an assistant professor in
Department of Electrical and Compurter Engineering,
Kettering University, MI, USA in 2010~2016. In
2017~2018 he joined University of Michigan-Dearborn
as associate professor. He is currently the associate
professor in EECS, University of Tennessee, Knoxville.
His research interest is power electronic modelling,
control and integration including variable frequency
motor drive system, high-voltage and high-power
DC/DC converter, electric vehicle battery chargers and
various wide-bandgap device applications.

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