Bahir Dar University

Faculty of Electrical and Computer

Engineering

Computer Architecture and Organization

[CoEg3091]
Chapter Two
Computer Modules

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 The computer system 2

In this chapter:
 Basic Computer Components and Function
 Interconnection Structure
 Bus Interconnection

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 Computer components 3

As discussed in Chapter 1, Virtually all contemporary

computer designs are based on von Neumann architecture
Key concepts:
 Data and instructions stored in a single R-W memory
 Contents are addressable by location
 Execution is sequential
Components reconfigured as application changes (called
programming)
Resulting “program” – hardwired program

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 Computer components 4

Another alternative:
 General purpose configuration of components (ALU)
 System accepts data and control signals and produce
results
 New set of control signals instead of rewiring hardware
 how control signals are supplied:
o The entire program is sequence of steps
o For each step, new set of control signals is needed
o Provide a unique code for each possible set of
control signals
o The sequence of codes/instructions is called
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software.
 Computer components 5

The above two components constitute the CPU

Other components:
 I/O components: for moving data into and out of
system
 Memory: to store instructions and data temporarily
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 Computer components 6

Central Processing Unit

 Control Unit
 Arithmetic and Logic Unit
 Registers
Input/output
 Data and instructions need to get into the system and
results out
Main Memory
 Temporary storage of code and results is needed
Interconnection structures
 Bus
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 Computer components 7

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 Computer function 8

Basic function: execution of a program

Two steps of program execution:
 Fetch
 Execute
Instruction cycle – the processing required for a single
instruction (i.e fetch and execute cycles)

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 Fetch cycle Instruction cycle 9

 Program Counter (PC) holds address of next

instruction to fetch
 Processor fetches instruction from memory location
pointed to by PC
 Increment PC
o Unless told otherwise
 Instruction loaded into Instruction Register (IR)
 Processor interprets instruction
 Instructions contain bits that specify action the
processor is to take
 These actions fall into 4 categories: Processor-memory,
Processor I/O, Data processing, Control
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 Instruction cycle 10

Execute cycle:
 Processor-memory
o Data transfer between CPU and main memory
 Processor I/O
o Data transfer between CPU and I/O module
 Data processing
o Some arithmetic or logical operation on data
 Control
o Alteration of sequence of operations
o e.g. jump
 Instruction execution may involve combination of the
above
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 Example of Program Execution 11

Example – consider the following machine:

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 Example of Program Execution 12

Program:
AC ← M(940)
AC ← AC + M(941)
M(941) ← AC

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 Instruction Cycle State Diagram 13

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 Interrupts 14

Interrupt
 Mechanism by which various events (e.g. I/O) may
interrupt normal sequence of processing
 Classes of interrupts:
o Program
• Overflow, division by zero, etc.
o Timer
• Generated by internal processor timer
• Used in pre-emptive multi-tasking
o I/O
• From I/O controller
o Hardware failure
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 Interrupts 15

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 Instruction cycle with interrupt 16

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 State diagram with interrupt 17

Reading Ass.: more on interrupts – text, pp 64-73

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 Interconnection Structures 18

All the components should be connected

Collection of paths connecting modules
Design depends on exchanges made b/n modules
Different type of connection for different type of unit
 Memory
 Input/Output
 CPU

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 Interconnection Structures 19

Memory connection
 Receives:
−Data
−Addresses (of locations)
−Control signals
−Read
−Write
−Timing
 Sends
−Data

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 Interconnection Structures 20

I/O connection
 Receives
−Control signals from computer
−Addresses from computer
−e.g. port number to identify peripheral
−Data from computer
−Data from peripheral
 Sends
−Control signals to peripherals
−e.g. spin disk
−Data to peripherals
−Data to computer
−Control signals to computer
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−Interrupts
 Interconnection Structures 21

CPU connection
 Receives
−Instructions
−Data
−Control
−interrupts
 Sends
−Data
−Address
−Control signals to other units

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 Interconnection Structures 22

The interconnection structure must support the

following types of transfers:
 Memory to processor: processor reads instruction or a
unit of data from memory
 Processor to memory: processor writes a unit of data to
memory
 I/O to processor: processor reads data from I/O device
via I/O module
 Processor to I/O: processor sends data to I/O device
 I/O to/from mem: I/O module exchanges data directly
with memory (DMA)

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 Bus Interconnection 23

Various interconnection structures have been tried

Most common – a single bus or multiple bus structures
Examples:
 Control/Address/Data bus (PC)
 Unibus (DEC-PDP)
BUS:
 Communication pathway connecting two or more
devices
 Usually broadcast
 Often grouped
 A number of channels in one bus
 e.g. 32 bit data bus is 32 separate single bit channels
 Power lines may not be shown
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 Bus Interconnection Scheme 24

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 Bus Interconnection 25

Data bus:
 Carries data
 Remember – no difference between “data”
and “instruction” at this level
 Bus width
 key determinant of performance
 typically 8, 16, 32, 64 bit

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 Bus Interconnection 26

Address bus:
 Identifies the source or destination of data
 e.g. CPU needs to read an instruction (data)
from a given location in memory
 Also used to address I/O ports
Bus width
 determines maximum memory capacity of
system
 e.g. 8080 has a 16 bit address bus giving 64k
address space

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 Bus Interconnection 27

Control bus
 Control and timing information
 Memory read/write signal
 I/O read/write signals
 Bus arbitration signals – requests, grants
 Interrupt signals – requests, acknowledgments
 Clock signals

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 General Bus Operation 28

Send data
 Obtain use of bus
 Transfer data
Request data
 Obtain use of bus
 Transfer request for data
 Wait for data

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 Physical Bus Architecture 29

What do buses look like?

 Parallel lines on circuit boards
 Ribbon cables
 Strip connectors on mother boards
 e.g. PCI
 Sets of wires

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 Physical Bus Architecture 30

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 Single Bus Problems 31

Lots of devices on one bus lead to:

 Increased bus length
 Propagation delays
 Complex, time consuming coordination of bus
use
 Bus becomes bottleneck
 aggregate data transfer approaches bus
capacity
Solution – multiple buses

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 Traditional Bus (with cache) 32

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 High Performance Bus 33

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 Readings 34

Text:
 Chapter 3, 73-94

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 35

THANK YOU!!!!

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