electronics
Article
A Nonisolated Transformerless High-Gain DC–DC Converter
for Renewable Energy Applications
Mohammad Zaid 1 , Ifham H. Malick 1 , Imtiaz Ashraf 1 , Mohd Tariq 1, * , Basem Alamri 2
and Eduardo M. G. Rodrigues 3,4, *
Citation: Zaid, M.; Malick, I.H.;
Ashraf, I.; Tariq, M.; Alamri, B.;
Rodrigues, E.M.G. A Nonisolated
Transformerless High-Gain DC–DC
Converter for Renewable Energy
Applications. Electronics 2022, 11,
2014. https://doi.org/10.3390/
electronics11132014
Academic Editors: Diego Bellan and
Jelena Loncarski
Received: 4 April 2022
Accepted: 6 June 2022
Published: 27 June 2022
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Copyright: © 2022 by the authors.
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This article is an open access article
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Attribution (CC BY) license (https://
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4.0/).
Electronics 2022, 11, 2014. https://doi.org/10.3390/electronics11132014
1 Department of Electrical Engineering, ZHCET, Aligarh Muslim University, Aligarh 202002, India;
zaidahmadzhcet@gmail.com (M.Z.); ifhmal@gmail.com (I.H.M.); iashrafamu@gmail.com (I.A.)
2 Department of Electrical Engineering, College of Engineering, Taif University, P.O. Box 11099,
Taif 21944, Saudi Arabia; b.alamri@tu.edu.sa
3 INESC-ID, Sustainable Power Systems Group, Av. Rovisco Pais 1, 1049-001 Lisboa, Portugal
4 Instituto Superior Tecnico, University of Lisbon, Av. Rovisco Pais 1, 1049-001 Lisboa, Portugal
* Correspondence: tariq.ee@zhcet.ac.in (M.T.); eduardo.g.rodrigues@tecnico.ulisboa.pt (E.M.G.R.)
Abstract: Dc–dc converters with a high gain, continuous input current, and common ground are usu-
ally employed in renewable energy applications to boost the generated output voltage of renewable
energy sources. In this paper, a high-gain dc–dc converter comprising a voltage multiplier cell (VMC)
and a common ground with continuous input current and low-voltage stress across semiconductor
devices is proposed. The converter produces a voltage gain of about ten times compared to the
conventional boost converter at a duty ratio of 50% by utilizing switched capacitors and switched
inductors. The simultaneous operation of both the switches with the same gate pulse offers easy and
simple control of the proposed converter with a wide range of operations. The boundary operation
of the converter is analyzed and presented in both modes, i.e., continuous conduction mode (CCM)
and discontinuous conduction mode (DCM). Ideal and nonideal analysis of the converter is carried
out by integrating real models of passive elements and semiconductor devices by using PLECS
software. The simulation is also used to calculate the losses and hence the working efficiency of the
converter. The performance of the converter analyzed in the steady state is compared with various
similar converters based on the voltage boosting capability and switching stresses. A hardware
prototype is also developed to confirm and validate the theoretical analysis and simulation of the
proposed converter.
Keywords: dc–dc converter; high gain; low-voltage stress; voltage multiplier cell; nonisolated converter
1. Introduction
High-gain boost converters have gained prominence in recent times due to their
suitability in various applications such as solar PV systems [1], switch-mode power supplies
(SMPS), electric vehicles, and aerospace applications. A conventional boost converter has
certain shortcomings such as discontinuous input and output currents and increased losses
in the system at higher duty cycle operations, which leads to its limited solar PV and fuel
cell applications. The traditional quadratic boost converter (TQBC) shown in Figure 1 uses
a single switch of high voltage and a current rating which results in low efficiency at higher
duty ratios. In the literature, many high-gain dc–dc converters are being published [2,3]
to overcome the limitations of the conventional boost and quadratic boost converter. The
use of coupled inductors, Z-source converters, switched inductors, switched capacitors,
and voltage multiplier cells (VMCs) are popular methods to increase the gain of high-gain
dc–dc converters.
https://www.mdpi.com/journal/electronics
 Electronics 2022, 11, x FOR PEER REVIEW 2 of 28
Electronics 2022, 11, x FOR PEER REVIEW 2 of 28
Electronics 2022, 11, 2014 2 of 26

D2
D2

L1 D1 L2 D0
L1 D1 L2 D0
u S R
uinin C2 S
C0
C0 R
C2

Figure 1. A traditional quadratic boost converter (TQBC).

Figure1.1.AAtraditional
Figure traditionalquadratic
quadraticboost
boostconverter
converter(TQBC).
(TQBC).
Isolated step-up quadratic boost converters are implemented in [4,5] with coupled
Isolatedstep-up step-up quadraticboost boostconverters
convertersare areimplemented
implementedinin[4,5] [4,5]with withcoupled
coupled
inductors that have aquadratic
Isolated high-voltage gain and low switching stress. The converter in [4] has
inductors
inductors that have a high-voltage gain and low switching stress. The converter in
in[4] has
hasa
a voltagethat doublerhavecella high-voltage
and produces gain and low
a higher gainswitching
as compared stress.toThe[5].converter
Soft switched [4]dc–dc
voltage
a converters doubler
voltage doubler cell and
cell and produces
produces a higher gain as compared to [5]. Soft switched dc–dc
converterseliminate eliminate
eliminate the switchingalosses
the switching higher[6,7]
losses gainhowever
as compared
[6,7]however
howevertheir theirto
their
[5]. Soft switched
hardware
hardware implementation
implementation
dc–dc
converters
and operation
operation are the
are difficult. switching
difficult. Various losses
Various Z-source [6,7]
Z-source converters
converters [8–11] hardware
[8–11] havehave been implementation
been proposed
proposed in in the
the
and
and operation are difficult. Variousimpedance
Z-source converters [8–11] have been proposed in the
literature
literaturethat that contains
that contains a
contains aa unique unique
unique impedance network.
network. In In [10], a quasi-Z source converter
literature
is implemented using a switched impedance
capacitor network.
and In [10],
switched [10],aainductor
quasi-Z
quasi-Zsource source converter
configurationconverter is
for
isimplemented
implemented
achieving
using
using
a high-voltage
a switched
a switched
gain
capacitor
along
and switched
capacitor
with low-voltageand switched inductorinductor
configuration
stress on capacitors
for achieving
configuration
and a continu- for
a high-voltage
achieving a gain
high-voltage along with
gain low-voltage
along with stress
low-voltage on capacitors
stress on and
capacitors a continuous
and a input
continu-
ous input
current, but current, but the lacks
the topology topology lacks a common
a common ground. ground. ground.
In [11], In In [11],
the hybrid the quasi-Z
hybrid quasi-Zsource
ous input
source current,
converter but
is the topology
proposed by a lacks a common
combination of traditional Z [11],
source the hybrid quasi-Z
converters.
converter
sourceAconverter is proposed by
is proposed a combination
by a combination of traditional Z
of traditional source converters.
A setset of of nonisolated
nonisolated switched
switched inductors and
inductors and switched Z
switched
source converters.
capacitor
capacitor converters are
converters dis-
are dis-
A
cussed in set of nonisolated
in [12–17].
[12–17]. The switched
The converter
converter proposed inductors
proposed in and
in [12] switched
[12] has
has aa switched capacitor
switched capacitor converters
capacitor and are
and quadratic
quadraticdis-
cussed
cussed
gain with in [12–17].
with The ground
converter proposed in [12] has ripples.
a switched Thecapacitor
converterand quadratic
gain aa common
common ground and and low input
low input current
current ripples. The converter is lightweight
is lightweight
gain
duewithto the
thea common
absence of ofground and lowand input cancurrent ripples. The
solarconverter is lightweight
due to absence aa transformer
transformer and can be utilized
be utilized for solar
for PV applications.
PV applications. In [13],
In [13],
duethe to the
authors absence
have of a
proposed transformer
a switched and can
inductor be utilized
boost for
converter solar PV
that applications.
has low current In stress
[13],
the authors have proposed a switched inductor boost converter that has low current stress
the authors
in inductors
inductors have
butproposed
suffers fromfroma switched inductor boost converter that has lowIncurrent stress
in but suffers aa low-voltage
low-voltage gain
gain and high-switch
and high-switch stresses.
stresses. [14], the
In [14], the twin
twin
induty
inductors
cycle and but suffers
and three from
three switches a low-voltage
switches configuration
configuration add gain and
add to high-switch
to the
the complexity
complexity of stresses.
of the In
the circuit[14], the
circuit [14,15] twin
[14,15] as as
duty cycle
duty cycle and
compared three
to [16]
[16] switches
which has twoconfiguration
two switches followingadd to thethe
following complexity
sameduty duty of cycle.
the circuit [14,15] as
A non-isolated
non-isolated
compared to which has switches the same cycle. A
compared
converterto [16]
is proposedwhichinhas
proposed [17]twoandswitches
has aa simplefollowing
simple design the assame
comparedduty cycle.
to [15,16]
[15,16] A non-isolated
along withwith aa
converter is in [17] and has design as compared to along
converter
high gain is
gain and proposed
and reduced in
reduced voltage[17] and has
voltage stresses a
stresses onsimple switches, diodes, and capacitors.along
design
on switches, as compared to [15,16] It haswith a
high a sym-
high gain and
metrical structure reduced
structure that voltage
that helps
helps to stresses
to ease
ease the on switches,
the choice
choice of of thediodes,
the components and capacitors.
components and its design. It has a sym-
design. In [18],
metrical
metrical
aa single structure
single switch that
switch nonisolated helps to
nonisolated topology ease
topology is the choice
is implemented of the
implemented with components
with low and
low switch its
switch stress. design.
stress. In In
In [19],
[19],[18],
the
the
atransformerless
single switch nonisolated
transformerless converter
convertershown topology
shown in is implemented
inFigure
Figure 22isisproposed.
proposed. withItItlow switch
consists
consists of aastress.
of VMC,In
VMC, with[19],
with the
aa gain
gain
transformerless
of
of six
six times
times thatthatconverter shown inboost
of a conventional Figure 2 is proposed.
converter with aItsingle consistsswitchof a and
VMC, two with a gain
inductors.
ofThesix times
The converter that
converter shown of a conventional
shown in in Figure
Figure 22 hasboost converter
has aa single
single switch with
switch but a single
but the switch
the converter and
converter lacks two inductors.
lacks aa common
common
The converter
ground.
ground. Moreover,
Moreover,shown theininput
the Figure
input 2 has pulsates.
current
current a single switch
pulsates. The but the proposed
The converter
converter converterin
proposed lacks
in this apaper
this common
paper has
has aa
ground.
common Moreover,
ground the
and input
continuous
common ground and continuous input current. current inputpulsates.
current. The converter proposed in this paper has a
common ground and continuous input current.

Switched Capacitors
Switched Capacitors C5
C5
L1 C D2 D1 D D6 D7
L1 C1 1 D2 D1 D5 5 D6 D7
C2
C2
D3 L2 C4 Co R
D3 L2 C4 Co R
Switched Inductor
V C3
Vinin Switched Inductor
based VMC S
based VMC S
C3
D4
D4

Figure 2.
Figure 2. Converter
Converter proposed
proposed in
in [19].
[19].
Figure 2. Converter proposed in [19].
Electronics 2022, 11, 2014 3 of 26

In [20], a modified Ćuk converter is proposed with switched capacitors. The authors
have proposed a buck-boost converter in [21] for renewable energy applications with
continuous input. The converter exhibits high efficiency above 95% around the 56.5% duty
cycle; however, the switching stress also increases drastically. In [22], an extendable boost
converter employing active-passive inductor cells (APIC) is proposed. The efficiency and
voltage gain at a lower duty ratio decrease drastically as the number of APICs is increased.
The authors in [23] have introduced an extended boost converter by implanting a cell
consisting of switched capacitors and inductors between a conventional boost converter.
The converter has the same voltage gain for the complementary duty ratio, which is nearly
constant, while the duty ratio is varied from 30% to 70%. A quadratic boost converter is
proposed in [24]. The gain of the converter is lower as compared to similar topologies.
A variety of quadratic boost converters are introduced in [25–30], each with its set of
advantages and disadvantages. The authors in [25] have proposed a simple quadratic boost
converter, but it lacks a common ground, whereas a modified quadratic boost converter
in [26] is implemented, resulting in twice the gain as compared to the quadratic boost
converter. The converter proposed in [27] has a common ground but a lower gain as
compared to the topology proposed in [28], which lacks a common ground. The quadratic
converter proposed by the authors in [29] has more components as compared to [30] but
has a higher gain at the cost of a decreased efficiency due to increased heat losses.
In this paper, a new transformerless high-gain dc–dc converter is implemented that
employs a VMC to boost the voltage. The attractive features of the proposed topology are
• The converter achieves a high gain of 10 times the conventional boost and 5 times that
of the quadratic boost converter at a 50% duty ratio.
• The converter has low voltage stress of 5% of the output voltage across switch S1 .
• The converter uses the same gate signal for both switches, which leads to its
easy operation.
• The topology has a continuous input current and a common ground, making it feasible
for PV applications.
The paper discusses the structure of the proposed topology and its detailed ideal
analysis in Section 2 followed by the nonideal analysis in Section 3. The comparison of
the proposed topology with various similar converters is carried out in Section 4. The
simulation and the experimental results are presented in Section 5 along with the efficiency
of the proposed converter at different input voltages and power.

2. Structure of Proposed High-Gain DC–DC Converter Topology

The components of the proposed nonisolated dc–dc converter topology depicted in
Figure 3 consist of a fixed DC input voltage source Vin ; two switches (MOSFETs) S1 and S2 ;
three inductors L1 , L2 , and L3 ; seven diodes D1 , D2 , D3 , D4 , D5 , D6 , and DO ; five capacitors
C1 , C2 , C3 , C4 , and CO ; and a resistive load RO with an output voltage of VO . The circuit
also consists of a VMC with elements L2 , L3 , C4 , D5 , and D6 . The nonisolated converter
does not include a high-frequency transformer and hence contributes to its low bulkiness,
size, and cost reduction. This further aids in easier control of the topology as compared to
isolated converters.

2.1. Operation of the Converter in Continuous Conduction Mode (CCM)

The proposed converter operates in two modes in each cycle while working in the
CCM state. Each mode is discussed in detail by providing the voltage and current equations
of each component in both modes.
Mode 1 (0 ≤ t ≤ tO ): In mode 1, both switches S1 and S2 are turned ON simul-
taneously, as shown in Figure 4, by applying the appropriate gate pulse. In this mode,
diodes D2 , D4 , D5 , and D6 are forward-biased, whereas the other diodes D1 , D3 , and DO
are reverse-biased. The inductor L1 is charged through the input voltage source and the
inductors L2 and L3 are charged through the capacitor C3 . The capacitor C3 is discharged,
Electronics 2022, 11, 2014 4 of 26

Electronics 2022, 11, x FOR PEER REVIEW 4 of 28

while the capacitor C5 is charged in this mode. The output capacitor CO discharges and
feeds the load to maintain a constant voltage VO across the output load resistor.
Figure 3. Proposed high-gain dc–dc converter topology.

2.1. Operation of the Converter in Continuous Conduction Mode (CCM)

The proposed converter operates in two modes in each cycle while working in the
CCM state. Each mode is discussed in detail by providing the voltage and current equa-
tions of each component in both modes.
Mode 1 (𝟎 ≤ 𝒕 ≤ 𝒕𝑶 ): In mode 1, both switches 𝑆 and 𝑆 are turned ON simultane-
ously, as shown in Figure 4, by applying the appropriate gate pulse. In this mode, di-
odes 𝐷 , 𝐷 , 𝐷 , and 𝐷 are forward-biased, whereas the other diodes 𝐷 , 𝐷 , and 𝐷
are reverse-biased. The inductor 𝐿 is charged through the input voltage source and the
inductors 𝐿 and 𝐿 are charged through the capacitor 𝐶 . The capacitor 𝐶 is dis-
charged, while the capacitor 𝐶 is charged in this mode. The output capacitor 𝐶 dis-
charges and feeds the load to maintain a constant voltage 𝑉 across the output load resis-
tor.
Figure 3. Proposed high-gain dc–dc converter topology.
topology.

2.1. Operation of the Converter in Continuous Conduction Mode (CCM)

The proposed converter operates in two modes in each cycle while working in the
CCM state. Each mode is discussed in detail by providing the voltage and current equa-
tions of each component in both modes.
Mode 1 (𝟎 ≤ 𝒕 ≤ 𝒕𝑶 ): In mode 1, both switches 𝑆 and 𝑆 are turned ON simultane-
ously, as shown in Figure 4, by applying the appropriate gate pulse. In this mode, di-
odes 𝐷 , 𝐷 , 𝐷 , and 𝐷 are forward-biased, whereas the other diodes 𝐷 , 𝐷 , and 𝐷
are reverse-biased. The inductor 𝐿 is charged through the input voltage source and the
inductors 𝐿 and 𝐿 are charged through the capacitor 𝐶 . The capacitor 𝐶 is dis-
charged, while the capacitor 𝐶 is charged in this mode. The output capacitor 𝐶 dis-
charges and feeds the load to maintain a constant voltage 𝑉 across the output load resis-
tor.

Figure 4.
Figure Conduction diagram
4. Conduction diagram of
of the
the converter
converter in
in ON-state
ON-state (Mode
(Mode 1).
1).

The voltage
The voltage and
and current
current equations
equations across
acrossthetheinductors
inductorsand
andcapacitors
capacitorsduring
duringmode
mode1
when both switches are ON can be expressed as (1) and (2), respectively.
1 when both switches are ON can be expressed as (1) and (2), respectively.
 𝑉 = 𝑉
𝑉 V= L1 𝑉= Vin
(1)


𝑉 = V 𝑉 C0+=𝑉V0

(1)
𝑉 = 𝑉 V =C3𝑉 ==VC1 𝑉 +=VC2−𝑉
𝐼 = 𝐼


⎧ VL2 = VL3 = VC3 = VC5 = −VC4

𝐼 = 𝐼 = 𝐼 = 𝐼 −𝐼
⎪ 
𝐼 = 𝐼 + 𝑖 − IL1 𝐼= =Iin 𝐼 − 𝐼 (2)
⎨  𝐼 = 𝐼

 IC1 = IC2 = ID2 = IS1 − Iin


⎪ IS2 = Iin 𝐼+ iC3
 =− 𝐼 Is1 = IC3 − IC1
⎩  𝐼 I= 𝐼 (2)
 D4 = IC5
of the converterICO = IO

Figure 4. Conduction diagram  
 in ON-state (Mode 1).

IC4 = IL2
The voltage and current equations across the inductors and capacitors during mode
Mode 2 (tO ≤ t ≤ T): In mode 2, both switches S1 and S2 are turned OFF simultane-
1 when both switches are ON can be expressed as (1) and (2), respectively.
𝑉 = 𝑉D1 , D3 and DO are forward-biased, whereas
ously. In Figure 5, it can be seen that diodes
the remainder of diodes D2 , D4 , D5 and𝑉D6=are 𝑉 reverse-biased. In this mode capacitor, C3 is
charged through capacitors C1 and C𝑉2 . Inductors (1)
= 𝑉 + 𝑉 L2 and L3 along with capacitor C4 transfer
power to load and charge, and 𝑉 =capacitor
𝑉 = 𝑉 C= O 𝑉 = − 𝑉 a constant voltage VO about the
maintains
𝐼 = 𝐼
⎧
𝐼 = 𝐼 = 𝐼 = 𝐼 −𝐼
⎪
𝐼 = 𝐼 + 𝑖 − 𝐼 = 𝐼 −𝐼
(2)
⎨ 𝐼 = 𝐼
⎪ 𝐼 = 𝐼
⎩ 𝐼 = 𝐼
Electronics 2022, 11, 2014 5 of 26

load. The voltage and current equations across the inductors and capacitors during Mode 2
when both switches are OFF can be expressed as (3) and (4), respectively.


 VC1 = VC2


 VL1 = Vin + VC1 − VC3 = Vin − VC1
VC0 = V0 (3)
V = VL2 + VL3 + VC4 − VC5 + VCo = VL2 + VL3 + VC4 − VC5 + VO

 C3



VL2 = VL3 = 21 (3 VC3 − V0 )
 − Iin
 IC1 = IC2 = ID1 = ID2 = 2

IC4 = IC5 = IDo = Iin + IC3

Electronics 2022, 11, x FOR PEER REVIEW  IC0 = I0 − Iin − IC3 6 of (4)
28


IL2 = IC4

Figure 5. Conduction diagram of the proposed converter in OFF state (Mode 2).
Figure 5. Conduction diagram of the proposed converter in OFF state (Mode 2).
The ideal voltage gain (M) can be calculated by using the volt-sec balance principle in
The voltages
an inductor in CCMacross the capacitors
operation as per the and inductors
following (shown
relation in Figure
given in (5),6) are represented
in (9) and can be easily evaluated by applying KVL in respective loops as,
 
ZDT ZT
1
VLON dt +(1 − V 𝐷)𝑉
LOFF dt
=0 (5)
⎧ T 𝑉 =𝑉 =
⎪ 0 2(3
DT − 𝐷)
⎪ (1 − 𝐷)𝑉
𝑉 = 2𝑉
Applying the⎪volt-sec principle = inductor L1
in the
⎪ (3 − 𝐷)
⎪ 
DT −(1 − 𝐷)𝑉!
𝑉 1= −R 𝑉V dt = − 𝑉RT = (9)
T in + (Vin −(3V− 𝐷)
C1 ) dt = 0
⎨ 0 𝑉 = 𝑉 V
DT (6)
⎪ VC3
 in
C1 = VC2 =−(𝐷
V(−𝐷)𝑉 1−(1
= 2
D ) − 𝐷)𝑉

⎪ 𝑉 = =
⎪ (1 − 𝐷) 2 (3 − 𝐷)
Applying the⎪volt-sec balance principle to L2
⎪𝑉 −(1 + 𝐷)𝑉 −(1 + 𝐷)𝑉
=
𝑉 = =
⎩ 2 (3 R−
T 𝐷) (1 − 𝐷)
!
DT
1
 R ( 3V C3 − VO )
VC3 dt + dt = 0

T 2
0 DT (7)
 (1− D )VO
VC3 = 2VC1 = (3− D)



Equating Equations (6) and (7)

V0 2(3 − D )
MCCM = = (8)
Vin (1 − D )2

where ‘D’ denotes the duty cycle for switches S1 and S2 .

 Figure 5. Conduction diagram of the proposed converter in OFF state (Mode 2).

Electronics 2022, 11, 2014 The voltages across the capacitors and inductors (shown in Figure 6) are represented
6 of 26
in (9) and can be easily evaluated by applying KVL in respective loops as,

(1 − 𝐷)𝑉
The voltages⎧across the capacitors
𝑉 = 𝑉 and = inductors (shown in Figure 6) are represented
⎪
in (9) and can be easily evaluated by applying2(3KVL
− 𝐷)in respective loops as,
⎪ (1 − 𝐷)𝑉
⎪  𝑉 = 2𝑉 =
VC1 = VC2(3=− 2𝐷)
(1− D )VO
⎪   (3− D )
⎪  −(1
(1−− D )𝐷)𝑉

VO

𝑉 = − 𝑉 VC3== − 𝑉 C1=
2V =


 (3− D )
(3 −−(𝐷) (9)
1− D )V
⎨ 

VC4 = −𝑉VC5==𝑉−VC3 = (3− D) O
⎪  (9)
⎪ 𝑉 (−𝐷)𝑉 VC0 −= 𝐷V(1
0 − 𝐷)𝑉
= =


⎪   VL1(1 = (− D)Vin = − D2((𝐷)
OFF− 𝐷)(1− D ) 2 (3 −
1− D )VO
3− D )
⎪ 

−(1 + 𝐷)𝑉
−( 1 + D )Vin−(1 +
= −(𝐷)𝑉1 + D )VO

⎪𝑉 VL2 = V =

=OFF
𝑉 =
L3OFF 2(3− D=) (1− D )2
⎩ 2 (3 − 𝐷) (1 − 𝐷)

Figure
Figure 6.
6. Inductor
Inductorvoltages.
voltages.

2.1.1. Calculation
2.1.1. Calculation of of Voltage
Voltage Stress
Stress
The voltage
The voltage stress
stress across
across the
the switches
switches as
as shown
shown inin Figure
Figure 77 and
and the
the diodes
diodes shown
shown inin
Figures 8 and 9 are evaluated at the instance when the switches are not conducting
Figures 8 and 9 are evaluated at the instance when the switches are not conducting and are
and
Electronics 2022, 11, x FOR PEER REVIEW 7 of 28
in the
are in OFF state.state.
the OFF The voltage stressstress
The voltage particularly refersrefers
particularly to theto
peak
the inverse voltagevoltage
peak inverse across
the switch.
across the switch.

Figure 7. Switch voltages.

Figure 7. Switch voltages.
Electronics 2022, 11, 2014 7 of 26

Figure 7. Switch voltages.

Figure 7. Switch voltages.

Figure
Figure 8.
8. Diode
Diode voltages.
voltages.
Figure 8. Diode voltages.

Figure 9. Diode voltages.

Figure 9.
Figure 9. Diode
Diode voltages.
voltages.

The voltage stresses across the switches in the OFF state are given as,

(1− D )2 V
 VS1 = (1 − D )VC1 = 2(3− D) o
(10)
VS2 = (1 − D )(VC5 − Vo ) = −2(1− D) Vo
(3− D )

The voltage stress across different diodes when they are not conducting can be ex-
pressed as in (11):
D (1− D )V



 VD1 = VD3 = D VC1 = 2(3− D) o
(1− D )2 V


VD2 = (1 − D )VC1 = 2(3− D) o




−2(1− D ) Vo (11)
VD4 = (1 − D )(VC3 − V0 ) = (3− D)
−( 1 − D ) V

VD5 = VD6 = (3− D) o




VD0 = −(32D


 Vo
−D)
 𝑖
⎧ 𝑖 = 𝑖 =
(1 − 𝐷)
⎪
⎪ 𝑖
𝑖 = 𝑖 =
⎪ √𝐷
⎪ 2(3 − 𝐷)𝑖
Electronics 2022, 11, 2014 ⎪ 𝑖 = 𝑖 = 8 of 26
(1 − 𝐷)
⎪
⎪𝑖 2𝑖
= 𝑖 = 2𝑖 =
⎪ √𝐷(1 − 𝐷)
2.1.2. Calculation
⎪ of Average and RMS Currents (3 − 𝐷)𝑖
⎪𝑖 currents
The average = 𝑖 through = 𝑖the capacitors
= and switches can be easily determined by
𝐷√𝐷(1 − 𝐷) (16)
applying the current-sec balance principle in capacitors.
⎨ 3−𝐷 1−𝐷 
⎪ 𝑖 = 𝑖 = 𝑖

ZDT ZT
⎪ 1 (1 − 𝐷) 𝐷
ICON dt + ICOFF dt = 0. (12)
⎪ T
⎪ 0 𝐷 DT
⎪ 𝑖 = 𝑖
The average switch currents (in 1 − 𝐷 10) are given as,
Figure
⎪
⎪ (5 − 𝐷)
𝑖 =
 IS1 = IL1 − ID1 = 𝑖 (3− D)(1+ D2 )io

⎪ (1avg
− 𝐷) 𝐷 (1 − 𝐷) D(1− D)
⎪ (13)
⎪ IS2avg = 12IL2 = (12i o
𝑖 =𝑖 = 𝑖 −D)

⎩ 𝐷 (1 − 𝐷)

Figure10.
Figure Switchcurrents.
10.Switch currents.

The average inductor currents (in Figure 11) are given as,

i L2avg = i L3avg = (1−ioD)





i DOavg = i D4avg = io




 2(3− D ) i
o
i L1avg = iin = (14)
(1− D )2
i D5avg = i D6avg = 2i L2avg = (12i


 o

 −D)
−


i ( 3 D )i o
D1avg = i D2avg = i D3avg = D (1− D )

The RMS values of the switch currents are given as,


iS1 = (3−√D)(1+ D)i2o
rms D D (1− D ) (15)
 iS2rms = √ 2io
D (1− D )
Figure 11. Inductor currents.
Electronics 2022, 11, 2014 9 of 26

Figure 10. Switch currents.

Figure 11.
Figure 11. Inductor
Inductor currents.
currents.

The RMS values of the various currents through the components are given as,

i L2rms = i L3rms = (1−ioD)




i DOrms = i D4rms = √io



D


2(3− D ) i o





 i L1 rms
= i in = (1− D )2
2iio

i = i = 2i L2rms = √ D (1− D )

D5rms D6rms




( 3 − D ) iO

i D1rms = i D2rms = i D3rms = √

q D (1− D )
D (16)
3− D
iC1rms = iC2rms = (1− D)2 1−DD io





 q

D
i = 1− D i o



 COrms

(5− D )
√

iC3rms = io


− D (1− D )


 ( 1 D )
1
iC5rms = iC4rms = √

io


D (1− D )

2.1.3. Design of Inductors and Capacitors

The ripple current in the inductor L1 can be found as in (17) and rearranged to obtain
the critical value of the inductor for CCM operation.

 (∆i L1 )ON = VLin1 DT
Vin D (1− D )2 V (17)
 L1 =
Cri (∆i ) f
D = 2(3− D)∆i Of
L1 ON s L1 s

The ripple current and the critical value of the inductors L2 and L3 can be found as
VC3
(∆i L2 )ON =
(
L2 (1 − D ) T
D (1− D )V (18)
L2Cri = L3Cri = (3− D)∆i Of
L2 s

The peak-to-peak ripple voltages across the capacitors can be given as


(3− D )V

 ∆Vc1 = ∆Vc2 = (1− D) R C0 f
 O 1 s
(5− D )V0

∆V =


c3 (1− D ) RO C3 f s
V0
(19)


 ∆Vc4 = ∆Vc5 = RO C4 f s
∆VcO = R DV


 0
O CO f s
Electronics 2022, 11, 2014 10 of 26

2.2. Operation of Converter in Discontinuous Conduction Mode (DCM)

Electronics 2022, 11, x FOR PEER REVIEW 11 of 28
The proposed converter can also operate in DCM. This mode consists of three different
sub-modes of operation, as depicted in Figure 12.

Figure 12.
Figure 12. Typical
Typical waveforms
waveforms during
duringDCM.
DCM.

(i) Mode 1: Involt-sec

Applying this mode, bothinswitches
balance inductorare
L1, turned ON for duty cycle D as in the case
we obtain,
of CCM.
(𝐷 + 𝐷′)𝑉
(ii) Mode 2: In this mode, both =
𝑉 switches are turned OFF and the inductors start(20)
discharg-
ing. The inductors discharge through D′diodes D , D , and D for a duty cycle D’ and
1 3 O
Applying volt-sec
the mode ends 2, we obtain,
at Din+LD’.
(iii) Mode 3: In this mode, none of the switches or diodes conduct, and the load is fed
entirely through the output capacitor 𝐷′𝑉 CO . The mode is operated for a duration
(21)
of
1 − D − D’. 𝑉 =
2(2𝐷 + 3𝐷′)
The inductors are charged in Mode 1 (from t = 0 to t = DT) and are discharged in Mode
From equating (20) and (21), we obtain,
2 (from t = DT to t = D’T). Hence, by applying volt-sec balance across the inductors, we
obtain the voltage gain in DCM.
Applying volt-sec 𝑉 2(𝐷 + L𝐷′)(2𝐷 + 3𝐷′) (22)
𝑀balance
= in inductor
= 1 , we obtain,
𝑉 𝐷′
( D + D 0 )Vin
Rearranging Equation (22), weVc1
obtain,
= (20)
D02

𝐷 + 4𝑀
Applying volt-sec in L2 , we obtain, − 5𝐷 (23)
𝐷 =
6−𝑀
D 0 VO
Vc1 = (21)
Under DCM analysis for inductor 𝐿 2,(we + 3D 0 )
2D have,

From Equating (20) and (21), we obtain,

∆𝑖
⎧ 𝑉 = 𝐿
VO 2(𝐷𝑇
D + D 0 )(2D + 3D 0 ) (24)
MDCM =
⎨∆𝑖 = =𝑉 𝐷′𝐷𝑇 (22)
Vin D 02
⎩ 𝐿 (2𝐷 + 3𝐷′)
Rearranging Equation (22), we obtain,
For DCM operation,
p
0 D2 + 4MDCM − 5D
D = ∆𝑖 (23)
6=−𝐼MDCM (25)
𝐼 =
2
From (24) and (25) we obtain,

4𝜏𝑓 𝐷 (26)
𝐷 =
𝐷 − 6𝜏𝑓
Electronics 2022, 11, 2014 11 of 26

Under DCM analysis for inductor L2 , we have,

VL2 = L2 ∆iDT
(
L2

VO D 0 DT (24)
∆i L2 = L (2D+3D0 )
2

For DCM operation,

Electronics 2022, 11, x FOR PEER REVIEW ∆i L2 12 of 28
IL2 = = IO (25)
2
From (24) and (25) we obtain,
where 𝜏 is the time constant represented as4τ f s Dand 𝑓 is the switching frequency of the
D0 = (26)
switches. D − 6τ f s
Equating (25) and (26), we obtain,
where τ is the time constant represented as RL2 and f s is the switching frequency of
O
the switches. 𝐷(𝐷 − 2𝜏𝑓 ) (27)
=
Equating (25) and (26),𝑀we obtain, 4 (𝜏𝑓 )
Let 𝐾 = τ𝑓 ; then,
D ( D − 2τ f s )
MDCM = 2
(27)
𝐷(𝐷 − 2𝐾4)(τ f s ) (28)
𝑀 =
4 (𝐾 )
Let Ke = τ f s ; then,
D ( D − 2Ke )
2.3. Converter Operation at Boundary MDCM =
Conditions . (28)
4 ( K e )2
The boundary condition represents the critical conduction state of the converter on
the Converter
2.3. boundaryOperation
of DCM atand CCM. The
Boundary relation for the boundary condition can be easily
Conditions
formulated by equating
The boundary the voltage
condition gainsthe
represents in critical
the CCM and DCMstate
conduction operations, respectively.
of the converter on
Theboundary
the boundaryofcondition
DCM and is determined by the boundary-normalized
CCM. The relation for the boundary condition time constant of the
can be easily
inductor 𝐿 by
formulated , isequating
as shownthein voltage
Figure 13. Theinvariation
gains the CCMin andtheDCM
time operations,
constant of respectively.
the inductor
as a function of the duty cycle is represented as
The boundary condition is determined by the boundary-normalized time constant of the
inductor L2 , is as shown in Figure 13. The variation in the time (29) constant of the inductor as
a function 𝐷(1
of − 𝐷)
the duty cycle is represented as
𝐾 = 𝐷 + √25 − 8𝐷 − 1
8(3 − 𝐷)
D (1 − D )  √ 
The maximum value ec K of 𝐾 is 0.00516 obtained at D = 0.55. The converter operates
= D + 25 − 8D − 1 (29)
8(3 − D )
in DCM mode for a time constant less than 𝐾 and in CCM mode for a time constant
more than 𝐾 .

0.06

0.05 CCM
0.04
Kec

0.03 DCM

0.02

0.01

0
0 0.2 0.4 0.6 0.8 1
Duty Ratio (D)
Figure 13. Boundary normalized inductor time constant versus the duty ratio.
Figure 13. Boundary normalized inductor time constant versus the duty ratio.
The maximum value of Kec is 0.00516 obtained at D = 0.55. The converter operates in
3. Nonideal Analysis
DCM mode for a time constant less than Kec and in CCM mode for a time constant more
than KThe
ec . nonideal analysis of the converter accounts for the power loss analysis of the
circuit. Thus far, only the ideal lossless analysis of the converter is being considered in the
paper, ignoring the parasitic series resistances of the inductors, equivalent series re-
sistance (ESR) of the capacitors, barrier potential voltage and leakage resistances of the
diode, and the ON-state resistance of the switches (MOSFET), as shown in Figure 14. The
loss analysis is proceeded by the inclusion of the above-mentioned parameters in the ideal
Electronics 2022, 11, 2014 12 of 26

3. Nonideal Analysis
The nonideal analysis of the converter accounts for the power loss analysis of the
circuit. Thus far, only the ideal lossless analysis of the converter is being considered in the
paper, ignoring the parasitic series resistances of the inductors, equivalent series resistance
(ESR) of the capacitors, barrier potential voltage and leakage resistances of the diode, and
the ON-state resistance of the switches (MOSFET), as shown in Figure 14. The loss analysis
is proceeded by the inclusion of the above-mentioned parameters in the ideal circuit of the
proposed topology. The nonidealities of the elements tend to decrease the voltage gain
Electronics 2022, 11, x FOR PEER REVIEW 13 of of
28
the converter and also result in an increase in power losses. The total power loss across all
the elements is given as,

2 6 5 3
Plosstotal = ∑ PSiloss + ∑ PDiloss + ∑ PCiloss + ∑ PLiloss (30) (30)
𝑃 = 𝑃 i =1 + 𝑃i=0 + 𝑃i=0 + i𝑃
=1

Figure14.
Figure 14.Nonideal
Nonidealrealization
realizationof
ofthe
theproposed
proposedtopology.
topology.

3.1.
3.1. Calculation
Calculation of
of Losses
Losses across
acrossSwitches
Switches
The
The losses across switchescan
losses across switches canbebe either
either conduction
conductionlosses
lossesthat
that are
are encountered
encounteredwhenwhen
the
the switch is ON and current flows through it, or they may be switching losses
switch is ON and current flows through it, or they may be switching losses that
that are
are
encountered
encounteredwhenwhenthetheswitch
switchis in thethe
is in transition from
transition the ON
from statestate
the ON to OFF
to state
OFF or vice-versa.
state or vice-
versa. S S1,2 S
1,2
Ploss total
= Ploss + Ploss (31)
conduction switching

𝑃 𝑃 ,
= calculations, ,
+ 𝑃resistance (31)
For the conduction loss the of both switches is assumed to be
the same, i.e., rS1 = rS2 = rs .
For the conduction loss calculations, the resistance of both switches is assumed to be
the same, i.e., 𝑟 = 𝑟 = 𝑟 . PS1,2

2 2
lossconduction = iS1rms rS1 + iS2rms rS2



  2  2
S1,2 (3−√D )(3 + D )io 2io
, Ploss = r + √ rS2 (32)
⎧ 𝑃 = 𝑖
conduction 𝑟 +D𝑖 D(1−𝑟D)2 S1 D (1− D )
S
= D)3 (11− D)4 ((3 − D )22𝑖(1 + D )2 + ( D )2 (1 − D )2 ) PO RrOs

⎪  P 1,2

⎪ (3conduction
loss − 𝐷)(1 +(𝐷)𝑖
𝑃 ,
= 𝑟 + 𝑟 (32)
⎨ 𝐷√𝐷(1 − 𝐷) √𝐷 (1 − 𝐷)
⎪
⎪𝑃 ,
1 𝑟
= ((3 − 𝐷) (1 + 𝐷) + (𝐷) (1 − 𝐷) )𝑃
⎩ (𝐷) (1 − 𝐷) 𝑅
For the calculation of switching losses for a switch operating at a switching frequency
of 𝒇𝒔 , the rise time (𝒕𝒓 ) and fall time (𝒕𝒇 ) of the gate pulses are considered. Then, the
switching losses can be given as,

,
𝑡 + 𝑡
⎧ 𝑃 = × 𝑖 𝑉 + 𝑖 𝑉 𝑓
⎪ 2
⎪ 𝑡 +𝑡 (3 − 𝐷)(1 + 𝐷)𝑖 (1 − 𝐷)𝑉 2𝑖 2𝑉
𝑃 ,
= × × + × ×𝑓 (33)
Electronics 2022, 11, 2014 13 of 26

For the calculation of switching losses for a switch operating at a switching frequency
of f s , the rise time (tr ) and fall time (t f ) of the gate pulses are considered. Then, the
switching losses can be given as,
t + t   
S1,2

r f

 P loss = 2 × i S1 avg
VS1 avg
+ i S2 avg
V S2 avg
fs

 switching
t + t
  
S1,2 r f (3− D )(1+ D )io (1− D )Vo 2io 2Vo
Ploss = 2 × 2 × 2(3− D )
+ × × fs (33)
 switching  t + Dt (3− D)  (1− D) (3− D)
S r −D 2
× 2D3(1+−2D
 1,2 f
Ploss = PO × f s


switching 2 D )(3− D )

3.2. Calculation of Losses across Diodes

For the calculation purpose, the cut-in voltage and resistance of all diodes are assumed
to be the same, i.e., VDO = VD1 = VD2 = VD3 = VD4 = VD5 = VD6 = VD and r DO = r D1 =
r D2 = r D3 = r D4 = r D5 = r D6 = r D . The losses across different diodes are given as:


 PDOloss = i DOavg VDO + i2DOrms r DO
  2
PDOloss = io VDO + √io

r DO (34)
  D2
VD 1 r

D
PDOloss = V Po + √ R PO


O D O


 PD1loss = i D1avg VD1 + i2D1rms r D1
 2 (35)
 PD1loss = D(3(− D ) VD
1− D ) V Po + (3− D )
√ rD
R PO
O D D (1− D ) O

 PD2loss = i D2avg VD2 + i2D2rms r D2
 2 (36)
 PD2loss = D(3(− D ) VD
1− D ) V
Po +
(3− D )
√ rD
R PO
O D D (1− D ) O

 PD3loss = i D3avg × VD3 + i2D3rms × r D3
 2 (37)
 PD3loss = D(3(− D ) VD
1− D ) V
Po + (3− D )
√ rD
R PO
O D D (1− D ) O

 PD4loss = i D4avg VD4 + i2D4 r D4
 2rms (38)
 PD4loss = V V
D
Po + √1 rD
R PO
O D O

 PD5loss = i D5avg VD5 + i2D5rms r D5
 2 (39)
 PD5loss = (1−2 D) V
V
D
P o + √ 2 rD
R PO
O D (1− D ) O

 PD6loss = i D6avg VD6 + i2D6rms r D6
 2 (40)
 PD6loss = (1−2 D) VD
V Po +
√ 2 rD
R PO
O D (1− D ) O

PDloss = PDOloss + PD1loss + PD2loss + PD3loss + PD4loss + PD5loss + PD6loss (41)

total

3.3. Calculation of Losses across Capacitors

For the calculation of conduction loss in capacitors, the parasitic resistances of the
capacitors rC1 , rC2 , rC3 , rC4 , and rC5 are assumed to be equal, while the resistance of the
capacitor CO is assumed to be rCO
2 2 2 2 2 2

 PClosstotal = iCOrms rCO + iC1rms rC1 + iC2rms rC2
 + iC3 r + iC4
rms C3
r + iC5
rms C4
r
rms C5
2

2

 q   q 
 D rCO 3− D 1− D rC1

 PCloss = 1− D RO PO + 2 (1− D )2 D RO PO +
total

 2  2 (42)
(5− D ) rC3 1 rC5

 √ PO + √ PO
(1− D ) D(1− D )  RO R

 D (1− D ) 2  O



rCO 44−24D + 4D rC

D
PCloss = (1− D) R PO + R PO


total O D (1− D )3 O
Electronics 2022, 11, 2014 14 of 26

3.4. Calculation of Losses across Inductors

The loss calculations for inductors are carried out by ignoring the ripple in the inductor
current through the leakage resistances r L1 , r L2 , and r L3 . Inductors L2 and L3 have the
same design values; hence, their parasitic resistances are assumed to be equal.

2 2 2
 PLlosstotal = i L1rms r L1 + i L2rms r L2 + i L3rms r L3

2
(43)
  2
2(3− D ) r L1 1 r L2
 PLlosstotal = (1− D)2

RO PO + 2 (1− D ) RO PO

3.5. Calculation of Efficiency of the Converter in Nonideal Mode

The efficiency of the converter is given as the ratio of the output power transferred to
the total input power fed to the circuit, which can be represented as the sum of the output
power and the total losses in the converter. The efficiency (η) is given as

P
 η = P0 + PS + PD 0 + PC + PL

loss loss loss loss
η= 1
= 1+1K (44)
 PS + PD + PC + PL
 1+ loss loss loss loss
P0

where K is a constant given simplified as,

 nh
i
 K = 1
( 3 − D ) 2 (1 + D )2 + ( D )2 (1 − D )2 r S


 D 3 (1− D )4 l RO
 (2D +3)(3− D ) VD



 + D (1− D ) VO
 m

 + 27−18DD +13D2 −4D3 +2D4 r D
3 (1− D )2 RO m
l (45)
D rCO 35−18D +3D2 rC



 + 1 − D RO + D ( 1 − D ) 3 RO

 " 2 #)
  2
 2(3− D ) r L1 1 r L2
+ RO + 2 1 − D


(1− D )2 RO



After substituting the value of K obtained in (45) in (44), we obtain,

D 3 (1 − D )4
η= h              i (46)
D3 (1 − D )4 + a RrS + b RrD + c rRCO + d RrC + e rRL1 + f Rrl2 + g V
V
D
O O O O O O O

where,
a = 9 + 12D − D2 − 6D3 + 2D4




b = 27 − 18D + 13D2 − 4D3 + 2D4




c = D 2 (1 − D )4





d = D (1 − D )2 35 − 18D + 3D2


(47)
e = 2D (3 − D )3




f = 2D (1 − D )4





g = D3 (1 − D )4 (3 − D )(2D + 3)


3.6. Calculation of Nonideal Voltage Gain

For the derivation of nonideal voltage gain, all the lossy components of the elements
such as the ON-state resistance of diodes and switches, ESRs of the inductor, and capacitor
are considered for the analysis. Thus far, the input and output powers are equal due
to lossless analysis, whereas, considering the above assumptions, the modified relation
between the input and output power can be expressed as:

Input Power = Output Power + Losses across elements

3.7. Variation in Nonideal Voltage Gain

The nonideal gain ( Mactual ) of the proposed converter is derived as,
 3.7. Variation in Nonideal Voltage Gain
The nonideal gain (𝑀 ) of the proposed converter is derived as,

1
⎧ 𝑀 = (𝑀 ) = 𝜂(𝑀 )
⎪
Electronics 2022, 11, 2014 1+ 𝐾 15 of 26
2𝐷 (1 − 𝐷) (3 − 𝐷) (48)
𝑀 =
⎨ 𝐷 (1 − 𝐷) +
⎪ 𝑟 𝑟 𝑟 𝑟 𝑟 𝑟 𝑉
𝑎 +𝑏 +𝑐 +𝑑 +𝑒 +𝑓 +𝑔
⎩ 𝑅 𝑅 1𝑅 𝑅 𝑅 𝑅 𝑉

 Mactual = 1+K ( MCCM )ideal = η ( MCCM )ideal
3 2


Mactual =  From the voltage gain 2D comparison
(1− D ) (3− Dof ) ideal and nonideal voltage  gains of the pro-
 posed
h  topology
  in Figure
 15,D 3 (is
it 1−
observed
D ) 4
+  that  both gains have
 similar
i  values up to(48)
the
duty r r r r r r V
a Rratio+ofb 0.4, and then the nonideal gain increases until D = 0.7 but deviate from the

S D CO C L1 L2 D
RO + c RO + d RO + e RO + f RO + g VO

  
O
ideal characteristics. Thereafter, it gradually decreases to zero at the unity duty ratio.
From the voltage
The voltage gaingain
of thecomparison
converterofcan ideal
be and nonideal
affected by thevoltage gains
parasitic of the proposed
resistances of dif-
topology in Figure 15, it is observed that both gains have
ferent elements of the converter such as the parasitic resistance of inductors, similar values up tocapacitors,
the duty
ratio of 0.4, andAs
and switches. then
the the nonideal
parasitic gain increases
resistances until elements
of different D = 0.7 but deviatethe
increase, from the ideal
voltage gain
characteristics. Thereafter, it
of the converter decreases gradually. gradually decreases to zero at the unity duty ratio.

55

45 M(Ideal)

M(Non-Ideal)
Voltage Gain (M)

35

25

15

5
0.1 0.3 0.5 0.7 0.9
Duty Cycle (D)

Figure15.
Figure 15. Comparison
Comparison of
of calculated
calculated ideal
ideal and
and simulated
simulated nonideal
nonideal voltage
voltage gain
gain of
of the
the proposed
proposed
converter.
converter.

The voltage gain of the converter can be affected by the parasitic resistances of different
elements of the converter such as the parasitic resistance of inductors, capacitors, and
switches. As the parasitic resistances of different elements increase, the voltage gain of the
converter decreases gradually.
From Figure 16, it can be observed that, when the parasitic resistance of the switch is
increased while other elements are kept ideal, the voltage gain of the converter decreases.
For the parasitic resistance of 0.2% of the load resistance, the maximum gain is at the duty
ratio of 0.7 with a gain of 24.18, while it decreases to 15.84 and 11.77 for 4% and 6% of the
parasitic resistance, respectively, at D = 0.7.
From Figure 17, it can be observed that, when the parasitic resistance of the inductor
is increased while other elements are kept ideal, the voltage gain of the converter decreases.
For a parasitic resistance of 0.2% of the load resistance, the maximum gain is at the duty
ratio of 0.75 with a gain close to 34, while it decreases to 24.88 and 19.80 for 4% and 6% of
the parasitic resistance, respectively, at D = 0.7.
From Figure 18, it can be observed that, when the parasitic resistance of the capacitor
is increased while other elements are kept ideal, the voltage gain of the converter decreases.
For the parasitic resistance of 0.2% of the load resistance, the maximum gain is at the duty
ratio of 0.8 with a gain of 63, while it decreases to around 41 and 21 for 4% and 6% of the
parasitic resistance, respectively, at a near-duty ratio of 0.8.
 From Figure 16, it can be observed that, when the parasitic resistance of the switch is
increased while other elements are kept ideal, the voltage gain of the converter decreases.
For the parasitic resistance of 0.2% of the load resistance, the maximum gain is at the duty
From Figure 16, it can be observed that, when the parasitic resistance of the switch is
ratio of 0.7 with a gain of 24.18, while it decreases to 15.84 and 11.77 for 4% and 6% of the
increased while other elements are kept ideal, the voltage gain of the converter decreases.
parasitic resistance, respectively, at D = 0.7.
For the parasitic resistance of 0.2% of the load resistance, the maximum gain is at the duty
Electronics 2022, 11, 2014 16 of 26
ratio of 0.7 with a gain of 24.18, while it decreases to 15.84 and 11.77 for 4% and 6% of the
parasitic resistance, respectively, at D = 0.7.

Figure 16. Voltage gain variation as per parasitic resistance of the switch.

From Figure 17, it can be observed that, when the parasitic resistance of the inductor
is increased while other elements are kept ideal, the voltage gain of the converter de-
creases. For a parasitic resistance of 0.2% of the load resistance, the maximum gain is at
the duty
Figure
Figure ratio
16.
16. of 0.75
Voltage
Voltage with
gain
gain a gain as
variation
variation close
perto
asper 34, while
parasitic
parasitic it decreases
resistance
resistance toswitch.
ofofthe
the 24.88 and 19.80 for 4%
switch.
and 6% of the parasitic resistance, respectively, at D = 0.7.
From Figure 17, it can be observed that, when the parasitic resistance of the inductor
is increased while other elements are kept ideal, the voltage gain of the converter de-
creases. For a parasitic resistance of 0.2% of the load resistance, the maximum gain is at
the duty ratio of 0.75 with a gain close to 34, while it decreases to 24.88 and 19.80 for 4%
and 6% of the parasitic resistance, respectively, at D = 0.7.

Electronics 2022, 11, x FOR PEER REVIEW 18 of 28

the duty ratio of 0.8 with a gain of 63, while it decreases to around 41 and 21 for 4% and
Figure 17.
Figure Voltage
17.Voltage gain
gain variation
variation as per
as per parasitic
parasitic resistance
resistance of the of the inductor.
inductor.
6% of the parasitic resistance, respectively, at a near-duty ratio of 0.8.
From Figure 18, it can be observed that, when the parasitic resistance of the capacitor
is increased while other elements are kept ideal, the voltage gain of the converter de-
creases. For the parasitic resistance of 0.2% of the load resistance, the maximum gain is at

Figure 17. Voltage gain variation as per parasitic resistance of the inductor.

From Figure 18, it can be observed that, when the parasitic resistance of the capacitor
is increased while other elements are kept ideal, the voltage gain of the converter de-
creases. For the parasitic resistance of 0.2% of the load resistance, the maximum gain is at

Figure
Figure 18. Voltage gain
18. Voltage gain variation
variation as
as per
per parasitic
parasitic resistance
resistance of
of the
the capacitor.
capacitor.

4. Comparison of the Proposed Topology

In this section, a comparison between the proposed topology with two traditional
topologies and recent topologies is discussed. The topologies are compared based on their
voltage gain (MCCM), number of inductors (NL), number of capacitors (NC) and number of
Electronics 2022, 11, 2014 17 of 26

4. Comparison of the Proposed Topology

In this section, a comparison between the proposed topology with two traditional
topologies and recent topologies is discussed. The topologies are compared based on their
voltage gain (MCCM ), number of inductors (NL ), number of capacitors (NC ) and number of
diodes (ND ) in the converter. The voltage stress appearing across the switches (Vsi /Vin ) is
also compared along with the availability of common ground.
For the comparison of the topologies, the graph between the ideal voltage gain and
the duty cycle is plotted in Figure 19a. Figure 19b depicts the comparison of the nonideal
gain of the converter with the ideal gain of some selected topologies whose gain intersects
Electronics 2022, 11, x FOR PEER REVIEW 1 of 1
the nonideal gain plot of the proposed topology. The voltage stress across the switches in
the compared converters is shown in Figure 20.

(a)

(b)
Figure
Figure 19.19.(a)
(a). Comparisonofofideal
Comparison ideal voltage
voltage gain of
of various
varioussimilar
similarconverters.
converters(b). Comparison of
[4,5,16,22,24–30].
(b) various topologies
Comparison withtopologies
of various the non-ideal
with voltage gain voltage
the nonideal of the proposed topology
gain of proposed topology [4,24,27,28].
It can be observed from Figure 19a that the proposed topology has the highest ideal
gain among all the high-gain boost converters compared to all converters. An ideal voltage
gain of above 14 is achieved by the proposed topology at a duty ratio of 40% and a gain of
20 is achieved at a duty ratio of 50%. The proposed converter also has a higher nonideal
gain, as shown in Figure 19b, as compared to the ideal gain of the similar topologies, as
presented in Table 1, until the duty ratio of 60%. The switching stress of the converter
is very low as compared to the traditional topologies. In converters [4,5], even with the
presence of an isolation transformer/coupled inductor operating at a transformation ratio
Electronics 2022, 11, 2014 18 of 26

(b)
of one, a lower gain than the proposed topology is produced, which works without a
Figure 19. (a). Comparison of ideal voltage gain of various similar converters. (b). Comparison of
transformer or coupled
various topologies inductor,
with the non-idealhence reducing
voltage theproposed
gain of the overall cost of the topology.
topology

Figure 20. Comparison

Figure20. Comparison of
of calculated
calculatedswitch
switchstress
stressversus
versusvoltage
voltagegain
gain.[4,5,16,22,24–29].

For n = 1, the ideal gain of the converter in [4] when compared with the gain of the
proposed converter is found to be half. Moreover, the voltage stress across the switch S1
in [4] increases significantly as shown in Figure 20.
The topology proposed in [16] also has a VMC and two switches and produces a
high gain at lower duty ratios with a lower number of components as compared with the
proposed topology, but it decreases as the duty ratio is increased above 40%. The proposed
converter despite having fewer inductors, switches and diodes than the converter [22] is
capable of producing a much higher voltage gain. Although the switch stress across the
converter [22] is very low as compared to the proposed one, the converter lacks a common
ground that is available in the proposed topology. The converters in [24,25], despite having
2 and 3 inductors respectively and 2 switches which is the same as used in the proposed
topology, produce a lower gain than the proposed topology and, concurrently, the voltage
stress across the switch.
In the case of the topology shown in [25], the switch stress increases after a conversion
gain ratio of 14. The converters in [26,27] also have three inductors but suffer from a
low-voltage gain. The switch S1 of [27] has high-voltage stress after a voltage gain of 8. The
quadratic boost converter in [29] has the same inductors as the proposed converter, but
the voltage gain is half as compared to the proposed converter, and it has a single switch
only. The topology in [29] exhibits high-voltage stress across switch S2 amongst all the
compared topologies. The topology in [30] has the least voltage stress across its switches
but suffers from a low ideal voltage gain, which is much lower than the nonideal voltage
gain produced by the proposed converter.
From the comparison, it can be inferred that the topology has the highest voltage
gain and the switch voltage gain across S1 is very low. The switch voltage gain across
the switch S2 is found to be high for low-voltage gains, but it does not increase further
as the voltage gain increases beyond 15. Hence, the proposed topology can be used at
a voltage gain higher than 14, which is easily achieved at any duty ratio beyond 40%.
Moreover, continuous input current and common ground are other advantages of the
proposed converter.
Electronics 2022, 11, 2014 19 of 26

Table 1. Comparison of proposed topology with certain similar topologies.

Common VSi
Topology NL NC NSW ND MCCM MCCM at D = 0.5 SCCM =
Ground Vin

Boost
1
Con- 1 1 1 1 (1− D )
2 Yes S = 1−1D
verter
Quadratic
Boost 1 1
2 2 1 3 4 Yes S=
Con- (1− D )2 (1− D )2
verter
1+1
2n+1+ D S1 = 1−1D
[4] coupled 5 2 5 14 Yes
inductor
(1− D )2 S2 = 1 + D 2
(1− D )

1+1
[5] coupled 3 1 5 1+ n − D 6 Yes S = 1−2D
(1− D )2
inductor

5+ D S1 = 1−1D
[16] 3 4 2 5 1− D
11 No 1
S2 = 2
(1− D )

1+7D S1 = 1
[22] 8 1 4 17 9 No
(1− D ) S = 11+ 5D
+7D

1 S1 = 1−1D
[24] 2 2 2 2 4 Yes 1
(1− D )2 S2 = 2
(1− D )

[25] 3 4 1 4 1+ D 6 Yes 1
S=
(1− D )2 (1− D )2

[26] 3 3 1 5 2 8 Yes 2
S=
(1− D )2 (1− D )2

1+3D S1 = 1−1D
[27] 3 5 2 4 10 Yes
(1− D )2 S2 = 1 + D 2
(1− D )

[28] 2 5 1 6 2(2− D ) 12 No 2− D
S=
(1− D )2 (1− D )2
3− D
(3− D )
S1 = D 2 (1− D )
.
[29] 3 6 1 6 10 Yes 3− D
(1− D )2 S2 =
(1− D )2
1− D
D2 −3D +3
S1 = D2 −3D +3
[30] 2 3 2 3 7 Yes 1
(1− D )2 S2 = D2 −3D +3
Proposed 2(3−D) S1 = 1
3 6 2 7 20 Yes
Topology (1−D)2 S2 = (1−4D)

5. Results
In this section, we discuss the simulation results performed on the Piecewise Linear
Electrical Circuit Simulation (PLECS) and the experimental results obtained on hardware
set-upfor the proposed topology.

5.1. Simulation Results

In this section, the simulation results of the proposed converter are presented. The
simulation was carried out in PLECS software at an input voltage of 20 V and switching
frequency of 50 kHz. The duty ratio was maintained at 0.4. The value of the inductor was
330 µΩ and its parasitic resistance was maintained at 0.12 Ω, while the value of capacitors
was 47 µΩ and its parasitic resistance was kept at 0.1 Ω. The ON-state resistance of the
switches was found to be 70 mΩ. With the above parameters, the simulation was performed
and the output voltage was found to be VO = 248.08 V at a 40% duty ratio with Vin = 20 V,
which can be seen in Figure 21.

Electronics 2022, 11, 2014
From Figure 23, the peak voltage across switches S1 and S2 was found to be
𝑉 ( ) = 30.687 V and 𝑉 ( ) = 155.43 V, respectively, while the RMS voltage was
𝑉 ( ) = 23.77 V and 𝑉 ( ) = 120.40 V, respectively. From Figure 24, the average ca-
pacitor voltages in the simulation were found to be 𝑉 = 𝑉 = 27.5209 𝑉 and 𝑉 =
58.65 𝑉, while from Figure 25, the capacitor voltages were 𝑉 = −56.58 𝑉, 𝑉 = 57.16 𝑉,
and 𝑉 = 𝑉 = 248.08 𝑉. The ripple in capacitor voltages was negligible and, hence, 20 of
the26

RMS and average voltages were found to be the same.

Figure 21.
Figure Simulatedoutput
21. Simulated outputvoltage
voltage (𝑉
(VO),),input
inputvoltage
voltage(𝑉
(Vin), ),and
andduty
dutycycle
cycle(D).
(D).

In Figure 22, the inductor current through inductor L1 was found to be IL1 =225.06
Electronics 2022, 11, x FOR PEER REVIEW
A
of 28
and IL2 = IL3 = 0.58 A for inductor L2 . The ripple in the current through the inductor was
lower and, hence, the average and RMS values were found to be the same.

Figure 22.
Figure Simulated inductor
22. Simulated inductor currents (IL1,,𝐼IL2, and
currents (𝐼 , and ) andduty
𝐼 I)L3and dutycycle
cycle(D).
(D).

From Figure 23, the peak voltage across switches S1 and S2 was found to be
VS1( peak) = 30.687 V and VS2( peak) = 155.43 V, respectively, while the RMS voltage was
VS1(rms) = 23.77 V. and VS1(rms) = 120.40 V, respectively. From Figure 24, the average capac-
itor voltages in the simulation were found to be VC1 = VC2 = 27.5209 V and VC3 = 58.65 V,
while from Figure 25, the capacitor voltages were VC4 = −56.58 V, VC5 = 57.16 V, and
VCO = VO = 248.08 V. The ripple in capacitor voltages was negligible and, hence, the RMS
and average voltages were found to be the same.

Figure 23. Simulated switch voltages and duty cycle (D).

Electronics 2022, 11, 2014 21 of 26

Figure 22. Simulated inductor currents (𝐼 , 𝐼 , and 𝐼 ) and duty cycle (D).

Figure 23.
Figure Simulated switch
23. Simulated switch voltages
voltages and
and duty
duty cycle
cycle (D).

Electronics 2022, 11, x FOR PEER REVIEW 23 of 28

Figure 24.
Figure Simulated capacitor
24. Simulated capacitor voltages
voltages and
and duty
duty cycle
cycle (D).
(D).

Figure 25.
Figure Simulatedcapacitor
25. Simulated capacitor voltages
voltages and
and duty
duty cycle
cycle (D).
(D).

5.2. Experimental Results

The experimental analysis of the proposed converter was carried out on the same
parameters as the simulation procedure. To verify the overall voltage boosting, continu-
ous current, and capacitor voltage handling capability of the proposed converter, a hard-
ware prototype of the proposed converter was tested under standard laboratory condi-
tions with the parameters mentioned in Table 2. To demonstrate the working of the topol-
Electronics 2022, 11, 2014 22 of 26

5.2. Experimental Results

The experimental analysis of the proposed converter was carried out on the same
parameters as the simulation procedure. To verify the overall voltage boosting, continuous
current, and capacitor voltage handling capability of the proposed converter, a hardware
prototype of the proposed converter was tested under standard laboratory conditions
with the parameters mentioned in Table 2. To demonstrate the working of the topology, a
converter with an output power of 200 W at a duty ratio of 40% was implemented with
a load resistance of 300 Ω. For switches S1 and S2 , Power MOSFET with part number
SPW52N50C3 provided with a duty cycle (D) of 0.4 operating at a switching frequency
(fs ) of 50 kHz was used, whereas diodes (DO − D6 ) with part number HER806 were used.
From Figure 26, a 20 V DC supply was used at the input side and an output of 240 V was
obtained for the same with Vgs as the gate drive signal.

Table 2. Hardware values of parameters.

Parameter Symbol Value

Input Voltage Vin 20 V
Duty Cycle D 0.4
Output Power PO 67 W
Load Resistance RO 850 Ω
L1 330 µH, ESR = 0.12 Ω
Inductors
L2 , L3 0.4 mH ESR = 0.14 Ω
C1 − C5 47 µF, ESR = 0.1 Ω
Capacitors
Electronics 2022, 11, x FOR PEER REVIEW
CO 100 µF, ESR = 0.22 Ω 24 of 28
Diodes DO to D6 HER806
Power MOSFETs S1 , S2 SPW52N50C3
V, respectively, in each cycle, which can be seen in Figure 28. The peak reverse blocking
Driver30 V for the switch 𝑆 and 160 V for switch 𝑆 for the
voltage is about TLP250H
output voltage of
𝐶 has a voltage of 30 V across it, while capacitors
Controller
240 V. Capacitor STM32F334R8
C3 and C4 have a
voltage of 60 VFrequency
Switching with very-low-voltage ripples
fs as in Figure 29. The experimental
50 kHz setup is
shown in Figure 30.

Figure 26.
Figure Top to
26.Top tobottom:
bottom:experimental
experimentalwaveforms
waveformsof
ofoutput
outputvoltage (VO),),input
voltage (𝑉 inputvoltage (Vin),), and
voltage (𝑉 and
𝑉 gs at D = 0.4.
V at D = 0.4.

From Figure 27, when the switches are ON, the inductors become charged and the
current through them increases. For inductor L1 , it increases from an initial value of 4.8 A
to a peak value of 5.2 A and it increases from an initial value of 0.7 A to a peak value of
1.0 A for inductors L2 and L3 . When the switches are OFF, the inductors release their stored
energy, and the currents through them decrease back to their initial values. During the
OFF state, the switches are reversed-biased and block a peak voltage of 30 V and 160 V,
 Electronics2022,
Electronics 2022,11,
11,xxFOR
FORPEER
PEERREVIEW
REVIEW 24 of
24 of 28
28

Electronics 2022, 11, 2014 V,respectively,

V, respectively,in ineach
eachcycle,
cycle,which
whichcan canbebeseen
seenin inFigure
Figure28.28.The
Thepeakpeakreverse
reverseblocking
blocking
23 of 26
voltageisisabout
voltage about30 30VVfor
forthe switch 𝑆𝑆 and
theswitch and160160VVfor switch 𝑆𝑆 for
forswitch forthe theoutput
outputvoltage
voltageof of
240 V.
240 Capacitor 𝐶𝐶 has
V. Capacitor has aa voltage
voltage of
of 30
30 VV across
across it,
it, while
while capacitors
capacitors CC33 andand CC44 have
have aa
voltage
voltage of60
of
respectively, 60VVwith
in with very-low-voltage
eachvery-low-voltage ripples
cycle, which canripples
be seenasas inFigure
inin Figure28.
Figure 29.The
29. Thepeak
The experimental
experimental setupisis
setup
reverse blocking
shown
shown in Figure
voltageinisFigure
about30.30.
30 V for the switch S1 and 160 V for switch S2 for the output voltage of
240 V. Capacitor C1 has a voltage of 30 V across it, while capacitors C3 and C4 have a voltage
of 60 V with very-low-voltage ripples as in Figure 29. The experimental setup is shown in
Figure 30.
Figure 31 shows the variation in efficiency with the output power as the input voltage
is increased. It can be observed that as the input voltage increases, the efficiency of
the converter increases. This occurs because with the increase in voltage, the current
decreases to conserve the power; hence, the conduction losses across various elements
of the converter including switches, diodes, and parasitic resistances of the inductor and
capacitor are reduced.
The maximum efficiency of the converter is found as 97.85% at 30 V, 66 W followed
by 96.5% for operation at 20 V for the same power. From Figure 32, the majority of the
conduction losses i.e., around 39%, occur in the capacitors, out of which 58.5% of the losses
in capacitors are due to capacitor C3 itself. The switches and diodes contribute 40% of
Figure
Figure 26.Top
the total
26. Toptotobottom:
losses. bottom: experimental
The losses waveforms
can be further
experimental waveforms ofoutput
reduced
of output voltage
by using (𝑉 ),),and
(𝑉
diodes
voltage input
inputswitches
voltage (𝑉 ),),and
voltage (𝑉
with and
low
𝑉 at D
𝑉parasitic = 0.4.
resistance.
at D = 0.4.

Figure27.
Figure
Figure Topto
27.Top
27. Top tobottom:
to bottom:experimental
bottom: experimentalwaveforms
experimental waveformsof
waveforms ofcurrent
of currentof
current of
ofinductor
inductor L11(𝑖(𝑖(i L1
inductorLL )),),inductor
,inductor
inductorLLL (𝑖(𝑖(i L2),),),
222
and 𝑉𝑉𝑔𝑠
and V at
𝑔𝑠 at
gs D = 0.4.
atDD==0.4.
0.4.

Figure28.
Figure Top to
28. Top to bottom:
bottom: experimentalwaveforms
bottom:experimental waveformsof ofoutput
outputvoltage ((𝑉
voltage (𝑉VO),),
),voltage
voltageacross
acrossswitch
switch
2 (𝑉 ),
S2 2(𝑉(VS2
S voltage
), )voltage across
across
, voltage switch
switch
across 𝑆
switch (𝑉
𝑆 (𝑉 ),
S1 (), and
VS1and 𝑉
), and at
𝑉 Vat D = 0.4.
at=D0.4.
gs D = 0.4.
 Electronics 2022,11,
Electronics 11, xFOR
FORPEER
PEERREVIEW
REVIEW 25 ofof 28
28
Electronics 2022,
2022, 11, x2014 2524 of 26

Figure
Figure 29.
Figure29. Top
29.Top to
Topto bottom:
tobottom: experimental
bottom:experimental waveforms
waveformsof
experimentalwaveforms ofofvoltage
voltageacross
voltage acrosscapacitor
across capacitorC
capacitor CC ((𝑉
VC3),)),, the
33 3(𝑉 the voltage
thevoltage
voltage
acrosscapacitor
across
across (𝑉C4),),and
capacitorCC444(𝑉
capacitor C ( V ) , andthe
and thevoltage
the voltageacross
voltage (𝑉 C1
acrosscapacitor C1 11(𝑉
across capacitor C ( V )) atatDD==0.4.
) at D =0.4.
0.4.

DCPower
DC PowerSupply
Supply DSO
DSO

Microcontroller
Microcontroller
(TMS32F28335)
(TMS32F28335)
DriverCircuit
Driver Circuit
PowerMOSFET
Power MOSFET(S)(S)
withHeat
with HeatSink
Sink
VariableLoad
Variable Load(R)
(R)

Inductor(L)
Inductor (L)

+ +
+
InputSupply(Vin)
Input Supply(Vin) +
__ VV
__
OO

PowerDiode(D)
Power Diode(D)

Capacitor(C)
Capacitor (C)
88Switch
SwitchGeneralized
GeneralizedTest
TestBench
Bench
Probes
Probes
Electronics 2022, 11, x FOR PEER REVIEW 26 of 28
Figure30.
Figure
Figure 30.A
30. Ageneralized
A generalizedtest
generalized testbench
test benchsetup
bench setupwith
setup with888switches.
with switches.
switches.

Figure31
Figure 31shows
showsthe thevariation
variationininefficiency
efficiencywith
withthe
theoutput
outputpower
poweras asthe
theinput
inputvoltage
voltage
is 100
increased. It can be observed that as the input voltage increases, the
is increased. It can be observed that as the input voltage increases, the efficiency of efficiency ofthe
the
converter Vin
converterincreases. = 10V
increases.This
Thisoccurs Vin = 20V
occursbecause
becausewith Vin
withthe = 30V
theincrease
increaseininvoltage,
voltage,the
thecurrent
currentdecreases
decreases
98
toconserve
conserve thepower;
power;hence,
hence,the
theconduction
conductionlosses
lossesacross
acrossvarious
variouselements
elementsof ofthe
thecon-
con-
to the
verterincluding
verter includingswitches,
switches,diodes,
diodes,and
andparasitic
parasiticresistances
resistancesofofthe
theinductor
inductorandandcapacitor
capacitor
96
arereduced.
reduced.
Efficiency of converter (%)

are
Themaximum
The maximumefficiency
efficiencyofofthe
theconverter
converterisisfound
foundasas97.85%
97.85%atat30
30V,V,66
66W Wfollowed
followed
94
by96.5%
by 96.5%forforoperation
operationatat20 20VVforforthe
thesame
samepower.
power.From
FromFigure
Figure32,
32,the
themajority
majorityof ofthe
the
conduction
conduction
92 lossesi.e.,
losses i.e.,around
around39%,
39%,occur
occurin inthe
thecapacitors,
capacitors,out
outof
ofwhich
which58.5%
58.5%of ofthe
thelosses
losses
incapacitors
in capacitorsarearedue
dueto tocapacitor
capacitorCC3 3itself.
itself.The
Theswitches
switchesandanddiodes
diodescontribute
contribute40% 40%of ofthe
the
total 90
losses. The losses can be further reduced by using diodes and
total losses. The losses can be further reduced by using diodes and switches with low switches with low
parasiticresistance.
parasitic resistance.
88

86
50 100 150 200
Power (W)

Figure31.
Figure 31. Simulated
Simulated efficiency
efficiencyvs.
vs. output
output power
power comparison
comparison of
of the
the proposed
proposed converter
converterat
at different
different
inputvoltages.
input voltages.

Switch Losses

Diode Losses
 E
86
50 100 150 200
Power (W)

Electronics 2022, 11, 2014 Figure 31. Simulated efficiency vs. output power comparison of the proposed converter at different
25 of 26
input voltages.

Switch Losses

Diode Losses

Inductor Losses
18%
39% Capacitor Losses

22%

21%

Figure 32. Distribution of losses across various elements of the converter.

6. Conclusions
Figure 32. Distribution of losses across various elements of the converter.
The converter produces an ideal voltage gain of 11 times at a duty ratio of 30% with
an ideal
6. Conclusion voltage gain of 14.44 at a duty ratio of 40%. The nonideal gain of the proposed
converter at a D less than 60% is still found to be higher as compared to the ideal gains of
The converter produces an ideal voltage gain of 11 times at a duty ratio of 30% with
the compared converters. In addition, the voltage stress across the switches is found to be
an ideal voltage gain of 14.44 at a duty ratio of 40%. The nonideal gain of the proposed
lower than the output voltage and is also much lower than the compared topologies even
converter at a D less than 60% is still found to be higher as compared to the ideal gains of
at higher duty ratios. The voltage stress across S1 is 6.92% of the Vo and across switch S2 ,
the compared converters. In addition, the voltage stress across the switches is found to be
it is 46.15% of Vo at the duty ratio of 40%. The maximum efficiency of 97.85% is obtained
lower
at 66than the output
W when voltage
the input and is
voltage is 30
also
V,much
whilelower than the
it is 96.44% at compared
a load of 38 topologies
W, keepingeventhe
atinput
highervoltage
duty ratios. The voltage stress across S 1 is 6.92% of the Vo and across switch S2,
at 20 V. The efficiency of the prototype model decreases with the power
it level
is 46.15%
due to Vo at
of the the duty
absence of ratio of 40%.
galvanic The maximum
isolation efficiency
and parasitic of 97.85%
resistances. Theisvoltage
obtained
and
atcurrent
66 W whenstresses across the elements are low, which can be observed from the analysisthe
the input voltage is 30 V, while it is 96.44% at a load of 38 W, keeping and
input voltage at 20 V. The efficiency of the prototype model decreases
the hardware results. The converter has a common ground and operates at continuous with the power
level
inputdue to the making
current, absenceitoffeasible
galvanic for isolation
low- andand parasitic resistances.
medium-power solar andThe voltageenergy
renewable and
current stresses
PV applications. across the elements are low, which can be observed from the analysis and
the hardware results. The converter has a common ground and operates at continuous
input
Authorcurrent, making itConceptualization,
Contributions: feasible for low- and medium-power
writing—original draftsolar and renewable
preparation, energy
M.Z., I.H.M. and
PV applications.
M.T.; supervision, M.Z. and I.A.; writing—review and editing, B.A. and E.M.G.R.; funding acquisition,
M.T., B.A. and E.M.G.R. All authors have read and agreed to the published version of the manuscript.
Funding: The authors would like to acknowledge the financial support from Taif University Re-
searchers Supporting Project Number (TURSP-2020/278), Taif University, Taif, Saudi Arabia and
from the collaborative research grant scheme (CRGS) project, Hardware-In-the-Loop (HIL) Lab,
Department of Electrical Engineering, Aligarh Muslim University, India having project numbers
CRGS/MOHD TARIQ/01 and CRGS/MOHD TARIQ/02.
Acknowledgments: The authors also acknowledge the support provided by the Hardware-In-the-
Loop (HIL) Lab and Non-Conventional Energy (NCE) Lab, Department of Electrical Engineering,
Aligarh Muslim University, India.
Conflicts of Interest: The authors declare no conflict of interest.

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