LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;

ENTITY TB_ELEVADOR IS
END TB_ELEVADOR;

ARCHITECTURE BEHAVIORAL OF TB_ELEVADOR IS

COMPONENT ELEVADOR IS
PORT(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
andar_elevator0 : in STD_LOGIC_VECTOR(3 DOWNTO 0);
solicitacao_ele0 : in STD_LOGIC_VECTOR(3 DOWNTO 0);
up_request_in : in STD_LOGIC_VECTOR(3 DOWNTO 0);
down_request_in : in STD_LOGIC_VECTOR(3 DOWNTO 0);
andar_atual_ele0 : out STD_LOGIC_VECTOR(1 DOWNTO 0);
estado_elevator0 : out STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;

SIGNAL w_rst : STD_LOGIC;

SIGNAL w_clk : STD_LOGIC;
SIGNAL andar_ele0 : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL solicitacao : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL up : STD_LOGIC_VECTOR(3 DOWNTO
0);
SIGNAL down : STD_LOGIC_VECTOR(3 DOWNTO
0);
SIGNAL andar_atual : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL estado : STD_LOGIC_VECTOR(1 DOWNTO 0)
--
BEGIN

UUT: ELEVADOR
PORT MAP(
rst => w_rst,
clk => w_clk,
andar_elevator0 => andar_ele0,
solicitacao_ele0 => solicitacao,
up_request_in => up_request,
down_request_in => down_request,
andar_atual_ele0 => andar_atual,
estado_elevator0 => estado
);

-- ---
-- --- PROCESSO DE RELÓGIO
-- ---
PROCESS
BEGIN
w_clk <= '0';
WAIT FOR 10 NS;
w_clk <= '1';
WAIT FOR 10 NS;
END PROCESS;
--
-- ---
-- --- CIRCUITO DE RESET
-- ---
PROCESS
BEGIN
w_rst <= '1';
WAIT FOR 100 NS;
w_rst <= '0';
WAIT;
END PROCESS;
--
-- ---
-- --- TESTE DO ELEVADOR
-- ---
PROCESS
BEGIN
wait for 100 ns;
wait for clk*10;

andar_atual <= '0';

rst<='1';
wait for clk*2;
rst<='0';

for i in 1 to 4 loop
wait for clk_period*2;
rst<='0';
solicitacao_ele0 <= '0';
estado_ele0 <= '00';
up <= '1';
wait for clk*2;
solicitacao_ele0 <= '1';
estado_ele0 <= '01';
andar_atual = andar_atual+1
wait for clk*2;
end loop

estado_ele0 <= '0';

up <= '0';
wait for clk*6
wait
END PROCESS;

END BEHAVIORAL;