Name : Ashwin Reddy Kambalapally

Mail id: k.ashwinreddy12@gmail.com Phone: +91-8686674715

Experience : 3 year 10 months of experience in Physical Design &

Physical Verification

Professional summary:

➢ Cerium Systems, Bangalore. Designation: Physical Design Engineer , Duration: 3 years

4 months ( March 2018 – july 2021)
➢ SpicaWorks PVT LTD , Hyderabad . Designation: Sr. Physical Design Engineer ,
Duration : 6 months (july 2021 - present)
➢ 7 Tape outs Experience in (deep submicron technologies) 10nm , 7nm which
include various domains like server and DDR IP platforms.
➢ Hands on experience in handling Place & Route tools/Platform like IC Compiler,
ICC2, ICV, Primetime, Formality & Calibre.

Technical Skills:
• Place & Route tools: ICC, ICC-ll
• Synthesis – DC Compiler
• FEV-Conformal LEC
• Timing Analysis: PrimeTime
• DRC and LVS – Calibre , ICV
• Scripting languages: TCL

• PROJECT DETAILS:

Project name: CPK

• Technology : 10nm
• Roles: Worked as a physical design and verification engineer. Performed sanity checks ,
floorplan , placement , cts , routing . Cleaned PV flows like DRC, LVS, TRCLVS ,
ECO’s (Timing and RV Fixes), Buffer insertions, diode insertions, PMJ checks, Terminal
checks, Density(Via, Poly,N+P,) .
• Tools used: Synopsys IC Compiler, IC Validator , IC Workbench
Project name: TIP

• Technology : 10nm
• Roles: Performed sanity checks , floorplan , placement , cts , routing . Cleaned PV flows
like DRC, LVS, TRCLVS, Extraction, Density, and Antenna. Implemented Timing Eco’s
and performed net improvement for timing fixes . Worked on Signal Integrity issues .
• Tools used: Synopsys IC Compiler, IC Validator , Primetime

Project name: JSC

• Technology : 10nm
• Roles : Worked as Physical Design Engineer . Owned 2 partitions , was responsible for
Timing closure of the design. STA closure, ECOs implementation, Formality check, PV
related feedbacks, Caliber, Signoff DRC/LVS

• Description: JSC was a test chip. Total number of blocks were 21.

• Tools used : ICC2, Calibre, Primetime

Project name: FBC

• Technology : 7nm
• Roles : Worked as Physical Design Engineer . Owned 2 partitions , was responsible for
Timing closure of the design. STA closure, ECOs implementation, Formality check, PV
related feedbacks, Signoff DRC/LVS

• Description: FBC was a test chip. Total number of blocks were 14.

• Tools used : ICC2, Primetime , ICV

Project name: PNC

• Technology : 7nm
• Roles : Worked as Physical Design Engineer . Owned 2 partitions , was responsible for
Timing closure of the design. STA closure, ECOs implementation, Formality check, PV
related feedbacks, Signoff DRC/LVS

• Description: PNC was a test chip. Total number of blocks were 10.

• Tools used : ICC2, Primetime , ICV

 Project name: DDR
• Technology : 10nm
• Roles: Worked as a physical verification engineer. Cleaned PV flows like DRC, LVS,
density and Antenna.
• Tools used: Synopsys IC Compiler 2, IC Validator

Project name: CPM

• Technology : 10nm
• Roles: Worked as a physical verification engineer. Cleaned PV flows like DRC, LVS,
Extraction, Density, and Antenna.
• Tools used: Synopsys IC Compiler, IC Validator

Project name : AVK

Technology : 7nm
Role :
Worked as Physical Design Engineer . Owned 2 partitions , was responsible for Timing
closure of the design. STA closure, ECOs implementation, Formality check, PV related feedbacks, Signoff
DRC/LVS
Description : AVC was a test chip. Total number of blocks were 20.
Tools used : ICC2, Primetime , ICV

Educational qualifications:

YEAR of
S.NO COURSE INSTITUTION UNIVERSITY PERCENTAGE
PASSING
CVR College
B.TECH. of JNTU, 82%
1.
(EEE) Engineering Hyderabad 2017
[Autonomous
]
Board of
Sri Gayatri Junior intermediate ,
2. Intermediate College Andhra
2013 94%
Pradesh

Board Of
Karthikeya S.S.C,
3. S.S.C 2011 93%
Concept School Andhra
Pradesh.

Declaration: I hereby declare that all the details furnished above are true to the best of
my knowledge and belief.

Place: Bangalore ASHWIN REDDY