Ngôn ngữ mô tả phần cứng VHDL

M 2 M 2
6.1. PROCESS ---------------------------------------------------------------------------------------------------------------------- 71

6.2. S Ê VARIABLES.-------------------------------------------------------------------------------------------------------- 72
MC C 6.3.
6.4.
IF. ------------------------------------------------------------------------------------------------------------------------------- 73
WAIT. -------------------------------------------------------------------------------------------------------------------------- 76
6.5. CASE. --------------------------------------------------------------------------------------------------------------------------- 79
Á LB Ê K ------------------------------------------------------------------------------------------------------------------- 3
6.6. LOOP. -------------------------------------------------------------------------------------------------------------------------- 84
1.1. GI TVHDL ------------------------------------------------------------------------------------------------------------ 3 6.7. BAD CLOCKING.----------------------------------------------------------------------------------------------------------------- 91
1.2. GI Â ( V Ã ) THI ÂÁ VHDL. ------------------------------------------------------ 4 6.8. S Ã À THI Â Â Â ÚH E.----------------------------------------------------------------------- 94
1.2.1 H H D HH Q E H A ----------------------------------------------------------- 4
Á LB Ê B VARIABLE ---------------------------------------------------------------------------------------------------- 97
1.2.2 Quy trinh thi k Q E H A -------------------------------------------------------------------------------- 5
1.2.3. H A -------------------------------------------------------------------------------------------------------------- 6 7.1. CONSTANT.------------------------------------------------------------------------------------------------------------------- 97
1.2.4. Chuy H A Q ------------------------------------------------------------------------------------------ 6 7.2. SIGNAL. ------------------------------------------------------------------------------------------------------------------------ 97
7.3. VARIABLE --------------------------------------------------------------------------------------------------------------------- 99
Á LB Á DÁ A--------------------------------------------------------------------------------------------------------------- 9
7.4. SU .---------------------------------------------------------------------------------------------------------------- 107
2.1. C Â VHDL Â Á . ----------------------------------------------------------------------------------------------------------- 9
Á LB HÊ B ------------------------------------------------------------------------------------------------------- 119
2.2. K Á DLIBRARY.--------------------------------------------------------------------------------------------------------------------- 9
2.3. ENTITY (TH Â ). -------------------------------------------------------------------------------------------------------------------11 8.1. GI .-------------------------------------------------------------------------------------------------------------------- 119
2.4. ARCHITECTURE ( CS Â). ------------------------------------------------------------------------------------------------------12 8.2. THI D 1 (THI D BH MAY MOORE).----------------------------------------------------------- 121
2.5. C Â CÃ . -------------------------------------------------------------------------------------------------------------17 8.3. THI 2. -------------------------------------------------------------------------------------------------------------- 129
8.4. KI À D : TW EA Ê ONEHOT. ------------------------------------------------------------------------------- 143
Á LB GÊ K ---------------------------------------------------------------------------------------------------------------21
Á LB Ê ÁÁ Á ------------------------------------------------------------------------------------------ 145
3.1. C Â Ã T . -------------------------------------------------------------------------------------------------21
3.2. C Â Ã R Ã A. ---------------------------------------------------------------------------------24 9.1. BARREL SHIFTER. ------------------------------------------------------------------------------------------------------------- 145
3.3. C Â ÂD (SUBTYPES).-----------------------------------------------------------------------------------------------------------25 9.2. B ÊDÊ ÃS ÂĐÃS . --------------------------------------------------------------------------------------- 148
3.4. M (ARRAYS). ---------------------------------------------------------------------------------------------------------------26 9.3. B Â CARRY R EE ÁÂ CARRY LOOK AHEAD.---------------------------------------------------------------- 152
3.5. M ÂÚ ( PORT ARRAY). --------------------------------------------------------------------------------------------------29 9.4. B Â ÃS Â S . ---------------------------------------------------------------------------------------------------- 156
3.6. KI Á (RECORDS). ------------------------------------------------------------------------------------------------------31 9.5. B T FÁ G. --------------------------------------------------------------------------------------------- 161
3.7. KI Ã ÂĐÃS ÃS ( SIGNED AND UNSIGNED).-----------------------------------------------------------31 9.6. B Ã U I E.--------------------------------------------------------------------------------------------------- 166
3.8. CHUY ÚÃ . -----------------------------------------------------------------------------------------------------------33 9.7. B Â F ÊD ÊD U E.----------------------------------------------------------------------------------- 169
3.9. TĐ .-------------------------------------------------------------------------------------------------------------------------------35 9.8. T Â Ã7 THANH. ----------------------------------------------------------------------------------------------- 170
3.10. C Â CÃ .----------------------------------------------------------------------------------------------------------------------------35 9.9. B E C .------------------------------------------------------------------------------------------------------------ 175
9.10. THI Á . ------------------------------------------------------------------------------------------------------------- 178
Á LB ÊC B THU Á B ---------------------------------------------------------------------------------------------43
Á LB Ê B B B B MÁ ------------------------------------------------------------- 185
4.1. TD . ------------------------------------------------------------------------------------------------------------------------43
4.1.1. H H -----------------------------------------------------------------------------------------------------------------43 10.1 T QUAN Â ÂPH M H TRPCQ PLD ---------------------------------------------------------------- 185
4.1.2. H ------------------------------------------------------------------------------------------------------------43 10.1.1. PALASM 2 (PAL ASSEMBLER) --------------------------------------------------------------------------------------- 185
H H T -----------------------------------------------------------------------------------------------------------44 10.1.2. AMAZE -------------------------------------------------------------------------------------------------------------------- 185
4 H H ------------------------------------------------------------------------------------------------------------44 10.1.3. PLAN ( Programmable Logic Analysis) --------------------------------------------------------------------------- 185
O H -----------------------------------------------------------------------------------------------------------------44 10.1.4. HELD (Harris Enhanced Language for Programmable Logic)---------------------------------------------- 185
4.2. THU Â C .---------------------------------------------------------------------------------------------------------------------44 10.1.5. PLPL (Programmable Logic Programming Language)------------------------------------------------------- 185
4.2.1. ThuU H ----------------------------------------------------------------------------------------------------------44 10.1.6. APEEL (Assembler for Programmable Electrically Erasable Logic)--------------------------------------- 185
4.2.2. ThuU H H ---------------------------------------------------------------------------------------------------------45 10.1.7. IPLDS II (Intel Programmable Logic Devolopment System II)---------------------------------------------- 186
4.3. THU Â C R Â NGH Á R Ã . ---------------------------------------------------------------------------46 10.1.8. CUPL ( Universal Compiler for Programmable Logic ) ------------------------------------------------------- 186
4.4. CHÙ D . ----------------------------------------------------------------------------------------------------------------------46 10.1.9. ABEL (Advanced Boolean Expression Language)-------------------------------------------------------------- 186
4.5. GENERIC. ----------------------------------------------------------------------------------------------------------------------47 XX : H B QVI MQ B -------------------------------------------------------------------------------------- 187
4.6. VCÃ . ----------------------------------------------------------------------------------------------------------------------------------48 10.2. S D PH M ISE WEDPACK 9.2 ------------------------------------------------------------------------------- 187
10.2. H H HD S I RH ------------------------------------------------------------ 187
Á LB Ê A CB CNG -----------------------------------------------------------------------------------------------------------53
10.2.2. TQ U Ì -------------------------------------------------------------------------------------------------- 189
5.1. SD ÊD .-------------------------------------------------------------------------------------------------------53 10.2.3. TQ U HQI Q ------------------------------------------------------------------------ 195
5.1.1. MQ I Q -----------------------------------------------------------------------------------------------53 10.2.4. Thi H H H ------------------------------------------------------------------------------------- 199
O H H RH -------------------------------------------------------------------------------------------53 10.3. GI THI PH M MODELSIM ISE WEB PACK------------------------------------------------------------------- 204
5.2. S Ã ÂÂ D .---------------------------------------------------------------------------------------------------------54
5.3. M TWHEN. --------------------------------------------------------------------------------------------------------------------55
5.4. GENERATE.--------------------------------------------------------------------------------------------------------------------64
5.5. BLOCK. -------------------------------------------------------------------------------------------------------------------------66
5.5.1. Simple BLOCK ----------------------------------------------------------------------------------------------------------------66
5.1.2. Guarded BLOCK -------------------------------------------------------------------------------------------------------------68
Á LB ÊA B M---------------------------------------------------------------------------------------------------------------71
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BEGIN
x <= a NAND b;
END myarch; Z(3) <= not (A and B);

Z(0) <= not (ABAR and BBAR);
â YZé
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ZaUZo dSj Z(2) <= not (A and BBAR);
Z(1) <= not (ABAR and B);
M [_ f ZS [Tmath Uf
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Else
UZabZqbfõadSZí _ f [ f d
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zUUvfZ TS
a
g _U mU ZS[Tmah U mUft Z[gTs f d
aY UmUbZ f Ts f d
aYZ f Z Y ZSkUmU Z <= not (ABAR and B);
Zn_ hnfZ fU_xf úZaõfã YUSZ f Z Y Is US [ fdzUn Zp ã Uãftuê End if;
fZW
a Y [j V Y 8vZS [UmUZ_xf ú[ f d
zUUS_ fbZ f ZaUZ f Z Y ãv End process;
n_xZuZZaõ fã Y 7W ZSh[agdZS k_xfúfZWa_xZuZU ùgfd
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END arc_behavioral;
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architecture identifier of entity_name is
ARCHITECTURE behavior OF nand IS Architecture_declarative_part
-- ;TMU Nf[ OfO lZ TUôa NkZ [ZS bg OfO Nl PMZT begin
BEGIN all_concurrent_statements
c <= NOT(a AND b); end
[architecture][architecture_simple_name];
END behavior;
Z
S[T
maU
mUf
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Z 0
EjM 2:
Component
ARCHITECTURE behavioral of decode2x4 is CkZKO[ [Z [ I PMZT _fOT .
BEGIN End component;
Process (A,B,ENABLE)
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Variable ABAR,BBAR: bit; _xfúU YC6C9ã Uã Z YZéSfíYf Z h tV h[U YCDI e S
gãv_xfúe
í
Begin ã _vU [Um
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ABAR := not A;
BBAR := not B;
:R 6>23<6 0 v w T Z
KtV 1: KtV 2:
Architecture arc_mach_cong of mach_cong is
Component Xor
Port( X,Y : in bit ; Z, T : out bit);
End component;
8i
VP2. 5 A KI Oer RS Component And
ENTITY rsff IS Port(L,M :input ;N,P : out bit );
PORT( r : IN std_logic; End component;

s : IN std_logic;
Begin
q : OUT std_logic;
G1 : Xor port map (A,B,Sum);
qb : OUT std_logic);
G2 : And port map (A, B, C);
END rsff;
ARCHITECTURE kien_truc OF rsff IS End arc_mach_cong;
COMPONENT nand -- ZT ZST M O ZS ZMZP

8 R
oIt
MRPDR
HFNL HMHRMGH O
GENERIC(delay : time);
PORT(a : IN std_logic;
vn_xZuZ fZbUS(_xZ
uZf
ds
b : IN std_logic;
c : OUT std_logic); EjM
END COMPONENT; Entity adder is
BEGIN Port (A,B,Ci : bit
u1: nand -- OgU ì a Xg TgZT TéZ ZMZP S, Cout : bit);
GENERIC MAP(5 ns) -- SUf P XMe On Tó TMe U End adder;
values
PORT MAP(s, qb, q); -- b Z : OT[ TgZT TéZ
Architecture arc_mixed of adder is
u2: nand -- thi Xê a' Xg TgZT TéZ ZMZP
Component Xor2
GENERIC MAP(5 ns)
Port( P1, P2 : in bit;
PORT MAP(q, r, qb);
PZ : out bit);
END kien_truc;
End compenent;
Signal S1 :bit;
Begin 1 ---------------------------------------
2 LIBRARY ieee;
X1 : Xor2 port map(A,B,S1);
3 USE ieee.std_logic_1164.all;
Process (A,B,Cin) 4 ---------------------------------------
Variable T1,T2,T3 : bit; 5 ENTITY dff IS
6 PORT ( d, clk, rst: IN STD_LOGIC;
Begin
7 q: OUT STD_LOGIC);
T1 := A and B; 8 END dff;
T2 := B and Cin ; 9 ---------------------------------------

10 ARCHITECTURE behavior OF dff IS
T3 := A and Cin;
11 BEGIN
Cout := T1 or T2 or T3 ; 12 PROCESS (rst, clk)
13 BEGIN
End process;
14 IF (rst='1') THEN
End arc_mixed ; 15 q <= '0';
16 ELSIF (clk'EVENT AND clk='1') THEN
2.5. 3cL_jM V ù 17 q <= d;
Trong m U n
kUZzYfSe f
duZTnk(htV ãgf[s h _pK=9A B [htV ãg 18 END IF;
ã Uf ZWar_T[UmUU
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mU fcgú_xbZ Y 19 END PROCESS;
20 END behavior;
KtV ( 09;;h [GW
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21 ---------------------------------------
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---------------------------------------
ENTITY example IS
PORT ( a, b, clk: IN BIT;
q: OUT BIT);
END example;
---------------------------------------
ARCHITECTURE example OF example IS
SIGNAL temp : BIT;
BEGIN
temp <= a NAND b;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk='1') THEN q<=temp;
END IF;
END PROCESS;
END example;
---------------------------------------
DY HC3: KIm: 20
n: DY HC3: KIm: 20
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EjM SIGNAL x: BIT;
BâVO(1. H PôVOT
WOKOâ K
-- d O WTMU Nf[ ZT lZ TUôa _ WUóa 3:C
SIGNAL y: BIT_VECTOR (3 DOWNTO 0);
-- e Xg bO ) NU b U NU NkZ fU ZT O Xg =B3
SIGNAL w: BIT_VECTOR (0 TO 7);
-- c Xg bjO , NU TlM NkZ T U ZT O SúU Xg =B3
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DY HC4: 95P49 M9 : 94 DY HC3: KIm: 20
n:
STD_ULOGIC( STD_ULOGIC_VECTOR): h f
Z Y aY[
U/_ Uf daYU hu SIGNAL a: BIT;
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_xf ú f
ds n_ ffbU a USHI9QJAD<>8= f Z YfZ(n kf Zs_ Y[mfd SIGNAL c: STD_LOGIC;
aY[
UJ SIGNAL d: STD_LOGIC_VECTOR(7 DOWNTO 0);
7DDA:6C0ãzYe S[ SIGNAL e: INTEGER RANGE 0 TO 255;
...
INTEGER: s Ygk
s )(T[
fe f -( * *.),* ã ( * *.),*)
a <= b(5); -- O Tj OrZS WUóa bp T ZS 3:C
NATURAL: ms Ygk
s ZxYo
_ f &ã ( * *.),* b(0) <= a; -- O Tj OrZS WUóa bp T ZS 3:C
REAL: s f
Z U _f
daY ZaúY f - &:).ã &:). c <= d(5); -- O Tj OrZS WUóa bp T ZS STD_LOGIC)
d(0) <= c; -- O Tj OrZS WUóa bp T ZS BC K< 8:4
Physic literals: s V Yã[h[U
mUãõ
[ Yhf Zf
Z[Y[
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b =g
a <= c; -- WTpZS O Tj WTpZS Tó W T WUóa 3:C d
t
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STD_LOGIC)
8ZS
dSU
fWd[
fWd
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Zg[U
mU f Zf
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H><C:9 hn JCH> <C:90U

mU [g V [g ã U ã Z YZé Sf d
aY Yv[ -- STD_LOGIC_VECTOR)
std_logic_arith c S f
Z h[ ieee 8ZzY U v ZuZ f
Z U Y[ Y Z e <= b; -- WTpZS O Tj WTpZS Tó W T WUóa :>C686A
x BIT_VECTOR)
HI9QAD<> 8QK:8IDG Z Y YS [fdUm
Ufam f e ZU_nf[
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d [g> CI:<:G
-- STD_LOGIC_VECTOR)
3cL_jM
3.2. 3cLTR MÀU
R WP RMpWP WQWPQ
x0 <= '0'; -- bit, std_logic, or std_ulogic value '0' VHDL cèYU
ZabZqb Y [V Yf ã Z YZé
SUm
U [gV [g=S [aõ[ [gV li g
x1 <= "00011111"; -- bit_vector, std_logic_vector, Y [V Yã Z YZé
Sã UUZdSV [ãokTSaY_integer hnenumerated.
-- std_ulogic_vector, signed, or unsigned
x2 <= "0001_1111"; -- ZS SãOT P U OT[ Tj Pò TmZT PaZS Ki R
WNPN WP RMpWP WQWPQ
TZ
TYPE integer IS RANGE -2147483647 TO +2147483647;
x3 <= "101111" -- bióa PUòZ ZT Thn c M _ Tê ThZ )+
-- Th O M WUóa Zge i O ZT ZST M O N U WUóa :>C686A
x4 <= B"101111" -- ZT kZ
TYPE natural IS RANGE 0 TO +2147483647;
x5 <= O"57" -- bióa PUòZ Nf ThZ O M _ Tê ThZ )+
-- Th O M WUóa Zge O i ZT ZST M O N U WUóa >2CDA2<
x6 <= X"2F" -- bi a PUòZ _ Tê X O ThZ O M _ Tê
ThZ )+ TYPE my_integer IS RANGE -32 TO 32;
n <= 1200; -- s ZSaekZ -- M ê O[Z OfO _ UZ S g ZS U PrZS ZT ZST M
m <= 1_200; -- s ZSaekZ OT[ Tj SãOT P U TYPE student_grade IS RANGE 0 TO 100;
IF ready THEN... -- Logic, th O TUôZ Z a MPe0CAD6 -- M ê O[Z OfO _ ZSaekZ T[ìO _ ZTUkZ ZS U PrZS ZT
ngh M
y <= 1.2E-5; -- real, not synthesizable
K 4fO WUóa ZS U PrZS UZT ZST M
q <= d after 10 ns; -- physical, not synthesizable
TYPE bit IS ('0', '1');
-- O ZT ZST M O N U WUóa 3:C
TYPE my_logic IS ('0', '1', 'Z');
EjM 8mUf
am f ã UbZq
bhn ZxYã UbZq
b _ Y[SU
mU [gV [g Zm
U
-- M ê O[Z O M _ PKX[SUO g ZS U PrZS ZT ZST M
nhau:
DY HC4: 95P49 M9 : 94 DY HC3: KIm: 20
n:
TYPE bit_vector IS ARRAY (NATURAL RANGE <>) OF BIT; 6dM X 4fO Tj [fZ T Xô bg WTpZS T Xô SU M OfO WUóa P
liôa bg OfO WUóa P XUôa O[Z
-- i O ZT ZST M O N U 3:CKE64C A
SUBTYPE my_logic IS STD_LOGIC RANGE '0' TO '1';
-- A2>86 /1 O _ P ZS ó OT T íZS OfO O WTpZS SU U
hãZ SIGNAL a: BIT;
-- NATURAL RANGE <>, on the other hand, indicates that the SIGNAL b: STD_LOGIC;
only
SIGNAL c: my_logic;
-- restriction is that the range must fall within the NATURAL
...
-- range.
b <= a; --WTpZS T Xô WTpZS Tó W T WUóa 3:C b U
TYPE state IS (idle, forward, backward, stop); STD_LOGIC)
-- M WUóa P XUôa UóZ TmZT O M OfO fe ãZS TfU T a b <= c; --h Xô OrZS WUóa O _ BC K< 8:4
hãZ
TYPE color IS (red, green, blue, white); 3.4. MôWP 1 b
-- Kióa P XUôa XUô Wk WTfO MúY n_ ffbZbU mUã[f YUvU Y [g 8ZzYU
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trong f
d YZbY[S_ f[gU a hn [gU
íe fíY Yh[ v _ Scalars: BIT, STD_LOGIC, STD_ULOGIC, and BOOLEAN.
_ Vectors: BIT_VECTOR, STD_LOGIC_VECTOR, STD_ULOGIC_VECTOR,
EjM Ki gd [ge
Sgão
k Z ã UU
mU [gV [gã UY[[f
Z[gf
daYU
mUhtV INTEGER, SIGNED, and UNSIGNED.
ph f
d U
SUBTYPE natural IS INTEGER RANGE 0 TO INTEGER'HIGH;

-- NATURAL is a kióa O[Z ê O[Z [R :>C68ER.
SUBTYPE my_logic IS STD_LOGIC RANGE '0' TO 'Z';
-- GúU XãU BC K< 8:40 G H F < -').
-- [ n eKX[SUO0 H
SUBTYPE my_color IS color RANGE red TO blue; 8i
VP(1. Minh hóIscalar I 4 4 4K c4L
-- WTU O[X[ 0 P S Z NXa cTU Tm
CZ U vfZfZùk ZxYZ U vã Z YZé
Sfd U_úY(9 ZaU 9j9 _n Z[U
-- my_color=(red, green, blue).
thi fU bZú[ã UUZ ã ZT [ Y [V Y n_ Z hk _ f [g_ [ W
i
SUBTYPE small_integer IS INTEGER RANGE -32 TO 32;
TYPE) c bZú[ã Uã Z YZé
Sãgf[s eS
gãv nf
t Z[g_ [ W
iH><C6A Wi
-- M ê O[Z O M :>C686A
DY HC4: 95P49 M9 : 94 DY HC3: KIm: 20
n:
VARIABLE h U8DCHI6CIU
vfZ ã U ZS
[Tm
ae d Y [gV [gãv 8z CZ ãpfZù
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b fd
s Y[
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SV [ãok
0
U
Zã Z_ f[g_úY_ [
0
... :="0001"; -- for 1D array
TYPE type_name IS ARRAY (specification) OF data_type;
... :=('0','0','0','1') -- for 1D array
ó ã[ _ P ZS WUóa ZS U
SIGNAL signal_name: type_name [:= initial_value]; ... :=(('0','1','1','1'), ('1','1','1','0')); -- for 1Dx1D or-
- 2D array
Id
aYU zbZmb f d
s _ fH>
<C6Aã U ZS[Tm
a Igk Z[
s vU
èYU
vfZ n_ f
DhL/3bKXPf
XObVUâVOP XT cS
PlVOP XT
CONSTANT ho U_ fK6G>
67A: <[
Sfd Z[f
õafkUZ
EZq bYm f
daYhtV n
kã UV Sf
ds ã Z YZé
S [ghn ZS
[Tm
aUm
Uft Z[g Z
E LoMG 0 0:
sau:
8ZzYf S_g jo kV Y_ f_úYU Z S*hW
Ufad_ [hWUf
adU vt UZf Z U n.T[f TYPE row IS ARRAY (7 DOWNTO 0)OF STD_LOGIC;
ãv n_ f_úY 9j9 ZuZ) ISY[_ [hW U
fadnZn ng (row) hn_úYZan
-- 1D array
ch Z n_Sfd (matrix) =í SUZzYf S_g T[ fTs f
dm[U YUS_ [hW Ufadf
d
fZnZBH7 _ae fe[Y[ X[U
SfT[
fUS v hnVwYf d
s U Yf dfZnZVwY& Z[ãv TYPE array1 IS ARRAY (0 TO 3) OF row;
s fZ UZ[ ãkã _úYe n Z e Sg0 -- 1Dx1D array

TYPE array2 IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
TYPE row IS ARRAY (7 DOWNTO 0) OF STD_LOGIC; -- 1D array
-- 1Dx1D
TYPE matrix IS ARRAY (0 TO 3) OF row; -- 1Dx1D array
TYPE array3 IS ARRAY (0 TO 3, 7 DOWNTO 0) OF STD_LOGIC;
SIGNAL x: matrix; -- 1Dx1D signal
-- 2D array
E Lo
MG 0 0 HW
D
SIGNAL x: row;
8m
UZ Zm
Uã jo
kV Y_úY 9j9 f
dsU
w ã Uf
Z UZ[ Z e
Sg0 SIGNAL y: array1;
TYPE matrix IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(7 SIGNAL v: array2;

DOWNTO 0); SIGNAL w: array3;
E Lo
MG 0 --------- 8m
UbZq
bYm hxZ YZ b 0---------------
MúYeSgão kf
Z Ue nZS
[UZ[g A g d Yh[Ujo
kV Y vV Sf
dsU
mUhW
Ufad -- 4fO Tj SfZ ãU X ZS bp T ZS NU Z P U he Xg T
Z Y ZmZan UZ Zf
dsUm
Uãõ[ YhxZ Y lô
-- b U bm WUóa bp T ZS O N Z Xg BC K< 8:4 OT[ O OfO
TYPE matrix2D IS ARRAY (0 TO 3, 7 DOWNTO 0) OF STD_LOGIC;
lZ TUôa
-- 2D array
-- (x,y,v,w).
* Kh ãK
PWmâVO/
x(0) <= y(1)(2); -- X a ' Oì P a ZS[ìO Z
-- (y is 1Dx1D)
x(1) <= v(2)(3); -- 2 cì P a ZS[ìO Z b U_ d
DY HC4: 95P49 M9 : 94 DY HC3: KIm: 20
n:
x(2) <= w(2,1); -- 1 cì P a ZS[ìO Z c U_ ' Z[U

mU ZS
[Tm
aINE: ZxYã UUZabZq
bfd
aY_ f:CI>IN Y[
ú[bZm
bã ZS
[
y(1)(1) <= x(6); Tma [gV [g Y [V Yã Z YZéSf
daY_ fE68 6<: _nUvfZ Z T[f
fan T f
Z[f B fhtV Z e
Sg0
y(2)(0) <= v(0)(0);
y(0)(0) <= w(3,3); ------- Package: --------------------------
w(1,1) <= x(7); LIBRARY ieee;
w(3,0) <= v(0)(3); USE ieee.std_logic_1164.all;
--------- <m hW
Ufad
0--------------------- ----------------------------
PACKAGE my_data_types IS
x <= y(0); -- h Xô OrZS WUóa A F
TYPE vector_array IS ARRAY (NATURAL RANGE <>) OF
x <= v(1); -- WTpZS T Xô WTpZS Tr T WUóa AF
bg STD_LOGIC_VECTOR(7 DOWNTO 0);
-- STD_LOGIC_VECTOR) END my_data_types;
x <= w(2); -- WTpZS T Xô c T U Xg ' --------------------------------------------
x <= w(2,2 DOWNTO 0);--WTpZS T Xô WTpZS Tr T WUóa A F d ------- Main code: -------------------------
-- STD_LOGIC) LIBRARY ieee;
v(0)<=w(2,2 DOWNTO 0); --illegal(mismatch: STD_LOGIC_VECTOR USE ieee.std_logic_1164.all;
-- x STD_LOGIC) USE work.my_data_types.all; -- user-defined package
v(0) <= w(2); -- illegal (w must have 2D index) ---------------------------
y(1) <= v(3); -- illegal (type mismatch: ROW x ENTITY mux IS
-- STD_LOGIC_VECTOR) PORT (inp: IN VECTOR_ARRAY (0 TO 3);
y(1)(7 DOWNTO 3) <= x(4 DOWNTO 0); -- legal (same type, ... );
-- same size) END mux;
v(1)(7 DOWNTO 3) <= v(2)(4 DOWNTO 0); -- legal (same type, ... ;
-- same size) --------------------------------------------
w(1,5 DOWNTO 1)<=v(2)(4 DOWNTO 0); -- illegal (type 8vf Zf Zùkf d

aYhtV fds _ f [gV [g Y [V Yã Z YZé Sã UY[n
mismatch) vector_array ãpã Ufõ
adS _n vU vfZU Z S_ fe ZxYjm Uã ZUm
UhW Uf
ad
m [hW UfadUZ S.T[f [gV [gã U gY[ f dang m fE68 6<: Y[ n
3.5. MôWPLWP 1 b _k QVSfSQfkbWehneS
gãvã Ue V Yf d
aY_ f:CI> IN ã jmUã Z_ fEDGI
CZ U ZzYf SãpT[f ZxYU v [gV [gã Uã Z YZéSfd Un aU
vZí _ f ã UY[8Zz f d
aYãaõ _pUZtZTS aY_f Zs_Uú_ f_ Zã JH:ã f Z UZ[
chi g Igk Z[
s fd
aYU mUãUã[_ USUmUU
Zo hn
aZaUd SUmUEDGI US_ f Yv[Y [V Yã Z YZé Smy_data_types U
vfZfZùkfd
aYf Z[f
mõ UZã[ _nã Ujo kV Yf ZnZ:CI>
IN UZzYfSU
vfZ bZúi c ã Zd
yUm
U
EDGI Z n_úYU mUK:8IDG Ch U Y Zm UU
ZaE68 6<: f
ds e ã Uf
duZTn
kV [ão
k í[_nU
v ZS
[Tm
a
CONSTANT:
DY HC4: 95P49 M9 : 94 DY HC3: KIm: 20
n:
------- Package: ------------------------------- fZSkhna Y[

mfdUvf
Z nV íYZaUo_ PMW VPLàVO o 9aãv && h
LIBRARY ieee; bi gV[ e +f d
aY Z[ & e T[gV[ e -3
USE ieee.std_logic_1164.all; e V Y [gV [gH> <C:9ZaUJCH><C:9 Yv[std_logic_arith c SfZ h[

---------------------------- ieee, phú[ã U ZS[Tma 7ùfU
ZùbUzbZm
bUSU ZzY [gV [gH> <C:9 hn
PACKAGE my_data_types IS JCH> <C:9 UvZ[gcgúU Z kgã[h[U mUbZqbf
am e ZU YZé S n Y Uh [
STD_LOGIC_VE8IDG U ZzYUZù
b Z U mUbZqbfam e ZU _ f Zt SU õZ
CONSTANT b: INTEGER := 7;
ZmUU mUbZq
bfam aY[
UfZuZxYã UbZqb
TYPE vector_array IS ARRAY (NATURAL RANGE <>) OF
STD_LOGIC_VECTOR(b DOWNTO 0); EjM
END my_data_types; 8m
UbZq
bfam Zb hn ZxYZ b ã[h[ [gV [ge
[YW
Vge
[YW
V0
----------------------------------------------
LIBRARY ieee;
3.6. Ki KôWPQRAN
LM USE ieee.std_logic_1164.all;
Bú YZ[fíYf Z _úY h[ã[_ Zm
Ud YU
ZzYU
Z SU
mUã[f YU
v [gV USE ieee.std_logic_arith.all; -- SnU OéZ TU Tk
li g Zm
U ZS
g bg[
...
KtV0
SIGNAL a: IN SIGNED (7 DOWNTO 0);
TYPE birthday IS RECORD
SIGNAL b: IN SIGNED (7 DOWNTO 0);
day: INTEGER RANGE 1 TO 31;
SIGNAL x: OUT SIGNED (7 DOWNTO 0);
month: month_name;
...
END RECORD;
v <= a + b; -- h Xô Tj [fZ _ TúO ;
3.7. Ki MÀU
R L
lM _dTQnWPM BR
PWN
M WMDWR
PWN
M w <= a AND b; -- WTpZS T Xô Tj [fZ X[SUO WTpZS ;
CZ ãp ã Ub f d U ão
kU mU [g V [g nk ã U ã Z YZé
Sfd
aY Yv[ 8m
UbZq
bfam Zb hn ZxYZ b h [e
fVQaY[
UQhW
Ufad
0
std_logic_arith c Sf
Z h[ ieee 8zbZm
bUSUZzYã U_[ZZSf daYhtV V [
LIBRARY ieee;
ão k0
USE ieee.std_logic_1164.all; -- WTpZS Tk SnU oU TùU
KtV0
...
SIGNAL x: SIGNED (7 DOWNTO 0); SIGNAL a: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL y: UNSIGNED (0 TO 3); SIGNAL b: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
A g d YU zbZm
bUSU
ZzYfí Yf h[HI9QAD<>
8QK:8IDG ZxYY[ Y Z SIGNAL x: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
INTEGER. ...
M fY[
mfdJCH><C:9 n_ fe ZxYTS
aY[ Z Zí lW
da KtV && T[g v <= a + b; -- WTpZS T Xô Tj [fZ _
di e fZbbZo + f
daY Z[ & n ) CZ Y g [gH><C:9 ã Ue V Y húO WTpZS ;
DY HC4: 95P49 M9 : 94 DY HC3: KIm: 20
n:
w <= a AND b; -- h Xô Tj [fZ X[SUO ; Nhi gZn

_UZgk ã[V [gU
vfZ ã Uf
u_f
daYYv[std_logic_arith c Sf
Z h[
KtV08m
UbZq
bfam e ZUh [std_logic_vector ieee:
LIBRARY ieee; conv_integer(p): chuy ã[_ ffZS_ e bUS [g>

CI:<:G JCH>
<C:9
SIGNED, ho U HI9Q JAD<>
8 f
Z nZ _ fY[
mfd>CI:<:G A g d Y
USE ieee.std_logic_1164.all;
HI9Q AD<> 8Q K:8IDG Z xYã U ã
USE ieee.std_logic_unsigned.all; -- bao g SnU Tk bg[
... conv_unsigned(p, b): chuy ã[_ ff
ZS_ e bUS [g>CI:<:G JCH>
<C:9
SIGNED, ho UHI9QJAD<> 8f
ZnZ_ fY[mf
dJCH><C:9h[ tUZU nTT[
f
SIGNAL a: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL b: IN STD_LOGIC_VECTOR (7 DOWNTO 0); conv_signed(p, b): chuy ã[_ ff
ZS_ e bUS [g>
CI:<:G JCH>
<C:9
SIGNAL x: OUT STD_LOGIC_VECTOR (7 DOWNTO 0); SIGNED, ho UHI9Q JAD<>
8fZ
nZ_ fY [
mfdH>
<C:9h[ t
UZU nTT[
fe
... conv_std_logic_vector(p, b): chuy ãi m ff

ZS_ e bf
ZgU [g V [g
v <= a + b; -- h Xô Tj [fZ _ TúO ; INTEGER, UNSIGNED, SIGNED, ho U HI9Q AD<>
8 f
ZnZ _ f Y
[mf
d
WTpZS P a STD_LOGIC_VECTOR v [t UZfZ UTT[f
e
w <= a AND b; -- h Xô Tj [fZ X[SUO ;
EjM L
Q bW RMÀU
R
3.8. Chuy W RMÀU
R LIBRARY ieee;
K=9A ZxYU ZabZqbU
mUbZqbfam fdUf[b s ZU aY[U f
mUã Y s U
mUV
li g Zm
U [g ZSg 9aãv f
Z Y nd ùfU fZ[fã[h [h[UU Zgk ã[V [gf
USE ieee.std_logic_arith.all;
m f [g n ke
SY_ f [g Zm U [g n kU vfZ ã UfZ UZ[ f d
aYZS[Um
UZUí
bú0ZaUU ZzYfSh[f_ ftfUaVWU
Zaã[gãvZaUU ZzYfSY[_ f;JC8I>DCf ...
m fYv[ã Uã Z YZéSfd U_n vU ZabZqbfZ UZ[ Um
UbZqbT[ ã[UZafS SIGNAL a: IN UNSIGNED (7 DOWNTO 0);
SIGNAL b: IN UNSIGNED (7 DOWNTO 0);
N gV [gã UcgS Z ãvY YZé S n(fam ZõYUvU Y [gU íe bùfUZù
b
ãSYã U ZS [Tm
afZgUh ZS[ [g b ZmU ZSgfZue
fVQaY[
UQ ,*USfZ h[ SIGNAL y: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
bU
ieee cung cù mUZn_UZgk ã[V fZ UZ[ ...
y <= CONV_STD_LOGIC_VECTOR ((a+b), 8);
KtV0U
mUbZq
bfam Zb hn ZxYZ b ã[h[U
mUfbU
a
-- Tj [fZ T Xô MN O OTaeóZ U D>B:8>6
TYPE long IS INTEGER RANGE -100 TO 100; TgZT
TYPE short IS INTEGER RANGE -10 TO 10; -- SUf ,-NU BC K< 8:4KE64C A _Ma n SfZ Oho y.
SIGNAL x : short;
M fU mU
ZZ mUUvf ZU Z ã pã Uã Ubã f d
aY_ Uf d Uã
okCvT SaY_ h[U
SIGNAL y : long; s V YU m
UYv [std_logic_signed h
nstd_logic_unsigned t fZh[ ieee. 8mUYv
[n k
... U ZabZq
bU mUbZq bfam h[V [gHI9Q AD<> 8Q K:8IDG ã Uf Z UZ [ gV
li gã
pn [gH> <C:9Z aUJCH> <C:9 _ fU mUZ f
y <= 2*x + 5; -- l U WTpZS Tr T WUóa
y <= long(2*x + 5); -- OK, k ]a O OTaeóZ U
TgZT WUóa X[ZS
DY HC4: 95P49 M9 : 94 DY HC3: KIm: 20
n:
,ClV SIGNAL z: STD_LOGIC_VECTOR (x'HIGH DOWNTO 0); -- 1D signal
8m
U [gV [gK=9Af YZ bU
íTú ã Uf
v_fff
daYTúY)( SIGNAL w1: mem1; -- 2D signal
SIGNAL w2: mem2; -- 1Dx1D signal
BâVO(2. TõVOP XK
bKS L T
SIGNAL w3: mem3; -- 1Dx1D signal
-------- Legal scalar assignments: ---------------------
x(2) <= a; -- same types (STD_LOGIC), correct indexing
y(0) <= x(0); -- same types (STD_LOGIC), correct indexing
z(7) <= x(5); -- same types (STD_LOGIC), correct indexing
b <= v(3); -- same types (BIT), correct indexing
w1(0,0) <= x(3); -- same types (STD_LOGIC), correct indexing
Table 3.2
Synthesizable data types.
Data types Synthesizable values
3cL_jM 3:C 3:CKE64C A v w v w

EjM B YQeWL
QR R_ RL
cLTR MÀli BC K< 8:4 BC K< 8:4KE64C A vGw v w v w vHw _[Xb P
BC KD< 8:4 BC KD< 8:4KE64C A vGw v w v w vHw aZ _[Xb P
8mUbZqbYm Zb hn ZxYZb ã Uf d
uZTn
k f
[bã UV Sf
dsU
mUã Z
S [ghnU
nghé mU ZS
[Tm
aftZ[ge
Sgão
k0 BOOLEAN True, False
>2CDA2< 7 [ [ ' )+ ),( )+
TYPE byte IS ARRAY (7 DOWNTO 0) OF STD_LOGIC; -- 1D
:>C686A 7 [ K' )+ ),( )+ [ ' )+ ),( )+
-- array
B:8>6 7 [ K' )+ ),( )+ [ ' )+ ),( )+
TYPE mem1 IS ARRAY (0 TO 3, 7 DOWNTO 0) OF STD_LOGIC; -- 2D
D>B:8>6 7 [ [ ' )+ ),( )+
-- array
User-defined integer type Subset of INTEGER
TYPE mem2 IS ARRAY (0 TO 3) OF byte; -- 1Dx1D
User-defined enumerated type Collection enumerated by user
-- array
SUBTYPE Subset of any type (pre- or user-defined)
TYPE mem3 IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(0 TO 7); --
1Dx1D ARRAY Single-type collection of any type above
-- array RECORD Multiple-type collection of any types above
SIGNAL a: STD_LOGIC; -- scalar signal Data Types 39
SIGNAL b: BIT; -- scalar signal TLFeBOOK
SIGNAL x: byte; -- 1D signal w1(2,5) <= y(7); -- same types (STD_LOGIC), correct indexing
SIGNAL y: STD_LOGIC_VECTOR (7 DOWNTO 0); -- 1D signal w2(0)(0) <= x(2); -- same types (STD_LOGIC), correct indexing
SIGNAL v: BIT_VECTOR (3 DOWNTO 0); -- 1D signal w2(2)(5) <= y(7); -- same types (STD_LOGIC), correct indexing
DY HC4: 95P49 M9 : 94 DY HC3: KIm: 20
n:
w1(2,5) <= w2(3)(7); -- same types (STD_LOGIC), correct -- Example of data type independent array initialization:
indexing
FOR i IN 0 TO 3 LOOP
------- Illegal scalar assignments: --------------------
FOR j IN 7 DOWNTO 0 LOOP
b <= a; -- type mismatch (BIT x STD_LOGIC)
x(j) <= '0';
w1(0)(2) <= x(2); -- index of w1 must be 2D
y(j) <= '0'
w2(2,0) <= a; -- index of w2 must be 1Dx1D
40 Chapter 3
------- Legal vector assignments: ----------------------
TLFeBOOK
x <= "11111110";
z(j) <= '0';
y <= ('1','1','1','1','1','1','0','Z');
w1(i,j) <= '0';
z <= "11111" & "000";
w2(i)(j) <= '0';
x <= (OTHERS => '1');
w3(i)(j) <= '0';
y <= (7 =>'0', 1 =>'0', OTHERS => '1');
END LOOP;
z <= y;
END LOOP;
y(2 DOWNTO 0) <= z(6 DOWNTO 4);
---------------------------------------------------------
w2(0)(7 DOWNTO 0) <= "11110000";
EjM 2R àW_dKR_N
L
w3(2) <= y;
KtV n k_[ZZSe Zm U ZS
gY[SbZqbYm _ fT[
fãí hnbZq
bYm _ fT[f
z <= w3(1);
S n7>
vector (nghé Ih[7> IQK:8IDG HI9QAD<>
8h[HI9QAD<> 8QK:8IDR,
z(5 DOWNTO 0) <= w3(1)(2 TO 7);
ho UHI9QJAD<> 8h [HI9QJAD<>
8QK:8IDG
w3(1) <= "00000000";
=S[ãaõ _pK=9Aã UY[[f Z[gbZtSV [8úZS[f
Z UZ[ bZqbfam 6C9Y[S
w3(1) <= (OTHERS => '0');
UmUft Z[ghnahnYm fcgúã f t Z[gd
S8Z Uv_ fe Zm UT[fY[SU ZzYãv
w2 <= ((OTHERS=>'0'),(OTHERS=>'0'),(OTHERS=>'0'),(OTHERS=>'0'));
ne YT[
f U YhnahnU Yd S _ fT[
ffd
aYhtV ãùgf[
s *T[ f
efdaYhtV
w3 <= ("11111100", ('0','0','0','0','Z','Z','Z','Z',), th ZS[ BõUZã[ egkd
Sf U
mUãaõ _p nkã UT[gV[ fds ZuZ)(0
(OTHERS=>'0'), (OTHERS=>'0'));
-- code 1---------------------
w1 <= ((OTHERS=>'Z'), "11110000" ,"11110000", (OTHERS=>'0'));
--------------------------------------------------------
------ Illegal array assignments: ----------------------
ENTITY and2 IS
x <= y; -- type mismatch
PORT (a, b: IN BIT;
y(5 TO 7) <= z(6 DOWNTO 0); -- wrong direction of y
x: OUT BIT);
w1 <= (OTHERS => '1'); -- w1 is a 2D array
END and2;
w1(0, 7 DOWNTO 0) <="11111111"; -- w1 is a 2D array
--------------------------------------------------------
w2 <= (OTHERS => 'Z'); -- w2 is a 1Dx1D array
ARCHITECTURE and2 OF and2 IS
w2(0, 7 DOWNTO 0) <= "11110000"; -- index should be 1Dx1D
BEGIN
DY HC4: 95P49 M9 : 94 DY HC3: KIm: 20
n:
x <= a AND b;
END and2;
---------------code 2---------------
ENTITY and2 IS
PORT (a, b: IN BIT_VECTOR (0 TO 3);
x: OUT BIT_VECTOR (0 TO 3));
8i
VP(3. Kí âUlXPòVOK
PW WàVUe KI hL (
END and2;
-------------------------------------------------------------- Code 2:
ARCHITECTURE and2 OF and2 IS

BEGIN
x <= a AND b;
END and2
8i
PW WàVUe KI hL (
EjM 2 LWP 1MMN
8i
VP(5. BùK
ùVO) K
PW hL ((
8i
VP(2. M àK
P K a I UeKI hL (
=uZ))hn)* cho thùkY[ú ã _ Uã ZUS_ fT U Y*T[ f_õUZã[ U v(ãg
K fcgú_xbZ Yf
ds 6U
f[hW=9A, 0 hna ST hn_ fãgd Se g_ 8v(Y[ ú[bZmbã Uã Ub IZ Zù f
, tùfUúUmUft
hi gUv [gV [gH> <C:9 fdaY Z[ Y[ ú[bZm
bfZ ZS
[ãgd SUv [g> CI:<:G
Code 1:
Ag f d
aYY[ú[bZmbfZ ZS[Uv_ fZn_U Zgk ã[U ahWde
[aX gU f
[a ã Ue
d Y VwY ) ã [gUS ST bZ Z bh[ [gUSf Y A g U TS ag _ U
ú
Yv[ef
VQaY[
UQSd
[f
Z VwY*US_ [Y[ ú[bZmb U v_xfú [gV [gH> <C:9 CZ
lõ[d Y_ fY[
mfdH><C:9ã U_xf úY[ Y Z _ fhW Ufad YZé
Snfí Yf Z
STD_LOGIC_VECTOR, ZxYY[ YINTEGER.
DY HC4: 95P49 M9 : 94 DY HC3: KIm: 20
n:
Code: *K ôVnYQ WP i
W1LR
_N84 )
1 ----- Solution 1: in/out=SIGNED ----------
2 LIBRARY ieee;
4 USE ieee.std_logic_arith.all;
5 ------------------------------------------
6 ENTITY adder1 IS 8i
PW hL ((
7 PORT ( a, b : IN SIGNED (3 DOWNTO 0);
8 sum : OUT SIGNED (4 DOWNTO 0));
9 END adder1;
10 ------------------------------------------
11 ARCHITECTURE adder1 OF adder1 IS
12 BEGIN
13 sum <= a + b;
14 END adder1;
15 ------------------------------------------
1 ------ Solution 2: out=INTEGER -----------

2 LIBRARY ieee;
4 USE ieee.std_logic_arith.all;
5 ------------------------------------------
6 ENTITY adder2 IS
7 PORT ( a, b : IN SIGNED (3 DOWNTO 0);
8 sum : OUT INTEGER RANGE -16 TO 15);
9 END adder2;
10 ------------------------------------------
11 ARCHITECTURE adder2 OF adder2 IS
12 BEGIN
13 sum <= CONV_INTEGER(a + b);
14 END adder2;
DY HC4: 95P49 M9 : 94 DY HC4: 95P49 M9 : 94
3Q àWP C> =C EsC8D 3C =8 y <= NOT (a AND b);

y <= a NAND b;
4.1. C cW 4.1.3. C c
W cWh L
b_ fe f
VHDL cung cù am f e
Sg0 8mUf
am f nkV YU ZaU
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SIGNAL x : STD_LOGIC; CzbZm
be V Yf
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VARIABLE y : STD_LOGIC_VECTOR(3 DOWNTO 0); <left operand> <shift operation> <right operand>
SIGNAL w: STD_LOGIC_VECTOR(0 TO 7);
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w <right operand> U
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x <= '1'; >CI:<:G 8vZS [fam f VUZ0
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SIGNAL d : STD_LOGIC_VECTOR(0 TO 7) IF (clk'EVENT AND clk='1')...

IF (NOT clk'STABLE AND clk='1')...
Ta s U
v0
WAIT UNTIL (clk'EVENT AND clk='1');
d'LOW = 0, d'HIGH = 7, d'LEFT = 7, d'RIGHT = 0, d'LENGTH = 8,
IF RISING_EDGE(clk)...
d'RANGE = (7 downto 0), d'REVERSE_RANGE = (0 to 7).
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FOR i IN RANGE (0 TO 7) LOOP ...
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FOR i IN x'RANGE LOOP ...
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FOR i IN RANGE (x'LOW TO x'HIGH) LOOP ...
ATTRIBUTE <attribute_name>:< attribute_type>;
FOR i IN RANGE (0 TO x'LENGTH-1) LOOP ...
ATTRIBUTE <attribute_name> OF< target_name>: <class> IS
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ATTRIBUTE number_of_inputs: INTEGER;
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FUNCTION "+" (a: INTEGER, b: BIT) RETURN INTEGER IS EjM 7N
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BEGIN
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IF (b='1') THEN RETURN a+1; g _m Tt
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tZ[gnena CvUv_ fãgdSV [gY_ Ttf8vm = log2(n).
ELSE RETURN a;
END IF;
END "+";
4.5. GENERIC.
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dUS v gx n. LIBRARY ieee;
ENTITY my_entity IS
ENTITY decoder IS
GENERIC (n : INTEGER := 8);
PORT ( ena : IN STD_LOGIC;
PORT (...);
sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
END my_entity;
x : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
ARCHITECTURE my_architecture OF my_entity IS
END decoder;
...
ARCHITECTURE generic_decoder OF decoder IS
END my_architecture;
BEGIN
8vf
ZUv Z[gZí f
ZS_e <:C:G>
8ã U_xf
úfd
aY_ f:CI>
IN KtV0
PROCESS (ena, sel)
GENERIC (n: INTEGER := 8; vector: BIT_VECTOR := "00001111");
VARIABLE temp1 : STD_LOGIC_VECTOR (x'HIGH
DOWNTO 0);
DY HC4: 95P49 M9 : 94 DY HC4: 95P49 M9 : 94
VARIABLE temp2 : INTEGER RANGE 0 TO x'HIGH; EjM : Generic parity detector.

BEGIN
VtV eSgãok_xbZ Y_ f_õUZbZm
fZ[ ftZbS
d[f
kCvTSaY__ fãghna
temp1 := (OTHERS => '1'); Ttfhn_ fãgdS gdSe UvY[
mfdT Y& Z[e ãghnaU
vY[mf
d n_ fn_ fe
temp2 := 0; ch hnT Y f daYUm
Ufd YZ bU w õ[
IF (ena='1') THEN
FOR i IN sel'RANGE LOOP
IF (sel(i)='1') THEN
temp2:=2*temp2+1;
ELSE 8i
VP)3. BùXPb P V hK
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temp2 := 2*temp2;
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END IF;
END LOOP; ENTITY parity_det IS
temp1(temp2):='0'; GENERIC (n : INTEGER := 7);
END IF; PORT ( input: IN BIT_VECTOR (n DOWNTO 0);
x <= temp1; output: OUT BIT);
END PROCESS; END parity_det;
END generic_decoder;
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Sgão
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ds ARCHITECTURE parity OF parity_det IS
BEGIN
PROCESS (input)
VARIABLE temp: BIT;
BEGIN
temp := '0';
8i
VP)2. lXPòVOS
í âKI ùUePWb FOR i IN input'RANGE LOOP
temp := temp XOR input(i);
CZ UZzYf Sf
Zùk Z[ena = 0 f
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END LOOP;
ch _ fTt
fbZt
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Zuãgd Sx =
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r output <= temp;
END PROCESS;
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END parity;
DY HC4: 95P49 M9 : 94 DY HC4: 95P49 M9 : 94
IdaYãaõ _pf
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8ã Z YZé
S 3 Z[ VARIABLE temp2: BIT_VECTOR (output'RANGE);
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Zuãg temp1 := '0';
dSagf
bgf3& Z[[bgf3&&&&&&& f
ZuãgdSagf
bgf3 hue ãghn an n_ f FOR i IN input'RANGE LOOP
s
temp1 := temp1 XOR input(i);
temp2(i) := input(i);
END LOOP;
temp2(output'HIGH) := temp1;
output <= temp2;
8i
VP)4 lXPòVOS
íquâKIPi
VP)
END PROCESS;
EjM Rb7N
WN
END parity;
MõUZe
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ns
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[Y[ Y Z - ãghn aãg 50 100 150 200 250 300 350 400 450 500
d
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k input 00 01 02 03 04 05
output 00 81 82 03 84 05
8i
VP)6. lXPòVOS
í âKI hL )(
CZ fSf
Zùk Z[ãghna[bgf3&&&&&&& f
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a
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ZuãgdSagf
bgf3 &&&&&&
ENTITY parity_gen IS
GENERIC (n : INTEGER := 7);
PORT ( input: IN BIT_VECTOR (n-1 DOWNTO 0);
output: OUT BIT_VECTOR (n DOWNTO 0));
END parity_gen;
ARCHITECTURE parity OF parity_gen IS

BEGIN
PROCESS (input)
VARIABLE temp1: BIT;
DY HC5: 3N854 854 DY HC5: 3N854 854
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DY HC5: 3N854 854 DY HC5: 3N854 854
B V sZ*- U v*ãghnaV [g ZS
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khi e&e HSgãoknUZ íYf
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LIBRARY ieee;
---------------------------------------------
ENTITY mux IS
PORT ( a, b, c, d, s0, s1: IN STD_LOGIC;
y: OUT STD_LOGIC);
KtV0
END mux;
--------------------------------------------- ------ With WHEN/ELSE -------------------------
ARCHITECTURE pure_logic OF mux IS outp <= "000" WHEN (inp='0' OR reset='1') ELSE
BEGIN "001" WHEN ctl='1' ELSE
y <= (a AND NOT s1 AND NOT s0) OR "010";
(b AND NOT s1 AND s0) OR ---- With WITH/SELECT/WHEN --------------------
(c AND s1 AND NOT s0) OR WITH control SELECT
(d AND s1 AND s0); output <= "000" WHEN reset,
END pure_logic; "111" WHEN set,
K fcS_xbZ Y UNAFFECTED WHEN OTHERS;
ns
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50 100 150 200 250 300 350 400 450 500
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DY HC5: 3N854 854 DY HC5: 3N854 854
------- S V YL=:C:AH:-------- WITH sel SELECT

y <= a WHEN "00",
LIBRARY ieee;
b WHEN "01",
c WHEN "10",
-------------------------------------------
d WHEN OTHERS;
ENTITY mux IS
END mux2;
PORT ( a, b, c, d: IN STD_LOGIC;
sel: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
EjM 2 V òWP QcR
y: OUT STD_LOGIC);
END mux;
-------------------------------------------
ARCHITECTURE mux1 OF mux IS
BEGIN
y <= a WHEN sel="00" ELSE 8i
VP*5. Bù U( àVOPb
b WHEN sel="01" ELSE
Mõ UZT ã_ )f
dõYf
Zm[U
Zaãgd
Sagf
bgf3[bgf Z[WS3&hnf
d ZmYU
Sa Z[
c WHEN sel="10" ELSE
ena = 1.
d;
LIBRARY ieee;
END mux1;
-------------------------------------------
----------------------------------------------
--- S V YL>
I=H:A:8IL=:C-----
ENTITY tri_state IS
LIBRARY ieee;
PORT ( ena: IN STD_LOGIC;
input: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-------------------------------------------
output: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
ENTITY mux IS
END tri_state;
PORT ( a, b, c, d: IN STD_LOGIC;
----------------------------------------------
ARCHITECTURE tri_state OF tri_state IS
y: OUT STD_LOGIC);
BEGIN
END mux;
output <= input WHEN (ena='0') ELSE
-------------------------------------------
(OTHERS => 'Z');
ARCHITECTURE mux2 OF mux IS
END tri_state;
BEGIN
----------------------------------------------
DY HC5: 3N854 854 DY HC5: 3N854 854
K fcgú_xbZ Y "001" WHEN x="00000010" ELSE

"010" WHEN x="00000100" ELSE
50 100 150 200 250 300 350 400 450 500 ns
"011" WHEN x="00001000" ELSE
ena "100" WHEN x="00010000" ELSE
input 01 00 01 00 "101" WHEN x="00100000" ELSE
output 01 00 ZZ 01 ZZ "110" WHEN x="01000000" ELSE

"111" WHEN x="10000000" ELSE
8i
VP*6. Kí âUlXPòVOK
PW hL *( "ZZZ";
END encoder1;
EjM 5WLMN
---------------------------------------------
---- S uG 10 0 4 ------
LIBRARY ieee;
---------------------------------------------
ENTITY encoder IS
PORT ( x: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
y: OUT STD_LOGIC_VECTOR (2 DOWNTO 0));
8i
VP*7. BùUePWbK
PW hL *)
END encoder;
M fT :C8D9:G U
v ãghna_ ãgdSh [_ 3 aY2 (n). Tõ
[_ ff
Z[ã[_ U
ZU v ---------------------------------------------
m fTt
fãghnaT Y HS
gãoknUZ íYfd
uZ_xbZ Ye V YL=:Cf ZW
aU úZS
[ ARCHITECTURE encoder2 OF encoder IS
Um
UZV YL=:C :AH:hnL>I= H:A:8I L=:C. BEGIN
WITH x SELECT
---- s V YL=:C:AH:-------------
y <= "000" WHEN "00000001",
LIBRARY ieee; "001" WHEN "00000010",
USE ieee.std_logic_1164.all; "010" WHEN "00000100",
--------------------------------------------- "011" WHEN "00001000",
ENTITY encoder IS "100" WHEN "00010000",
PORT ( x: IN STD_LOGIC_VECTOR (7 DOWNTO 0); "101" WHEN "00100000",
y: OUT STD_LOGIC_VECTOR (2 DOWNTO 0)); "110" WHEN "01000000",
END encoder; "111" WHEN "10000000",
--------------------------------------------- "ZZZ" WHEN OTHERS;
ARCHITECTURE encoder1 OF encoder IS END encoder2;
BEGIN
---------------------------------------------
y <= "000" WHEN x="00000001" ELSE
DY HC5: 3N854 854 DY HC5: 3N854 854
K fcgú_xbZ Y0
100 200 300 400 500 600 700 800 900 1000 ns
x 00 01 02 03 04 05 06 07 08 09 0A 0B
y Z 0 1 Z 2 Z 3 Z
8i
VP*8. Kí âUlXPòVOK
PW hL *)
EjM 1D
8i
VP*10. Hoà ùVOK
PVPKIK
bKXPãV 1 C
Bp Yg f
Z UZ[ _xbZ Y0
----------------------------------------------
LIBRARY ieee;
8i
VP*9. ALU
MõUZ6AJ fZ UZ[ U
mUbZq
bf am aY[ Uhnfam ZUã[h [ZS[ãghnaShnT USE ieee.std_logic_unsigned.all;
8ZzYã Uã[g Z[ T[*Tt t sel(3:0). Tuêf
ZgUhnaY[
mfdUSeW_n Z[e f
ZU ----------------------------------------------
hi fZS
afm
Un ah [V [g7úYV [ão k_xfúU
mUf
ZSafm
UUS6AJ ENTITY ALU IS
PORT (a, b: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
cin: IN STD_LOGIC;
y: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END ALU;
----------------------------------------------
ARCHITECTURE dataflow OF ALU IS
SIGNAL arith, logic: STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
----- Arithmetic unit: ------
WITH sel(2 DOWNTO 0) SELECT
DY HC5: 3N854 854 DY HC5: 3N854 854
arith <= a WHEN "000", 5.4. GENERATE.

a+1 WHEN "001", <:C:G6I: n_ f Z[ Ze aYeaY Zm
UCvfíYã í Yh[ Z[ Zf
g f
a-1 WHEN "010", LOOP trong vi UU
ZabZq
bUm
Uãaõ Zã Uf
Z UZ[ b õ[_ fe naãv
b WHEN "011", M gV YUS vn;DG <:C:G6I:
b+1 WHEN "100",
label: FOR identifier IN range GENERATE
b-1 WHEN "101",
(concurrent assignments)
a+b WHEN "110",
END GENERATE;
a+b+cin WHEN OTHERS;
----- Logic unit: -----------
M fU
mUZ ZmUe V Y<:C:G6I: nV Y>
; ãok_ Zã :AH: ZxYã Ue
d YB fU m
UZZSkã Ue V YnV Y>;fd
aY;DG<:C:G6I:
WITH sel(2 DOWNTO 0) SELECT
logic <= NOT a WHEN "000", M ge V Y Z e
Sg
NOT b WHEN "001",
label1: FOR identifier IN range GENERATE
a AND b WHEN "010",
...
a OR b WHEN "011",
label2: IF condition GENERATE
a NAND b WHEN "100",
a NOR b WHEN "101", (concurrent assignments)
a XOR b WHEN "110", END GENERATE;
NOT (a XOR b) WHEN OTHERS; ...

-------- Mux: --------------- END GENERATE;
WITH sel(3) SELECT u(
y <= arith WHEN '0', SIGNAL x: BIT_VECTOR (7 DOWNTO 0);
logic WHEN OTHERS;
SIGNAL y: BIT_VECTOR (15 DOWNTO 0);
END dataflow;
SIGNAL z: BIT_VECTOR (7 DOWNTO 0);
----------------------------------------------
...
K fcgú_xbZ Y
G1: FOR i IN x'RANGE GENERATE
50 100 150 200 250 300 350 400 450 500 ns
z(i) <= x(i) AND y(i+8);
a 00 01 02 03 04 05
END GENERATE;
arith 00 02 02 04 03 05
b 00 01 02 03 04 05 M fã[gU bZú
[UZz nY[[Zõ USVpkbZú
[ã U ZS[Tm
a nefSf
[U g ZxYe
cin ZxYZ b IdaYhtV e
SgUZa[
UW ZxYã U ZS
[Tm
a nefS
f[U s ZxYZ b 0
logic FF FE FD FC 04 05
0 1 0 1 2 3
NotOK: FOR i IN 0 TO choice GENERATE
sel
y 00 02 02 04 03 05 (concurrent statements)
END GENERATE;
8i
VP*11. Kí âUlXPòVOKI hL **
DY HC5: 3N854 854 DY HC5: 3N854 854
Z[gd
yZí h Z[ Z<:C:G6I:U
ZzYf
Se jq
fhtV e
Sg0 row(i) <= row(i-1)(6 DOWNTO 0) & '0';
END GENERATE;
EjM EN
L QR
ON
outp <= row(sel);
KtV eSg_[ZZaõU
Zah[Ue V Y<:C:G6I: Id
aYãvãghnae ã UVU
Zã[
END shifter;
m fTt
fhnfõ
afZnZãgdSKtV ãghnaUv*ã YhnY[ mf
dTS ãg n fZu
K fcgú_xbZ Y0
ãgdSe ã U_xfúZ eSg0
50 100 150 200 250 300 350 400 450 500 ns
row(0): 0 0 0 0 1 1 1 1
inp 0 1 0 0
row(1): 0 0 0 1 1 1 1 0 outp 00 01 02 03 04
sel 0 1 2 3 4
row(2): 0 0 1 1 1 1 0 0
row(3): 0 1 1 1 1 0 0 0 8i
VP*12. Kí âUlXPòVOKI hL *+
row(4): 1 1 1 1 0 0 0 0 CZ ZuZf Sf Zù
k g[bgf3 && f ZuãgdS agf
bgf3&&&&&& Z[e
W 3&
agf
bgf3 &&&&& & Z[e
W3 agfbgf3&&&& && geW3(
8Z íYf
duZ_xbZ Y
5.5. BLOCK.
------------------------------------------------
8vZS
[ aõ
[Z[ Z7AD8 0H[
_bWhn<gS
dVW
V
LIBRARY ieee;
USE ieee.std_logic_1164.all; 5.5.1. Simple BLOCK
------------------------------------------------ Kh [ Z7AD8 U
ZabZq
bãf_ f Z[ Ze aYeaYhna_ fãaõ ã[gãvY[
zb
UZaU
mUãaõ ZV ãUhnV cgú Zí 8ù
gfdzUUSU
ZzY Z e S
g0
ENTITY shifter IS
PORT ( inp: IN STD_LOGIC_VECTOR (3 DOWNTO 0); label: BLOCK
sel: IN INTEGER RANGE 0 TO 4; [declarative part]
outp: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); BEGIN
END shifter; (concurrent statements)
------------------------------------------------ END BLOCK label;
ARCHITECTURE shifter OF shifter IS 8m

U Z[ Z7AD8 ãf[
sf[b ZS
g Z htV e
Sg0
SUBTYPE vector IS STD_LOGIC_VECTOR (7 DOWNTO 0);
------------------------
TYPE matrix IS ARRAY (4 DOWNTO 0) OF vector;
ARCHITECTURE example ...
SIGNAL row: matrix;
BEGIN
BEGIN
...
row(0) <= "0000" & inp;
block1: BLOCK
G1: FOR i IN 1 TO 4 GENERATE
BEGIN
DY HC5: 3N854 854 DY HC5: 3N854 854
... 5.1.2. Guarded BLOCK

END BLOCK block1 M f<gSdVWV7AD8 n_ f Z[7AD8 ãUT[fCvU Z S_ fã[g [ hn
... BLOCK ch ã Uf
Z UZ[ Z[ã[g [ ãvU
vY[
mfd nIGJ:
block2: BLOCK gf
Cù d
zU Z e
Sg0
BEGIN
label: BLOCK (guard expression)
...
[declarative part]
END BLOCK block2;
BEGIN
...
(concurrent guarded and unguarded statements)
END example;
END BLOCK label;
------------------------
f
u_Z[gd
yZí h Z[7AD8 f
Sã[jq
fhtV e
Sg0
KtV0
KtV 08Zfe V Y<gS d
VWV7AD8 Id aYhtV n
k Z[ n
aU 3 f
Zu
b1: BLOCK
kh [ã íUZaõ
fã Y Z[ãv Z[ Ze ã íUf
Z UZ[
SIGNAL a: STD_
-------------------------------
BEGIN
LIBRARY ieee;
a <= input_sig
END BLOCK b1;
-------------------------------
M fãaõ 7AD8 U
vfZ ã Uãff
daY_ fãaõ 7AD8 Zm
U Z[ãvU
zbZm
bZ
ENTITY latch IS
sau:
PORT (d, clk: IN STD_LOGIC;
label1: BLOCK
q: OUT STD_LOGIC);
[declarative part of top block]
END latch;
BEGIN
-------------------------------
[concurrent statements of top block]
ARCHITECTURE latch OF latch IS
label2: BLOCK
BEGIN
[declarative part nested block]
b1: BLOCK (clk='1')
BEGIN
BEGIN
(concurrent statements of nested block)
q <= GUARDED d;
END BLOCK label2;
END BLOCK b1;
[more concurrent statements of top block]
END latch;
END BLOCK label1;
-------------------------------
DY HC5: 3N854 854 DY HC5: 3N854 854
K fquú_xbZ Y 100 200 300 400 500 600 700 800 900 1000 ns
clk
100 200 300 400 500 600 700 800 900 1000 ns
d
clk q
rst
d
q 8i
VP*14. K fcgú_xbZ YUShtV +.
8i
VP* 1 3 . K í âUlXPòVOKPW hL *,
KtV (09;; V Y<gSdVWV7AD8 Ida YhtV nkUZz Yf

Se jW_ jqfZaõfã Y
c S_ fId[YWdIZaõfã Yã YT e V í Y
-------------------------------
LIBRARY ieee;
-------------------------------
ENTITY dff IS
PORT ( d, clk, rst: IN STD_LOGIC;
q: OUT STD_LOGIC);
END dff;
-------------------------------
ARCHITECTURE dff OF dff IS
BEGIN
b1: BLOCK (clk'EVENT AND clk='1')
BEGIN
q <= GUARDED '0' WHEN rst='1' ELSE d;
END BLOCK b1;
END dff;
------------------------------
K kM Ng FV IBoG (
DY HC6: 3N9: 49t DY HC6: 3N9: 49t
3Q àWP) <tCDú=CÃ
10 20 30 40 50 60 70 80 90 ns
rst
6.1. PROCESS clk
EGD8:HH nbZ f g f US_pK=9A Cvã U_xfúT[UmUUog Z>; L6>I q
CASE, ho UADDE hnT[VSZe mUZ Zõ

k Yaõ[fd L6> I ã Ue V Y
8i
VP+ 2. Kí âUlXPòVO
PROCESS phú[ã UUn
[ãffdaY_pU
ZtZhnã Uf
Z UfZ[ _ [f
Z[ã[_ _ ff
t
hi gf
daYVSZe mU
Z Zõ
kfZS
kã[ library IEEE;
3nXPbX/ use IEEE.STD_LOGIC_1164.all;

entity DFF is
[label:] PROCESS (sensitivity list)
Port(d,clk,rst:in std_logic;
[VARIABLE name type [range] [:= initial_value;]]
q:out std_logic);
BEGIN
end DFF;
(sequential code)
architecture Behaviour of DFF is
END PROCESS [label];
begin
K6G>67A:H nf
gêUZ C ge V Y UZzYbZú
[ã U ZS[Tm
afd
aYbZ ZS
[
process(clk,rst)
Tm
aUSEGD8:HH fd Uf Zam7:<>
C <[mf
d Z[f
õa ZxYfZ fZbUZùk
ã ãõ
[V[ Z[_xbZ Y begin
-- wait on rst,clk;
CZp UèYã Ue V YfgêU
Z _ UãtUZ n oYU
Sa Zú YãUã UUS_p
CZp U
vfZ nTù
f êf n
a Yaõ[f
d f Zam if (rst='1') then
q <= '0';
elsif (clk'Event and clk='1') then
E(B q <= d;
end if;
end process;
end Behaviour;
6.2. BR
PW U _dE RKU
N
K=9A Uv ZS[UmUZ ã Z YZé S UmU Y[
mfd Zx Y féZ0T Y H><C6A Za U T Y
K6G>67A: H> <C6A Uv f Z ã U ZS[Tma f da Y E68 6<: :CI> IN Za U
8i
VP+1. DFF v h
VP MMS
PlVO VO ù ARCHITECTURE (trong ph ZS[TmaU S v f da Y Z[K6G>67A: UvfZ ã U
_xfúTs fda Y_ fbZ U S_pf g f f da YEGD8:HH 9aãv fda Y Z[Y[
mfd
c SbZ fd UUvf Z nf an U U bZ eSg gx nU UT
<[ mf
d U SK6G>
67A: UvfZ Zx YTSaY[ ã Z YZé
S Yan[EGD8:HH_ fUmUZ
tr Uf[b gU f Zu vbZú[ã U Ym f
Zn ZH>
<C6A Id
a YUmUZj ZmU Ub
DY HC6: 3N9: 49t DY HC6: 3N9: 49t
nh fK6G> 67A: nfUfZufSU

vfZf tZfam fUfZuY[
mfd_ [US vfd
aYVwY 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 ns
l Zf [bf ZWa [gãv ZxYbZú [nf d YZbUSH> <C6A Z[ã Ue V Y clk

fdaYEGD8:HH Y[ mfd_ [US vUZ f Ycgmfã UTúaf
an ã U
vfZ V Yã U digit 0 1 2 3 4 5 6 7 8 9
sau khi k ff
ZzUcgmf
duZUZõ
kZ[ fõ
[USEGD8:HH
8iVP+ 4 . K í âUlXPòVO
EZq bf am Ym U
ZaH>
<C6A n 23 e
[Y23+ f
daY Z[h[K6G>
67A: n 0
3 hS
d
:= 5). LIBRARY ieee;
6.3. IF.
>; L6>I 86H: hnADDE nUmUUog Zã[h[_pf g f 9aãv UZzYU
ZUv
th ã Ue V YTs fdag PROCESS, FUNCTION ho UEGD8:9JG: ENTITY counter IS
PORT (clk : IN STD_LOGIC;
V Ygks fUU
v_ f fcgúbZ ã Z f YZbe f[ gZamU
ùgf
dzUhnf
dmZã[
digit : OUT INTEGER RANGE 0 TO 9);
eo
ghn
abZ U Y
END counter;
3nXPbX/
IF conditions THEN assignments; ARCHITECTURE counter OF counter IS

ELSIF conditions THEN assignments; BEGIN
...
count: PROCESS(clk)
ELSE assignments;
VARIABLE temp : INTEGER RANGE 0 TO 10;
END IF;
BEGIN
E
IF (clk'EVENT AND clk='1') THEN
IF (x<y) THEN temp:="11111111";
temp := temp + 1;
ELSIF (x=y AND w='0') THEN temp:="11110000";
IF (temp=10) THEN temp := 0;
ELSE temp:=(OTHERS =>'0');
END IF;
E(B
END IF;
digit <= temp;
END PROCESS count;
END counter;
8i
VP+3. Bù í
UKP ôPXX
PdV
DY HC6: 3N9: 49t DY HC6: 3N9: 49t
E(C internal <= (OTHERS => '0');

ELSIF (clk'EVENT AND clk='1') THEN
internal <= d & internal(internal'LEFT DOWNTO
1);
END IF;
END PROCESS;
q <= internal(0);
END behavior;
8i
VP+5. Thanh ghi d K
P)
6.4. WAIT.
50 100 150 200 250 300 350 400 450 500 550 600 650 ns
EZq
bfam L6>Iãx[ Z[fíYf Z > ; Igk Z[
s Z[gZí _ fã ZVõYU
vfZ
clk
V Yã U=í S Z[> ; 86H: ZaUADDEã Ue V Y EGD8:HH ZxYfZ
rst
Uv_ fVSZe
mUZ Zõ
k Z[L6> Iã Ue V Y
d
internal U ? ? ? C 6 3 1 0 / OHWO
q
WAIT UNTIL signal_condition;
8iVP+ 6 . K í âUlXPòVO WAIT ON signal1 [, signal2, ... ];
WAIT FOR time;
LIBRARY ieee;
8og ZL6> IJCI>AZ UZ _ ff
t Z[gVaãvf
ZtU
ZZbU Za_pã YT Zí n
_p ZxYã YT Z[EGD8:HH ZxYU vVSZemUZ Zõ
kfdaYfd YZb n k
[nU
WAIT phú o
g Zãgf[sfdaYEGD8:HH EGD8:HHã UfZ Uhi _ [f
Z[
ENTITY shiftreg IS ã[_ Z[Ybã[g [
GENERIC (n: INTEGER := 4); -- # of stages
E
PORT (d, clk, rst: IN STD_LOGIC;
q: OUT STD_LOGIC); Thanh ghi 8 bit v [f
t Z[gd
WeW
fã YT
END shiftreg; PROCESS -- no sensitivity list

BEGIN
ARCHITECTURE behavior OF shiftreg IS WAIT UNTIL (clk'EVENT AND clk='1');
SIGNAL internal: STD_LOGIC_VECTOR (n-1 DOWNTO 0); IF (rst='1') THEN
BEGIN output <= "00000000";

PROCESS (clk, rst)
output <= input;
BEGIN
END IF;
IF (rst='1') THEN
END PROCESS;
DY HC6: 3N9: 49t DY HC6: 3N9: 49t
L6>IDC fdaYU mUZj Zm

U Z Z[gf t Z[g EGD8:HHã UãfY[ U Za process
ã Z[Tù f êft Z[g naf
ZSkã[EGD8:HHe f[bfUf Z UZ[ Tù
f ê Z[ na begin
m ff
ZSkã[fdaYd e
fZaUU jgùfZ[
wait on rst,clk;
E Thanh ghi 8 bit v [f

t hi gd
WeW
fZxYã YT if (rst='1') then
q <= '0';
PROCESS
elsif (clk'Event and clk='1') then
BEGIN
q <= d;
WAIT ON clk, rst;
end if;
IF (rst='1') THEN
end process;
output <= "00000000";
end DFF;
output <= input; E ( C B ã__ fU
Z ef
ZbbZo & 9 0
END IF; 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 ns
END PROCESS; clk
WAIT FOR ch V Yã _xb

Z YKtV0L6>
I;DG+e
1 digit 0 1 2 3 4 5 6 7 8 9
E ( B DFF v [f
tZ[gd
WeW
fZxYã YT 8iVP+ 8 . K í âUl XPòVO
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 ns
LIBRARY ieee;
rst
d
clk
ENTITY counter IS
q
PORT (clk : IN STD_LOGIC;
8iVP+ 7 . K í âUlXPòVO digit : OUT INTEGER RANGE 0 TO 9);
library IEEE; END counter;
use IEEE.STD_LOGIC_1164.all;
entity DFF is ARCHITECTURE counter OF counter IS
Port(d,clk,rst:in std_logic; BEGIN
q:out std_logic); PROCESS -- no sensitivity list
end DFF; VARIABLE temp : INTEGER RANGE 0 TO 10;
architecture DFF of DFF is BEGIN
begin WAIT UNTIL (clk'EVENT AND clk='1');

temp := temp + 1;
DY HC6: 3N9: 49t DY HC6: 3N9: 49t
IF (temp=10) THEN WHEN value1 | value2 |... -- value1 or value2 or ...

temp := 0;
BâVO+1. AW bVPO IE85= c31A5
END IF;
digit <= temp; WHEN CASE
END PROCESS;
Ki g Z Yf
Z[ Tu f
END counter;
Ch Yan[EGD8:HH Ch f
daYEGD8:HH
S V Y FUNCTION, ho U FUNCTION, ho U
6.5. CASE. PROCEDURE PROCEDURE
86H: n ZVgk Zù
fUZa_pf
g f ã[r
_h[>
; ADDE hnL6>
I
fU
Tù úe Zam hbZú
[ 8vh[
8v
3nXPbX/ ã U [_f d
S WITH/SELECT/WHEN
S bZq bYm Zù
f
CASE identifier IS 1 fê
Bù
cho m [ [_f
dS
WHEN value => assignments;
T Zam ZxY t
UZ
UNAFFECTED NULL
WHEN value => assignments; f
hoõ
...
E
END CASE;
VyI 419
E
WITH sel SELECT
CASE control IS
x <= a WHEN "000",
WHEN "00" => x<=a; y<=b;
b WHEN "001",
WHEN "01" => x<=b; y<=c;
c WHEN "010",
WHEN OTHERS => x<="0000"; y<="ZZZZ";
UNAFFECTED WHEN OTHERS;
END CASE;
VyI/ 1
L Z86H: f g f fíYf h[L=:C fZb Iù fUúe Zam h ãgbZú [ã U
ki _f d
Shuhkf ZamDI=:GHdùfZ gtUZI ZamcgS fd Y Zm
UnCJAA Tú CASE sel IS
sao c SJC6;;:8I:9 s ã Ue V Y Z[ ZxYU vZaõ
fã Y n o thay th Kt WHEN "000" => x<=a;
d 0L=:CDI=:GH34CJAA1Igk Z[ s 86H:UZabZqb Z[gbZqbYm h[_ [
WHEN "001" => x<=b;
ã[g [ [_f d
SfdaY Z[L=:CUZU ZabZq
b_ f
WHEN "010" => x<=c;
Gi Y Z f
daYf
d YZbUSL=:C ão
k L=:ChSgW U
vfZU
v)VõY0 WHEN OTHERS => NULL;
WHEN value -- single value END CASE;
WHEN value1 to value2 -- range, for enumerated data types E B V sZBJM*

-1
-- only V 9
6/
DY HC6: 3N9: 49t DY HC6: 3N9: 49t
IF (sel="00") THEN x<=a; WHEN '1' => q<='0';

ELSIF (sel="01") THEN x<=b; WHEN '0' =>
ELSIF (sel="10") THEN x<=c; IF (clk'EVENT AND clk='1') THEN
ELSE x<=d; q <= d;
VyI/ 1 END IF;

WHEN OTHERS => NULL;-- Unnecessary,rst is of
CASE sel IS
-- type BIT
WHEN "00" => x<=a;
END CASE;
WHEN "01" => x<=b;
END PROCESS;
WHEN "10" => x<=c;
END dff3;
WHEN OTHERS => x<=d;
E ( C B ã_ZS
[UZ ef
ZbbZo & 99 &ãgd
Sn(A:9 f
ZSZ
END CASE;
E ( B DFF v [f
tZ[gd
WeW
f ZxYã YT
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 ns
rst
clk
8iVP + 9 . K í â Ul XPòVO
LIBRARY ieee; -- Unnecessary declaration, -- because

8i
VP+10. Bù í
U K
P ôPXXPdV
USE ieee.std_logic_1164.all; -- BIT was used instead of
ns
-- STD_LOGIC 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300
reset
ENTITY dff IS
clk
PORT (d, clk, rst: IN BIT; temp1 0 1 0 1 0 1 2 3 4 0 1
q: OUT BIT); temp2 0
digit1 7E 30 7E 30 7E 30 6D 79 33 7E 30
END dff;
digit2 7E
ARCHITECTURE dff3 OF dff IS

BEGIN 8i
VP+11. Kí âUlXPòVO
PROCESS (clk, rst)
LIBRARY ieee;
BEGIN
CASE rst IS
ENTITY counter IS
DY HC6: 3N9: 49t DY HC6: 3N9: 49t
PORT (clk, reset : IN STD_LOGIC; WHEN 6 => digit1 <= "1011111"; --5F
digit1, digit2 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)); WHEN 7 => digit1 <= "1110000"; --70
END counter; WHEN 8 => digit1 <= "1111111"; --7F
ARCHITECTURE counter OF counter IS WHEN 9 => digit1 <= "1111011"; --7B
BEGIN WHEN OTHERS => NULL;
PROCESS(clk, reset) END CASE;
VARIABLE temp1: INTEGER RANGE 0 TO 10; CASE temp2 IS
VARIABLE temp2: INTEGER RANGE 0 TO 10; WHEN 0 => digit2 <= "1111110"; --7E
BEGIN WHEN 1 => digit2 <= "0110000"; --30
---------------------- counter: ---------------------- WHEN 2 => digit2 <= "1101101"; --6D
IF (reset='1') THEN WHEN 3 => digit2 <= "1111001"; --79
temp1 := 0; WHEN 4 => digit2 <= "0110011"; --33
temp2 := 0; WHEN 5 => digit2 <= "1011011"; --5B
ELSIF (clk'EVENT AND clk='1') THEN WHEN 6 => digit2 <= "1011111"; --5F
temp1 := temp1 + 1; WHEN 7 => digit2 <= "1110000"; --70
IF (temp1=10) THEN WHEN 8 => digit2 <= "1111111"; --7F
temp1 := 0; WHEN 9 => digit2 <= "1111011"; --7B
temp2 := temp2 + 1; WHEN OTHERS => NULL;
IF (temp2=10) THEN END CASE;
temp2 := 0; END PROCESS;
END IF; END counter;
END IF;
6.6. LOOP.
END IF;
LOOP h gtU
Z Z[_ fbZ US_pbZú [ã UfZ Z[ Z[g <[ Y Z >
;
---- BCD to SSD conversion: -------- L6>I hn86H: ADDE nVgk Zù
fã[h[_pfg f huhk vUèYUvf
Z ã Ue
CASE temp1 IS d YTs fdaYEGD8:HH ;JC8I>DC ZS
kEGD8:9JG:
WHEN 0 => digit1 <= "1111110"; --7E
3lWQR L
cLQ M WP >>
WHEN 1 => digit1 <= "0110000"; --30
3nXPbX/ FOR/LOOP: kVOT
êX KT
êXT
àUù ôT
ãVK
ô VP
WHEN 2 => digit1 <= "1101101"; --6D
WHEN 3 => digit1 <= "1111001"; --79 [label:] FOR identifier IN range LOOP
WHEN 4 => digit1 <= "0110011"; --33 (sequential statements)
WHEN 5 => digit1 <= "1011011"; --5B END LOOP [label];
DY HC6: 3N9: 49t DY HC6: 3N9: 49t
WHILE/LOOP: kVOT
êX KT
êXK
PW í
VSP ì S VS
PlVOPâWUeV END LOOP;
[label:] WHILE condition LOOP

DhL/V =5FB
(sequential statements) FOR i IN 0 TO 15 LOOP

END LOOP [label]; NEXT WHEN i=skip; -- jumps to next iteration
EXIT: s LVO S
í PnK kVOT
êX (...)
END LOOP;
[label:] EXIT [label] [WHEN condition];
E ((B B LWPL
lWQ KRTQnWPM
NEXT: s LVO ò IK
bK K kVOT
êX
[label:] NEXT [loop_label] [WHEN condition];
E VyI2: 7::
x(i) <= enable AND w(i+2);
y(0, i) <= w(i);
END LOOP;
M fãUã[_ cgS fd YUS;DGADDE fíYf f õah[<:C:G6I: nY[[Zõ 8i

VP+12. BùK
ùVOK
jVP S
PlVOL
t [f
Z[gbZú
[nf éZ 9aãv _ f ZS
[Tm
a [g ;DG[>
C &ID UZa[
UWADDE h[
ns
UZa[
UWn_ ffZS
_e ãghn a ZxYf éZ ZxY fZ bf Ycgm
fã U 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300
cin
V E V E895 a 92 40 04 31 86 C6 32
b 24 81 09 63 0D 8D 65
s B7 C2 0D 94 93 53 97
WHILE (i < 10) LOOP cout
WAIT UNTIL clk'EVENT AND clk='1';

8iVP + 1 3 . K í â UlXPòVO
(other statements)
END LOOP; M [bZ n t U Seíã n_ fT U Y ã k ã
E V 5F9
B sj = aj XOR bj XOR cj
FOR i IN data'RANGE LOOP OV 0 MV 2> NV A MV 2> OV A NV 2> OV
CASE data(i) IS /WDH 4oVO 7MVM K KbKD53B

WHEN '0' => count:=count+1;
----- S o lu tio n 1 : G e n e ric , w ith V E C T O R S ----- ---
WHEN OTHERS => EXIT;
LIBRARY ieee;
END CASE;
DY HC6: 3N9: 49t DY HC6: 3N9: 49t
ENTITY adder IS END adder;

GENERIC (length : INTEGER := 8); ARCHITECTURE adder OF adder IS
PORT ( a, b: IN STD_LOGIC_VECTOR (length-1 DOWNTO 0); BEGIN
cin: IN STD_LOGIC; PROCESS (a, b, c0)
s: OUT STD_LOGIC_VECTOR (length-1 DOWNTO 0); VARIABLE temp : INTEGER RANGE 0 TO 511;
cout: OUT STD_LOGIC); BEGIN
END adder; IF (c0='1') THEN temp:=1;
ARCHITECTURE adder OF adder IS ELSE temp:=0;
BEGIN END IF;
PROCESS (a, b, cin) temp := a + b + temp;
VARIABLE carry : STD_LOGIC_VECTOR (length DOWNTO 0); IF (temp > 255) THEN
BEGIN c8 <= '1';
carry(0) := cin; temp := temp; ---256
FOR i IN 0 TO length-1 LOOP ELSE c8 <= '0';
s(i) <= a(i) XOR b(i) XOR carry(i); END IF;
carry(i+1) := (a(i) AND b(i)) OR (a(i) AND s <= temp;
carry(i)) OR (b(i) AND carry(i)); END PROCESS;
END LOOP; END adder;
cout <= carry(length); E ((C
END PROCESS;
B VUZãí Y[
ú0VU ZhW
Ufadãghn
a t U
ZfZ U. & ZaU h bZtSfd
m[ Z[
END adder; dUZT[
fAH7bZú[ã Uã[ & C geZ[
Xf3&f
Zuagf
b3[b1 ge
Z[X
f3 f
Zuagf
b&
/W
DH 4oVOVWV-generic v K
bK9
=B575 3 & hnagf
b[3[b[
-1) v [ i 7.
---- Solution 2: non-generic, with INTEGERS ----

LIBRARY ieee;
ENTITY adder IS
PORT ( a, b: IN INTEGER RANGE 0 TO 255;
c0: IN STD_LOGIC;
s: OUT INTEGER RANGE 0 TO 255;
c8: OUT STD_LOGIC);
DY HC6: 3N9: 49t DY HC6: 3N9: 49t
ARCHITECTURE RTL OF barrel IS

BEGIN
PROCESS (inp, shift)
BEGIN
IF (shift=0) THEN
outp <= inp;
ELSE
outp(0) <= '0';
FOR i IN 1 TO inp'HIGH LOOP
outp(i) <= inp(i-1);
END LOOP;
END IF;
END PROCESS;
END RTL;
E ((
D B V wxL V _N
L WQ YQeW K ù Ki
W cR
50 100 150 200 250 300 350 400 450 500 550 600 ns
8i
VP+14. BùLK
P VOâV
data 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D
Kí âUlXPòVO/ 8 7 6 5 4
zeros
20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 ns
8i
inp 00 14 28 3C 50 64 78
shift 0 1 LIBRARY ieee;

outp 00 14 28 3C A0 C8 F0 USE ieee.std_logic_1164.all;
8i
ENTITY LeadingZeros IS
LIBRARY ieee; PORT ( data: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
USE ieee.std_logic_1164.all; zeros: OUT INTEGER RANGE 0 TO 8);
ENTITY barrel IS END LeadingZeros;
GENERIC (n: INTEGER := 8); ARCHITECTURE behavior OF LeadingZeros IS
PORT ( inp: IN STD_LOGIC_VECTOR (n-1 DOWNTO 0); BEGIN
shift: IN INTEGER RANGE 0 TO 1; PROCESS (data)
outp: OUT STD_LOGIC_VECTOR (n-1 DOWNTO 0)); VARIABLE count: INTEGER RANGE 0 TO 8;
END barrel;
DY HC6: 3N9: 49t DY HC6: 3N9: 49t
BEGIN U :K:CI Uvf

Zf d
uZT[
s VUZY[
úe _ fY[
mfd [_ f
dS_ Uã Z SVU 3
count := 0; ho Uf
ZxYTm
a_ ffZxYã[b UaU afaU
Ske f
STW
FOR i IN data'RANGE LOOP
PROCESS (clk)
CASE data(i) IS
BEGIN
WHEN '0' => count := count + 1;
IF (clk'EVENT) THEN
WHEN OTHERS => EXIT;
counter := counter + 1;
END CASE;
END IF;
END LOOP;
...
zeros <= count;
END PROCESS;
END PROCESS;
Z[EGD8:HHã UU Zõ
k_ [fZ[ã[_ U fZS
kã[T ã_ U vfZ ã Uf YZS[
END behavior;
f
ds _ [U
Zg êUaU Igk Z[s ã[g n
k ZxYjú kdSC gf
duZT[s VU
ZY[
úfZ[f
m fY[
mfd_ Uã Z _ f_õ
UZ [e ã Uf YZb T [huU Z _ fe US U e
6.7. Bad Clocking.
ã UcgS fo_1 g ZxYU vY[mfd_ Uã ZY[úfZ[ff
Zu_ ffZxYã[b [hn
Id
uZT[s VU
Z v[UZgY ZxYU v Zú Yf YZbU m
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f
t Z[gY[ Y ZS
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e V íYU Yf õ[e o _ Id aYf d YZb n kf
duZT[s VU
ZUvfZfZxYTm a N g_ ff
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Z Zõk Z Y ZxYjgù fZi f
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fê
m ff
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YSVaW e afZaVhSgWS
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E B ã_ bZú
[ã Uf Yf
õ[_ [e U
Zgk f
[bUSf
t Z[gUaU e V íY
c Ye V í Y PROCESS (clk)
PROCESS (clk) BEGIN
BEGIN counter := counter + 1;
IF (clk'EVENT AND clk='1') THEN ...
counter <= counter + 1; END PROCESS;
ELSIF(clk'EVENT AND clk='0') THEN =S[ãaõ _pEGD8:HHeSge ã Uf YZbU ZtZjm

UT [Tù
f êf
duZT[
s VU
Zna
Igk Z[
s U Zz d Ye V Y_ fft Z[g Zm
U ZSgfd
aY_ [EGD8:HH
counter <= counter + 1;
END IF; PROCESS (clk)
... BEGIN
END PROCESS; IF (clk'EVENT AND clk='1') THEN
IduZT[
s VU
ZU vfZUwf ZxYTm
ad Yf
t Z[gU
agf
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d Y x <= d;
h bnkh[UT[s VUZe Tfd
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END PROCESS;
Zt
SUõZcgS f
d Y Zm
UnfZgUftZ:K:CIbZú[Uv[
s quan t [ã[g [ [_
f
dS KtV0 Z > ; U :K:CI SV U 3 n ãzY Z Y U Z e V Y>; PROCESS (clk)
DY HC6: 3N9: 49t DY HC6: 3N9: 49t
BEGIN USE ieee.std_logic_1164.all;

y <= d; ENTITY ram IS
GENERIC ( bits: INTEGER := 8;-- # of bits per word
END IF;
words: INTEGER := 16);--#of words in the mem
END PROCESS;
PORT ( wr_ena, clk: IN STD_LOGIC;
E ()B G6B GSVa_6U
WeeBW
_ad
k VgY Y ,f Z j.T[
f
addr: IN INTEGER RANGE 0 TO words-1;
data_in: IN STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
data_out: OUT STD_LOGIC_VECTOR (bits-1 DOWNTO 0));
END ram;
ARCHITECTURE ram OF ram IS

TYPE vector_array IS ARRAY (0 TO words-1) OF
STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
8i
VP+17. RAM SIGNAL memory: vector_array;
50 100 150 200 250 300 350 400 450 500 550 600 ns
BEGIN
wr_ena PROCESS (clk, wr_ena)

clk BEGIN
addr 3 4 5 2 3 4 5 IF (wr_ena='1') THEN
data_in 32 33 34 35 36 37 38
data_out UU 32 UU 33 UU 34 UU 32 33 34
memory(addr) <= data_in;
8iVP+ 1 8 . K í âUlXPòVO END IF;

END IF;
M õUZ Uv TgeV [g hna VSfSQ[ TgeV [g dS VSfSQagf Tgeã S UZ SVVd U Y END PROCESS;
ft Z[g UaU U hnUmUUZo UZabZqbYZ[ idQW S Z[idQW Sã UjmU Z fõ[ data_out <= memory(addr);
e V í Y f[b fZWa U S U hWUfadUv _ ffõ[VSfSQ[ bZú[ã U g fd fõ[ã S UZ
END ram;
ã U_x fúT [SVVd g dS VSfSQagf T Y UmUZ j ZmU bZú[Z[ fZ [s f UV
li gUZ T [SVVd 6.8. S M WPVf ùW QR T L
cLVòL
Q QY
Bpfg fU vfZ ã Ue V Yã fZ UZ[ U
mUZ VpkZSkf Z bId
aYfd YZb
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h Vp
kU mUfZSZYZ[nU f Z[fhuhke ã Uegkd
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s
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aYf d YZbZ f Zb=í S g_pã UV YU Za
v [ã g hna U SfZS Z YZ[ huh k fõ[e V í Y f[b fZWa U SU V e YZ[ãrY[mfd
h f Z bfZuTúYfZfãkã s ã U_xff údyd
nYf d
aY_p
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LIBRARY ieee; f
Zaú_p U
mUf
[sgU
Zg f
dsU
vUm
Ugfã Ujq
f0
DY HC6: 3N9: 49t DY HC6: 3N9: 49t
Lu ú_ Tú
afùfUúft Z[gãghnae V Yf daYEGD8:HHjgùfZ[ f
daY sel: IN INTEGER RANGE 0 TO 3;
dSZe m
UZ Zõ
kUS vId uZT[s VUZã SdSUúZTma g_ ff
t Z[gãghnaãp x, y: OUT STD_LOGIC);
UZa ZxYã UU Z Sf
daYVSZe mU
Z Zõ k hne
Sgãvj gft Z[gãpã U
END example;
ch S
Lu ú_ Tú
afùfUúf ZbUmUft Z[gãghn aãgd Sã UTSaY_ fd
aY_p ARCHITECTURE example OF example IS
búYfZfãkã US_õ UZUvfZ ã UU Z S ã[g n kãzYh[Uú_pfg f hn
BEGIN
_pã YfZ[ 8m UãUfú ZxYãkã USU mUft Z[gãgdSUvf
Z Yo
kU Zah[U
PROCESS (a, b, c, d, sel)
t YZbã egkdSUmUUZfã Y[ U
mUY[mfd[ f d U
BEGIN
E ( B Thi T Vò
LQ QY R
IF (sel=0) THEN
x<=a;
y<='0';
ELSIF (sel=1) THEN
x<=b;
y<='1';
ELSIF (sel=2) THEN
8i
VP6. 19. Mà
KP õP X I cK
bKâ
VOP
x<=c;
ns
50 100 150 200 250 300 350 400 450 500 550 600 ELSE
a
x<=d;
b
c END IF;
d END PROCESS;
sel 0 3 1
END example;
x
y HSg Z[T[
s VU
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8i
VP+ 2 0 . K í âUlXPòVO ã[fd UeW3& fcgúk3 & f
daY Z[k3 Z[e
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x h o õfã Y Z _ fT V s Z k3 & Z[eW 3 && Za U3 geW 3 & Igk y = (sel(0) AND sel(1)) OR (sel(0) AND y) OR (sel(1) AND y)
Z[ s UmUã Uf
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9aãv _ fU
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UU Y6C9DG ãpã Uf Z UZ[ fd
úh TúYf
Zf(
LIBRARY ieee; f
dmZe V YUZf s e V Y M nY[mfd ZxYjmUã Z Z k23 M 1
USE ieee.std_logic_1164.all; [ã UU
phú Z SV [U
mUVwY((hn(*Vaãvk3eW&
ENTITY example IS
PORT (a, b, c, d: IN STD_LOGIC;
DY HC7: 80 4 2 K 70 2 DY HC7: 80 4 2 K 70 2
ZS
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vfZ ã Uf
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CONSTANT.
bZS
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mUY[
mfdV [g ZxYféZ a-static):
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(PROCESS), s Ub Zf v ZxYfUf Zu<[mfd_ [US ZxY s ã Uã[ã
e
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ã UãUf d U Z[ ffZzUEGD8:HH ;JC8I>
DC ZaUEGD8:9JG:fíY Y
8DCHI6CIhn<:C:G>
8U vf
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Z ã Ue V YTs f
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m fbZ US_pfg f fd
aYEGD8:HH ;JC8I>
DC ZaUEGD8:9JG:
Zt
SUõZ ZmUúZZ Yã fcgú Z[ Z[gbZq
bYm ã Ufõ
aU YH><C6A
7.1. CONSTANT. IduZT[s VUZUvf ZfZxYTmahnf
Zamfe f YZb ZaUUvfZ egkd
S_õUZe
S[
CONSTANT ph Uh U
Zah[Uf
Z[f bU
mUY[
mfd_ Uã Z (b YUmUZUZ jq
fbZqbYm Ug[U Y 9aãv h[Ujqf bUm
UY[
mfd Z[fõa s
ã Uf Z UZ[ h [K6G>67A:
3nXPbX/ CONSTANT name : type := value;
E ) B B ã_e e f
daY_ fh
WUf
ad Zb
Zo
DhL/
20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 ns
CONSTANT set_bit : BIT := '1';
din 00 01 02 03 04 05 06
CONSTANT datamemory : memory := (('0','0','0','0'),
temp 0 1 2 3 4 5 6
('0','0','0','1'),
ones 0 1 2 3 4 5
('0','0','1','1'));
8DCHI6CIU vfZ ã U ZS[Tmafd

aYE68 6<: :CI> INhn6G8=>I:8IJG: 8i
VP, I :í âUlXPòVO
Z[ ZS[Tm
af d
aYYv[bS USYW v nf an UUYv[U vf
Z ã Ue V Yb [ Z[g
LIBRARY ieee;
th UfZ Wf [f
k Z[ ZS [Tmafd
aYf Z Uf
Z e SgEDGI v nfan UUh[fùfU
úUm
U
ki f dzU S
dUZ[
fWU
fgdWfZW
af Z Uf
Z Z[ ZS [Tmaf
daY [ fdzU f
daYbZ ZS [ USE ieee.std_logic_1164.all;
TmaUS v vU Zf an UUh[_pUS [ f dzUãv ENTITY count_ones IS

PORT ( din: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
7.2. SIGNAL. ones: OUT INTEGER RANGE 0 TO 8);
SIGNAL ph Uh Y[
ú[cgkfU
mUY[mf
dhnahnd
SUS_õU
ZU èY Z nY[SU m
Uãí END count_ones;
v Ts f
daYUS v It Z[gT[gV[ U Zah[U f [_õU
ZUmUVok IZ Z[ n
tùfU
úUm
UEDGIUS:CI> IN nUm
UftZ[g_ Uã Z
ARCHITECTURE not_ok OF count_ones IS
3nXPbX/ SIGNAL name : type [range] [:= initial_value]; SIGNAL temp: INTEGER RANGE 0 TO 8;
E BEGIN
PROCESS (din)
SIGNAL control: BIT := '0';
BEGIN
SIGNAL count: INTEGER RANGE 0 TO 100; temp <= 0;
SIGNAL y: STD_LOGIC_VECTOR (7 DOWNTO 0); FOR i IN 0 TO 7 LOOP
DY HC7: 80 4 2 K 70 2 DY HC7: 80 4 2 K 70 2
IF (din(i)='1') THEN LIBRARY ieee;

temp <= temp + 1; USE ieee.std_logic_1164.all;
END IF; ENTITY count_ones IS
PORT ( din: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
END LOOP;
ones: OUT INTEGER RANGE 0 TO 8);
ones <= temp;
END count_ones;
END PROCESS;
ARCHITECTURE ok OF count_ones IS
END not_ok;
BEGIN
PROCESS (din)
7.3. VARIABLE
VARIABLE temp: INTEGER RANGE 0 TO 8;
CY Uõ[h[8DCHI6CIhnH>
<C6A K6G>67A:UZ T[gV[ fZxYf
[ UUT
BEGIN
CvUZUvf
Z ã Ue V YTs fdaYEGD8:HH ;JC8I>DC ZS
kEGD8:9JG:
temp := 0;
fd
aY_pfg f K[UUb ZfY[ mfdUS v nfUf ZuhuhkY[mfd_ [U
vfZ
ã U bfUe V Yfd
aYVwY Zf [bf
ZWaUS_p
IF (din(i)='1') THEN
3nXPbX/ VARIABLE name : type [range] [:= init_value]; temp := temp + 1;
END IF;
DhL/ END LOOP;
VARIABLE control: BIT := '0'; ones <= temp;
END PROCESS;
VARIABLE count: INTEGER RANGE 0 TO 100;
END ok;
VARIABLE y: STD_LOGIC_VECTOR (7 DOWNTO 0) := "10001000";
BâVO, AW bVPO IA9
7=1 cD1 9
12 5
Khi VARIABLE ch U
vfZ ã Ue V Yf
daY_pf g f ZS[Tm
aUS vU ZUvf
Z
ã Uf Z UZ[ fd
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Z f YZbã UU Zã Ujqf Z[_xbZ Y
WQW WP Bi gV[ e
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mU_õ
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Khi c b ZfT[ nfUf
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ZtZjm
Uhn ZxYU
vfZxY FUNCTION, hay PROCEDURE
Tm
an ah Z[gbZq
bYm Vaf
duZT[
s VUZ fíY Y
ns
Hoò WP C b Zf ZxYfUf Zufd
aY_p C b ZffUf ZuY[
mfd_ [U
vfZ
50 100 150 200 250 300 350 400 450 500 550 600
tu f Y[mfd_ [U ZUvfZ V Y ã Ue V Yf d
aYVwY Zf [b
zU f f ZzU EGD8:HH theo c S_p
din 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D
FUNCTION, hay PROCEDURE)
ones 0 1 2 1 2 3 1 2 3 2 3
S M WP Trong PACKAGE, ENTITY, hay Ch fd
aY _p f g f f d
aY
ARCHITECTURE. Trong PROCESS, FUNCTION, hay
8i
VP,(I :í âUlXPòVO fU
ENTITY, tù úUmUEDGI nU mU PROCEDURE
SIGNAL m Uã Z
DY HC7: 80 4 2 K 70 2 DY HC7: 80 4 2 K 70 2
E ) C B M WTi
WQ -1 WHEN 2 => y<=c;
WHEN 3 => y<=d;
END CASE;
END PROCESS;
END not_ok;
/W
DH S E MG 5 .71 d MG
-- Solution 2: using a VARIABLE (ok) ----

8i
VP,( 2ùLVS
gVP)
-1 LIBRARY ieee;
/W
DH S E MG 5
39 7 H MGd MG
-- Solution 1: using a SIGNAL (not ok) -- ENTITY mux IS

LIBRARY ieee;
y: OUT STD_LOGIC);
END mux;
ENTITY mux IS
ARCHITECTURE ok OF mux IS
BEGIN
y: OUT STD_LOGIC);
PROCESS (a, b, c, d, s0, s1)
END mux;
VARIABLE sel : INTEGER RANGE 0 TO 3;
BEGIN
ARCHITECTURE not_ok OF mux IS
sel := 0;
SIGNAL sel : INTEGER RANGE 0 TO 3;
IF (s0='1') THEN sel := sel + 1;
BEGIN
END IF;
PROCESS (a, b, c, d, s0, s1)
IF (s1='1') THEN sel := sel + 2;
BEGIN
END IF;
sel <= 0;
CASE sel IS
IF (s0='1') THEN sel <= sel + 1;
WHEN 0 => y<=a;
END IF;
WHEN 1 => y<=b;
IF (s1='1') THEN sel <= sel + 2;
WHEN 2 => y<=c;
END IF;
WHEN 3 => y<=d;
CASE sel IS
END CASE;
WHEN 0 => y<=a;
END PROCESS;
WHEN 1 => y<=b;
END ok;
DY HC7: 80 4 2 K 70 2 DY HC7: 80 4 2 K 70 2
M f [f Z Yjgks Z[e V YH> <C6A n ZxY Z vU vf Zk sgUg_ f /W

DH 6H MGd MG
khoúYfZ[Y[
S ã Ub Zf9aãv bZqbYm e
W23e W VwY , fdaYUmUZ
---- Solution 1: not OK ---------------
k fcgúU Yf
Zs_ Tù
f Y[ mf
dh Sã Ufõa[ fd UUZaeW h [bZq
bYm e
W23
& VwY + UvfZ ZxYU vfZ[Y[
Sãf õ
a [g n kãzYh [h[e W 23e
W ( LIBRARY ieee;
VwY . o k ZxY nhù ã Z[e V YK6G> 67A: bZq

bYm US v gx fU USE ieee.std_logic_1164.all;
fZu
Zt
SUõZfZ (UvfZ n_ fhù ã f
daYUmUZ nZí _ fbZqbf am ãSYã c tõ
a ENTITY dff IS
UZaU YH> <C6A eW VwY + , hn . UvfZ ZxYã UU Zùb Z Iv_ õ [ PORT ( d, clk: IN STD_LOGIC;
ch _ fbZq
bYm h [H><C6Aã UbZqbTs fd
aYEGD8:HH huhkbZ _ _ U Z q: BUFFER STD_LOGIC;
jqfbZqbYm Ug[U Y eW 23e
W ( ZaUãí Y[ú nã Sd SfZxYTm a [hn f
qbar: OUT STD_LOGIC);
fZzUh[UT[
s VUZ o kUèY ZxYTSaY[ nhù ã Z[e V YK6G> 67A:
END dff;
20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 ns
s0
s1 ARCHITECTURE not_ok OF dff IS

a
BEGIN
b
c PROCESS (clk)
d
BEGIN
y
50 100 150 200 250 300 350 400 450 500 550 600 ns
q <= d;
s0
s1
qbar <= NOT q;
a END IF;
b
END PROCESS;
c
d END not_ok;
y
/W
DH e MG
8i
VP,( :í âUlXPòVOKbKP c ---- Solution 2: OK -------------------
LIBRARY ieee;
E ) D D F F v R _d K
ENTITY dff IS
PORT ( d, clk: IN STD_LOGIC;
q: BUFFER STD_LOGIC;
8i
VP,(K 466 qbar: OUT STD_LOGIC);
DY HC7: 80 4 2 K 70 2 DY HC7: 80 4 2 K 70 2
END dff; E)E B L

QR ùW L
QR ù
W L
ULTK R)
ARCHITECTURE ok OF dff IS
BEGIN
PROCESS (clk)
BEGIN
q <= d; 8i
VP,(
L 2ùK
PIãV
END IF; Th UZ [ ZS
[ãgd
S_ fnV Sf
ds H>
<C6A U
agf h
n_ fV Sf
ds K6G>
67A:
END PROCESS; (count2).
qbar <= NOT q; ns
20 40 60 80 100 120 140 160 180 200 220 240 260 280 300
END ok; clk
IdaYU mUZ UmUbZq

bYm c23V VwY , hncTS
d23CDIc VwY ãgã YT count1 0 1 2 3 4 5 6 7
huhkU mUY[
mfd_ [USU ZzYe UZ ã UV Y zU ff ZzUEGD8:HH ok nhù count2 0 1 2 3 4
ã ã[h[cTS dT[huY[mfd_ [USc ZxYh S_ [f õ

ad S9aãv cTS
de Z Y[ m out1
tr ãúaY[mf
dUèUSc <[ mfdãzYUScTS de T f
d _ fUZg êã YZ YokU Za out2
mõ U
Zn _h[U ZxYU ZtZjmU
8i
VP,(L :í âUlXPòVO
Id
aYU mUZ( f
ZSkcTS
d23CDIc VwY)& Ts Yan
[EGD8:HH VaãvbZq
bftZ
LIBRARY ieee;
Z _ fT[gf
Z Uã YfZ[ãzY
50 100 150 200 250 300 350 400 450 500 550 600 ns
d
ENTITY freq_divider IS
clk
q PORT ( clk : IN STD_LOGIC;
qbar out1, out2 : BUFFER STD_LOGIC);

END freq_divider;
50 100 150 200 250 300 350 400 450 500 550 600 ns
clk ARCHITECTURE example OF freq_divider IS

q SIGNAL count1 : INTEGER RANGE 0 TO 7;
qbar
BEGIN
8iVP,(K :í âUlXPòVOKbKP c PROCESS (clk)

VARIABLE count2 : INTEGER RANGE 0 TO 7;
BEGIN
DY HC7: 80 4 2 K 70 2 DY HC7: 80 4 2 K 70 2
count1 <= count1 + 1; IF (clk'EVENT AND clk='1') THEN

count2 := count2 + 1; output1 <= temp; -- output1 stored
IF (count1 = 7 ) THEN output2 <= a; -- output2 stored
out1 <= NOT out1; END IF;
count1 <= 0; END PROCESS;
END IF; Trong PROCESS ti bf
ZWaU
Z agf
bgf ã U gf
d agf
bgf
(e f
õaU
mUZe V YU
mU
IF (count2 = 7 ) THEN c YaY[ U
out2 <= NOT out2; PROCESS (clk)

count2 := 0; BEGIN
END IF; IF (clk'EVENT AND clk='1') THEN
END IF; output1 <= temp; -- output1 stored
END PROCESS; END IF;
END example; output2 <= a; -- output2 not stored
END PROCESS;
7.4. S Q WQPQR
S X[
b-Xabã UegkdSf _pT[f d
uZT[s VUZB UãtU
Z n ZxYUZ Z[gf
[bU Trong PROCESS, bi Z _ She M lZ TUôa d ó X a
ks
gUge f ZSZYZ[f[thi g_nU
w ãú
_Tú aãaõ _pf
Z UZ[ _õU
Z_aY_g PROCESS (clk)
VARIABLE temp: BIT;
M fH> <C6Ae[Z_ fX[b-flop bù
fU Z[ na_ fbZq
bYm ã Uf
õad
Sfõ
[e UZgk
ti bUSft Z[g Zm
U Z[_ fbZq bYm ã YT júkdSEZq
bYm ã YT UvfZU Z BEGIN
xú kd
STs fdaYEGD8:HH ;JC8I> DC ZS
kEGD8:9JG: fZ Y n_ f ZS[Tm
a IF (clk'EVENT AND clk='1') THEN
ki g >;e[
YS :K:CI ZaU L6> IJCI>A temp <= a;
M fK6G>67A:e ZxYe [ZU m

UX[
b-flop c f Z[f gY[ mf
dUS v ZxYTS aY[ END IF;
r [EGD8:HH ZaU;JC8I> DC ZaUEGD8:9JG: Igk Z[ s g_ fY[
mfd x <= temp; -- temp causes x to be stored
ã UYm cho m fT[ fõ[e U
Zgk f[bUSf t Z[g Zm UhnY[mfdf
Z_ UZtã U END PROCESS;
ã Sf[_ fft Z[g d[EGD8:HH f
ZuU mUX[b-flop s ã Ue
gkdSB fK6G>67A:
E ) B DFF v [chncTS
d
Uwe [Z_ ffZSZYZ[ Z[vã Ue V Yf d U_ fY[ mf
dh Sã UYm U
Za v
8m UZ U v(bZq
bYm H>
<C6Aã YT VwY ,- huhk(X[
b-flop s ã Ue
[Z
E
8m UZ(U v_ ffd
aYUmUbZq
bYm nã YT h[Uf YZbe gx e gkdSUZ_ f
Trong PGD8:HH agf
bgf hnagf
bgf
(ãge ã U gf d e
gkd
SUm
UX[
b-flop), b [hu flip-flop
cúZS[ãgã UYm f õ
[e UZgk f[bUSf
t Z[g Zm
UU
PROCESS (clk)
BEGIN
DY HC7: 80 4 2 K 70 2 DY HC7: 80 4 2 K 70 2
ARCHITECTURE two_dff OF dff IS

BEGIN
PROCESS (clk)
BEGIN
q <= d; -- generates a register
qbar <= NOT d; -- generates a register
8i
VP,)I 3bKUàK
P a I UeKIK
bKP c END IF;
END PROCESS;
50 100 150 200 250 300 350 400 450 500 550 600 ns
END two_dff;
d
clk /W
DH Sinh mx
R022
q
---- Solution 2: One DFF ----------------
qbar
LIBRARY ieee;
50 100 150 200 250 300 350 400 450 500 550 600 ns USE ieee.std_logic_1164.all;
d
clk
ENTITY dff IS
q
qbar
8iVP,)I :í âUlXPòVOKbKP c qbar: OUT STD_LOGIC);
/WDH S in h h a i D F F END dff;
---- Solution 1: Two DFFs ---------------

ARCHITECTURE one_dff OF dff IS
LIBRARY ieee;
BEGIN
PROCESS (clk)
BEGIN
ENTITY dff IS
q <= d; -- generates a register
END IF;
qbar: OUT STD_LOGIC);
END PROCESS;
END dff;
qbar <= NOT q; -- uses logic gate (no register)
DY HC7: 80 4 2 K 70 2 DY HC7: 80 4 2 K 70 2
END one_dff; END PROCESS;
E)C B V -7 END counter;
/W
DH
M fbZqbYm H>
<C6Aã YT jú kd
S VwY )-14). Ch e V YU
mUH><C6A 8Zz
Z[ ZxYU vft Z[gbZ ã Ue V Y U agfU ã U ZS [Tm
a Z [g
7J;;:G VwY * T [hu vã UYm _ fY[
mfdhnU èYã UãU e V Y [f õ
[
VwY * B fH><C6A Y[ Y Z _ fK6G>67A: U vfZUèYã Uf Y Z[e
d YfdaY_pf g f
8i
VP,) 2ù í
U q7 ------ Solution 2: With SIGNALS only -------
ENTITY counter IS
3bK
P/
PORT ( clk, rst: IN BIT;
M fbZqbYm K6G>
67A:ã YT ã Uf S
adS VwY *-15). M fK6G>67A:UvfZ
count: BUFFER INTEGER RANGE 0 TO 7);
e
[ZU mUfZSZYZ[T[hubZq
bYm US v VwY + fõ[e U Zgk f[bUSf t Z[g
END counter;
Zm
UU VwY * hnY[ mfdUS v ZxYd[EGD8:HH VwY
------ Solution 1: With a VARIABLE --------

ARCHITECTURE counter OF counter IS
ENTITY counter IS
BEGIN
PORT ( clk, rst: IN BIT;
PROCESS (clk, rst)
count: OUT INTEGER RANGE 0 TO 7);
BEGIN
END counter;
IF (rst='1') THEN
count <= 0;
ARCHITECTURE counter OF counter IS
BEGIN
count <= count + 1;
PROCESS (clk, rst)
END IF;
VARIABLE temp: INTEGER RANGE 0 TO 7;
END PROCESS;
BEGIN
END counter;
IF (rst='1') THEN
T (U
mUZf
ds )X[
b-Xabã Ue
gkd
Sã Y[ )T[
fftZ[gãgd
SUagf
temp:=0;
50 100 150 200 250 300 350 400 450 500 550 600 ns
rst
temp := temp+1;
clk
END IF;
count 0 1 2 3 4 5 6 7
count <= temp;
DY HC7: 80 4 2 K 70 2 DY HC7: 80 4 2 K 70 2
50 100 150 200 250 300 350 400 450 500 550 600 ns c := b;
rst
b := a;
clk
a := din;
count 0 1 2 3 4 5 6 7
END IF;
8i
VP,) :íquâUlXPòVOK
bKP c END PROCESS;
E ) D Thanh ghi d L
Q LY END shift;
/W
DH
8mUT[ ã UfZSkfZ T[U mUH>

<C6A VwY. hnU mUbZqbYm ã Ufõad
Sfd
aY
th f f
dUf[b f V[-VagfVwY )- , Z[U
mUbZqbYm ft Z[gf
õ[e U
Zgk f[b
ftZ[g Zm
Ue[ZU mUf
ZSZYZ[_õ UZãzYe ã UegkdS
-------- Solution 2: -----------------

8i
VP,)K BPIVPOP LK
P)KX ENTITY shift IS
/WD
H PORT ( din, clk: IN BIT;
dout: OUT BIT);
)K6G> 67A:ã Ue V Y ST hnUVwY & Igk Z[ sUmUT[ ã Ue V Y
END shift;
fd UUmUY[mf
dã UYm UZaU
ZzY ãúa Y Uf Z f Tfãgh[VagfVwY ) hn
k ff
ZzUh [V[ VwY , fcgúnU m
UX[b-flop s ã Ue
gkd
S gfdUmUY[
mfdf
bZqbUZõ
k[ f d UUSEGD8:HH ARCHITECTURE shift OF shift IS
-------- Solution 1: ----------------- SIGNAL a, b, c: BIT;

BEGIN
ENTITY shift IS
PROCESS (clk)
PORT ( din, clk: IN BIT;
dout: OUT BIT); BEGIN
END shift;
a <= din;
b <= a;
ARCHITECTURE shift OF shift IS
BEGIN c <= b;
dout <= c;
PROCESS (clk)
END IF;
VARIABLE a, b, c: BIT;
END PROCESS;
BEGIN
END shift;
dout <= c; 3bK
P(/
DY HC7: 80 4 2 K 70 2 DY HC7: 80 4 2 K 70 2
8m UT[ Y[ Y Zau c SU
mUZ ãpT UZ[_ Z Yf daYfZ ffdUf[b f V[-dout, 50 100 150 200 250 300 350 400 450 500 550 600 ns
VwY )- , Igk Z[ s _ fbZq

bYm U Za_ fT[ nfUf Zuhn Z[UmUT[ ãSY din
ã Ue V Yf daYf Z ff dUf[b eSg Z[UmUY[
mfdh Sã UYm UZaU ZzY VwY
clk
13- +fZnZ VwY fíYã íYh[U 03V[ <[mf
dUSUd[EGD8:HHf daYVwY
dout
ti bfZW
a VwY , Z[_ fbZq bYm ftZ[g Vagf23U júkdSf
õ[e UZgk f[bUS
U 9aãv _ ff ZSZYZ[e ã Ue gkdSf UmUZ) s ZxYf õa fcgú_õ UZU
ZtZ
50 100 150 200 250 300 350 400 450 500 550 600 ns
jm U
din
-------- Solution 3: ----------------- clk
dout
ENTITY shift IS
PORT ( din, clk: IN BIT; 50 100 150 200 250 300 350 400 450 500 550 600 ns
dout: OUT BIT); din
END shift; clk
dout
ARCHITECTURE shift OF shift IS

8iVP,)K :í âUlXPòVOKbKP c(
BEGIN
E ) E T h a n h g h i d LQ KR
PROCESS (clk)
VARIABLE a, b, c: BIT;
BEGIN
a := din;
b := a;
c := b;
8iVP,)L Bh a n h g h i d KP)
dout <= c;
END IF; B it r a ( q ) p h ú[ n*e U aU V í YeSgT[fhna V GWeWfbZú[ n Zx Yã YT jam
tùfUúUmUã gdSX[b- f lo p v & Z[ tUZZaõf
END PROCESS;
END shift; /WDH
gd
SVagfnT e UaU V íYe
Sgãghn
aV[ U
mUZ Z YU
Z _ fe
S V Y _ fH><C6A ã e[ Z UmU X[b- Xab 8mU fZS Z YZ[ã U fõa T [hu_ fbZqb
V íYeS
gãghna U
mUZ(
Ym UZa_ fft Z[ gã UfõadSfõ[e UZgk f[ bU Sft Z[ g ZmU Vw Y - 1 8 ) .
---- Solution 1: With an internal SIGNAL ---
LIBRARY ieee;
DY HC7: 80 4 2 K 70 2 DY HC7: 80 4 2 K 70 2
END shiftreg;
ENTITY shiftreg IS
PORT ( d, clk, rst: IN STD_LOGIC; ARCHITECTURE behavior OF shiftreg IS
q: OUT STD_LOGIC); BEGIN
END shiftreg; PROCESS (clk, rst)
VARIABLE internal: STD_LOGIC_VECTOR (3 DOWNTO
ARCHITECTURE behavior OF shiftreg IS 0);
SIGNAL internal: STD_LOGIC_VECTOR (3 DOWNTO 0); BEGIN
BEGIN IF (rst='1') THEN
PROCESS (clk, rst) internal := (OTHERS => '0');
BEGIN ELSIF (clk'EVENT AND clk='1') THEN
IF (rst='1') THEN internal := d & internal(3 DOWNTO 1);
internal <= (OTHERS => '0'); END IF;
ELSIF (clk'EVENT AND clk='1') THEN q <= internal(0);
internal <= d & internal(3 DOWNTO 1); END PROCESS;
END IF; END behavior;
END PROCESS; 8m U
c mõZã Uf YZ bnY[ Y ZS
g *X[
b-Xabã Ue
gkd
S
q <= internal(0); 50 100 150 200 250 300 350 400 450 500 550 600 ns
END behavior; clk
rst
3bK
P:
d
internal 0 1 0 1 0 1 0 1 0
S V Y_ fK6G> 67A: EZq
bYm f
õ[e U
Zgk f[bUSft Z[g Zm
Uã UfõadS
q
cho m fT[ VwY - . Z Y Z[Y[ mfdUS vd[EGD8:HH vã UU Zgk
ã _ fbad ff
daYVwY(& vU èYe
gkdSUm
UfZSZYZ[ 8i
VP,)L :í âUlXPòVO
-- Solution 2: With an internal VARIABLE ---
LIBRARY ieee;
ENTITY shiftreg IS
PORT ( d, clk, rst: IN STD_LOGIC;
q: OUT STD_LOGIC);
DY HC8: 3P 97c4 9 P0 DY HC8: 3P 97c4 9 P0
3Q àWP < GCAó=7C8 9 CZ hk_ f_m

kxf
x_m
fZ gZõ n_ fT ,f
ZxYe 2M N H e
0, , 4 f
daYã
v0
X - T bZ bU
mUf
tZ[gh
naUSx
fx_S
f0
M ffZ[f _õUZe Uvf
Z ã UU Z[
Sn _ (f
ZnZbZ 0T j V [ghnT ã[g
khi B [cgS Z Y[ST ã[g Z[ hnT j V li gf
daY_õ
UZã UT[gV[ X = { x1 f jn(t)}
Bm kf dõYfZm[Z gZõ ;HB n_ fU xY YZ _xZuZZamãUT[fUZaU

mU_õU
Z T bU
mUf
tZ[gd
SUSx
fx_S
f0
logic tu f BxZuZãvU vfZdùfã UY[
zbã fd
aYfZ[f US Z Y aõ [Z
th Y n aãv ãUT[fnU mUfZS
afm
UUS Z YZ fZ YãvfZW
a Zgx VõYfg f Y = {y1 f k
m(t)}
Zan f an jmUã Z
T bZbU
mUf
dõYf
Zm[USx
fx_S
f0
8.1. Gi RQR S = {s1 f e

s(t)}
=uZeS
gãokUZdSe
íã Z[US_ f_m kfd
õYfZm[_ fbZSId aYZuZ n
kbZ
mõU
ZVpkU
Z SUm
U_õUZVp
k X[
b-flops), ph USaUZ S_õUZ aY[
UfZb =n
_ (s, x) Z
n_U
Zgk f
dõYf
Zm[USx
fx_S
f
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Hn n_ãgd
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mbftZfa
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m[h
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fBaad
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h
nx f
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Quay lõ uZh fds _õ UZU fhi f ã UU Z[Sn_Z S[ã
a õ K[UUZ[Sã
aõ
Zf Z n ke Y[
zbUZzYf SfZ[f ffZ í 8ZzYf Se f
Z[f (b Z fZW
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kU ZzYfSe f
Z UZ[
fdaYEGD8:HHh nbZ _õ UZf ZbU Z
zYf SUvfZf Z UZ[ fZW
aU ù
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tu f Z aU fZ bU úUùgfd
zU f g f Igk Z [
s _pf g fU vfZm bV YUZa
cú(a õ[aY[
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8i
VP A Uba àVOPb
IZ xYf Z YU mUftZ[gUa Uh nUmUf
tZ [gd W
eWffd
aYbZ _õ UZV
pke j
gùfZ[
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UZfZbU
v(ãghn
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S0
trong PROCESS (tr Z [ftZ [gdW
eWfnã YT Z aU Z xYã Ue V Y ft Z[g
ghnaf
Z Zùf0nãghnafd
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õ[US_m
k L6> Iã Ue V Yf ZS kUZa Z> ; Z [f
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[
ghnaf
Z (0nãghnaf Ts Yan [ hi f õ [e ã UfZ[f bU Z
af d
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m[f[bfZWaV aã ve U
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Ph _õ
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DY HC9: THI 91 9 O3 P 3c DY HC8: 3P 97c4 9 P0
CZ f ZnZ_ fcgkfU Z bZ íYbZm b;HB fZuf

ZtU
ZZ bh[U m
UZ fZ Y_nf
ZSa Vi Uf Z[f U ZabZ _õ UZVpkn kfZuãí Y[ú hu v n_ fUZg UíTú hne
fm
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v [U mUZ f
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úU m
UfdõYfZm[US;HB 7 [hk g
Khi soõ f
Zúa_pK=9A f ZuUm
UfdõYfZm[nke ã U ZS [Tmafd
aYbZ ãgUS m gã U_pZamf ZWaU
mUZ_ Uã Z _pZam Z bZo f ZuUZzYfSe U aY2n
ph 6G8=> I:8IJG:V [VõY [gV [g [f sã Uã Z YZé ST[ Y [e Flip-flop, v [ ne fdõYfZm[
d Y
RtOH MLn
Thit DHRH O
8.2. Thi T QN TR QR T QN VnQk
WQV bV N
ZuZ fZubZ _õUZf Zb n ãkã huhk_pUS ve ZxYU f Z[ff
ZWa
8vhn [bZ íYbZmbUvf
Z ã UZuZfZnZã fZ[f _ f;HB 8ZzYf Se _xfú
tu f I f ZùfU
ZzYfS s e V Y_pã YfZ[HaYfd
aYh tV _ gV [ãok
chi ti f_ fhtV _ g_n_õU
ZZan f
an ã UUùgfd
zUhnV VnYm
bV YId aYãv
UZzYfSe e V Y_pfg f h[Uog Z86H:ãvYhS
[fd
wfd
gYfo_
ph _õ U
ZVp kUS_mkfd
õYf Zm
[e f
mUZT[fh[bZ _õUZf Z bUS v ZuZh
fd
s PROCESS (input, pr_state)
BEGIN
TùfU
úUm
Ufd
õYf
Zm[US_m
k gx gx ã U ZS
[Tm
adyd
nYT YU
mUZe V Y [g
CASE pr_state IS
d [g[fs
WHEN state0 =>
RtOH MLn
Thit DHE
XV IF (input = ...) THEN
IdsZ uZfd
s U mUX[
b-flop n _ b Z _õ U
ZVpk8mUãgh n
af Ts Y a n[USbZ output <= <value>;
nknU m
UftZ [gUaUh ndWeWf8mUf
tZ [g nkã U [h[U m
U;[b-flop. M fãg nx_state <= state1;
hnaZ mUTsf daY nf dõYf Z
m[f[bfZ
Wa gd SVgk Zù
fUSbZ n knf dSYfZm
[ ELSE ...
hi f õ[ j okV YU Z ab Z _õ UZVpkn kfSU e V YU ùgf
dzUEGD8:HH END IF;
Trong cùgf
dzUUSEGD8:HHU Z
zYf SUafZ e e V YUmUU
og Zf g f Z WHEN state1 =>
l Z> ; L6>I 86H: ADDE IF (input = ...) THEN
Z
gx _ gf
Z[f USb
Z _õ
UZV
pke Z e
Sg0 output <= <value>;
nx_state <= state2;
PROCESS (reset, clock)
ELSE ...
BEGIN
1. L M ) 04 END IF;
Trang_thai_hien_tai <= Trang_thai_0 ;
1. EH D 4 G EH D ) 04 WHEN state2 =>
Trang_thai_hien_tai <= Trang_thai_tiep_theo;
END IF ; IF (input = ...) THEN
END PROCESS ; output <= <value>;
nx_state <= state2;
BpU Zd S ãok nd
ùfã
íY [
ú CvU
ZUZ S_ ff
tZ [gdWe
Wfã YT It Z
[gd W
eWf ELSE ...
nke j
mUã ZfdõYfZm[ Z[ãgUSZ th Y e
Sgãv n gfd ã YT f
dõYfZm[ END IF;
ti bf
ZWafõ[e V í Yã xYZ hnã Sd
SãgdSUSb Z _õ U
ZVpkfd
õYfZm
[Z[ ...
tõ[
END CASE;
END PROCESS;
aõ _p ão
kUèYd
ùfãí Y[
ú hn ve f
Z UZ[ (U
xYh[UU
ZtZ0 CASE pr_state IS
WHEN state0 =>
<m Y[mfdUZaãgdS
Thi f bfd
SYfZm
[f[bf
ZWa IF (input = ...) THEN
output <= <value>;
SLW
Mr VRP
nMGR
HWIcho kiu
SRHI
tRt
nx_state <= state1;
9 [ã
okn Z
gx _ gZ
anU
Z Zh [gf
Z[f 0 ELSE ...
LIBRARY ieee; END IF;
USE ieee.std_logic_1164.all; WHEN state1 =>
----------------------------------------------------- IF (input = ...) THEN
ENTITY <entity_name> IS output <= <value>;
PORT ( input: IN <data_type>; nx_state <= state2;
reset, clock: IN STD_LOGIC; ELSE ...
output: OUT <data_type>); END IF;
END <entity_name>; WHEN state2 =>
----------------------------------------------------- IF (input = ...) THEN
ARCHITECTURE <arch_name> OF <entity_name> IS output <= <value>;
TYPE state IS (state0, state1, state2, state3, ...); nx_state <= state3;
SIGNAL pr_state, nx_state: state; ELSE ...
BEGIN END IF;
---------- PhéZ ãOT Pie ------------------------ ...
PROCESS (reset, clock) END CASE;
BEGIN END PROCESS;
IF (reset='1') THEN END <arch_name>;
pr_state <= state0; EjM 2 V234

ELSIF (clock'EVENT AND clock='1') THEN
M fT ã_ n_ fhtV US_m kBaad
Wãgd SUZ bZ f
ZgUhn
a fcgúUSfd
õY
pr_state <= nx_state; f
Zm[Z[ f
õ[<[ Y Z _ f_õ U
ZfZSZYZ[hn_ f_õ UZVp
kãí Y[
ú f
Z[f
END IF; mõUZnkU ZzYf
SU vf
Z V YbZ íYbZm bfZxYfZ Y Z Z YbZ _õ UZ
mõUZfZ b Z Y ãokfSe V YbZ í YbZm
b;HB
END PROCESS;
---------PhéZ ãOT T ------------------------ Giúe f
SU fZ[f T ã_ _aVg & CZ hkUZzYf
Se U Uv_ f_S
kU v&
PROCESS (input, pr_state) f
dSYfZm[8m
UfdõYfZm
[ ão
kã UY[nl Wd
a aW [W ZuZf
dõYfZm
[US
_mkã UUZa Z e
Sg0
BEGIN
PROCESS (rst, clk)

BEGIN
IF (rst='1') THEN
pr_state <= zero;
pr_state <= nx_state;
END IF;
END PROCESS;
------------- Phan mach to hop: -----------------
8i
VP A àVO PbKI ù í
U234 PROCESS (pr_state)
BEGIN
BpK=9AU èYY[ Y Z Zgx _ gUSf Z[f _ g Id aYãv0 [gV [g [f
CASE pr_state IS
se jgùfZ[ VwY 12, thi f USph _õ UZVp ke f VwY ,ã VaY()
thi f USbZ _õ U
Zf Zb_õ UZf Zb e jgù
fZ[ f VwY(+ (/ 9aU v& WHEN zero =>
fdSYfZm
[s e YUS
UfZSZYZ[T Y nPaY210 ] = 4. count <= "0000";
nx_state <= one;
Bpf
Z[f e Z e
Sg0
WHEN one =>
-------------------------------------------------
count <= "0001";
LIBRARY ieee;
nx_state <= two;
WHEN two =>
-------------------------------------------------
count <= "0010";
ENTITY counterBCD IS
nx_state <= three;
PORT ( clk, rst: IN STD_LOGIC;
WHEN three =>
count: OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
count <= "0011";
END counterBCD;
nx_state <= four;
-------------------------------------------------
WHEN four =>
ARCHITECTURE state_machine OF counterBCD IS
count <= "0100";
TYPE state IS (zero, one, two, three, four,
nx_state <= five;
five, six, seven, eight, nine);
WHEN five =>
SIGNAL pr_state, nx_state: state;
count <= "0101";
BEGIN
nx_state <= six;
------------- Phan mach day: -----------------
WHEN six =>
count <= "0110";

nx_state <= seven;
WHEN seven =>
count <= "0111";
nx_state <= eight;
WHEN eight =>
count <= "1000";
8i
VP ) ba àVOPbKI hL
nx_state <= nine;
WHEN nine =>
Bpf
Z[f e Z e
Sg0
count <= "1001"; -------------------------------------------------

nx_state <= zero; LIBRARY ieee;
END CASE; USE ieee.std_logic_1164.all;

----------------------------------------------
END PROCESS;
ENTITY vd_FSM IS
END state_machine;
PORT ( a, b, d, clk, rst: IN BIT;
-------------------------------------------------
x: OUT BIT);
BxbZ Y fcgú
0
END vd_FSM;
----------------------------------------------
ARCHITECTURE state_machine OF vd_FSM IS
TYPE state IS (stateA, stateB);
SIGNAL pr_state, nx_state: state;
BEGIN
---------- Phan mach day: ----------------------
8i
VP (:í âUlXPòVOKI ù í
U234 PROCESS (rst, clk)
BEGIN
EjM <cb òWP QcRT QoLTR
IF (rst='1') THEN
=uZ* ne íã Z[US ;HB ãí Y[
ú = f Z YUv(fd
õYfZm
[0fd
õYfZm
[6 hn pr_state <= stateA;
trõYf
Zm[7 Bm
kbZú
[UZgk f
dõYf
Zm[ Z[ Z ã UV3 hnãgd S_aY_g n ELSIF (clk'EVENT AND clk='1') THEN
j3S Z[_mk fd
õYfZm
[6ZaUj3T Z[_m k f
dõYf
Zm[7 pr_state <= nx_state;
END IF;
END PROCESS;
---------- Phan mach to hop: -----------------
PROCESS (a, b, d, pr_state)
BEGIN
CASE pr_state IS
WHEN stateA =>
x <= a;
IF (d='1') THEN nx_state <= stateB;
ELSE nx_state <= stateA;
END IF;
WHEN stateB => 8i
VP + A UàK
PS 8i
VP + A UàK
PS
x <= b;
IF (d='1') THEN nx_state <= stateA;
gf
Cù d
zU Z f
daYZuZ.,(e nã[f YUSf
Z[f [g(
ELSE nx_state <= stateB; fZ UZ[n cùgfd

zU_ [ nkUZzYf SU Uvhn[e f
ZSkã[eah [f
Z[f [g
END IF; KtV U ZzYf SUvfZ e V Y_ ff
tZ[gf Zs
_ Zf tZ[gfd
gYY[ S ãftZfam
END CASE; Y[
mfdãgd S ãaõ fds Z YU ZU Zgk UmUY[
mfdUS vfZnZft Z[gãgdS Z[
END PROCESS; s [ UaU f ZSkã[bZ _õ UZVp
k Hf ZSkã[ nkUZzYf
Se fZùkf
daY Zgx
END state_machine; m gUZd SV [ão k0
---------------------------------------------- 6HS MLr

SLW
VRP
nMGR
HWIDBR
HIt
Rt
K fcgú_xbZ Y0
LIBRARY ieee;
-----------------------------------------------------
--
ENTITY <ent_name> IS
PORT (input: IN <data_type>;
reset, clock: IN STD_LOGIC;
output: OUT <data_type>);
END <ent_name>;
8i
VP *:í âUlXPòVOK
PW hL -----------------------------------------------------
ARCHITECTURE <arch_name> OF <ent_name> IS
8.3. Thi T TR TYPE states IS (state0, state1, state2, state3, ...);
CZ UZzYfSfZùkfd
aY [gf
Z[f f
ZuUZUvf
dõYf
Zm[Z[ f
õ[ã U gf
d Iù f SIGNAL pr_state, nx_state: states;
SIGNAL temp: <data_type>;
cúU
mU_õUZ Z hke ã Ufv_ ff Z fd
aYZuZ., Id aYfd YZb n k g
BEGIN
mõU
Z n_mkBW Sk ãgdSUS vbZ fZgUhn
aãghnaZ[ fõ[ ãgd
SUvf
Zf ZS
k
---------- Phan mach day: --------------------------
ã[Z[ãghn afZSkã[ãgdS ZxYã YT PROCESS (reset, clock)
BEGIN
Trong nhi g YV Yf
t Z[gã Uk
sgUg nã YT f
ZuãgdSe U
Z Ub Zf Z[
IF (reset='1') THEN
thay ã[e UaU f
õadS_m
kã YT BWSk ãgd
SbZú
[ã U gf d ff Z
fdaYZuZ.,(
---------- Phan mach to hop: -------------------------- SIGNAL pr_state, nx_state: state;

PROCESS (pr_state)
SIGNAL temp: BIT;
BEGIN
CASE pr_state IS BEGIN
WHEN state0 => ----- Phan mach day: ----------------------
temp <= <value>;
IF (condition) THEN nx_state <= state1; PROCESS (rst, clk)
... BEGIN
END IF;
WHEN state1 => IF (rst='1') THEN
temp <= <value>;
IF (condition) THEN nx_state <= state2; pr_state <= stateA;
...
END IF; ELSIF (clk'EVENT AND clk='1') THEN
WHEN state2 => x <= temp;
temp <= <value>;
IF (condition) THEN nx_state <= state3; pr_state <= nx_state;
...
END IF; END IF;
...
END CASE;
END PROCESS;
END PROCESS; ---------- Phan mach to hop: -----------------
END <arch_name>;
PROCESS (a, b, d, pr_state)
HaemZ Zgx _ gUSf

Z[f [g(h [f Z[f i g UZzYfSf Zù
kUZUv_ fe BEGIN
Zm
U ZS
gVgk Zùfãv njgù
fZ[ f
t Z[gfd
gYY[SfW_b It Z[g nke U
vf mU CASE pr_state IS
d Y gfd ãgdSUS_m k8ZUZaU
mUY[mf
dUZgk f
ZnZãgd S Z[Z[Uve fZS
k WHEN stateA =>
ã[e [ UaU temp <= a;
IF (d='1') THEN nx_state <= stateB;
EjM 8ZzYfSe Zu õ[fZ[f UShtV .( Igk Z[
s ão
kU ZzYfS
ELSE nx_state <= stateA;
mu ãgdSnã YT U ZfZSkã[ Z[U
ve [ f
ZSkã[UaU KuhkfdaYhtV
n
kUZzYf
Se fZ[f f
ZWa [g( END IF;
WHEN stateB =>
----------------------------------------------
temp <= b;
library IEEE;
IF (d='1') THEN nx_state <= stateA;
ELSE nx_state <= stateB;
----------------------------------------------
END IF;
ENTITY VD_FSM2 IS
END CASE;
PORT ( a, b, d, clk, rst: IN BIT;
END PROCESS;
x: OUT BIT);
END VD_FSM2;
END VD_FSM2;
----------------------------------------------
----------------------------------------------
ãokU
ZzYfSf
ZùkUv(X[
b Xabã Ue V Y _ fU
m[ã _pZamf
dõYf
Zm[US
ARCHITECTURE VD_FSM2 OF VD_FSM2 IS
_m
k_ fUm
[ã gf d ãgd
S
TYPE state IS (stateA, stateB);
B _xbZ Y fcgúã UU
ZdSf
daYZuZV [ão
k0 BpUS_m
kã Uf
Z[f Ze
Sg0
----------------------------------------------
library IEEE;
----------------------------------------------
ENTITY Bo_doan_xau IS
PORT ( d, clk, rst: IN BIT;
q: OUT BIT);
END Bo_doan_xau;
8i
VP ,:í âUlXPòVOK
PW hL (
--------------------------------------------
EjM 2 YQc QRWL
Q R ARCHITECTURE state_machine OF Bo_doan_xau IS
TYPE state IS (zero, one, two, three);
8ZzYfS_g fZ[f _ f_õU
Z_nãghna ng YT[f [f
[bhnãgd
Sn Z[
ãgUvjgo
fZ[ UZg[ n&fd
aYU
mUf
d YZbU w õ[ SIGNAL pr_state, nx_state: state;
BEGIN
ZuZf
dõYfZm
[US_m
kã UU Zd Sf daYZuZ. ão kU
ZzYf
SUv*f
dõYf
Zm[hn
U
ZzYfScgk Unfd
õYfZm
[zero, one, tow, three. --------- Phan mach day: --------------------
PROCESS (rst, clk)
IdSYf
Zm[& nf
dõYf
Zm[UZ ãgf [
s
BEGIN
IdSYf
ZS[ nfdSYf
Zm[ãpUv hnUZ 1 th (
TrõYf
Zm[( nf
dõYf
Zm[ãpUv hnãSYU Z fZ) IF (rst='1') THEN
TrõYf
Zm[) nf
dõYf
Zm[fZgã íUjo
g pr_state <= zero;
END IF;
END PROCESS;
---------- Phan mach to hop: ---------------
PROCESS (d, pr_state)
BEGIN
CASE pr_state IS
WHEN zero =>
q <= '0';
IF (d='1') THEN nx_state <= one;
8i
VP A àVO PbKI ùXPbP VK
Pú
ELSE nx_state <= zero; EjM ( 2 R TQRW h

WPR QnWP C 3
END IF;
CZ ãpY[[f Z[g bZ _õ U
Z_õUZf Zb T ã[g Z[ e n_õ
UZhtV ffã U
v
WHEN one => th fZ UZ[ Z[gcgú Z[_xZuZZam_m
kfdõYfZm
[IdaYhtV n kUZzYfSe
q <= '0'; thi f _ fIA8h [ Z YãUã[_ã Uf v_ U Z f d
aYZuZ. &0
IF (d='1') THEN nx_state <= two;
ELSE nx_state <= zero;
END IF;
WHEN two =>
q <= '0';
IF (d='1') THEN nx_state <= three;
ELSE nx_state <= zero;
END IF;
WHEN three => 8i
VP IA VOa
gVT
yPWà ùVOKIB 3
q <= '1';
IF (d='0') THEN nx_state <= zero;
ELSE nx_state <= three;
END IF;
END CASE;
END PROCESS;
END state_machine;
--------------------------------------------
K fcgú_xbZ Ye Z e
Sg0
8i
VP Pi
VP àVOPbKIB 3
ão
kUZzYf
SfZù
kUv)U
Zãf
ZSaf
mU0
Ch Kk
WQ Q WP: U
Zã n
k_õ
UZU
v*f
dõYf
Zm[_ [f
dõYf
Zm[nãU
l bf
Z[Y[
S bf d
uZ 5
8i
VP .:í âUlXPòVOK
PW ù WbVVPV d Ch TRV 8ZabZq
bfùfUúf
Z[Y[S ã U bfd
uZfd Uã Uh[fs
v [ Y[
mfd Z VahkZ f Z YUvfZ V VnYã U [_ f
dSf
daYe
gfcgm
fd
uZTS V Y
Ch B WMKb N gfZ[f bZ f
Z Ye t
UZZaõ
fãr hnYf
daY Z[f
t count := 0;
hi ge
fSVTkã U tUZZaõf ELSIF (clk'EVENT AND clk='1') THEN
Yf
Z [ ãxYZ f e ,&=O gx Zaõ
fã Y count := count + 1;
IF (count = time) THEN
Bpf
Z[f 0
---------------------------------------------------------
count := 0;
---
END IF;
library IEEE;
END IF;
END PROCESS;
ENTITY Bodk_den_giao_thong IS
----------- Phan mach to hop: ----
PORT ( clk, stby, test: IN STD_LOGIC;
PROCESS (pr_state, test)
r1, r2, y1, y2, g1, g2: OUT STD_LOGIC);
BEGIN
END Bodk_den_giao_thong;
CASE pr_state IS
-------------------------------------------------
WHEN RG =>
ARCHITECTURE state_machine_be OF Bodk_den_giao_thong IS
r1<='1';r2<='0';y1<='0'; y2<='0'; g1<='0';
CONSTANT timeMAX : INTEGER := 2700;
g2<='1';
CONSTANT timeRG : INTEGER := 1800;
nx_state <= RY;
CONSTANT timeRY : INTEGER := 300;
IF (test='0') THEN time <= timeRG;
CONSTANT timeGR : INTEGER := 2700;
ELSE time <= timeTEST;
CONSTANT timeYR : INTEGER := 300;
END IF;
CONSTANT timeTEST : INTEGER := 60;
WHEN RY =>
TYPE state IS (RG, RY, GR, YR, YY);
r1<='1';r2<='0';y1<='0';y2<='1';g1<='0';
SIGNAL pr_state, nx_state: state; g2<='0';
SIGNAL time : INTEGER RANGE 0 TO timeMAX; nx_state <= GR;
BEGIN IF (test='0') THEN time <= timeRY;
-------------Phan mach day: ---- ELSE time <= timeTEST;
PROCESS (clk, stby) END IF;
VARIABLE count : INTEGER RANGE 0 TO timeMAX; WHEN GR =>
BEGIN r1<='0';r2<='1';y1<='0';y2<='0';g1<='1';
IF (stby='1') THEN g2<='0';
pr_state <= YY; nx_state <= YR;
IF (test='0') THEN time <= timeGR;

END IF;
WHEN YR =>
r1<='0';r2<='1';y1<='1'; y2<='0'; g1<='0';
g2<='0';
nx_state <= RG;
IF (test='0') THEN time <= timeYR;
END IF;
WHEN YY =>
r1<='0';r2<='0';y1<='1'; y2<='1'; g1<='0'; 8i
VP I:í âUlXPòVOB 3 K
Pí ùPL i
VPP VO
g2<='0';
U
Z ã i _f
dS0
nx_state <= RY;
END CASE;
END PROCESS;
END state_machine_be;
----------------------------------------------------
CZ fSfZù
ke Y;[b-XabãpV Yã f
Z UZ[ _õ
UZ n +U
m[0)U
m[U
Za gf
d
trõYf
Zm[Z[ f
õ[ (U
m[Uw õ [U
ZaT ã_
U vf
Z V VnYf
Zùk fcgú_xbZ Y ão
kfSf
Z UZ[ Y[
ú_f
Z[Y[
SfZ Ufã[
100 l
K fcgú_xbZ Yã UU
ZdSf
daYZuZV [ão
k0 8i
VP :í âUlXPòVOB 3 K
Pí ùS U I
U
Z ã Zaõ
fã YTuZf
Z Ye
fTk3&f
Wef3&0 EjM ) 2 YQc j
WQR
8ZzYf
S_g f Z[f _ f_õ
UZ_nf f
t Z[gUaU U ã Sd
Sft Z[g Z f
daY
ZuZV [ão
k0
END PROCESS;
----- Phan mach day cua may 2: ---
PROCESS(clk)
BEGIN
pr_state2 <= nx_state2;
END IF;
END PROCESS;
---- Phan mach to hop cua may 1: -----
8i
VP 4àVOh
VP K
ãVàW PROCESS (pr_state1)
BEGIN
ão
k_õ
UZbZú
[Zaõ
fã Y U
ú(e USf
t Z[gU
CASE pr_state1 IS
BpU
Z íYf
duZ0
WHEN one =>
----------------------------------------- out1 <= '0';
ENTITY Bo_phat_tin_hieu IS nx_state1 <= two;
PORT ( clk: IN BIT; WHEN two =>
outp: OUT BIT); out1 <= '1';
END Bo_phat_tin_hieu; nx_state1 <= three;
----------------------------------------- WHEN three =>
ARCHITECTURE state_machine OF Bo_phat_tin_hieu IS out1 <= '1';
TYPE state IS (one, two, three); nx_state1 <= one;
SIGNAL pr_state1, nx_state1: state; END CASE;
SIGNAL pr_state2, nx_state2: state; END PROCESS;
SIGNAL out1, out2: BIT; ---- TMZ MOu T[ OaM Me ' -----
BEGIN PROCESS (pr_state2)
----- Phan mach day cua may 1: --- BEGIN
PROCESS(clk) CASE pr_state2 IS
BEGIN WHEN one =>
IF (clk'EVENT AND clk='1') THEN out2 <= '1';
pr_state1 <= nx_state1; nx_state2 <= two;
END IF; WHEN two =>
out2 <= '0'; Ki g_pZamaW Zafã UY[[f

Z[gf
daYUm
U YV Y_ne YUm
UX[ b-flop
nx_state2 <= three; nhi g Z fd
aYU m
UUZ[
b;E<6 CZ Yf
daYUm
U_õ
UZ6H>
8fZu_p Z bZo õ [
ã U gf [
s Zí
WHEN three =>
out2 <= '1'; KtV0<[
úe U
ZzYf
SUv_ f_m
kfd
õYf
Zm[U
v.f
dSYf
Zm[Z f
daYTúYV [ão
k0
nx_state2 <= one;
END CASE;
END PROCESS;
outp <= out1 AND out2;
END state_machine;
------------------------------------------
K fcgú_xbZ Y0
BâVO ePWb àVO PbK

PWUba6A àVOPb
V [.fd
õYf Zm
[US_m
knkf
Zue YX[
b-Xabã Uk
sgUg Yh[U
mU [g_p
Zame T Y0
3 (=log28), Yh[ [g_pZ

am Zb
Zo
8i
VP (:í âUlXPòVOK
PW hL + 5 ( n(n-1)/2= 8 => n = 5 ), Yh[ [g_pZ
amf
iaZ
af
8, Yh[[g_pZamaW
Zaf
8.4. Ki VfQ c WQ YQeW WP>WN
Q
_pZamf dõYfZm
[US_m kfd
õYfZm[UZzYf
SU vfZUZ _ ffdaYhn[ [gU
v
s [g_pZam_ Uã Z n Z bZo ìgã[_US [g_pZam n kn vk sgUge
YX[ b-Xabt
f ZùfIdaYfd YZ b nkh[ _õ UZX[
b-Xabf
ZuUvfZUZzYfS
n
U vfZ _pZamã U( trõYf Zm[CZ Uã[_ US [g_pZam n k n vks
gUgh
logic nhi gZí hn vU Z_Zí eah[ Z Y [g ZmU
8m [U g[U Y n [g_pZamaW Zafh [ [g_pZam n kU ZzYfSU e V Y

flip-flop cho 1 trõYf Zm [Kuhk vãw[Z[e YX[
b-flop l ZùfId
aYf
d Y
h bn k h[ X[ b-flop (n bit) ch UvfZ _pZamã U f dõYfZm[CZ YT õ[
bZ íYbZm bn kõ [k sgUgf tZf am aY[U[f Zù
fhnfUã ZSZ Zù f
M f [g _ Y[S( [gfd
s n [g_pZamfiaZaff
daY_ ff
dõYf Zm[U ZU
v(T[f
Kuhkh[ X[b-Xab T[ff
ZuU
ZzYfSUvfZ _pZamã U -1)/2 trõYf
Zm[
DY HC9: THI 91 9 O3 P 3c DY HC9: THI 91 9 O3 P 3c
3Q àWP, THI C: C8y< 3 3<ó38

Ph n
kUZzYf
Se f
duZTn
kUm
U_õ
UZe
Sg0
Barrel shifter
B e ae mZ ZxYVù ghnUvVùg
B U Y
B U Z[ SVù gU Zù
_f éZ
B ã[g Z[ _m kTm ZnY
B Z V [g [f [b
B U Zgk ã[e aYeaYe Sg n [f
[b
SSD
B bZm fft Z[g
B Z
9.1. Barrel Shifter.

Híã US_õ UZUST VU ZTS d
dWã UU Zd
Sfd
aYZuZ/ ghn a nhWUf
ad.T[f
gdSnbZ[
s Tú VUZUSãghn a h[ YVU Zã Uã Z YZé ST[.ãghn a
eZ[X
f f aã Bõ ch g _ Uv)T VU ZTSd
dWd[sY _ [_ fU m[Y[ Y Z
fdaYhtV ,/ CZ YU ZzYf SbZú[UZg d Y TS
ddW ãgf
[sU vUZU v ãg &
ã U f [h[_ fT V sZ f daY Z[TS
ddWfZ (Uv(ãghn a & hnTSdd
W
cu [U YUvf[*ãghn a& hWU
fad Zí fZuUZzYfSbZú[V (ãghn an
& KtV ge Z[
Xf3 && f ZuUZ TS
ddWãgf[
s YokdSVUZUw ge Z[
Xf3
fZufù
fUm
UãgYokdSVUZ 8i
VP. 2ùLK
PIM
T
Bpf
Z[f e Z e
Sg0
---------------------------------------------
LIBRARY ieee;
---------------------------------------------
ENTITY barrel IS
PORT ( inp: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
shift: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
outp: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END barrel;
---------------------------------------------
ARCHITECTURE behavior OF barrel IS outp(i) <= '0';

BEGIN END LOOP;
PROCESS (inp, shift) FOR i IN 4 TO inp'HIGH LOOP
VARIABLE temp1: STD_LOGIC_VECTOR (7 DOWNTO 0); outp(i) <= temp2(i-4);
VARIABLE temp2: STD_LOGIC_VECTOR (7 DOWNTO 0); END LOOP;
BEGIN END IF;
---- Bo dich thu nhat ----- END PROCESS;
IF (shift(0)='0') THEN END behavior;
temp1 := inp; ---------------------------------------------
ELSE K fcgú_xbZ Y0
temp1(0) := '0';
temp1(i) := inp(i-1);
END LOOP;
END IF;
---- Bo dich thu 2 -----
IF (shift(1)='0') THEN
8i
VP. :í âUlXPòVOK
PW ùLK
PIM
T
temp2 := temp1; 9.2. B cWQTQnWPM _dL

lM
ELSE =uZ/)Z[ s e íã UST e
aemZ t U
ZfZ Uc ShWUfadã Ue aemZ nYWWd[
U
FOR i IN 0 TO 1 LOOP )ãgdSbZú[ã UUgYUùbn0 ãgd SnS4T ãgd SnS3Tãgd SUw õ[
temp2(i) := '0';
nS2T )Y[ú
[bZmbã UY[[f
Z[g0ãgf [
s jqfShnT nU m
Ue UvVùgfdaY Z[(
[bZm
giú bU
w õ [nUm
Ue ZxYVù g fcgú_xbZ Ye U ZaUZzYfSf
ZùkdyZí
END LOOP;
temp2(i) := temp1(i-2);
END LOOP;
END IF;
---- Bo dich thu 3 -----
IF (shift(2)='0') THEN
outp <= temp2;
ELSE 8i
VP.( lPi
VPKI ù W bVP
B e
aemZU
vVù
g0 B cWQTQnWPM
n_ h[Uh[e U vVùgZaUe ZxYVù gfZuU

ZzYfSãgbZú
[ ZS
[Tm
aYv[ Ph _pK=9Ae
Sgão
k nTú e
SaUSbZ _pãpã Uf
duZTn
k T e
aemZ
std_logic_arith (c f
ZU ZzYfSe f
Zùkf
daYãaõ _pV [ão
k ZxYVù
g
<f QRt k K cWQL

lM ---- Bo so sanh khong dau 1: -----------
LIBRARY ieee;
---- Bo so sanh co dau: ----------------
LIBRARY ieee; USE ieee.std_logic_1164.all;
USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; --rat can thiet!
USE ieee.std_logic_arith.all; -- can thiet! ----------------------------------------

---------------------------------------- ENTITY Bo_so_sanh_khong_dau1 IS
ENTITY Bo_so_sanh_co_dau IS GENERIC (n: INTEGER := 7);
GENERIC (n: INTEGER := 7); PORT (a, b: IN UNSIGNED (n DOWNTO 0);
PORT (a, b: IN SIGNED (n DOWNTO 0);
x1, x2, x3: OUT STD_LOGIC);
END Bo_so_sanh_khong_dau1;
END Bo_so_sanh_co_dau;
----------------------------------------
----------------------------------------
ARCHITECTURE arc OF Bo_so_sanh_khong_dau1 IS
ARCHITECTURE arc OF Bo_so_sanh_co_dau IS
BEGIN
BEGIN
x1 <= '1' WHEN a > b ELSE '0'; x1 <= '1' WHEN a > b ELSE '0';
x2 <= '1' WHEN a = b ELSE '0'; x2 <= '1' WHEN a = b ELSE '0';
x3 <= '1' WHEN a < b ELSE '0'; x3 <= '1' WHEN a < b ELSE '0';
END arc; END arc;
---------------------------------------- ----------------------------------------
K
K fcgú
0
8i
VP.):í âUlXPòVO ù W bVPK
jL 8i
VP.* :í â ù W bVPS
PlVOL
B cWQTQnWPM 9.3. B LWP3 bAR

YYU
N_dK LWP3 b T1QNM
8Sd
dkd[
bbWhnU
Sdd
k aa SZW
SV n(bZ í YbZm
bU ã[ ã f
Z[f UmU
UT U Y
B e
aemZ ZxYVùgU
vfZUèYã UfZ UZ[ h[HI9QAD<>
8QK:8IDGH f
daY
EZ íYbZmbãgf[
sU vfZg [nksgUgbZ U Yt ffd
aY Z[U
m[fZ ZS
[lõ
[
f
d YZb n k ZxYU f
Z[fbZú
[ZS
[Tmaef
VQaY[
UQS
d[f
Z
ZSZZí
<f QRt k WQ
BxD
xMGD
BPP
VPI
OOK
F
---- Bo so sanh khong dau: -----------
=uZ
V/,U
ZdS T U Yd
[bbWU
Sdk*T
[fZxYV
ùg0
LIBRARY ieee;
----------------------------------------
ENTITY comparator IS
GENERIC (n: INTEGER := 7);
PORT (a, b: IN STD_LOGIC_VECTOR (n DOWNTO 0);
END comparator;
---------------------------------------- 8i
VP.+A ùK
ùVO X
XTMK
Ia
ARCHITECTURE unsigned OF comparator IS Id

se íã f
SU vfZf Zùk h[_ [T [f_ fãí h T U Yãkã e ã UfZ UZ[
BEGIN BúYfZfUST U Yãkã ã UU Zd ST
sU õZeíã fdaYãvST nU
mUT t
fãg
x1 <= '1' WHEN a > b ELSE '0'; hn
aU[ nT[fZ h na enT [
ff Y U
agfnT[
fZ d SI T úYf
Zff
SV V nYf tZ
ã U0 s = a xor b xor cin
x2 <= '1' WHEN a = b ELSE '0';
x3 <= '1' WHEN a < b ELSE '0'; cout = (a and b) xor (a and cin) xor (b xor cin)
END unsigned;
T UxYfZ Uf
dsfSj
okV YUZ í Yf
duZK=9A Z e
Sg ã
okU
ZzYf
SUvf
Zmb
BxbZ Y fcgú
0 d YUZ
aTùf êe Yãgh
nan a0
LIBRARY ieee;
---------------------------------------------
ENTITY Bo_cong_carry_ripple IS
GENERIC (n: INTEGER := 4);
PORT ( a, b: IN STD_LOGIC_VECTOR (n-1 DOWNTO 0);
cin: IN STD_LOGIC;
8i
VP.*2. Kí âKI ù W bVPS
PlVOL
s: OUT STD_LOGIC_VECTOR (n-1 DOWNTO 0);
cout: OUT STD_LOGIC);
END Bo_cong_carry_ripple;
---------------------------------------------
ARCHITECTURE arc OF Bo_cong_carry_ripple IS
SIGNAL c: STD_LOGIC_VECTOR (n DOWNTO 0);
BEGIN
c(0) <= cin;
G1: FOR i IN 0 TO n-1 GENERATE
s(i) <= a(i) XOR b(i) XOR c(i);
c(i+1) <= (a(i) AND b(i)) OR
(a(i) AND c(i)) OR 8i
VP. A bùK
ùVOcarry look ahead
(b(i) AND c(i));
MõUZã UZaõ
fã YV Sfd
s UmU Zm
[[s
_ YWW
dSf
Whnbd
abS
YSf
W8ZtZãUã[_
END GENERATE; n
kãpn_UZaT U Y nkf
Z UZ[ h[fUã ZSZZí eah[T U Yf
d U
cout <= c(n);
Giúe (ãghna n(T[ fSTf
Zu(f
t Z[gbbd
abS
YSf
W hnYYWW
dSf
W ã Uf
tZ Z
END arc;
sau: g = a and b
---------------------------------------------
p = a or b
K fcgú_xbZ Y0
N gU
ZzYf
SjW
_ST nU
mUhW
Ufad
0 a = a(n- S S& 1T3T - T T&
f
ZuYbã Uf
tZ Z e
Sg0 p = p(n- b b&1Y3Y - Y Y&
Id
aYãv0 g(i) = a(i) and b(i)
p(i) = a(i) or b(i)
AzU n
khW
Ufad Z e n
0U3U - U U& f
daYãv0
8i
VP.,:í âUlXPòVOK
PW ùK
ùVO XXT
MKIa c(0) = cin
BxD
xMGD
BPP
VKNN BHF
BE c(1) = c(0)p(0) + g(0)
Híã T U YU
Sdd
kaa S
ZWS
V*T[
fã UU
ZdSf
daYZuZ/. V [ão
k0 c(2) = c(0)p(0)p(1) + g(0)p(1) + g(1)
c(i) = c(i-1)p(i-1) + g(i-1)
T UxYf
Z Uf
uZf
ds U
ZzYf
Sh[fU
Z í Yf
duZf
Z[f T U YU
Sdd
k aa S
ZWS
V*
T[
fZ eS
g0
--------------------------------------------- (g(0) AND p(1) AND p(2)) OR

LIBRARY ieee; (g(1) AND p(2)) OR g(2);
USE ieee.std_logic_1164.all; c(4) <= (cin AND p(0) AND p(1) AND p(2) AND p(3)) OR
--------------------------------------------- (g(0) AND p(1) AND p(2) AND p(3)) OR
ENTITY Bo_cong_carry_look_ahead IS (g(1) AND p(2) AND p(3)) OR
PORT ( a, b: IN STD_LOGIC_VECTOR (3 DOWNTO 0); (g(2) AND p(3)) OR g(3);
cin: IN STD_LOGIC; cout <= c(4);
s: OUT STD_LOGIC_VECTOR (3 DOWNTO 0); END Bo_cong_carry_look_ahead;
cout: OUT STD_LOGIC); ---------------------------------------------
END Bo_cong_carry_look_ahead; K fcgú_xbZ Y0
---------------------------------------------
ARCHITECTURE Bo_cong_carry_look_ahead OF
Bo_cong_carry_look_ahead IS
SIGNAL c: STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL p: STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL g: STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN 8i
VP. :í âUlXPòVOK
PW ùK
ùVOcarry look ahead
---- PGU: ---------------------------------
9.4. B L
QR d L
Q V WQ
G1: FOR i IN 0 TO 3 GENERATE
Id U Z[ã[hn
afZ[f U
ZzYf
SU bZú
[ ZUõ
[fZgff
am U
Z[S
0
p(i) <= a(i) XOR b(i);
ThusRR
NWMD
HIB
g(i) <= a(i) AND b(i);
s(i) <= p(i) XOR c(i); M Uãt UZUSf
Zgff
am nU
ZzYf
SU f
tZk3STf
daYãvST n Z Ye U YU
v
END GENERATE; (n+1) bit.
---- CLAU: -------------------------------- Thu ff am ã Uf Z Z[ f

daYTúY//fdaYãvS3 & 3 10 hnT3 &&
c(0) <= cin; (=(3)10). K fcgúe f
Zgã U0f
Z íYk3 && 3)10 hne V d3 &&& 3(10).
c(1) <= (cin AND p(0)) OR
g(0); Ch ù _d B cWQ ù _d K y CQ cLL
QL
c(2) <= (cin AND p(0) AND p(1)) OR 3 1011 < 0011000 0 ZxYn
_Yu
(g(0) AND p(1)) OR 2 1011 < 0001100 0 ZxYn
_Yu
g(1);
1 1011 > 0000110 1 Tr UfSU
ZaUfT
0 0101 > 0000011 1 Tr UfSU
ZaUfT
c(3) <= (cin AND p(0) AND p(1) AND p(2)) OR
8iVP VARIABLE temp2: INTEGER RANGE 0 TO 15;

0010
9.9. BEGIN
Thu WbVK
PI
----- ;T[U M[ bMt NM X[U -------
[f
Giú Zt
UZf
Zgff
am0 temp1 := a;
temp2 := b;
gf
[sU Zgk e U
Z[Sf
ZnZe ( T[
fT YU
mUZf
Zs_ hn
aeS
g -1 bit 0 ,
IF (b=0) THEN err <= '1';
s TUZ[
Sh Y[ Ygks
Hae
mZe T UZ[
Sh[s UZ[
S C ge T U
Z[S Zí ZaUT Ye UZ[
SfZuYm ELSE err <= '0';
k3 hnf
ZSke TUZ[
ST YZ[gUSe T U Z[
Sh[e U
Z[SCY Uõ
[fZuk3& END IF;
Fgmf
duZf
Z UZ[ [
s fUU
Zaã Z[Zf ----- y(3): ---------------------------
IZ íYnVp
kT[
fUSke V ne
xTU
Z[SU
g[U Y IF (temp1 >= temp2 * 8) THEN
f
Z[t k T U Z[
SnkfZuU
ZzYfSUv(bZ íYbZm
b08ú(bZ í YbZm
bãgf ZU y(3) <= '1';
hi fZWa_pf g f0EZ íYbZm bf
Z Zù fUZf
Z UZ[ T YUog [ XbZ íY temp1 := temp1 - temp2*8;
bZmbf
Z (f Z UZ[ T YUúUog [Xhnaab ELSE y(3) <= '0';
Bpf
Z[f T U
Z[Se Z e
Sg0 END IF;
----- y(2): ---------------------------
RtR
Thit HFNO
Hg MGO
HWO:
IF (temp1 >= temp2 * 4) THEN
----- Phuong phap 1: step-by-step -------------------
y(2) <= '1';
LIBRARY ieee;
temp1 := temp1 - temp2 * 4;
ELSE y(2) <= '0';
--------------------------------------------------
END IF;
ENTITY Bo_chia IS
----- y(1): ---------------------------
PORT ( a, b: IN INTEGER RANGE 0 TO 15;
IF (temp1 >= temp2 * 2) THEN
y: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
y(1) <= '1';
rest: OUT INTEGER RANGE 0 TO 15;
temp1 := temp1 - temp2 * 2;
err : OUT STD_LOGIC);
ELSE y(1) <= '0';
END Bo_chia;
END IF;
--------------------------------------------------
----- y(0): ---------------------------
ARCHITECTURE arc OF Bo_chia IS
IF (temp1 >= temp2) THEN
BEGIN
y(0) <= '1';
PROCESS (a, b)
temp1 := temp1 - temp2;
VARIABLE temp1: INTEGER RANGE 0 TO 15;
ELSE y(0) <= '0';
END IF; VARIABLE temp1: INTEGER RANGE 0 TO 15;

----- Phan du: ---------------------- VARIABLE temp2: INTEGER RANGE 0 TO 15;
rest <= temp1; BEGIN
END PROCESS; ----- Khoi tao gia tri va bat loi: -------
END arc; temp1 := a;
-------------------------------------------------- temp2 := b;
K fcgú_xbZ Y0 IF (b=0) THEN err <= '1';

ELSE err <= '0';
END IF;
----- thuong: ------------------------------
FOR i IN n DOWNTO 0 LOOP
IF(temp1 >= temp2 * 2**i) THEN
y(i) <= '1';
temp1 := temp1 - temp2 * 2**I;
8i
VP. :í âUlXPòVO ùK
PI
ELSE y(i) <= '0';
RtR
Thit HFNOHg MGOHWO :
END IF;
------ Phuong phap 2:----------------------------- END LOOP;
LIBRARY ieee; ----- phan du: ----------------------
USE ieee.std_logic_1164.all; rest <= temp1;
-------------------------------------------------- END PROCESS;
ENTITY Bo_chia2 IS END arc;
GENERIC(n: INTEGER := 3); --------------------------------------------------
PORT ( a, b: IN INTEGER RANGE 0 TO 15; K fcgú_xbZ Y0
y: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
rest: OUT INTEGER RANGE 0 TO 15;
err : OUT STD_LOGIC);
END Bo_chia2;
--------------------------------------------------
ARCHITECTURE arc OF Bo_chia2 IS
BEGIN 8i
VP. :í âUlXPWVO ùK
PI P
PROCESS (a, b)
9.5. B R TQRWVcbKcWQdWP chuy ã f dõYfZm[(+IuZZg YfíYf e ã U b õ [UZafùfU

úUmUf
dõYfZm
[
IdaYhtV nkU ZzYfSe f
Z[f T ã[g Z[ _mkTm ZnY _mkTm ZnYe cho t [f
dõYfZS[(& C gfd
õYfZm[(+ã Ujm UZ f Zuf
ZSZ aã UbZo bZm f
Tm U
mUfZSZ ah[Y[m(+jg 8ZzYfSe f
Z[f f
ZWa_xZuZ_mk;HB gd
S hn ZxYU Zgk ã[Igk Z[ s gf d
õYf Zm[*&ã Ujm UZ f ZuS [
UWã Uf dú
hnãghnaUST ã[g Z[ ã UfZ Z[ f
daYZuZ/ lõ[T[hkf dõYfZm
[e UZgk f[fdõYfZm [)+ãv n fdõYfZm[_n V[_Wã Ufdú
lõ[hn U SVkTSdã UbZo bZmf8v)f d
õYf Zm
[fõ
adSUZgfd
uZ q bãv nf fZSZ
It Z[ghnan [UWQ[ V[_WQ[ hncgSd
fWd
Q[ f
ZxYTmad Y_ fã Yf[ fí Y k aã UbZo bZm fhn_m kfd õ
[fdõYf Zm[& 7n[f
am n ke ã UU Z[
SfZnZ(
Yã UY [hnafn
[ Zaú CYan[dSU
wU v(ãghnaã[g Z[ 0ãghnad
WeW
fde
f ph 0
hnãghn aUaU U 7 ã[g Z[ f d
ú [T Y)f t Z[gãgdS0U
SVkQagfã
bZo bZm
ffZSZ a [ UWQagfhnV[_WQagfUb Zfõ[fZS
kã[ Trong ph ãg0V[ _õ
aUíTú [
s cgS ã f
Z[f T ã[g Z[ _m
kTm
ZnY Z f d
aYZuZ/
Id
s ZuZ/ UèYU ZdSã ZuZf
dõYfZm
[US_mk;HB 8m
Ue Ts f
daYUm
UhwY Trong ph (08m
UUZU Y_ d Yã Uf
Zs_hn
a
f
dw T[gV[ f Yf
n[ Zaú US Zm
UZZnY U
ZU vUmU[UW V[
_WhncgSdf
Wdn
ã UUZùbZ ãokUZzYfSU
Z YZ[s UgbZ _ fUSTn [f
am0CZu hn
aã ZuZfd
õYfZm[US
_m k ZuZ/ U ZzY f
SfZù
kU v &f dõYf
Zm[ Z hkU U v*T[
fã _pZamUm
U
trõYfZm[fUnU e V Y*X[ b-flop.
<f QR T WQ
------------------------------------------------------
LIBRARY ieee;
------------------------------------------------------
ENTITY Bo_dieu_khien_may_bh IS
PORT ( clk, rst: IN STD_LOGIC;
nickel_in, dime_in, quarter_in: IN BOOLEAN;
candy_out, nickel_out, dime_out: OUT
STD_LOGIC);
END Bo_dieu_khien_may_bh;
------------------------------------------------------
ARCHITECTURE state_machine OF Bo_dieu_khien_may_bh IS
TYPE state IS (st0, st5, st10, st15, st20, st25,
st30, st35, st40, st45);
8i
VP. Pi
VP àVOPbKI ù ì S
P VUba bVPcVO SIGNAL present_state, next_state: STATE;
BEGIN
TrõYfZm
[& nfdõYfZm
[nf d
õYfZm
[ ZxY n
_ YuUúI ãv g ã Y [UWã U
g [hnaf
n[ Zaú _mke UZgk fd
õYfZm
[ã f d
õYfZm[+ g ã YV[ _Wã U ---- Lower section of the FSM (Sec. 8.2): ---------
g [hn
afn[ Zaú f
Zu_mkU
Zgk f[fdõYf
Zm[ &ZaU g ã YcgS
dfW
dfZu_m
ke
PROCESS (rst, clk) END IF;

BEGIN WHEN st10 =>
IF (rst='1') THEN candy_out <= '0';
present_state <= st0; nickel_out <= '0';
ELSIF (clk'EVENT AND clk='1') THEN dime_out <= '0';
present_state <= next_state; IF (nickel_in) THEN next_state <= st15;
END IF; ELSIF (dime_in) THEN next_state <= st20;
END PROCESS; ELSIF (quarter_in) THEN next_state <=
st35;
---- Upper section of the FSM (Sec. 8.2): ---------
ELSE next_state <= st10;
PROCESS (present_state, nickel_in, dime_in, quarter_in)
END IF;
BEGIN
WHEN st15 =>
CASE present_state IS
candy_out <= '0';
WHEN st0 =>
nickel_out <= '0';
candy_out <= '0';
dime_out <= '0';
nickel_out <= '0';
IF (nickel_in) THEN next_state <= st20;
dime_out <= '0';
ELSIF (dime_in) THEN next_state <= st25;
ELSIF (quarter_in) THEN next_state <=
st40;
st25;
END IF;
WHEN st20 =>
END IF;
candy_out <= '0';
WHEN st5 =>
nickel_out <= '0';
candy_out <= '0';
dime_out <= '0';
nickel_out <= '0';
dime_out <= '0';
st45;
st30;
END IF;
WHEN st25 =>

candy_out <= '1';
nickel_out <= '0';
dime_out <= '0';
next_state <= st0;
WHEN st30 =>
candy_out <= '1';
nickel_out <= '1';
dime_out <= '0';
next_state <= st0;
WHEN st35 =>
8i
VP. :í âUlXPòVO ù ì S
P VUba bVPcVO
candy_out <= '1';
nickel_out <= '0'; 9.6. B WQ WMÀU
R W RRY
dime_out <= '1'; Híã Z[UST Z V [g [f [bã UU Zd Sfd
aYZuZ/ ) CvTS aY_ _ f
next_state <= st0; ãghn aV [g [f [b V[ hn_ fãgd SV [ge aYe aY VSfS,0& CYan [dSU
w
Uvf t Z[gã[g Z[ U f t Z[gUaU =S [ft Z[gY[m_emfã Uf õ
ad ST[_õ U
Z
WHEN st40 =>
n0ft Z[gW d
dW dd
adhnf t Z[gVS
fSQhS[
V ghn aj U Z S &Tt f7[fãgf[s n
candy_out <= '0'; bit b fãg gT[ fn f Zu_õUZTfãg Z V [g T[ ff
[bf ZWa nUmUT[
fV [g
nickel_out <= '1'; hoõ fã Y7[ ffZ / nT[fUZ 0T[ fn k3 & ge YUmUT[ff daYV [g S
dime_out <= '0'; ch hnT Y f d
aYf d YZ U w õ [7[
f & nT[fef
ab0T[fnke _SYY[ mf
dn
n gcgmf d
uZU Zgk ã[nãzY B f [ã UbZm fZ[ Z[T[ fU Z ZxYã U
next_state <= st35;
ki _ f d
SZaUT[ fef
ab ZxYbZú [S Z[cgmfduZ Z ffZzU_n ZxYU v [
WHEN st45 =>
n aã UbZm fZ[ fZuV [gã U gf dfdaYU mUfZSZYZ[Ts f daYe U Zgk
candy_out <= '0'; hn aVS f
S,0& hnãgd SVSf
SQhS[Vã Ujm UZ
nickel_out <= '0';
dime_out <= '1';
next_state <= st35;
END CASE;
END PROCESS;
END state_machine;
------------------------------------------------------
8i
VP. (A ùVPVL T Vô í
X
K fcgú_xbZ Y0
fZ[f _õU
Zn kU
ZzYf
Se e V Y_ fhn
[T[ ã n_UmUT[ ã_ T[ jm
U ELSIF (count = 10) THEN
nh e T[
f Z ã UT[ gfd V [gT[ ftZfam [hnT[ f
dgYY[
S temp := (reg(1) XOR reg(2) XOR reg(3) XOR
reg(4) XOR reg(5) XOR reg(6) XOR
<f QR T K WQ WMÀU
R W RRY WQ
reg(7) XOR reg(8)) OR NOT reg(9);
--------------------------------------------- err <= temp;
LIBRARY ieee; count := 0;
USE ieee.std_logic_1164.all; reg(0) := din;
--------------------------------------------- IF (temp = '0') THEN
ENTITY Bo_nhan_du_lieu_nt IS data_valid <= '1';
PORT ( din, clk, rst: IN BIT; data <= reg(7 DOWNTO 1);
data: OUT BIT_VECTOR (6 DOWNTO 0); END IF;
err, data_valid: OUT BIT); END IF;
END Bo_nhan_du_lieu_nt; END IF;
--------------------------------------------- END IF;
ARCHITECTURE arc OF Bo_nhan_du_lieu_nt IS END PROCESS;
BEGIN END arc;
PROCESS (rst, clk) -------------------------------------------------
VARIABLE count: INTEGER RANGE 0 TO 10; K fquú_xbZ Y0
VARIABLE reg: BIT_VECTOR (10 DOWNTO 0);
VARIABLE temp : BIT;
BEGIN
IF (rst='1') THEN
count:=0;
reg := (reg'RANGE => '0');
temp := '0';
err <= '0';
data_valid <= '0';
IF (reg(0)='0' AND din='1') THEN
reg(0) := '1';
ELSIF (reg(0)='1') THEN
count := count + 1;
8i
VP. ):í âUlXPòVO ùVPVL T
IF (count < 10) THEN
reg(count) := din;
9.7. B L
Q bW WP WP QdWQW RRY dout: OUT STD_LOGIC);
B U Zgk eaYe aYf ZnZ [f [b n_ faõ[ YV YUSfZSZYZ[VU Z7 END Bo_chuyen_dl_ss_nt;

chuy ã[ n ke fZ UZ[ h[UY [ã[_ f Z[V [g [f[b K[Ue Vng b -------------------------------------------------
chuy ã[ n k nd
ùfU f Z[fhtV0Id
aYU m
UUaUZ[
b6H>8 Z[ ZxYUvã U mU ARCHITECTURE Bo_chuyen_dl_ss_nt OF Bo_chuyen_dl_ss_nt IS
UZo V ã UZadSã Yf Z[fùfUúU
mUT[
fV [g Z[ãvU
ZzYfSU f Z[fbZú
[e
SIGNAL reg: STD_LOGIC_VECTOR (7 DOWNTO 0);
d YT U Zgk ã[eaYe aYf ZnZ [f[b
BEGIN
Híã Z[UST U
Zgk ã[e
aYe
aYf
ZmZ [f
[bã Uf
duZTn
kfd
aYZuZ/ +
PROCESS (clk)
BEGIN
IF (load='1') THEN reg <= d;
ELSE reg <= reg(6 DOWNTO 0) & '0';
END IF;
8i
VP. *2ùK
PaV WVO WVO PcVPVô í
X
END IF;
Id
aYãv0 END PROCESS;
dout <= reg(7);
d(7:0) nhW
UfadV [gã Y [ã[
dout nãgd
SfZ Uf END Bo_chuyen_dl_ss_nt;
clk: ghn
aUSjgYUaU -------------------------------------------------
load: ghn
ajm
UZ K fcgú_xbZ g:
KWUfadVã U gf d ã YT f d
aYthanh ghi d UZdWY Z[aS V fd
õYf Zm[US
afZu
d [gã U õ bhn
afZSZYZ[VU ZfZWafZ f T[ fBH7 nTtfY ãgd S Zùfhnãg
dS nV . M [ Z[aSVfd
úõ [& f ZuT[
ff[bf ZWaã Ujgù fZ[ fõ
[ãgd SUS_ [
e V íYUSjgYã YZ Sau khi tù fUú.T[ fã UY [ã[ãgd Sfd õ[_ UfZùb
UZaã UZgk ã[f[bfZWa
Bpf
Z[f Ze
Sg0
LIBRARY ieee;
8i
VP. +:í âUlXPòVOK
PW ùK
PaV WVO WVO PcVPVô í
X
------------------------------------------------- 9.8. C mL
QàR i
WUN
M* Q WQ
ENTITY Bo_chuyen_dl_ss_nt IS 8ZzYf SfZ[f f
dwU
Zí[h[HH9 e
WhW e WY_WfV[
ebS
k Híã US_õ U
Zã U
ch dSfd
aYZuZ/ CvTS aY_ (ãghn a nU hnef
ab hn_ fãgd Sn
PORT ( d: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
Vagf,0
& ãgd Sn
ke ã UZ[ fZf
ds HH9 Phú
[ãú
_Túad YX
dk = 1Khz
clk, load: IN STD_LOGIC;
--------------------------------------------------------
LIBRARY ieee;
--------------------------------------------------------
ENTITY Trochoiled7thanh IS
PORT ( clk, stop: IN BIT;
dout: OUT BIT_VECTOR (6 DOWNTO 0));
END Trochoiled7thanh;
8i
VP. ,A KIAA4 --------------------------------------------------------
Mõ U
ZUSU ZzYfSe fõad
S_ fe UZgk ã Y [
s fUfZW
aUZ[g [
_ ã YZ US ARCHITECTURE arc OF Trochoiled7thanh IS
U
m Uãaõ HH9 YfZ[ vUwf õadSe VU
ZUZgk UZ Yl bY[SUmUf
ZSZ CONSTANT time1: INTEGER := 4; -- Gia tri thuc te hien thi la
ZSg8ZzYf SU
vfZ T[gV[ cgkf
duZUS v Z eS
g0 80
CONSTANT time2: INTEGER := 2; -- Gia tri thuc te hien thi is
a -> ab -> b -> bc -> c -> cd -> d -> de -> e -> ef -> f -> fa -> a.
30
TYPE states IS (a, ab, b, bc, c, cd, d, de, e, ef, f, fa);
SIGNAL present_state, next_state: STATES;
SIGNAL count: INTEGER RANGE 0 TO 5;
SIGNAL flip: BIT;
BEGIN
------- Phan mach day cua arc : ------------
PROCESS (clk, stop)
BEGIN
IF (stop='1') THEN
present_state <= a;
8i
VP. Pi
VP àVOPb IF ((flip='1' AND count=time1) OR
(flip='0' AND count=time2)) THEN
Fgmf duZe V Y õ [ Z[U
vft Z[gHfabhn Z[ãv_õ
UZe fd õ[f
dõYf Zm[ShnUZ
UZaã Z[e fabjg Yf Zùbf
d õ [= fZ YUSU ZzYfSe Y[ õ[U m
Uf d
õYf Zm
[S count <= 0;
b, c, d , e, f trong khoúYfZ[Y[ Sf[
_W 3.&_ehn U mUf
dõYfZm[STTUU VVWW X present_state <= next_state;
XSnf [
_W (3)&_e ELSE count <= count + 1;
BpU
Z íYf
duZUSU
ZzYf
Se Z e
Sg: END IF;
END IF; dout <= "0001000"; -- Decimal 8

END PROCESS; flip<='1';
------- Phan mach to hop: ------------ next_state <= de;
PROCESS (present_state) WHEN de =>
BEGIN dout <= "0001100"; -- Decimal 12
CASE present_state IS flip<='0';
WHEN a => next_state <= e;
dout <= "1000000"; -- Decimal 64 WHEN e =>
flip<='1'; dout <= "0000100"; -- Decimal 4
next_state <= ab; flip<='1';
WHEN ab => next_state <= ef;
dout <= "1100000"; -- Decimal 96 WHEN ef =>
next_state <= b; flip<='0';
WHEN b => next_state <= f;
dout <= "0100000"; -- Decimal 32 WHEN f =>
next_state <= bc; flip<='1';
WHEN bc => next_state <= fa;
dout <= "0110000"; -- Decimal 48 WHEN fa =>
next_state <= c; flip<='0';
WHEN c => next_state <= a;
dout <= "0010000"; -- Decimal 16 END CASE;
flip<='1'; END PROCESS;
next_state <= cd; END arc;
WHEN cd => --------------------------------------------------------
dout <= "0011000"; -- Decimal 24 Kí âUlXPòVO/
flip<='0';
next_state <= d;
WHEN d =>
END Bo_phat_tin_hieu;
-----------------------------------------------------
ARCHITECTURE arc OF Bo_phat_tin_hieu IS
TYPE states IS (zero, one, two, three, four, five, six,
seven);
SIGNAL present_state, next_state: STATES;
SIGNAL temp: STD_LOGIC;
8i
VP. .:í âUlXPòVOK
PW kK
P g
VAA4
BEGIN
9.9. B YQc j
WQR --- Phan mach day: ---
T _ fft Z[gUaU f
S_aY_g f Zgã U_ fft Z[gU
vVSYe vY Z fdaY PROCESS (clk)
ZuZ/(& K [Tn[f
am aõ[nkUZzYf SUvf
Z e V YbZ íYbZmb;HB ZaU BEGIN
bZ íYbZmbfd
gk fZ Y8ú(bZ íYbZmbãgã UUZzYfSf
duZTn
kV [ãok0
Hg MGO
HWO2 8 present_state <= next_state;
wave <= temp;
END IF;
END PROCESS;
--- Phan mach to hop: ---
PROCESS (present_state)
BEGIN
8i
VP. 8i
VPLà
VOj
VOK
ãVX
Pb
CASE present_state IS
It Z [gUSZ uZ/( &UvfZ ã U_xZ uZ Z _ f;HB .fdõYfZm[H V YT WHEN zero => temp<='0'; next_state <= one;
ã_ f &ã 8ZzYfSUvfZfZ[f b_ fe vYT Y & Z [T[ ã_ 3 & WHEN one => temp<='1'; next_state <= two;
xung th Zù fh nT Y Z [T[ ã_ 3 jgYfZ Z S[ h h Z fd
aYZ uZ WHEN two => temp<='0'; next_state <= three;
/( & f Z UfZ[ã UT tõaevY nkfZ
uks
gUg*X[ b-Xa
b0fd
aYã vUv)Um
[ã g
WHEN three => temp<='1'; next_state <= four;
tr e ã_ )T[ f _ fU
m[ã gf de vY T [
f f
Z[f T f õaevY nkUZzY
WHEN four => temp<='1'; next_state <= five;
ta thi f f
ZW a [g(U f Ze Z eSg0
WHEN five => temp<='1'; next_state <= six;
-----------------------------------------------------
WHEN six => temp<='0'; next_state <= seven;
LIBRARY ieee;
WHEN seven => temp<='0'; next_state <= zero;
USE ieee.std_logic_1164.all; END CASE;
----------------------------------------------------- END PROCESS;
ENTITY Bo_phat_tin_hieu IS END arc;
PORT (clk: IN STD_LOGIC; -----------------------------------------------------
wave: OUT STD_LOGIC);
K fcgú_xbZ Y0 WHEN 4 => wave <= '1';

WHEN 5 => wave <= '1';
WHEN 6 => wave <= '0';
WHEN 7 => wave <= '0';
END CASE;
if count = 7 then
8i
VP. :í âUlXPòVOàW jVO
count := 0;
EZ íYbZm
bfd
gk f
Z Y0 else
8ZzYfSf
Z[f T bZm
fft Z[gf
ZWabZ í YbZm
bfd
gk f
Z Yh [U
og Z>
;Z count := count + 1;
sau: end if ;
END PROCESS;
---------------------------------------
END arc;
LIBRARY ieee;
---------------------------------------
---------------------------------------
K fcgú_xbZ Y0
ENTITY Bo_phat_tin_hieu2 IS
PORT (clk: IN BIT;
wave: OUT BIT);
END Bo_phat_tin_hieu2;
---------------------------------------
ARCHITECTURE arc OF Bo_phat_tin_hieu2 IS 8i
VP. Kí âUlXPòVOàW jVO PM
WXP VOXPbX a
ìVPôVO
BEGIN
9.10. Thi T K WQ
PROCESS
Id
aYãaõ n
kUZzYf
Se f
Z[f U
mU_õ
UZT Z e
Sg0
VARIABLE count: INTEGER RANGE 0 TO 7;
BEGIN ROM
RAM v [TgeV [ghn
adSfm
UZd[
WAIT UNTIL (clk'EVENT AND clk='1');
ROM v [TgeV [ghn
adSZS[U
Z[g
CASE count IS
WHEN 0 => wave <= '0'; ROM (Read Only Memory): B Z UZ ãUhnYZ[0Híã USGDB ã UU ZdSfd
aY
ZuZ/() KuGDB nT Z U Z ãU ZxYU vft Z[gUaU U
Zo UZabZqbYZ[ v
WHEN 1 => wave <= '1';
ch U
vftZ[ghn aTgeãSU Zhnft Z[gdSnTgeV [g
WHEN 2 => wave <= '0';
WHEN 3 => wave <= '1';
"10000000");
BEGIN
data <= memory(addr);
END rom;
---------------------------------------------------
K fcgú_xbZ Y0
8i
VP. (A KI
Bpf
Z[f GDB Z e
Sg0
---------------------------------------------------
LIBRARY ieee;
8i
VP. ):í âUlXPòVOPíS
í
---------------------------------------------------
ENTITY rom IS
RAM v [ã YTgehn
adSd
[sYT[f
0Híã USG6B h[ã YTgehn
adSd
[sYT[f
ã UfZ Z[ f
daYZuZ/(+
GENERIC ( bits: INTEGER := 8; -- # of bits per word
words: INTEGER := 8); -- # of words in the
memory
PORT ( addr: IN INTEGER RANGE 0 TO words-1;
data: OUT STD_LOGIC_VECTOR (bits-1 DOWNTO 0));
END rom;
---------------------------------------------------
ARCHITECTURE rom OF rom IS
CONSTANT memory: vector_array := ( "00000000",
"00000010",
"00000100", 8i
VP. * 1 VOL T bK
P
"00001000",
CZ U ZzYf SfZù
kfd
s ZuZ G6B U vUmUTgeV [ghn aVS
fSQ[ TgeV [gd S
"00010000", VSfSQagfTgeãSU Zft Z[gU hnft Z[gUZabZq
bãUYZ[ Z[f t Z[gUZabZq
b
"00100000", YZ[ãUã Ujm U Z nYZ[fZuf
õ[_ [jgY s f[bfZW
aUSU f ZuV [gãghn a
"01000000", [ã U gf
(data_in) phú d tõ
[hfdtS
VVdhnV [gd SbZú[ã UãUf ãSU ZSVVd
Bpf
Z[f G6B e Z e
Sg0 ---------------------------------------------------
---------------------------------------------------------
K fcgú_xbZ Y0
library IEEE;
---------------------------------------------------
ENTITY ram IS
8i
VP. +:í
t quâUlXPòVO 1 K
j VOL T cW IS
PbKVPI
-------- memory---------- RAM v [ã YTgee
aYe
aY0
PORT ( wr_ena, clk: IN STD_LOGIC; Híã USG6B h[ã YTgeeaYeaYã Uf Z Z[ f

daYZuZ/( 9 [gã U
addr: IN INTEGER RANGE 0 TO words-1; YZ[hn
aG6B ZS
kã UãUf G6B f
Z UZ[ f
ds U Y ã YTge
data_in: IN STD_LOGIC_VECTOR (bits-1 DOWNTO 0);
data_out: OUT STD_LOGIC_VECTOR (bits-1 DOWNTO 0));
END ram;
---------------------------------------------------
ARCHITECTURE ram OF ram IS
SIGNAL memory: vector_array;
BEGIN
PROCESS (clk, wr_ena)
BEGIN
IF (wr_ena='1') THEN
8i
VP. , 1 VOL T K
PVO
memory(addr) <= data_in;
Bpf
Z[f e Z e
Sg0
END IF; -------------------------------------------------

END IF; LIBRARY ieee;
END PROCESS; USE ieee.std_logic_1164.all;
data_out <= memory(addr); -------------------------------------------------
END ram; ENTITY ramc IS
DY HC9: THI 91 9 O3 P 3c

-- memory
PORT ( clk, wr_ena: IN STD_LOGIC;
addr: IN INTEGER RANGE 0 TO words-1;
bidir: INOUT STD_LOGIC_VECTOR (bits-1 DOWNTO 0));
END ramc;
-------------------------------------------------
ARCHITECTURE arc OF ramc IS
SIGNAL memory: vector_array;
BEGIN
PROCESS (clk, wr_ena)
BEGIN
IF (wr_ena='0') THEN
bidir <= memory(addr);
ELSE
bidir <= (OTHERS => 'Z');
memory(addr) <= bidir;
END IF;
END IF;
END PROCESS;
END arc;
-------------------------------------------------
Trang 183 / 208 ThikI kGd D iHd VHDL ThikI kGd D iHC 2 Page 184 / 208
DY HC10: 4 g48 4 6 43 3 9 t 9h6 DY HC10: 4 g48 4 6 43 3 9 t 9h6
6E::A n_ ff d
uZT[s VU Zãí Y[ú bZ Z bh [U
mUk s
gUgf Z[f v Shn Z hnUv
38âá=710: 8â =74 =B 4 =7 ch U Y_xbZ Y 6E::Ag _ _ fU Z í Yf
duZe aõ f
Zúaf
an _n ZuZhn Y d S
PHú=< < C8Ã3C fZWaf
[sgUZg US? :9:8 CZ Y Zgkfã[_ UST T[ s dUZn k n ZxYZ fdã
t [Y[
úU mUT[gfZ U aY[
UEZ _ _ 6E::AU n[ãffdsU m
U_m kf
tZU m Zo USUxY
fk>7B hnUmUU
x Yfk ZmUfZt
UZZ bh [ v
10.1 T =7 D1= 3 3 8ú=< < 8 CA 3 1 4
8m UbZ _ _ Z fdU ZaU
mUh[_õU h l bf
duZã UU m
UUxYfkbZm
ffd
[ [
s fU Yn
k 10.1.7. IPLDS II (Intel Programmable Logic Devolopment System II)
U nYU v Z[gf
tZãSVõY Uvth Z tr U Za Z[g aõ
[h[_õ
UZ Zm
U ZSgsUvf
tZUõZ Ph _ _ > EA9H> >ã UU xYfk>f W gi i thi gã Z f dUZaU mUh[_õ UZZ :EA9
tranh mõZ_ fdaYf
Zf d Yh[_õU Z bf duZ [gUíTú USbZ _ _ n k nUZabZq bf Z[f f ZWa(bZ í YbZm b nbZ í YbZm
b
V YbZ í Yf duZãõ[e 7aaWS hnbZ í YbZm b [f sUmU Z f[Y[úU mUT[g
10.1.1. PALASM 2 (PAL ASSEMBLER)
th UaY[
U>EA9H> >e V YfZgfY[
ú[ãí giú :HEG:HHD> > MV. v nf ZgfY[ú[ã U
Ph _ _ E6A6HB (USU xYf
kBB>nbZ m _ f[sgUZg UZaU
mUh[_õ
UZ bfd
uZ bZmff
d[ T [ãõ[ZU8S[ X
ad[S vã UV Yã f Z UZ[ h[Ud zfY U mUftU
Ze fdaY
ok nT T[s VU Zf
Z Z th (Z f
dUZaUm
Uh[mõUZZaõ
fã Y ZxYã YT Z U mU UmUZn_ aY[UUSU mUh[_õUZVaU xYf k>f W sú jgù fI í Yf Z U m
UbZ m _
vi mõUZZ PAL c SUxYfkBB>h[_õUZZ EA6hnUm
Uh[_õUZUSUxYfkAMD. fd U>EA9H> >Un
[ãfã Uf d
aYU mU_mkf tZUSU xYf k>7B hnU mU_mkftZ Zm UU
v
10.1.2. AMAZE cùgZuZfZt
UZZ bã Ue V Y r _ h [U xYU bf duZUZah[_õ UZ
Ph _ _ 6B6O:ã UU xYf kH[YWf[

UebZmff
d[ hn vã UU gYUùbU
ZaUmU ZmUZ 10.1.8. CUPL ( Universal Compiler for Programmable Logic )
ZnYe V Yh[_õ UZ bfduZUSU xYf k BaVgWUZtZUSbZ _ _ 6B6O: n Ph _ _ 8JEAã UU xYfk6e
e[f
WVIWUZaaYkY[[fZ[ghna _ /.) o k nT
7A6HI 7aaW S aY[
U HfSf
WIdSe X
WdV Yã T[ s VUZUmUfZxYf
[ Y hn
a chuy T[s VUZhõ Yã UZ f dUZa(/ aõ
[h[mõUZUmU aõ[ UúEGDB hnUm
UU xYfk
ã[eSYU m
UX[WUZ í Yf
duZUZg USH[ YWf[
UeU m
UX[WU
vbZ m d Y n HI9 ch fõah[_õUZ bfd
uZ ZmU8JEA n_ f Yx ng _õZZ f dUZaUmUbZ í Yf
duZ
AMAZE h fd ã _xbZ YUmUhW
Ufí [_ fd
Sã fZ[f fZW
ak s
gUgUS Y [e V Y c Sãõ[e 7aaWS TúYe fZfhnfZ[f e íã f
dõYfZm[8JEAã Us V YZgZf
10.1.3. PLAN ( Programmable Logic Analysis) UmU_m kh[f
tZUm Zo f
dsUmUZ ã[gZnZ ZmU ZSgZf d
s _mkh[f
tZUSU xYfk
>7B ZSk8EB K6M JC> MhnK6M KBH
Ph _ _ EA6C ã UU xYfkCS
f[aS HW
_[U
aVgUfadY[[thi gZ f
dU ZaU
mUh[_õUZ
l bfd
uZU h Shn Z EA6C nm f Yx Y ãí Y[ú V Yã f Z UZ[ Um
UT[gfZU 10.1.9. ABEL (Advanced Boolean Expression Language)
c Sãõ[e 7aaW
S hnUv Zú YY[ S
af[bh [U
mUU xYU bf d
uZã bf duZUZah[ 67:A nbZ _ _ USU xYf
k9S
fS>& vã Ue V YZgZfUm
U aõ[h[_õ
UZ b
mõ U
Z f
duZ ZmU ZS
g U ú:EGDB ok nT T[
s VU
Zhõ YU
v Z[gUZ U Yh fd
10.1.4. HELD (Harris Enhanced Language for Programmable Logic) fí Yf Z 8JEA
8xYf k=S
dd[
ebZmff
d[ bZ _ _ =:A9 ã Z f
dUZaU
mU ZmUZZnYe V Yh[_õUZ Ids ãok ngi [thi geí UU mUbZ _ _Z f
dU Zah[_õ
UZ bf
duZã eaõ f
Zúa
l bf
duZUSZ =:A9 e V YY[SaV[ fí Yf Z bZ _ _ EA6C Z YU èYUv n bfduZUZaUmUh[_õUZ CYan
[dSUw Z[gbZ _ _ USUmUU
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Ngôn ngữ mô tả phần cứng VHDL

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Ngôn ngữ mô tả phần cứng VHDL

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M 2 M 2

6.1. PROCESS ---------------------------------------------------------------------------------------------------------------------- 71

1.2.2 Quy trinh thi T VòL

1.2.4. Chuy WVfE84 _d VòL

T _pK=9A n k _õUZv f ã Uf õadS Igk Z[

3Q àWP C DCA 3<t

3cL àW_ E84 L

ENTITY entity_name IS ARCHITECTURE architecture_name OF entity_name IS

END myarch; Z(3) <= not (A and B);

Architecture arc_mach_cong of mach_cong is

Port( X,Y : in bit ; Z, T : out bit);

ENTITY rsff IS Port(L,M :input ;N,P : out bit );

PORT( r : IN std_logic; End component;

COMPONENT nand -- ZT ZST M O ZS ZMZP

T2 := B and Cin ; 9 ---------------------------------------

8Zz 0K=9A ZxYbZo T[fU

EjM DFF k fZ bh[U YC6C9

H><C:9 hn JCH> <C:90U

SUBTYPE natural IS INTEGER RANGE 0 TO INTEGER'HIGH;

s fZ UZ[ ãkã _úYe n Z e Sg0 -- 1Dx1D array

TYPE matrix IS ARRAY (0 TO 3) OF STD_LOGIC_VECTOR(7 SIGNAL v: array2;

x(2) <= w(2,1); -- 1 cì P a ZS[ìO Z c U_ ' Z[U

w(1,1) <= x(7); LIBRARY ieee;

w(3,0) <= v(0)(3); USE ieee.std_logic_1164.all;

-- STD_LOGIC_VECTOR) END my_data_types;

x <= w(2); -- WTpZS T Xô c T U Xg ' --------------------------------------------

-- STD_LOGIC) LIBRARY ieee;

v(0)<=w(2,2 DOWNTO 0); --illegal(mismatch: STD_LOGIC_VECTOR USE ieee.std_logic_1164.all;

-- x STD_LOGIC) USE work.my_data_types.all; -- user-defined package

v(0) <= w(2); -- illegal (w must have 2D index) ---------------------------

y(1) <= v(3); -- illegal (type mismatch: ROW x ENTITY mux IS

-- STD_LOGIC_VECTOR) PORT (inp: IN VECTOR_ARRAY (0 TO 3);

-- same size) END mux;

-- same size) --------------------------------------------

w(1,5 DOWNTO 1)<=v(2)(4 DOWNTO 0); -- illegal (type 8vf Zf Zùkf d

------- Package: ------------------------------- fZSkhna Y[

USE ieee.std_logic_1164.all; e V Y [gV [gH> <C:9ZaUJCH><C:9 Yv[std_logic_arith c SfZ h[

w <= a AND b; -- h Xô Tj [fZ X[SUO ; Nhi gZn

LIBRARY ieee; conv_integer(p): chuy ã[_ ffZS_ e bUS [g>

... conv_std_logic_vector(p, b): chuy ãi m ff

,ClV SIGNAL z: STD_LOGIC_VECTOR (x'HIGH DOWNTO 0); -- 1D signal

3cL_jM 3:C 3:CKE64C A v w v w

-- array RECORD Multiple-type collection of any types above

SIGNAL a: STD_LOGIC; -- scalar signal Data Types 39

SIGNAL b: BIT; -- scalar signal TLFeBOOK

ARCHITECTURE and2 OF and2 IS

EjM 2 LWP 1MMN

1 ------ Solution 2: out=INTEGER -----------

3Q àWP C> =C EsC8D 3C =8 y <= NOT (a AND b);

SIGNAL d : STD_LOGIC_VECTOR(0 TO 7) IF (clk'EVENT AND clk='1')...

M fãaõ <:C:G>8 Z[ã Ue V YU bZú

GENERIC (parameter_name : parameter_type := parameter_value); Z[f

VARIABLE temp2 : INTEGER RANGE 0 TO x'HIGH; EjM : Generic parity detector.

temp1(temp2):='0'; GENERIC (n : INTEGER := 7);

END IF; PORT ( input: IN BIT_VECTOR (n DOWNTO 0);

x <= temp1; output: OUT BIT);

END PROCESS; END parity_det;

ARCHITECTURE parity OF parity_gen IS

8mUãaõ _pe aYe aY ZxYf Z e V YU m

EjM M fãaõ _pY_TS Z[ Ze aYe

BEGIN "001" WHEN ctl='1' ELSE

y <= (a AND NOT s1 AND NOT s0) OR "010";

(b AND NOT s1 AND s0) OR ---- With WITH/SELECT/WHEN --------------------